This series will add eDP controller support for Qualcomm SC7280 platform. These patches are baseline changes with which we can enable eDP display on sc7280. The sc7280 eDP controller can also support additional features such as which will be enabled in subsequent patch series.
This is based on Bjorn's changes in the below mentioned series to support both eDP and DP programming through the same driver: https://patchwork.kernel.org/project/linux-arm-msm/list/?series=564841
Summary of changes:
Changes in V2: - Remove gpio programming from DP driver - Implemented code review comments
Changes in V1: - Add support for eDP on SC7280 platform. - Add the new compatible string to documentation.
Sankeerth Billakanti (2): drm/msm/dp: Add support for SC7280 eDP dt-bindings: Add SC7280 compatible string
.../bindings/display/msm/dp-controller.yaml | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 4 ++-- drivers/gpu/drm/msm/dp/dp_ctrl.c | 20 ++++++++++++++++++-- drivers/gpu/drm/msm/dp/dp_display.c | 10 +++++++++- 4 files changed, 30 insertions(+), 5 deletions(-)
From: Sankeerth Billakanti sbillaka@codeaurora.org
The eDP controller on SC7280 is similar to the eDP/DP controllers supported by the current driver implementation.
SC7280 supports one EDP and one DP controller which can operate concurrently.
The following are some required changes to support eDP on sc7280: 1. SC7280 eDP support in the dp_display driver. 2. ASSR support programming for the sink device. 3. SSC support programming for the sink device.
Signed-off-by: Sankeerth Billakanti quic_sbillaka@quicinc.com --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 4 ++-- drivers/gpu/drm/msm/dp/dp_ctrl.c | 20 ++++++++++++++++++-- drivers/gpu/drm/msm/dp/dp_display.c | 10 +++++++++- 3 files changed, 29 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index ce6f32a..516cc19 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -856,9 +856,9 @@ static const struct dpu_intf_cfg sm8150_intf[] = { };
static const struct dpu_intf_cfg sc7280_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), + INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), - INTF_BLK("intf_5", INTF_5, 0x39000, INTF_EDP, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23), + INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23), };
/************************************************************* diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 62e75dc..9fea49c 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -119,7 +119,7 @@ void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl) static void dp_ctrl_config_ctrl(struct dp_ctrl_private *ctrl) { u32 config = 0, tbd; - u8 *dpcd = ctrl->panel->dpcd; + const u8 *dpcd = ctrl->panel->dpcd;
/* Default-> LSCLK DIV: 1/4 LCLK */ config |= (2 << DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT); @@ -1228,7 +1228,9 @@ static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl, int *training_step) { int ret = 0; + const u8 *dpcd = ctrl->panel->dpcd; u8 encoding = DP_SET_ANSI_8B10B; + u8 ssc, assr; struct dp_link_info link_info = {0};
dp_ctrl_config_ctrl(ctrl); @@ -1238,9 +1240,21 @@ static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl, link_info.capabilities = DP_LINK_CAP_ENHANCED_FRAMING;
dp_aux_link_configure(ctrl->aux, &link_info); + + if (dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) { + ssc = DP_SPREAD_AMP_0_5; + drm_dp_dpcd_write(ctrl->aux, DP_DOWNSPREAD_CTRL, &ssc, 1); + } + drm_dp_dpcd_write(ctrl->aux, DP_MAIN_LINK_CHANNEL_CODING_SET, &encoding, 1);
+ if (dpcd[DP_EDP_CONFIGURATION_CAP] & DP_ALTERNATE_SCRAMBLER_RESET_CAP) { + assr = DP_ALTERNATE_SCRAMBLER_RESET_ENABLE; + drm_dp_dpcd_write(ctrl->aux, DP_EDP_CONFIGURATION_SET, + &assr, 1); + } + ret = dp_ctrl_link_train_1(ctrl, training_step); if (ret) { DRM_ERROR("link training #1 failed. ret=%d\n", ret); @@ -1312,9 +1326,11 @@ static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl) struct dp_io *dp_io = &ctrl->parser->io; struct phy *phy = dp_io->phy; struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp; + const u8 *dpcd = ctrl->panel->dpcd;
opts_dp->lanes = ctrl->link->link_params.num_lanes; opts_dp->link_rate = ctrl->link->link_params.rate / 100; + opts_dp->ssc = dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5; dp_ctrl_set_clock_rate(ctrl, DP_CTRL_PM, "ctrl_link", ctrl->link->link_params.rate * 1000);
@@ -1406,7 +1422,7 @@ void dp_ctrl_host_deinit(struct dp_ctrl *dp_ctrl)
static bool dp_ctrl_use_fixed_nvid(struct dp_ctrl_private *ctrl) { - u8 *dpcd = ctrl->panel->dpcd; + const u8 *dpcd = ctrl->panel->dpcd;
/* * For better interop experience, used a fixed NVID=0x8000 diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index c867745..c16311b 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -144,8 +144,16 @@ static const struct msm_dp_config sc8180x_dp_cfg = { .num_descs = 3, };
+static const struct msm_dp_config sc7280_dp_cfg = { + .descs = (struct msm_dp_desc[]) { + { .io_start = 0x0aea0000, .connector_type = DRM_MODE_CONNECTOR_eDP }, + }, + .num_descs = 1, +}; + static const struct of_device_id dp_dt_match[] = { { .compatible = "qcom,sc7180-dp", .data = &sc7180_dp_cfg }, + { .compatible = "qcom,sc7280-edp", .data = &sc7280_dp_cfg }, { .compatible = "qcom,sc8180x-dp", .data = &sc8180x_dp_cfg }, { .compatible = "qcom,sc8180x-edp", .data = &sc8180x_dp_cfg }, {} @@ -1440,7 +1448,7 @@ void msm_dp_irq_postinstall(struct msm_dp *dp_display)
dp_hpd_event_setup(dp);
- dp_add_event(dp, EV_HPD_INIT_SETUP, 0, 100); + dp_add_event(dp, EV_HPD_INIT_SETUP, 0, 1); }
void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor *minor)
On Wed, 20 Oct 2021 at 15:14, Sankeerth Billakanti quic_sbillaka@quicinc.com wrote:
From: Sankeerth Billakanti sbillaka@codeaurora.org
The eDP controller on SC7280 is similar to the eDP/DP controllers supported by the current driver implementation.
SC7280 supports one EDP and one DP controller which can operate concurrently.
The following are some required changes to support eDP on sc7280:
- SC7280 eDP support in the dp_display driver.
- ASSR support programming for the sink device.
- SSC support programming for the sink device.
Please split your patch according to these changes. Each item should go in a separate patch.
Signed-off-by: Sankeerth Billakanti quic_sbillaka@quicinc.com
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 4 ++-- drivers/gpu/drm/msm/dp/dp_ctrl.c | 20 ++++++++++++++++++-- drivers/gpu/drm/msm/dp/dp_display.c | 10 +++++++++- 3 files changed, 29 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index ce6f32a..516cc19 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -856,9 +856,9 @@ static const struct dpu_intf_cfg sm8150_intf[] = { };
static const struct dpu_intf_cfg sc7280_intf[] = {
INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
INTF_BLK("intf_5", INTF_5, 0x39000, INTF_EDP, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
Why does intf_0 receive index 1? I think you have a mistake in the dp_descs below. Also note that the latest patch started using MSM_DP_CONTROLLER_n symbols instead of using raw numbers.
};
/************************************************************* diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 62e75dc..9fea49c 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -119,7 +119,7 @@ void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl) static void dp_ctrl_config_ctrl(struct dp_ctrl_private *ctrl) { u32 config = 0, tbd;
u8 *dpcd = ctrl->panel->dpcd;
const u8 *dpcd = ctrl->panel->dpcd; /* Default-> LSCLK DIV: 1/4 LCLK */ config |= (2 << DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT);@@ -1228,7 +1228,9 @@ static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl, int *training_step) { int ret = 0;
const u8 *dpcd = ctrl->panel->dpcd; u8 encoding = DP_SET_ANSI_8B10B;u8 ssc, assr; struct dp_link_info link_info = {0}; dp_ctrl_config_ctrl(ctrl);@@ -1238,9 +1240,21 @@ static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl, link_info.capabilities = DP_LINK_CAP_ENHANCED_FRAMING;
dp_aux_link_configure(ctrl->aux, &link_info);
if (dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) {ssc = DP_SPREAD_AMP_0_5;drm_dp_dpcd_write(ctrl->aux, DP_DOWNSPREAD_CTRL, &ssc, 1);}drm_dp_dpcd_write(ctrl->aux, DP_MAIN_LINK_CHANNEL_CODING_SET, &encoding, 1);if (dpcd[DP_EDP_CONFIGURATION_CAP] & DP_ALTERNATE_SCRAMBLER_RESET_CAP) {assr = DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;drm_dp_dpcd_write(ctrl->aux, DP_EDP_CONFIGURATION_SET,&assr, 1);}ret = dp_ctrl_link_train_1(ctrl, training_step); if (ret) { DRM_ERROR("link training #1 failed. ret=%d\n", ret);@@ -1312,9 +1326,11 @@ static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl) struct dp_io *dp_io = &ctrl->parser->io; struct phy *phy = dp_io->phy; struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp;
const u8 *dpcd = ctrl->panel->dpcd; opts_dp->lanes = ctrl->link->link_params.num_lanes; opts_dp->link_rate = ctrl->link->link_params.rate / 100;opts_dp->ssc = dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5; dp_ctrl_set_clock_rate(ctrl, DP_CTRL_PM, "ctrl_link", ctrl->link->link_params.rate * 1000);@@ -1406,7 +1422,7 @@ void dp_ctrl_host_deinit(struct dp_ctrl *dp_ctrl)
static bool dp_ctrl_use_fixed_nvid(struct dp_ctrl_private *ctrl) {
u8 *dpcd = ctrl->panel->dpcd;
const u8 *dpcd = ctrl->panel->dpcd; /* * For better interop experience, used a fixed NVID=0x8000diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index c867745..c16311b 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -144,8 +144,16 @@ static const struct msm_dp_config sc8180x_dp_cfg = { .num_descs = 3, };
+static const struct msm_dp_config sc7280_dp_cfg = {
.descs = (struct msm_dp_desc[]) {{ .io_start = 0x0aea0000, .connector_type = DRM_MODE_CONNECTOR_eDP },
I think you'd want to have sc7280-dp using DP_CONTROLLER_0 and sc7280-edp using DP_CONTROLLER_1. See latest Bjorn's patches.
},.num_descs = 1,+};
static const struct of_device_id dp_dt_match[] = { { .compatible = "qcom,sc7180-dp", .data = &sc7180_dp_cfg },
{ .compatible = "qcom,sc7280-edp", .data = &sc7280_dp_cfg }, { .compatible = "qcom,sc8180x-dp", .data = &sc8180x_dp_cfg }, { .compatible = "qcom,sc8180x-edp", .data = &sc8180x_dp_cfg }, {}@@ -1440,7 +1448,7 @@ void msm_dp_irq_postinstall(struct msm_dp *dp_display)
dp_hpd_event_setup(dp);
dp_add_event(dp, EV_HPD_INIT_SETUP, 0, 100);
dp_add_event(dp, EV_HPD_INIT_SETUP, 0, 1);}
void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor *minor)
The Qualcomm Innovatin Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Quoting Sankeerth Billakanti (2021-10-20 05:14:10)
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 62e75dc..9fea49c 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -1238,9 +1240,21 @@ static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl, link_info.capabilities = DP_LINK_CAP_ENHANCED_FRAMING;
dp_aux_link_configure(ctrl->aux, &link_info);
if (dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) {
Please add a static inline macro in include/drm/drm_dp_helper.h that makes this more readable. Something similar to drm_dp_is_branch() but with a human readable replacement for "is_branch". Maybe drm_dp_ssc()?
ssc = DP_SPREAD_AMP_0_5;drm_dp_dpcd_write(ctrl->aux, DP_DOWNSPREAD_CTRL, &ssc, 1);}drm_dp_dpcd_write(ctrl->aux, DP_MAIN_LINK_CHANNEL_CODING_SET, &encoding, 1);if (dpcd[DP_EDP_CONFIGURATION_CAP] & DP_ALTERNATE_SCRAMBLER_RESET_CAP) {
And this one already has a helper, drm_dp_alternate_scrambler_reset_cap().
assr = DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;drm_dp_dpcd_write(ctrl->aux, DP_EDP_CONFIGURATION_SET,&assr, 1);}ret = dp_ctrl_link_train_1(ctrl, training_step); if (ret) { DRM_ERROR("link training #1 failed. ret=%d\n", ret);@@ -1312,9 +1326,11 @@ static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl) struct dp_io *dp_io = &ctrl->parser->io; struct phy *phy = dp_io->phy; struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp;
const u8 *dpcd = ctrl->panel->dpcd; opts_dp->lanes = ctrl->link->link_params.num_lanes; opts_dp->link_rate = ctrl->link->link_params.rate / 100;opts_dp->ssc = dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5; dp_ctrl_set_clock_rate(ctrl, DP_CTRL_PM, "ctrl_link", ctrl->link->link_params.rate * 1000);@@ -1406,7 +1422,7 @@ void dp_ctrl_host_deinit(struct dp_ctrl *dp_ctrl)
static bool dp_ctrl_use_fixed_nvid(struct dp_ctrl_private *ctrl) {
u8 *dpcd = ctrl->panel->dpcd;
const u8 *dpcd = ctrl->panel->dpcd; /* * For better interop experience, used a fixed NVID=0x8000diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index c867745..c16311b 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -144,8 +144,16 @@ static const struct msm_dp_config sc8180x_dp_cfg = { .num_descs = 3, };
+static const struct msm_dp_config sc7280_dp_cfg = {
.descs = (struct msm_dp_desc[]) {
const
{ .io_start = 0x0aea0000, .connector_type = DRM_MODE_CONNECTOR_eDP },},.num_descs = 1,+};
static const struct of_device_id dp_dt_match[] = { { .compatible = "qcom,sc7180-dp", .data = &sc7180_dp_cfg },
{ .compatible = "qcom,sc7280-edp", .data = &sc7280_dp_cfg }, { .compatible = "qcom,sc8180x-dp", .data = &sc8180x_dp_cfg }, { .compatible = "qcom,sc8180x-edp", .data = &sc8180x_dp_cfg }, {}@@ -1440,7 +1448,7 @@ void msm_dp_irq_postinstall(struct msm_dp *dp_display)
dp_hpd_event_setup(dp);
dp_add_event(dp, EV_HPD_INIT_SETUP, 0, 100);
dp_add_event(dp, EV_HPD_INIT_SETUP, 0, 1);
This has no explanation. What is it?
Hi Stephen,
On 2021-10-21 23:32, Stephen Boyd wrote:
Quoting Sankeerth Billakanti (2021-10-20 05:14:10)
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 62e75dc..9fea49c 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -1238,9 +1240,21 @@ static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl, link_info.capabilities = DP_LINK_CAP_ENHANCED_FRAMING;
dp_aux_link_configure(ctrl->aux, &link_info);
if (dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) {Please add a static inline macro in include/drm/drm_dp_helper.h that makes this more readable. Something similar to drm_dp_is_branch() but with a human readable replacement for "is_branch". Maybe drm_dp_ssc()?
Okay, I will add a macro, drm_dp_max_downspread (to be consistent with the spec and other macros in the file) in drm_dp_helper.h file.
ssc = DP_SPREAD_AMP_0_5;drm_dp_dpcd_write(ctrl->aux, DP_DOWNSPREAD_CTRL, &ssc,1);
}drm_dp_dpcd_write(ctrl->aux, DP_MAIN_LINK_CHANNEL_CODING_SET, &encoding, 1);if (dpcd[DP_EDP_CONFIGURATION_CAP] &DP_ALTERNATE_SCRAMBLER_RESET_CAP) {
And this one already has a helper, drm_dp_alternate_scrambler_reset_cap().
Okay, I will use that.
assr = DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;drm_dp_dpcd_write(ctrl->aux, DP_EDP_CONFIGURATION_SET,&assr, 1);}ret = dp_ctrl_link_train_1(ctrl, training_step); if (ret) { DRM_ERROR("link training #1 failed. ret=%d\n", ret);@@ -1312,9 +1326,11 @@ static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl) struct dp_io *dp_io = &ctrl->parser->io; struct phy *phy = dp_io->phy; struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp;
const u8 *dpcd = ctrl->panel->dpcd; opts_dp->lanes = ctrl->link->link_params.num_lanes; opts_dp->link_rate = ctrl->link->link_params.rate / 100;opts_dp->ssc = dpcd[DP_MAX_DOWNSPREAD] &DP_MAX_DOWNSPREAD_0_5; dp_ctrl_set_clock_rate(ctrl, DP_CTRL_PM, "ctrl_link", ctrl->link->link_params.rate * 1000);
@@ -1406,7 +1422,7 @@ void dp_ctrl_host_deinit(struct dp_ctrl *dp_ctrl)
static bool dp_ctrl_use_fixed_nvid(struct dp_ctrl_private *ctrl) {
u8 *dpcd = ctrl->panel->dpcd;
const u8 *dpcd = ctrl->panel->dpcd; /* * For better interop experience, used a fixed NVID=0x8000diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index c867745..c16311b 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -144,8 +144,16 @@ static const struct msm_dp_config sc8180x_dp_cfg = { .num_descs = 3, };
+static const struct msm_dp_config sc7280_dp_cfg = {
.descs = (struct msm_dp_desc[]) {const
Will add it.
{ .io_start = 0x0aea0000, .connector_type =DRM_MODE_CONNECTOR_eDP },
},.num_descs = 1,+};
static const struct of_device_id dp_dt_match[] = { { .compatible = "qcom,sc7180-dp", .data = &sc7180_dp_cfg },
{ .compatible = "qcom,sc7280-edp", .data = &sc7280_dp_cfg }, { .compatible = "qcom,sc8180x-dp", .data = &sc8180x_dp_cfg }, { .compatible = "qcom,sc8180x-edp", .data = &sc8180x_dp_cfg }, {}@@ -1440,7 +1448,7 @@ void msm_dp_irq_postinstall(struct msm_dp *dp_display)
dp_hpd_event_setup(dp);
dp_add_event(dp, EV_HPD_INIT_SETUP, 0, 100);
dp_add_event(dp, EV_HPD_INIT_SETUP, 0, 1);This has no explanation. What is it?
Will add explanation for it as a comment.
From: Sankeerth Billakanti sbillaka@codeaurora.org
The Qualcomm SC7280 platform supports an eDP controller, add compatible string for it to dp-controller.
Signed-off-by: Sankeerth Billakanti quic_sbillaka@quicinc.com --- Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 1 + 1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 63e585f..ab2bb1b 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -17,6 +17,7 @@ properties: compatible: enum: - qcom,sc7180-dp + - qcom,sc7280-edp - qcom,sc8180x-dp - qcom,sc8180x-edp
Hi,
On Wed, Oct 20, 2021 at 5:14 AM Sankeerth Billakanti quic_sbillaka@quicinc.com wrote:
From: Sankeerth Billakanti sbillaka@codeaurora.org
The Qualcomm SC7280 platform supports an eDP controller, add compatible string for it to dp-controller.
Signed-off-by: Sankeerth Billakanti quic_sbillaka@quicinc.com
Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 1 + 1 file changed, 1 insertion(+)
I think you ignored some of the feedback that was given on v1. Perhaps you could go back and re-read that feedback? See the replies to:
https://lore.kernel.org/r/1628726882-27841-3-git-send-email-sbillaka@codeaur...
For one, ${SUBJECT} needs updating. It's probably as simple as adding the "msm/dp" tag, like:
dt-bindings: msm/dp: Add SC7280 compatible string
For another, Stephen requested that you add "sc7280-dp" too.
Hi Doug,
Sorry about that, this is the first time I am posting changes upstream and still getting hold of conventions.
I think I misinterpreted your subject line comment and changed the just title to include dp-controller. I will correct it in the next version.
sc7280-dp will be added later when dp support for sc7280 will be posted. I will reply on the feedback email from Stephen.
Thank you, Sankeerth
-----Original Message----- From: Doug Anderson dianders@chromium.org Sent: Wednesday, October 20, 2021 11:11 PM To: quic_sbillaka quic_sbillaka@quicinc.com Cc: dri-devel dri-devel@lists.freedesktop.org; linux-arm-msm linux-arm-msm@vger.kernel.org; freedreno freedreno@lists.freedesktop.org; LKML linux-kernel@vger.kernel.org; Sankeerth Billakanti sbillaka@codeaurora.org; Rob Clark robdclark@gmail.com; Sean Paul seanpaul@chromium.org; Stephen Boyd swboyd@chromium.org; Kalyan Thota kalyan_t@codeaurora.org; Abhinav Kumar abhinavk@codeaurora.org; Kuogee Hsieh khsieh@codeaurora.org; Krishna Manikandan mkrishn@codeaurora.org Subject: Re: [PATCH v2 2/2] dt-bindings: Add SC7280 compatible string
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Hi,
On Wed, Oct 20, 2021 at 5:14 AM Sankeerth Billakanti quic_sbillaka@quicinc.com wrote:
From: Sankeerth Billakanti sbillaka@codeaurora.org
The Qualcomm SC7280 platform supports an eDP controller, add compatible string for it to dp-controller.
Signed-off-by: Sankeerth Billakanti quic_sbillaka@quicinc.com
Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 1
1 file changed, 1 insertion(+)
I think you ignored some of the feedback that was given on v1. Perhaps you could go back and re-read that feedback? See the replies to:
https://lore.kernel.org/r/1628726882-27841-3-git-send-email-sbillaka@codeaur...
For one, ${SUBJECT} needs updating. It's probably as simple as adding the "msm/dp" tag, like:
dt-bindings: msm/dp: Add SC7280 compatible string
For another, Stephen requested that you add "sc7280-dp" too.
dri-devel@lists.freedesktop.org
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Dmitry Baryshkov -
Doug Anderson -
quic_sbillaka -
Sankeerth Billakanti
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sbillakaļ¼ codeaurora.org -
Stephen Boyd