Remove all unused dpu_hw_blk features and functions: - dpu_hw_blk_get()/_put() and respective refcounting, - global list of all dpu_hw_blk instances, - dpu_hw_blk_ops and empty implementation inside each hw_blk subdriver.

This leaves dpu_hw_blk as a placeholder with just type and index.

Signed-off-by: Dmitry Baryshkov dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c | 104 +----------------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h | 19 +--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 4 +- .../gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c | 4 +- .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 4 +- 10 files changed, 10 insertions(+), 145 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c index 819b26e660b9..abad043f35f5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c @@ -11,33 +11,16 @@ #include "dpu_hw_mdss.h" #include "dpu_hw_blk.h"

-/* Serialization lock for dpu_hw_blk_list */ -static DEFINE_MUTEX(dpu_hw_blk_lock); - -/* List of all hw block objects */ -static LIST_HEAD(dpu_hw_blk_list); - /** * dpu_hw_blk_init - initialize hw block object * @hw_blk: pointer to hw block object * @type: hw block type - enum dpu_hw_blk_type * @id: instance id of the hw block - * @ops: Pointer to block operations */ -void dpu_hw_blk_init(struct dpu_hw_blk *hw_blk, u32 type, int id, - struct dpu_hw_blk_ops *ops) +void dpu_hw_blk_init(struct dpu_hw_blk *hw_blk, u32 type, int id) { - INIT_LIST_HEAD(&hw_blk->list); hw_blk->type = type; hw_blk->id = id; - atomic_set(&hw_blk->refcount, 0); - - if (ops) - hw_blk->ops = *ops; - - mutex_lock(&dpu_hw_blk_lock); - list_add(&hw_blk->list, &dpu_hw_blk_list); - mutex_unlock(&dpu_hw_blk_lock); }

/** @@ -51,89 +34,4 @@ void dpu_hw_blk_destroy(struct dpu_hw_blk *hw_blk) pr_err("invalid parameters\n"); return; } - - if (atomic_read(&hw_blk->refcount)) - pr_err("hw_blk:%d.%d invalid refcount\n", hw_blk->type, - hw_blk->id); - - mutex_lock(&dpu_hw_blk_lock); - list_del(&hw_blk->list); - mutex_unlock(&dpu_hw_blk_lock); -} - -/** - * dpu_hw_blk_get - get hw_blk from free pool - * @hw_blk: if specified, increment reference count only - * @type: if hw_blk is not specified, allocate the next available of this type - * @id: if specified (>= 0), allocate the given instance of the above type - * return: pointer to hw block object - */ -struct dpu_hw_blk *dpu_hw_blk_get(struct dpu_hw_blk *hw_blk, u32 type, int id) -{ - struct dpu_hw_blk *curr; - int rc, refcount; - - if (!hw_blk) { - mutex_lock(&dpu_hw_blk_lock); - list_for_each_entry(curr, &dpu_hw_blk_list, list) { - if ((curr->type != type) || - (id >= 0 && curr->id != id) || - (id < 0 && - atomic_read(&curr->refcount))) - continue; - - hw_blk = curr; - break; - } - mutex_unlock(&dpu_hw_blk_lock); - } - - if (!hw_blk) { - pr_debug("no hw_blk:%d\n", type); - return NULL; - } - - refcount = atomic_inc_return(&hw_blk->refcount); - - if (refcount == 1 && hw_blk->ops.start) { - rc = hw_blk->ops.start(hw_blk); - if (rc) { - pr_err("failed to start hw_blk:%d rc:%d\n", type, rc); - goto error_start; - } - } - - pr_debug("hw_blk:%d.%d refcount:%d\n", hw_blk->type, - hw_blk->id, refcount); - return hw_blk; - -error_start: - dpu_hw_blk_put(hw_blk); - return ERR_PTR(rc); -} - -/** - * dpu_hw_blk_put - put hw_blk to free pool if decremented refcount is zero - * @hw_blk: hw block to be freed - */ -void dpu_hw_blk_put(struct dpu_hw_blk *hw_blk) -{ - if (!hw_blk) { - pr_err("invalid parameters\n"); - return; - } - - pr_debug("hw_blk:%d.%d refcount:%d\n", hw_blk->type, hw_blk->id, - atomic_read(&hw_blk->refcount)); - - if (!atomic_read(&hw_blk->refcount)) { - pr_err("hw_blk:%d.%d invalid put\n", hw_blk->type, hw_blk->id); - return; - } - - if (atomic_dec_return(&hw_blk->refcount)) - return; - - if (hw_blk->ops.stop) - hw_blk->ops.stop(hw_blk); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h index 2bf737f8dd1b..fb3be9a36a50 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h @@ -7,19 +7,9 @@

#include <linux/types.h> #include <linux/list.h> -#include <linux/atomic.h>

struct dpu_hw_blk;

-/** - * struct dpu_hw_blk_ops - common hardware block operations - * @start: start operation on first get - * @stop: stop operation on last put - */ -struct dpu_hw_blk_ops { - int (*start)(struct dpu_hw_blk *); - void (*stop)(struct dpu_hw_blk *); -};

/** * struct dpu_hw_blk - definition of hardware block object @@ -29,17 +19,10 @@ struct dpu_hw_blk_ops { * @refcount: reference/usage count */ struct dpu_hw_blk { - struct list_head list; u32 type; int id; - atomic_t refcount; - struct dpu_hw_blk_ops ops; };

-void dpu_hw_blk_init(struct dpu_hw_blk *hw_blk, u32 type, int id, - struct dpu_hw_blk_ops *ops); +void dpu_hw_blk_init(struct dpu_hw_blk *hw_blk, u32 type, int id); void dpu_hw_blk_destroy(struct dpu_hw_blk *hw_blk); - -struct dpu_hw_blk *dpu_hw_blk_get(struct dpu_hw_blk *hw_blk, u32 type, int id); -void dpu_hw_blk_put(struct dpu_hw_blk *hw_blk); #endif /*_DPU_HW_BLK_H */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index 8981cfa9dbc3..ad60d59d3106 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -560,8 +560,6 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops, ops->get_bitmask_dspp = dpu_hw_ctl_get_bitmask_dspp; };

-static struct dpu_hw_blk_ops dpu_hw_ops; - struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx, void __iomem *addr, const struct dpu_mdss_cfg *m) @@ -586,7 +584,7 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx, c->mixer_count = m->mixer_count; c->mixer_hw_caps = m->mixer;

- dpu_hw_blk_init(&c->base, DPU_HW_BLK_CTL, idx, &dpu_hw_ops); + dpu_hw_blk_init(&c->base, DPU_HW_BLK_CTL, idx);

return c; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c index e42f901a7de5..d2f1045a736a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c @@ -85,8 +85,6 @@ static const struct dpu_dspp_cfg *_dspp_offset(enum dpu_dspp dspp, return ERR_PTR(-EINVAL); }

-static struct dpu_hw_blk_ops dpu_hw_ops; - struct dpu_hw_dspp *dpu_hw_dspp_init(enum dpu_dspp idx, void __iomem *addr, const struct dpu_mdss_cfg *m) @@ -112,7 +110,7 @@ struct dpu_hw_dspp *dpu_hw_dspp_init(enum dpu_dspp idx, c->cap = cfg; _setup_dspp_ops(c, c->cap->features);

- dpu_hw_blk_init(&c->base, DPU_HW_BLK_DSPP, idx, &dpu_hw_ops); + dpu_hw_blk_init(&c->base, DPU_HW_BLK_DSPP, idx);

return c; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 6f0f54588124..db78842e3999 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -289,8 +289,6 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops, ops->bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk; }

-static struct dpu_hw_blk_ops dpu_hw_ops; - struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx, void __iomem *addr, const struct dpu_mdss_cfg *m) @@ -317,7 +315,7 @@ struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx, c->mdss = m; _setup_intf_ops(&c->ops, c->cap->features);

- dpu_hw_blk_init(&c->base, DPU_HW_BLK_INTF, idx, &dpu_hw_ops); + dpu_hw_blk_init(&c->base, DPU_HW_BLK_INTF, idx);

return c; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c index 6ac0b5a0e057..554bb881de3a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c @@ -160,8 +160,6 @@ static void _setup_mixer_ops(const struct dpu_mdss_cfg *m, ops->setup_border_color = dpu_hw_lm_setup_border_color; }

-static struct dpu_hw_blk_ops dpu_hw_ops; - struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx, void __iomem *addr, const struct dpu_mdss_cfg *m) @@ -184,7 +182,7 @@ struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx, c->cap = cfg; _setup_mixer_ops(m, &c->ops, c->cap->features);

- dpu_hw_blk_init(&c->base, DPU_HW_BLK_LM, idx, &dpu_hw_ops); + dpu_hw_blk_init(&c->base, DPU_HW_BLK_LM, idx);

return c; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c index 720813e5a8ae..863229dd0140 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c @@ -58,8 +58,6 @@ static void _setup_merge_3d_ops(struct dpu_hw_merge_3d *c, c->ops.setup_3d_mode = dpu_hw_merge_3d_setup_3d_mode; };

-static struct dpu_hw_blk_ops dpu_hw_ops; - struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(enum dpu_merge_3d idx, void __iomem *addr, const struct dpu_mdss_cfg *m) @@ -81,7 +79,7 @@ struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(enum dpu_merge_3d idx, c->caps = cfg; _setup_merge_3d_ops(c, c->caps->features);

- dpu_hw_blk_init(&c->base, DPU_HW_BLK_MERGE_3D, idx, &dpu_hw_ops); + dpu_hw_blk_init(&c->base, DPU_HW_BLK_MERGE_3D, idx);

return c; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c index 245a7a62b5c6..334d5b28f533 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c @@ -261,8 +261,6 @@ static void _setup_pingpong_ops(struct dpu_hw_pingpong *c, c->ops.setup_dither = dpu_hw_pp_setup_dither; };

-static struct dpu_hw_blk_ops dpu_hw_ops; - struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx, void __iomem *addr, const struct dpu_mdss_cfg *m) @@ -284,7 +282,7 @@ struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx, c->caps = cfg; _setup_pingpong_ops(c, c->caps->features);

- dpu_hw_blk_init(&c->base, DPU_HW_BLK_PINGPONG, idx, &dpu_hw_ops); + dpu_hw_blk_init(&c->base, DPU_HW_BLK_PINGPONG, idx);

return c; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index 34d81aa16041..ceb2488ea270 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -706,8 +706,6 @@ static const struct dpu_sspp_cfg *_sspp_offset(enum dpu_sspp sspp, return ERR_PTR(-ENOMEM); }

-static struct dpu_hw_blk_ops dpu_hw_ops; - struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, void __iomem *addr, struct dpu_mdss_cfg *catalog, bool is_virtual_pipe) @@ -735,7 +733,7 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, hw_pipe->cap = cfg; _setup_layer_ops(hw_pipe, hw_pipe->cap->features);

- dpu_hw_blk_init(&hw_pipe->base, DPU_HW_BLK_SSPP, idx, &dpu_hw_ops); + dpu_hw_blk_init(&hw_pipe->base, DPU_HW_BLK_SSPP, idx);

return hw_pipe; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c index 01b76766a9a8..5d2c33ec1de7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c @@ -295,8 +295,6 @@ static const struct dpu_mdp_cfg *_top_offset(enum dpu_mdp mdp, return ERR_PTR(-EINVAL); }

-static struct dpu_hw_blk_ops dpu_hw_ops; - struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx, void __iomem *addr, const struct dpu_mdss_cfg *m) @@ -324,7 +322,7 @@ struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx, mdp->caps = cfg; _setup_mdp_ops(&mdp->ops, mdp->caps->features);

- dpu_hw_blk_init(&mdp->base, DPU_HW_BLK_TOP, idx, &dpu_hw_ops); + dpu_hw_blk_init(&mdp->base, DPU_HW_BLK_TOP, idx);

return mdp; }

Each DSPP block is tied to a single LM. No LMs can share single DSPP block. So there is no need to handle DSPP blocks through all resource allocation/deallocation/assignment, just receive DSPP block as a part of LM hardware instance.

Signed-off-by: Dmitry Baryshkov dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 6 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 116 ++++++-------------- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 2 - 6 files changed, 44 insertions(+), 88 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 288e95ee8e1d..b3d50f6d976d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -977,7 +977,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC]; struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC]; struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; - struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL }; int num_lm, num_ctl, num_pp; int i, j;

@@ -1028,9 +1027,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); - dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_DSPP, hw_dspp, - ARRAY_SIZE(hw_dspp));

for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i]) @@ -1043,7 +1039,7 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,

cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]); cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]); - cstate->mixers[i].hw_dspp = to_dpu_hw_dspp(hw_dspp[i]); + cstate->mixers[i].hw_dspp = cstate->mixers[i].hw_lm->dspp; }

cstate->num_mixers = num_lm; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c index 76f8b8f75b82..35675744a6b7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c @@ -5,6 +5,7 @@ #include "dpu_kms.h" #include "dpu_hw_catalog.h" #include "dpu_hwio.h" +#include "dpu_hw_dspp.h" #include "dpu_hw_lm.h" #include "dpu_hw_mdss.h"

@@ -182,6 +183,9 @@ struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx, c->cap = cfg; _setup_mixer_ops(m, &c->ops, c->cap->features);

+ if (cfg->dspp && cfg->dspp < DSPP_MAX) + c->dspp = dpu_hw_dspp_init(cfg->dspp, addr, m); + dpu_hw_blk_init(&c->base, DPU_HW_BLK_LM, idx);

return c; @@ -189,5 +193,7 @@ struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx,

void dpu_hw_lm_destroy(struct dpu_hw_mixer *lm) { + if (lm) + dpu_hw_dspp_destroy(lm->dspp); kfree(lm); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h index 4a6b2de19ef6..effb78311a43 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h @@ -64,6 +64,7 @@ struct dpu_hw_mixer { const struct dpu_lm_cfg *cap; const struct dpu_mdp_cfg *mdp; const struct dpu_ctl_cfg *ctl; + struct dpu_hw_dspp *dspp;

/* ops */ struct dpu_hw_lm_ops ops; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index d6717d6672f7..195a854245fa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -164,7 +164,6 @@ struct dpu_global_state { uint32_t mixer_to_enc_id[LM_MAX - LM_0]; uint32_t ctl_to_enc_id[CTL_MAX - CTL_0]; uint32_t intf_to_enc_id[INTF_MAX - INTF_0]; - uint32_t dspp_to_enc_id[DSPP_MAX - DSPP_0]; };

struct dpu_global_state diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index fd2d104f0a91..bb03ff8b8c9f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -9,7 +9,6 @@ #include "dpu_hw_ctl.h" #include "dpu_hw_pingpong.h" #include "dpu_hw_intf.h" -#include "dpu_hw_dspp.h" #include "dpu_hw_merge3d.h" #include "dpu_encoder.h" #include "dpu_trace.h" @@ -35,6 +34,14 @@ int dpu_rm_destroy(struct dpu_rm *rm) { int i;

+ for (i = 0; i < ARRAY_SIZE(rm->mixer_blks); i++) { + struct dpu_hw_mixer *hw; + + if (rm->mixer_blks[i]) { + hw = to_dpu_hw_mixer(rm->mixer_blks[i]); + dpu_hw_lm_destroy(hw); + } + } for (i = 0; i < ARRAY_SIZE(rm->pingpong_blks); i++) { struct dpu_hw_pingpong *hw;

@@ -51,14 +58,6 @@ int dpu_rm_destroy(struct dpu_rm *rm) dpu_hw_merge_3d_destroy(hw); } } - for (i = 0; i < ARRAY_SIZE(rm->mixer_blks); i++) { - struct dpu_hw_mixer *hw; - - if (rm->mixer_blks[i]) { - hw = to_dpu_hw_mixer(rm->mixer_blks[i]); - dpu_hw_lm_destroy(hw); - } - } for (i = 0; i < ARRAY_SIZE(rm->ctl_blks); i++) { struct dpu_hw_ctl *hw;

@@ -94,40 +93,6 @@ int dpu_rm_init(struct dpu_rm *rm, memset(rm, 0, sizeof(*rm));

/* Interrogate HW catalog and create tracking items for hw blocks */ - for (i = 0; i < cat->mixer_count; i++) { - struct dpu_hw_mixer *hw; - const struct dpu_lm_cfg *lm = &cat->mixer[i]; - - if (lm->pingpong == PINGPONG_MAX) { - DPU_DEBUG("skip mixer %d without pingpong\n", lm->id); - continue; - } - - if (lm->id < LM_0 || lm->id >= LM_MAX) { - DPU_ERROR("skip mixer %d with invalid id\n", lm->id); - continue; - } - hw = dpu_hw_lm_init(lm->id, mmio, cat); - if (IS_ERR_OR_NULL(hw)) { - rc = PTR_ERR(hw); - DPU_ERROR("failed lm object creation: err %d\n", rc); - goto fail; - } - rm->mixer_blks[lm->id - LM_0] = &hw->base; - - if (!rm->lm_max_width) { - rm->lm_max_width = lm->sblk->maxwidth; - } else if (rm->lm_max_width != lm->sblk->maxwidth) { - /* - * Don't expect to have hw where lm max widths differ. - * If found, take the min. - */ - DPU_ERROR("unsupported: lm maxwidth differs\n"); - if (rm->lm_max_width > lm->sblk->maxwidth) - rm->lm_max_width = lm->sblk->maxwidth; - } - } - for (i = 0; i < cat->merge_3d_count; i++) { struct dpu_hw_merge_3d *hw; const struct dpu_merge_3d_cfg *merge_3d = &cat->merge_3d[i]; @@ -204,21 +169,38 @@ int dpu_rm_init(struct dpu_rm *rm, rm->ctl_blks[ctl->id - CTL_0] = &hw->base; }

- for (i = 0; i < cat->dspp_count; i++) { - struct dpu_hw_dspp *hw; - const struct dpu_dspp_cfg *dspp = &cat->dspp[i]; + for (i = 0; i < cat->mixer_count; i++) { + struct dpu_hw_mixer *hw; + const struct dpu_lm_cfg *lm = &cat->mixer[i];

- if (dspp->id < DSPP_0 || dspp->id >= DSPP_MAX) { - DPU_ERROR("skip dspp %d with invalid id\n", dspp->id); + if (lm->pingpong == PINGPONG_MAX) { + DPU_DEBUG("skip mixer %d without pingpong\n", lm->id); + continue; + } + + if (lm->id < LM_0 || lm->id >= LM_MAX) { + DPU_ERROR("skip mixer %d with invalid id\n", lm->id); continue; } - hw = dpu_hw_dspp_init(dspp->id, mmio, cat); + hw = dpu_hw_lm_init(lm->id, mmio, cat); if (IS_ERR_OR_NULL(hw)) { rc = PTR_ERR(hw); - DPU_ERROR("failed dspp object creation: err %d\n", rc); + DPU_ERROR("failed lm object creation: err %d\n", rc); goto fail; } - rm->dspp_blks[dspp->id - DSPP_0] = &hw->base; + rm->mixer_blks[lm->id - LM_0] = &hw->base; + + if (!rm->lm_max_width) { + rm->lm_max_width = lm->sblk->maxwidth; + } else if (rm->lm_max_width != lm->sblk->maxwidth) { + /* + * Don't expect to have hw where lm max widths differ. + * If found, take the min. + */ + DPU_ERROR("unsupported: lm maxwidth differs\n"); + if (rm->lm_max_width > lm->sblk->maxwidth) + rm->lm_max_width = lm->sblk->maxwidth; + } }

return 0; @@ -271,15 +253,13 @@ static bool _dpu_rm_check_lm_peer(struct dpu_rm *rm, int primary_idx, * available and appropriate * @pp_idx: output parameter, index of pingpong block attached to the layer * mixer in rm->pingpong_blks[]. - * @dspp_idx: output parameter, index of dspp block attached to the layer - * mixer in rm->dspp_blks[]. * @reqs: input parameter, rm requirements for HW blocks needed in the * datapath. * Return: true if lm matches all requirements, false otherwise */ static bool _dpu_rm_check_lm_and_get_connected_blks(struct dpu_rm *rm, struct dpu_global_state *global_state, - uint32_t enc_id, int lm_idx, int *pp_idx, int *dspp_idx, + uint32_t enc_id, int lm_idx, int *pp_idx, struct dpu_rm_requirements *reqs) { const struct dpu_lm_cfg *lm_cfg; @@ -305,22 +285,6 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(struct dpu_rm *rm, } *pp_idx = idx;

- if (!reqs->topology.num_dspp) - return true; - - idx = lm_cfg->dspp - DSPP_0; - if (idx < 0 || idx >= ARRAY_SIZE(rm->dspp_blks)) { - DPU_ERROR("failed to get dspp on lm %d\n", lm_cfg->dspp); - return false; - } - - if (reserved_by_other(global_state->dspp_to_enc_id, idx, enc_id)) { - DPU_DEBUG("lm %d dspp %d already reserved\n", lm_cfg->id, - lm_cfg->dspp); - return false; - } - *dspp_idx = idx; - return true; }

@@ -332,7 +296,6 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, { int lm_idx[MAX_BLOCKS]; int pp_idx[MAX_BLOCKS]; - int dspp_idx[MAX_BLOCKS] = {0}; int i, j, lm_count = 0;

if (!reqs->topology.num_lm) { @@ -351,7 +314,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,

if (!_dpu_rm_check_lm_and_get_connected_blks(rm, global_state, enc_id, i, &pp_idx[lm_count], - &dspp_idx[lm_count], reqs)) { + reqs)) { continue; }

@@ -371,7 +334,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,

if (!_dpu_rm_check_lm_and_get_connected_blks(rm, global_state, enc_id, j, - &pp_idx[lm_count], &dspp_idx[lm_count], + &pp_idx[lm_count], reqs)) { continue; } @@ -389,8 +352,6 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, for (i = 0; i < lm_count; i++) { global_state->mixer_to_enc_id[lm_idx[i]] = enc_id; global_state->pingpong_to_enc_id[pp_idx[i]] = enc_id; - global_state->dspp_to_enc_id[dspp_idx[i]] = - reqs->topology.num_dspp ? enc_id : 0;

trace_dpu_rm_reserve_lms(lm_idx[i] + LM_0, enc_id, pp_idx[i] + PINGPONG_0); @@ -635,11 +596,6 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm, hw_to_enc_id = global_state->intf_to_enc_id; max_blks = ARRAY_SIZE(rm->intf_blks); break; - case DPU_HW_BLK_DSPP: - hw_blks = rm->dspp_blks; - hw_to_enc_id = global_state->dspp_to_enc_id; - max_blks = ARRAY_SIZE(rm->dspp_blks); - break; default: DPU_ERROR("blk type %d not managed by rm\n", type); return 0; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h index 1f12c8d5b8aa..91952af6c75b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h @@ -19,7 +19,6 @@ struct dpu_global_state; * @mixer_blks: array of layer mixer hardware resources * @ctl_blks: array of ctl hardware resources * @intf_blks: array of intf hardware resources - * @dspp_blks: array of dspp hardware resources * @lm_max_width: cached layer mixer maximum width * @rm_lock: resource manager mutex */ @@ -28,7 +27,6 @@ struct dpu_rm { struct dpu_hw_blk *mixer_blks[LM_MAX - LM_0]; struct dpu_hw_blk *ctl_blks[CTL_MAX - CTL_0]; struct dpu_hw_blk *intf_blks[INTF_MAX - INTF_0]; - struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0]; struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];

uint32_t lm_max_width;

Each PINGPONG block is tied to a single LM. No LMs can share single PINGPONG block. So there is no need to handle PINGPONG blocks through all resource allocation/deallocation/assignment, just receive PINGPONG block as a part of LM hardware instance.

Signed-off-by: Dmitry Baryshkov dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 12 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 10 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 6 +- .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 99 ++----------------- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 2 - drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 9 +- 8 files changed, 26 insertions(+), 114 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index b3d50f6d976d..d98b4e4097fb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -974,10 +974,9 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, struct drm_crtc *drm_crtc; struct dpu_crtc_state *cstate; struct dpu_global_state *global_state; - struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC]; struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC]; struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; - int num_lm, num_ctl, num_pp; + int num_lm, num_ctl; int i, j;

if (!drm_enc) { @@ -1020,18 +1019,11 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, break;

/* Query resource that have been reserved in atomic check step. */ - num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_PINGPONG, hw_pp, - ARRAY_SIZE(hw_pp)); num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm));

- for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) - dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i]) - : NULL; - cstate = to_dpu_crtc_state(drm_crtc->state);

for (i = 0; i < num_lm; i++) { @@ -1040,6 +1032,8 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]); cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]); cstate->mixers[i].hw_dspp = cstate->mixers[i].hw_lm->dspp; + + dpu_enc->hw_pp[i] = cstate->mixers[i].hw_lm->pingpong; }

cstate->num_mixers = num_lm; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c index 35675744a6b7..fd09b9ab9b4b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c @@ -8,6 +8,7 @@ #include "dpu_hw_dspp.h" #include "dpu_hw_lm.h" #include "dpu_hw_mdss.h" +#include "dpu_hw_pingpong.h"

#define LM_OP_MODE 0x00 #define LM_OUT_SIZE 0x04 @@ -163,7 +164,8 @@ static void _setup_mixer_ops(const struct dpu_mdss_cfg *m,

struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx, void __iomem *addr, - const struct dpu_mdss_cfg *m) + const struct dpu_mdss_cfg *m, + struct dpu_hw_merge_3d **merge_3d_blks) { struct dpu_hw_mixer *c; const struct dpu_lm_cfg *cfg; @@ -185,6 +187,8 @@ struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx,

if (cfg->dspp && cfg->dspp < DSPP_MAX) c->dspp = dpu_hw_dspp_init(cfg->dspp, addr, m); + if (cfg->pingpong && cfg->pingpong < PINGPONG_MAX) + c->pingpong = dpu_hw_pingpong_init(cfg->pingpong, addr, m, merge_3d_blks);

dpu_hw_blk_init(&c->base, DPU_HW_BLK_LM, idx);

@@ -193,7 +197,9 @@ struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx,

void dpu_hw_lm_destroy(struct dpu_hw_mixer *lm) { - if (lm) + if (lm) { dpu_hw_dspp_destroy(lm->dspp); + dpu_hw_pingpong_destroy(lm->pingpong); + } kfree(lm); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h index effb78311a43..182740f2914b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h @@ -64,6 +64,7 @@ struct dpu_hw_mixer { const struct dpu_lm_cfg *cap; const struct dpu_mdp_cfg *mdp; const struct dpu_ctl_cfg *ctl; + struct dpu_hw_pingpong *pingpong; struct dpu_hw_dspp *dspp;

/* ops */ @@ -83,16 +84,19 @@ static inline struct dpu_hw_mixer *to_dpu_hw_mixer(struct dpu_hw_blk *hw) return container_of(hw, struct dpu_hw_mixer, base); }

+struct dpu_hw_merge_3d; /** * dpu_hw_lm_init(): Initializes the mixer hw driver object. * should be called once before accessing every mixer. * @idx: mixer index for which driver object is required * @addr: mapped register io address of MDP * @m : pointer to mdss catalog data + * @merge_3d_blks: Pointer to merge 3d blocks */ struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx, void __iomem *addr, - const struct dpu_mdss_cfg *m); + const struct dpu_mdss_cfg *m, + struct dpu_hw_merge_3d **merge_3d_blks);

/** * dpu_hw_lm_destroy(): Destroys layer mixer driver context diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h index a9e960b8814b..a3db536210bf 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h @@ -149,6 +149,7 @@ static inline struct dpu_hw_pingpong *to_dpu_hw_pingpong(struct dpu_hw_blk *hw) return container_of(hw, struct dpu_hw_pingpong, base); }

+struct dpu_rm; /** * dpu_hw_pingpong_init - initializes the pingpong driver for the passed * pingpong idx. diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index 057fdf0ca9f4..0b936258bde0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -161,7 +161,6 @@ struct vsync_info { struct dpu_global_state { struct drm_private_state base;

- uint32_t pingpong_to_enc_id[PINGPONG_MAX - PINGPONG_0]; uint32_t mixer_to_enc_id[LM_MAX - LM_0]; uint32_t ctl_to_enc_id[CTL_MAX - CTL_0]; uint32_t intf_to_enc_id[INTF_MAX - INTF_0]; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index 2ddf02eda2e5..7792dff60bcd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -7,7 +7,6 @@ #include "dpu_kms.h" #include "dpu_hw_lm.h" #include "dpu_hw_ctl.h" -#include "dpu_hw_pingpong.h" #include "dpu_hw_intf.h" #include "dpu_encoder.h" #include "dpu_trace.h" @@ -41,14 +40,6 @@ int dpu_rm_destroy(struct dpu_rm *rm) dpu_hw_lm_destroy(hw); } } - for (i = 0; i < ARRAY_SIZE(rm->pingpong_blks); i++) { - struct dpu_hw_pingpong *hw; - - if (rm->pingpong_blks[i]) { - hw = to_dpu_hw_pingpong(rm->pingpong_blks[i]); - dpu_hw_pingpong_destroy(hw); - } - } for (i = 0; i < ARRAY_SIZE(rm->ctl_blks); i++) { struct dpu_hw_ctl *hw;

@@ -85,24 +76,6 @@ int dpu_rm_init(struct dpu_rm *rm, memset(rm, 0, sizeof(*rm));

/* Interrogate HW catalog and create tracking items for hw blocks */ - for (i = 0; i < cat->pingpong_count; i++) { - struct dpu_hw_pingpong *hw; - const struct dpu_pingpong_cfg *pp = &cat->pingpong[i]; - - if (pp->id < PINGPONG_0 || pp->id >= PINGPONG_MAX) { - DPU_ERROR("skip pingpong %d with invalid id\n", pp->id); - continue; - } - hw = dpu_hw_pingpong_init(pp->id, mmio, cat, dpu_kms->hw_merge_3d); - if (IS_ERR_OR_NULL(hw)) { - rc = PTR_ERR(hw); - DPU_ERROR("failed pingpong object creation: err %d\n", - rc); - goto fail; - } - rm->pingpong_blks[pp->id - PINGPONG_0] = &hw->base; - } - for (i = 0; i < cat->intf_count; i++) { struct dpu_hw_intf *hw; const struct dpu_intf_cfg *intf = &cat->intf[i]; @@ -154,7 +127,7 @@ int dpu_rm_init(struct dpu_rm *rm, DPU_ERROR("skip mixer %d with invalid id\n", lm->id); continue; } - hw = dpu_hw_lm_init(lm->id, mmio, cat); + hw = dpu_hw_lm_init(lm->id, mmio, cat, dpu_kms->hw_merge_3d); if (IS_ERR_OR_NULL(hw)) { rc = PTR_ERR(hw); DPU_ERROR("failed lm object creation: err %d\n", rc); @@ -213,53 +186,6 @@ static bool _dpu_rm_check_lm_peer(struct dpu_rm *rm, int primary_idx, return true; }

-/** - * _dpu_rm_check_lm_and_get_connected_blks - check if proposed layer mixer meets - * proposed use case requirements, incl. hardwired dependent blocks like - * pingpong - * @rm: dpu resource manager handle - * @global_state: resources shared across multiple kms objects - * @enc_id: encoder id requesting for allocation - * @lm_idx: index of proposed layer mixer in rm->mixer_blks[], function checks - * if lm, and all other hardwired blocks connected to the lm (pp) is - * available and appropriate - * @pp_idx: output parameter, index of pingpong block attached to the layer - * mixer in rm->pingpong_blks[]. - * @reqs: input parameter, rm requirements for HW blocks needed in the - * datapath. - * Return: true if lm matches all requirements, false otherwise - */ -static bool _dpu_rm_check_lm_and_get_connected_blks(struct dpu_rm *rm, - struct dpu_global_state *global_state, - uint32_t enc_id, int lm_idx, int *pp_idx, - struct dpu_rm_requirements *reqs) -{ - const struct dpu_lm_cfg *lm_cfg; - int idx; - - /* Already reserved? */ - if (reserved_by_other(global_state->mixer_to_enc_id, lm_idx, enc_id)) { - DPU_DEBUG("lm %d already reserved\n", lm_idx + LM_0); - return false; - } - - lm_cfg = to_dpu_hw_mixer(rm->mixer_blks[lm_idx])->cap; - idx = lm_cfg->pingpong - PINGPONG_0; - if (idx < 0 || idx >= ARRAY_SIZE(rm->pingpong_blks)) { - DPU_ERROR("failed to get pp on lm %d\n", lm_cfg->pingpong); - return false; - } - - if (reserved_by_other(global_state->pingpong_to_enc_id, idx, enc_id)) { - DPU_DEBUG("lm %d pp %d already reserved\n", lm_cfg->id, - lm_cfg->pingpong); - return false; - } - *pp_idx = idx; - - return true; -} - static int _dpu_rm_reserve_lms(struct dpu_rm *rm, struct dpu_global_state *global_state, uint32_t enc_id, @@ -267,7 +193,6 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,

{ int lm_idx[MAX_BLOCKS]; - int pp_idx[MAX_BLOCKS]; int i, j, lm_count = 0;

if (!reqs->topology.num_lm) { @@ -284,9 +209,8 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, lm_count = 0; lm_idx[lm_count] = i;

- if (!_dpu_rm_check_lm_and_get_connected_blks(rm, global_state, - enc_id, i, &pp_idx[lm_count], - reqs)) { + if (reserved_by_other(global_state->mixer_to_enc_id, i, enc_id)) { + DPU_DEBUG("lm %d already reserved\n", i + LM_0); continue; }

@@ -304,10 +228,8 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, continue; }

- if (!_dpu_rm_check_lm_and_get_connected_blks(rm, - global_state, enc_id, j, - &pp_idx[lm_count], - reqs)) { + if (reserved_by_other(global_state->mixer_to_enc_id, j, enc_id)) { + DPU_DEBUG("lm %d already reserved\n", j + LM_0); continue; }

@@ -323,10 +245,8 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,

for (i = 0; i < lm_count; i++) { global_state->mixer_to_enc_id[lm_idx[i]] = enc_id; - global_state->pingpong_to_enc_id[pp_idx[i]] = enc_id;

- trace_dpu_rm_reserve_lms(lm_idx[i] + LM_0, enc_id, - pp_idx[i] + PINGPONG_0); + trace_dpu_rm_reserve_lms(lm_idx[i] + LM_0, enc_id); }

return 0; @@ -492,8 +412,6 @@ static void _dpu_rm_clear_mapping(uint32_t *res_mapping, int cnt, void dpu_rm_release(struct dpu_global_state *global_state, struct drm_encoder *enc) { - _dpu_rm_clear_mapping(global_state->pingpong_to_enc_id, - ARRAY_SIZE(global_state->pingpong_to_enc_id), enc->base.id); _dpu_rm_clear_mapping(global_state->mixer_to_enc_id, ARRAY_SIZE(global_state->mixer_to_enc_id), enc->base.id); _dpu_rm_clear_mapping(global_state->ctl_to_enc_id, @@ -548,11 +466,6 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm, int i, num_blks, max_blks;

switch (type) { - case DPU_HW_BLK_PINGPONG: - hw_blks = rm->pingpong_blks; - hw_to_enc_id = global_state->pingpong_to_enc_id; - max_blks = ARRAY_SIZE(rm->pingpong_blks); - break; case DPU_HW_BLK_LM: hw_blks = rm->mixer_blks; hw_to_enc_id = global_state->mixer_to_enc_id; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h index 4c0c15453c98..a618c0ef43db 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h @@ -15,7 +15,6 @@ struct dpu_global_state;

/** * struct dpu_rm - DPU dynamic hardware resource manager - * @pingpong_blks: array of pingpong hardware resources * @mixer_blks: array of layer mixer hardware resources * @ctl_blks: array of ctl hardware resources * @intf_blks: array of intf hardware resources @@ -23,7 +22,6 @@ struct dpu_global_state; * @rm_lock: resource manager mutex */ struct dpu_rm { - struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0]; struct dpu_hw_blk *mixer_blks[LM_MAX - LM_0]; struct dpu_hw_blk *ctl_blks[CTL_MAX - CTL_0]; struct dpu_hw_blk *intf_blks[INTF_MAX - INTF_0]; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h index 6714b088970f..23b587b10d77 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h @@ -835,20 +835,17 @@ DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_ctls, );

TRACE_EVENT(dpu_rm_reserve_lms, - TP_PROTO(uint32_t id, uint32_t enc_id, uint32_t pp_id), - TP_ARGS(id, enc_id, pp_id), + TP_PROTO(uint32_t id, uint32_t enc_id), + TP_ARGS(id, enc_id), TP_STRUCT__entry( __field( uint32_t, id ) __field( uint32_t, enc_id ) - __field( uint32_t, pp_id ) ), TP_fast_assign( __entry->id = id; __entry->enc_id = enc_id; - __entry->pp_id = pp_id; ), - TP_printk("id:%d enc_id:%u pp_id:%u", __entry->id, - __entry->enc_id, __entry->pp_id) + TP_printk("id:%d enc_id:%u", __entry->id, __entry->enc_id) );

TRACE_EVENT(dpu_vbif_wait_xin_halt_fail,

For each LM there is at max 1 peer LM which can be driven by the same CTL, so there no need to have a mask instead of just an ID of the peer LM.

Signed-off-by: Dmitry Baryshkov dmitry.baryshkov@linaro.org --- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 30 +++++-------------- 3 files changed, 11 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index e4444452759c..f21f630af476 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -497,7 +497,7 @@ static const struct dpu_lm_sub_blks sdm845_lm_sblk = { .features = _fmask, \ .sblk = _sblk, \ .pingpong = _pp, \ - .lm_pair_mask = (1 << _lmpair), \ + .lm_pair = _lmpair, \ .dspp = _dspp \ }

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index ea4647d21a20..08864f0addc4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -494,14 +494,14 @@ struct dpu_sspp_cfg { * @features bit mask identifying sub-blocks/features * @sblk: LM Sub-blocks information * @pingpong: ID of connected PingPong, PINGPONG_MAX if unsupported - * @lm_pair_mask: Bitmask of LMs that can be controlled by same CTL + * @lm_pair: ID of LM that can be controlled by same CTL */ struct dpu_lm_cfg { DPU_HW_BLK_INFO; const struct dpu_lm_sub_blks *sblk; u32 pingpong; u32 dspp; - unsigned long lm_pair_mask; + unsigned long lm_pair; };

/** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index dbcf4929810b..969286c6f104 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -150,28 +150,19 @@ static bool _dpu_rm_needs_split_display(const struct msm_display_topology *top) }

/** - * _dpu_rm_check_lm_peer - check if a mixer is a peer of the primary + * _dpu_rm_get_lm_peer - get the id of a mixer which is a peer of the primary * @rm: dpu resource manager handle * @primary_idx: index of primary mixer in rm->mixer_blks[] - * @peer_idx: index of other mixer in rm->mixer_blks[] - * Return: true if rm->mixer_blks[peer_idx] is a peer of - * rm->mixer_blks[primary_idx] */ -static bool _dpu_rm_check_lm_peer(struct dpu_rm *rm, int primary_idx, - int peer_idx) +static int _dpu_rm_get_lm_peer(struct dpu_rm *rm, int primary_idx) { const struct dpu_lm_cfg *prim_lm_cfg; - const struct dpu_lm_cfg *peer_cfg;

prim_lm_cfg = to_dpu_hw_mixer(rm->mixer_blks[primary_idx])->cap; - peer_cfg = to_dpu_hw_mixer(rm->mixer_blks[peer_idx])->cap;

- if (!test_bit(peer_cfg->id, &prim_lm_cfg->lm_pair_mask)) { - DPU_DEBUG("lm %d not peer of lm %d\n", peer_cfg->id, - peer_cfg->id); - return false; - } - return true; + if (prim_lm_cfg->lm_pair >= LM_0 && prim_lm_cfg->lm_pair < LM_MAX) + return prim_lm_cfg->lm_pair - LM_0; + return -EINVAL; }

static int _dpu_rm_reserve_lms(struct dpu_rm *rm, @@ -205,17 +196,12 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, ++lm_count;

/* Valid primary mixer found, find matching peers */ - for (j = i + 1; j < ARRAY_SIZE(rm->mixer_blks) && - lm_count < reqs->topology.num_lm; j++) { + j = _dpu_rm_get_lm_peer(rm, i); + /* ignore the peer if there is an error or if the peer was already processed */ + if (j > i) { if (!rm->mixer_blks[j]) continue;

- if (!_dpu_rm_check_lm_peer(rm, i, j)) { - DPU_DEBUG("lm %d not peer of lm %d\n", LM_0 + j, - LM_0 + i); - continue; - } - if (reserved_by_other(global_state->mixer_to_enc_id, j, enc_id)) { DPU_DEBUG("lm %d already reserved\n", j + LM_0); continue;

DPU1 driver supports only hardware with the version of 4.0 and higher (>= sdm845), so drop the dpu_hw_lm_setup_blend_config() used by previous hardware generations.

Signed-off-by: Dmitry Baryshkov dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 26 +---------------------- 1 file changed, 1 insertion(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c index fd09b9ab9b4b..7d5b620f7f42 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c @@ -23,9 +23,6 @@ #define LM_FG_COLOR_FILL_SIZE 0x10 #define LM_FG_COLOR_FILL_XY 0x14

-#define LM_BLEND0_FG_ALPHA 0x04 -#define LM_BLEND0_BG_ALPHA 0x08 - static const struct dpu_lm_cfg *_lm_offset(enum dpu_lm mixer, const struct dpu_mdss_cfg *m, void __iomem *addr, @@ -117,24 +114,6 @@ static void dpu_hw_lm_setup_blend_config_sdm845(struct dpu_hw_mixer *ctx, DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); }

-static void dpu_hw_lm_setup_blend_config(struct dpu_hw_mixer *ctx, - u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op) -{ - struct dpu_hw_blk_reg_map *c = &ctx->hw; - int stage_off; - - if (stage == DPU_STAGE_BASE) - return; - - stage_off = _stage_offset(ctx, stage); - if (WARN_ON(stage_off < 0)) - return; - - DPU_REG_WRITE(c, LM_BLEND0_FG_ALPHA + stage_off, fg_alpha); - DPU_REG_WRITE(c, LM_BLEND0_BG_ALPHA + stage_off, bg_alpha); - DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); -} - static void dpu_hw_lm_setup_color3(struct dpu_hw_mixer *ctx, uint32_t mixer_op_mode) { @@ -154,10 +133,7 @@ static void _setup_mixer_ops(const struct dpu_mdss_cfg *m, unsigned long features) { ops->setup_mixer_out = dpu_hw_lm_setup_out; - if (m->hwversion >= DPU_HW_VER_400) - ops->setup_blend_config = dpu_hw_lm_setup_blend_config_sdm845; - else - ops->setup_blend_config = dpu_hw_lm_setup_blend_config; + ops->setup_blend_config = dpu_hw_lm_setup_blend_config_sdm845; ops->setup_alpha_out = dpu_hw_lm_setup_color3; ops->setup_border_color = dpu_hw_lm_setup_border_color; }

Replace dpu_hw_dspp callbacks with direct functions calls.

Signed-off-by: Dmitry Baryshkov dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 6 +++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c | 15 ++++++--------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h | 19 ++++++------------- 3 files changed, 15 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 5a0a6741a431..bf3048e44001 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -462,14 +462,14 @@ static void _dpu_crtc_setup_cp_blocks(struct drm_crtc *crtc) ctl = mixer[i].lm_ctl; dspp = mixer[i].hw_dspp;

- if (!dspp || !dspp->ops.setup_pcc) + if (!dspp) continue;

if (!state->ctm) { - dspp->ops.setup_pcc(dspp, NULL); + dpu_hw_dspp_setup_pcc(dspp, NULL); } else { _dpu_crtc_get_pcc_coeff(state, &cfg); - dspp->ops.setup_pcc(dspp, &cfg); + dpu_hw_dspp_setup_pcc(dspp, &cfg); }

mixer[i].flush_mask |= ctl->ops.get_bitmask_dspp(ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c index 977b25968f34..c17f2bf3324f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c @@ -22,7 +22,7 @@ #define PCC_BLUE_G_OFF 0x24 #define PCC_BLUE_B_OFF 0x30

-static void dpu_setup_dspp_pcc(struct dpu_hw_dspp *ctx, +void dpu_hw_dspp_setup_pcc(struct dpu_hw_dspp *ctx, struct dpu_hw_pcc_cfg *cfg) {

@@ -33,6 +33,11 @@ static void dpu_setup_dspp_pcc(struct dpu_hw_dspp *ctx, return; }

+ if (!test_bit(DPU_DSPP_PCC, &ctx->cap->features)) { + DRM_ERROR("called for wrong DSPP block\n"); + return; + } + if (!cfg) { DRM_DEBUG_DRIVER("disable pcc feature\n"); DPU_REG_WRITE(&ctx->hw, base, PCC_DIS); @@ -54,13 +59,6 @@ static void dpu_setup_dspp_pcc(struct dpu_hw_dspp *ctx, DPU_REG_WRITE(&ctx->hw, base, PCC_EN); }

-static void _setup_dspp_ops(struct dpu_hw_dspp *c, - unsigned long features) -{ - if (test_bit(DPU_DSPP_PCC, &features)) - c->ops.setup_pcc = dpu_setup_dspp_pcc; -} - static const struct dpu_dspp_cfg *_dspp_offset(enum dpu_dspp dspp, const struct dpu_mdss_cfg *m, void __iomem *addr, @@ -108,7 +106,6 @@ struct dpu_hw_dspp *dpu_hw_dspp_init(enum dpu_dspp idx, /* Assign ops */ c->idx = idx; c->cap = cfg; - _setup_dspp_ops(c, c->cap->features);

dpu_hw_blk_init(&c->base, DPU_HW_BLK_DSPP, idx);

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h index 7fa189cfcb06..e712e3e4c67b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h @@ -36,19 +36,15 @@ struct dpu_hw_pcc_cfg { };

/** - * struct dpu_hw_dspp_ops - interface to the dspp hardware driver functions * Caller must call the init function to get the dspp context for each dspp * Assumption is these functions will be called after clocks are enabled */ -struct dpu_hw_dspp_ops { - /** - * setup_pcc - setup dspp pcc - * @ctx: Pointer to dspp context - * @cfg: Pointer to configuration - */ - void (*setup_pcc)(struct dpu_hw_dspp *ctx, struct dpu_hw_pcc_cfg *cfg); - -}; +/** + * setup_pcc - setup dspp pcc + * @ctx: Pointer to dspp context + * @cfg: Pointer to configuration + */ +void dpu_hw_dspp_setup_pcc(struct dpu_hw_dspp *ctx, struct dpu_hw_pcc_cfg *cfg);

/** * struct dpu_hw_dspp - dspp description @@ -65,9 +61,6 @@ struct dpu_hw_dspp { /* dspp */ int idx; const struct dpu_dspp_cfg *cap; - - /* Ops */ - struct dpu_hw_dspp_ops ops; };

/**

Replace dpu_hw_pingpong callbacks with direct functions calls.

Signed-off-by: Dmitry Baryshkov dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 +- .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 31 ++--- .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 36 ++---- .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 111 ++++++++---------- 4 files changed, 70 insertions(+), 112 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index ac03f329491d..72a3cd08295e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -226,14 +226,14 @@ static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong *hw_pp, unsigned bp dither_cfg.temporal_en = 0; break; default: - hw_pp->ops.setup_dither(hw_pp, NULL); + dpu_hw_pingpong_setup_dither(hw_pp, NULL); return; }

memcpy(&dither_cfg.matrix, dither_matrix, sizeof(u32) * DITHER_MATRIX_SZ);

- hw_pp->ops.setup_dither(hw_pp, &dither_cfg); + dpu_hw_pingpong_setup_dither(hw_pp, &dither_cfg); }

void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index adbd59326b99..0525db90f2c6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -345,12 +345,6 @@ static void dpu_encoder_phys_cmd_tearcheck_config(

DPU_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0);

- if (!phys_enc->hw_pp->ops.setup_tearcheck || - !phys_enc->hw_pp->ops.enable_tearcheck) { - DPU_DEBUG_CMDENC(cmd_enc, "tearcheck not supported\n"); - return; - } - dpu_kms = phys_enc->dpu_kms;

/* @@ -401,8 +395,8 @@ static void dpu_encoder_phys_cmd_tearcheck_config( phys_enc->hw_pp->idx - PINGPONG_0, tc_cfg.sync_cfg_height, tc_cfg.sync_threshold_start, tc_cfg.sync_threshold_continue);

- phys_enc->hw_pp->ops.setup_tearcheck(phys_enc->hw_pp, &tc_cfg); - phys_enc->hw_pp->ops.enable_tearcheck(phys_enc->hw_pp, tc_enable); + dpu_hw_pingpong_setup_tearcheck(phys_enc->hw_pp, &tc_cfg); + dpu_hw_pingpong_enable_tearcheck(phys_enc->hw_pp, tc_enable); }

static void _dpu_encoder_phys_cmd_pingpong_config( @@ -479,11 +473,11 @@ static void dpu_encoder_phys_cmd_enable(struct dpu_encoder_phys *phys_enc) static void _dpu_encoder_phys_cmd_connect_te( struct dpu_encoder_phys *phys_enc, bool enable) { - if (!phys_enc->hw_pp || !phys_enc->hw_pp->ops.connect_external_te) + if (!phys_enc->hw_pp) return;

trace_dpu_enc_phys_cmd_connect_te(DRMID(phys_enc->parent), enable); - phys_enc->hw_pp->ops.connect_external_te(phys_enc->hw_pp, enable); + dpu_hw_pingpong_connect_external_te(phys_enc->hw_pp, enable); }

static void dpu_encoder_phys_cmd_prepare_idle_pc( @@ -495,19 +489,13 @@ static void dpu_encoder_phys_cmd_prepare_idle_pc( static int dpu_encoder_phys_cmd_get_line_count( struct dpu_encoder_phys *phys_enc) { - struct dpu_hw_pingpong *hw_pp; - if (!phys_enc->hw_pp) return -EINVAL;

if (!dpu_encoder_phys_cmd_is_master(phys_enc)) return -EINVAL;

- hw_pp = phys_enc->hw_pp; - if (!hw_pp->ops.get_line_count) - return -EINVAL; - - return hw_pp->ops.get_line_count(hw_pp); + return dpu_hw_pingpong_get_line_count(phys_enc->hw_pp); }

static void dpu_encoder_phys_cmd_disable(struct dpu_encoder_phys *phys_enc) @@ -528,8 +516,7 @@ static void dpu_encoder_phys_cmd_disable(struct dpu_encoder_phys *phys_enc) return; }

- if (phys_enc->hw_pp->ops.enable_tearcheck) - phys_enc->hw_pp->ops.enable_tearcheck(phys_enc->hw_pp, false); + dpu_hw_pingpong_enable_tearcheck(phys_enc->hw_pp, false); phys_enc->enable_state = DPU_ENC_DISABLED; }

@@ -582,7 +569,7 @@ static bool dpu_encoder_phys_cmd_is_ongoing_pptx( if (!phys_enc) return false;

- phys_enc->hw_pp->ops.get_vsync_info(phys_enc->hw_pp, &info); + dpu_hw_pingpong_get_vsync_info(phys_enc->hw_pp, &info); if (info.wr_ptr_line_count > 0 && info.wr_ptr_line_count < phys_enc->cached_mode.vdisplay) return true; @@ -605,7 +592,7 @@ static void dpu_encoder_phys_cmd_prepare_commit( return;

/* If autorefresh is already disabled, we have nothing to do */ - if (!phys_enc->hw_pp->ops.get_autorefresh(phys_enc->hw_pp, NULL)) + if (!dpu_hw_pingpong_get_autorefresh(phys_enc->hw_pp, NULL)) return;

/* @@ -617,7 +604,7 @@ static void dpu_encoder_phys_cmd_prepare_commit( * 5. Enable TE back */ _dpu_encoder_phys_cmd_connect_te(phys_enc, false); - phys_enc->hw_pp->ops.setup_autorefresh(phys_enc->hw_pp, 0, false); + dpu_hw_pingpong_setup_autorefresh(phys_enc->hw_pp, 0, false);

do { udelay(DPU_ENC_MAX_POLL_TIMEOUT_US); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c index 5c1ce835cf49..9c78dd06188b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c @@ -61,7 +61,7 @@ static const struct dpu_pingpong_cfg *_pingpong_offset(enum dpu_pingpong pp, return ERR_PTR(-EINVAL); }

-static void dpu_hw_pp_setup_dither(struct dpu_hw_pingpong *pp, +void dpu_hw_pingpong_setup_dither(struct dpu_hw_pingpong *pp, struct dpu_hw_dither_cfg *cfg) { struct dpu_hw_blk_reg_map *c; @@ -92,7 +92,7 @@ static void dpu_hw_pp_setup_dither(struct dpu_hw_pingpong *pp, DPU_REG_WRITE(c, base + PP_DITHER_EN, 1); }

-static int dpu_hw_pp_setup_te_config(struct dpu_hw_pingpong *pp, +int dpu_hw_pingpong_setup_tearcheck(struct dpu_hw_pingpong *pp, struct dpu_hw_tear_check *te) { struct dpu_hw_blk_reg_map *c; @@ -122,7 +122,7 @@ static int dpu_hw_pp_setup_te_config(struct dpu_hw_pingpong *pp, return 0; }

-static void dpu_hw_pp_setup_autorefresh_config(struct dpu_hw_pingpong *pp, +void dpu_hw_pingpong_setup_autorefresh(struct dpu_hw_pingpong *pp, u32 frame_count, bool enable) { DPU_REG_WRITE(&pp->hw, PP_AUTOREFRESH_CONFIG, @@ -130,13 +130,13 @@ static void dpu_hw_pp_setup_autorefresh_config(struct dpu_hw_pingpong *pp, }

/* - * dpu_hw_pp_get_autorefresh_config - Get autorefresh config from HW + * dpu_hw_pingpong_get_autorefresh - Get autorefresh config from HW * @pp: DPU pingpong structure * @frame_count: Used to return the current frame count from hw * * Returns: True if autorefresh enabled, false if disabled. */ -static bool dpu_hw_pp_get_autorefresh_config(struct dpu_hw_pingpong *pp, +bool dpu_hw_pingpong_get_autorefresh(struct dpu_hw_pingpong *pp, u32 *frame_count) { u32 val = DPU_REG_READ(&pp->hw, PP_AUTOREFRESH_CONFIG); @@ -145,7 +145,7 @@ static bool dpu_hw_pp_get_autorefresh_config(struct dpu_hw_pingpong *pp, return !!((val & BIT(31)) >> 31); }

-static int dpu_hw_pp_poll_timeout_wr_ptr(struct dpu_hw_pingpong *pp, +int dpu_hw_pingpong_poll_timeout_wr_ptr(struct dpu_hw_pingpong *pp, u32 timeout_us) { struct dpu_hw_blk_reg_map *c; @@ -162,7 +162,7 @@ static int dpu_hw_pp_poll_timeout_wr_ptr(struct dpu_hw_pingpong *pp, return rc; }

-static int dpu_hw_pp_enable_te(struct dpu_hw_pingpong *pp, bool enable) +int dpu_hw_pingpong_enable_tearcheck(struct dpu_hw_pingpong *pp, bool enable) { struct dpu_hw_blk_reg_map *c;

@@ -174,7 +174,7 @@ static int dpu_hw_pp_enable_te(struct dpu_hw_pingpong *pp, bool enable) return 0; }

-static int dpu_hw_pp_connect_external_te(struct dpu_hw_pingpong *pp, +int dpu_hw_pingpong_connect_external_te(struct dpu_hw_pingpong *pp, bool enable_external_te) { struct dpu_hw_blk_reg_map *c = &pp->hw; @@ -197,7 +197,7 @@ static int dpu_hw_pp_connect_external_te(struct dpu_hw_pingpong *pp, return orig; }

-static int dpu_hw_pp_get_vsync_info(struct dpu_hw_pingpong *pp, +int dpu_hw_pingpong_get_vsync_info(struct dpu_hw_pingpong *pp, struct dpu_hw_pp_vsync_info *info) { struct dpu_hw_blk_reg_map *c; @@ -220,7 +220,7 @@ static int dpu_hw_pp_get_vsync_info(struct dpu_hw_pingpong *pp, return 0; }

-static u32 dpu_hw_pp_get_line_count(struct dpu_hw_pingpong *pp) +u32 dpu_hw_pingpong_get_line_count(struct dpu_hw_pingpong *pp) { struct dpu_hw_blk_reg_map *c = &pp->hw; u32 height, init; @@ -246,21 +246,6 @@ static u32 dpu_hw_pp_get_line_count(struct dpu_hw_pingpong *pp) return line; }

-static void _setup_pingpong_ops(struct dpu_hw_pingpong *c, - unsigned long features) -{ - c->ops.setup_tearcheck = dpu_hw_pp_setup_te_config; - c->ops.enable_tearcheck = dpu_hw_pp_enable_te; - c->ops.connect_external_te = dpu_hw_pp_connect_external_te; - c->ops.get_vsync_info = dpu_hw_pp_get_vsync_info; - c->ops.setup_autorefresh = dpu_hw_pp_setup_autorefresh_config; - c->ops.get_autorefresh = dpu_hw_pp_get_autorefresh_config; - c->ops.poll_timeout_wr_ptr = dpu_hw_pp_poll_timeout_wr_ptr; - c->ops.get_line_count = dpu_hw_pp_get_line_count; - - c->ops.setup_dither = dpu_hw_pp_setup_dither; -}; - struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx, void __iomem *addr, const struct dpu_mdss_cfg *m, @@ -281,7 +266,6 @@ struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx,

c->idx = idx; c->caps = cfg; - _setup_pingpong_ops(c, c->caps->features);

if (cfg->merge_3d && cfg->merge_3d < MERGE_3D_MAX) c->merge_3d = merge_3d_blks[cfg->merge_3d - MERGE_3D_0]; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h index a3db536210bf..78d2fed4c6a3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h @@ -56,75 +56,65 @@ struct dpu_hw_dither_cfg { u32 matrix[DITHER_MATRIX_SZ]; };

-/** - * - * struct dpu_hw_pingpong_ops : Interface to the pingpong Hw driver functions +/* * Assumption is these functions will be called after clocks are enabled - * @setup_tearcheck : program tear check values - * @enable_tearcheck : enables tear check - * @get_vsync_info : retries timing info of the panel - * @setup_autorefresh : configure and enable the autorefresh config - * @get_autorefresh : retrieve autorefresh config from hardware - * @setup_dither : function to program the dither hw block - * @get_line_count: obtain current vertical line counter */ -struct dpu_hw_pingpong_ops { - /** - * enables vysnc generation and sets up init value of - * read pointer and programs the tear check cofiguration - */ - int (*setup_tearcheck)(struct dpu_hw_pingpong *pp, - struct dpu_hw_tear_check *cfg);

- /** - * enables tear check block - */ - int (*enable_tearcheck)(struct dpu_hw_pingpong *pp, - bool enable); +/** + * enables vysnc generation and sets up init value of + * read pointer and programs the tear check cofiguration + */ +int dpu_hw_pingpong_setup_tearcheck(struct dpu_hw_pingpong *pp, + struct dpu_hw_tear_check *cfg);

- /** - * read, modify, write to either set or clear listening to external TE - * @Return: 1 if TE was originally connected, 0 if not, or -ERROR - */ - int (*connect_external_te)(struct dpu_hw_pingpong *pp, - bool enable_external_te); +/** + * enables tear check block + */ +int dpu_hw_pingpong_enable_tearcheck(struct dpu_hw_pingpong *pp, + bool enable);

- /** - * provides the programmed and current - * line_count - */ - int (*get_vsync_info)(struct dpu_hw_pingpong *pp, - struct dpu_hw_pp_vsync_info *info); +/** + * read, modify, write to either set or clear listening to external TE + * @Return: 1 if TE was originally connected, 0 if not, or -ERROR + */ +int dpu_hw_pingpong_connect_external_te(struct dpu_hw_pingpong *pp, + bool enable_external_te);

- /** - * configure and enable the autorefresh config - */ - void (*setup_autorefresh)(struct dpu_hw_pingpong *pp, - u32 frame_count, bool enable); +/** + * provides the programmed and current + * line_count + */ +int dpu_hw_pingpong_get_vsync_info(struct dpu_hw_pingpong *pp, + struct dpu_hw_pp_vsync_info *info);

- /** - * retrieve autorefresh config from hardware - */ - bool (*get_autorefresh)(struct dpu_hw_pingpong *pp, - u32 *frame_count); +/** + * configure and enable the autorefresh config + */ +void dpu_hw_pingpong_setup_autorefresh(struct dpu_hw_pingpong *pp, + u32 frame_count, bool enable);

- /** - * poll until write pointer transmission starts - * @Return: 0 on success, -ETIMEDOUT on timeout - */ - int (*poll_timeout_wr_ptr)(struct dpu_hw_pingpong *pp, u32 timeout_us); +/** + * retrieve autorefresh config from hardware + */ +bool dpu_hw_pingpong_get_autorefresh(struct dpu_hw_pingpong *pp, + u32 *frame_count);

- /** - * Obtain current vertical line counter - */ - u32 (*get_line_count)(struct dpu_hw_pingpong *pp); +/** + * poll until write pointer transmission starts + * @Return: 0 on success, -ETIMEDOUT on timeout + */ +int dpu_hw_pingpong_poll_timeout_wr_ptr(struct dpu_hw_pingpong *pp, u32 timeout_us);

- /** - * Setup dither matix for pingpong block - */ - void (*setup_dither)(struct dpu_hw_pingpong *pp, - struct dpu_hw_dither_cfg *cfg); -}; +/** + * Obtain current vertical line counter + */ +u32 dpu_hw_pingpong_get_line_count(struct dpu_hw_pingpong *pp); + +/** + * Setup dither matix for pingpong block + */ +void dpu_hw_pingpong_setup_dither(struct dpu_hw_pingpong *pp, + struct dpu_hw_dither_cfg *cfg);

struct dpu_hw_pingpong { struct dpu_hw_blk base; @@ -134,9 +124,6 @@ struct dpu_hw_pingpong { enum dpu_pingpong idx; const struct dpu_pingpong_cfg *caps; struct dpu_hw_merge_3d *merge_3d; - - /* ops */ - struct dpu_hw_pingpong_ops ops; };

/**

Replace dpu_hw_intf callbacks with direct functions calls.

Signed-off-by: Dmitry Baryshkov dmitry.baryshkov@linaro.org --- .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 28 +++-------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 28 ++++------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 49 +++++++++---------- 3 files changed, 38 insertions(+), 67 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 868bb2f06125..e7a30246eb00 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -202,9 +202,6 @@ static void programmable_fetch_config(struct dpu_encoder_phys *phys_enc, u32 vfp_fetch_start_vsync_counter = 0; unsigned long lock_flags;

- if (WARN_ON_ONCE(!phys_enc->hw_intf->ops.setup_prg_fetch)) - return; - vfp_fetch_lines = programmable_fetch_get_num_lines(phys_enc, timing); if (vfp_fetch_lines) { vert_total = get_vertical_total(timing); @@ -220,7 +217,7 @@ static void programmable_fetch_config(struct dpu_encoder_phys *phys_enc, vfp_fetch_lines, vfp_fetch_start_vsync_counter);

spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); - phys_enc->hw_intf->ops.setup_prg_fetch(phys_enc->hw_intf, &f); + dpu_hw_intf_setup_prg_fetch(phys_enc->hw_intf, &f); spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); }

@@ -253,10 +250,6 @@ static void dpu_encoder_phys_vid_setup_timing_engine( }

mode = phys_enc->cached_mode; - if (!phys_enc->hw_intf->ops.setup_timing_gen) { - DPU_ERROR("timing engine setup is not supported\n"); - return; - }

DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n"); drm_mode_debug_printmodeline(&mode); @@ -287,13 +280,12 @@ static void dpu_encoder_phys_vid_setup_timing_engine( intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx;

spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); - phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf, + dpu_hw_intf_setup_timing_engine(phys_enc->hw_intf, &timing_params, fmt); phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);

/* setup which pp blk will connect to this intf */ - if (phys_enc->hw_intf->ops.bind_pingpong_blk) - phys_enc->hw_intf->ops.bind_pingpong_blk( + dpu_hw_intf_bind_pingpong_blk( phys_enc->hw_intf, true, phys_enc->hw_pp->idx); @@ -440,9 +432,6 @@ static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)

DPU_DEBUG_VIDENC(phys_enc, "\n");

- if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing)) - return; - dpu_encoder_helper_split_config(phys_enc, phys_enc->hw_intf->idx);

dpu_encoder_phys_vid_setup_timing_engine(phys_enc); @@ -560,16 +549,13 @@ static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc) return; }

- if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing)) - return; - if (phys_enc->enable_state == DPU_ENC_DISABLED) { DPU_ERROR("already disabled\n"); return; }

spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); - phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 0); + dpu_hw_intf_enable_timing_engine(phys_enc->hw_intf, 0); if (dpu_encoder_phys_vid_is_master(phys_enc)) dpu_encoder_phys_inc_pending(phys_enc); spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); @@ -608,7 +594,7 @@ static void dpu_encoder_phys_vid_handle_post_kickoff( trace_dpu_enc_phys_vid_post_kickoff(DRMID(phys_enc->parent), phys_enc->hw_intf->idx - INTF_0); spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); - phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 1); + dpu_hw_intf_enable_timing_engine(phys_enc->hw_intf, 1); spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); phys_enc->enable_state = DPU_ENC_ENABLED; } @@ -642,10 +628,10 @@ static int dpu_encoder_phys_vid_get_line_count( if (!dpu_encoder_phys_vid_is_master(phys_enc)) return -EINVAL;

- if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_line_count) + if (!phys_enc->hw_intf) return -EINVAL;

- return phys_enc->hw_intf->ops.get_line_count(phys_enc->hw_intf); + return dpu_hw_intf_get_line_count(phys_enc->hw_intf); }

static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 8df75936d906..3988700dcc85 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -80,7 +80,7 @@ static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf, return ERR_PTR(-EINVAL); }

-static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, +void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, const struct intf_timing_params *p, const struct dpu_format *fmt) { @@ -197,7 +197,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format); }

-static void dpu_hw_intf_enable_timing_engine( +void dpu_hw_intf_enable_timing_engine( struct dpu_hw_intf *intf, u8 enable) { @@ -206,7 +206,7 @@ static void dpu_hw_intf_enable_timing_engine( DPU_REG_WRITE(c, INTF_TIMING_ENGINE_EN, enable != 0); }

-static void dpu_hw_intf_setup_prg_fetch( +void dpu_hw_intf_setup_prg_fetch( struct dpu_hw_intf *intf, const struct intf_prog_fetch *fetch) { @@ -230,7 +230,7 @@ static void dpu_hw_intf_setup_prg_fetch( DPU_REG_WRITE(c, INTF_CONFIG, fetch_enable); }

-static void dpu_hw_intf_bind_pingpong_blk( +void dpu_hw_intf_bind_pingpong_blk( struct dpu_hw_intf *intf, bool enable, const enum dpu_pingpong pp) @@ -238,6 +238,9 @@ static void dpu_hw_intf_bind_pingpong_blk( struct dpu_hw_blk_reg_map *c = &intf->hw; u32 mux_cfg;

+ if (!test_bit(DPU_INTF_INPUT_CTRL, &intf->cap->features)) + return; + mux_cfg = DPU_REG_READ(c, INTF_MUX); mux_cfg &= ~0xf;

@@ -249,7 +252,7 @@ static void dpu_hw_intf_bind_pingpong_blk( DPU_REG_WRITE(c, INTF_MUX, mux_cfg); }

-static void dpu_hw_intf_get_status( +void dpu_hw_intf_get_status( struct dpu_hw_intf *intf, struct intf_status *s) { @@ -265,7 +268,7 @@ static void dpu_hw_intf_get_status( } }

-static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf) +u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf) { struct dpu_hw_blk_reg_map *c;

@@ -277,18 +280,6 @@ static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf) return DPU_REG_READ(c, INTF_LINE_COUNT); }

-static void _setup_intf_ops(struct dpu_hw_intf_ops *ops, - unsigned long cap) -{ - ops->setup_timing_gen = dpu_hw_intf_setup_timing_engine; - ops->setup_prg_fetch = dpu_hw_intf_setup_prg_fetch; - ops->get_status = dpu_hw_intf_get_status; - ops->enable_timing = dpu_hw_intf_enable_timing_engine; - ops->get_line_count = dpu_hw_intf_get_line_count; - if (cap & BIT(DPU_INTF_INPUT_CTRL)) - ops->bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk; -} - struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx, void __iomem *addr, const struct dpu_mdss_cfg *m) @@ -313,7 +304,6 @@ struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx, c->idx = idx; c->cap = cfg; c->mdss = m; - _setup_intf_ops(&c->ops, c->cap->features);

dpu_hw_blk_init(&c->base, DPU_HW_BLK_INTF, idx);

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h index 0ead64d3f63d..8661571fec67 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h @@ -44,37 +44,35 @@ struct intf_status { u32 line_count; /* current line count including blanking */ };

-/** - * struct dpu_hw_intf_ops : Interface to the interface Hw driver functions +/* * Assumption is these functions will be called after clocks are enabled - * @ setup_timing_gen : programs the timing engine - * @ setup_prog_fetch : enables/disables the programmable fetch logic - * @ enable_timing: enable/disable timing engine - * @ get_status: returns if timing engine is enabled or not - * @ get_line_count: reads current vertical line counter - * @bind_pingpong_blk: enable/disable the connection with pingpong which will - * feed pixels to this interface */ -struct dpu_hw_intf_ops { - void (*setup_timing_gen)(struct dpu_hw_intf *intf, - const struct intf_timing_params *p, - const struct dpu_format *fmt);

- void (*setup_prg_fetch)(struct dpu_hw_intf *intf, - const struct intf_prog_fetch *fetch); +/* dpu_hw_intf_setup_timing_engine: programs the timing engine */ +void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf, + const struct intf_timing_params *p, + const struct dpu_format *fmt);

- void (*enable_timing)(struct dpu_hw_intf *intf, - u8 enable); +/* dpu_hw_intf_setup_prg_fetch : enables/disables the programmable fetch logic */ +void dpu_hw_intf_setup_prg_fetch(struct dpu_hw_intf *intf, + const struct intf_prog_fetch *fetch);

- void (*get_status)(struct dpu_hw_intf *intf, - struct intf_status *status); +/* dpu_hw_intf_enable_timing_engine: enable/disable timing engine */ +void dpu_hw_intf_enable_timing_engine(struct dpu_hw_intf *intf, + u8 enable);

- u32 (*get_line_count)(struct dpu_hw_intf *intf); +/* dpu_hw_intf_get_status: returns if timing engine is enabled or not */ +void dpu_hw_intf_get_status(struct dpu_hw_intf *intf, + struct intf_status *status);

- void (*bind_pingpong_blk)(struct dpu_hw_intf *intf, - bool enable, - const enum dpu_pingpong pp); -}; +/* dpu_hw_intf_get_line_count: reads current vertical line counter */ +u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf); + +/* dpu_hw_intf_bind_pingpong_blk: enable/disable the connection with pingpong + * which will feed pixels to this interface */ +void dpu_hw_intf_bind_pingpong_blk(struct dpu_hw_intf *intf, + bool enable, + const enum dpu_pingpong pp);

struct dpu_hw_intf { struct dpu_hw_blk base; @@ -84,9 +82,6 @@ struct dpu_hw_intf { enum dpu_intf idx; const struct dpu_intf_cfg *cap; const struct dpu_mdss_cfg *mdss; - - /* ops */ - struct dpu_hw_intf_ops ops; };

/**

All supported hardware instances feature DPU_VBIF_QOS_REMAP option, so just mark setup_dither as mandatory rather than optional callback.

Signed-off-by: Dmitry Baryshkov dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c index b757054e1c23..377d5e8ae615 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c @@ -204,8 +204,7 @@ static void _setup_vbif_ops(struct dpu_hw_vbif_ops *ops, ops->get_limit_conf = dpu_hw_get_limit_conf; ops->set_halt_ctrl = dpu_hw_set_halt_ctrl; ops->get_halt_ctrl = dpu_hw_get_halt_ctrl; - if (test_bit(DPU_VBIF_QOS_REMAP, &cap)) - ops->set_qos_remap = dpu_hw_set_qos_remap; + ops->set_qos_remap = dpu_hw_set_qos_remap; ops->set_mem_type = dpu_hw_set_mem_type; ops->clear_errors = dpu_hw_clear_errors; ops->set_write_gather_en = dpu_hw_set_write_gather_en;

Downstream driver uses dpu->caps->smart_dma_rev to update sspp->cap->features with the bit corresponding to the supported SmartDMA version. Upstream driver does not do this, resulting in SSPP subdriver not enbaling setup_multirect callback. Make SSPP subdriver check global smart_dma_rev to decide if setup_multirect should be enabled.

Signed-off-by: Dmitry Baryshkov dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 8 ++++---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 16 ++++++++++++---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 9 +++++---- 3 files changed, 21 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index f21f630af476..5552f45f818c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -145,7 +145,7 @@ static const struct dpu_caps sdm845_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .qseed_type = DPU_SSPP_SCALER_QSEED3, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, + .smart_dma_rev = DPU_SMART_DMA_V2, .ubwc_version = DPU_HW_UBWC_VER_20, .has_src_split = true, .has_dim_layer = true, @@ -161,7 +161,7 @@ static const struct dpu_caps sc7180_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0x9, .qseed_type = DPU_SSPP_SCALER_QSEED4, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, + .smart_dma_rev = DPU_SMART_DMA_V2, .ubwc_version = DPU_HW_UBWC_VER_20, .has_dim_layer = true, .has_idle_pc = true, @@ -173,7 +173,7 @@ static const struct dpu_caps sm8150_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .qseed_type = DPU_SSPP_SCALER_QSEED3, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ + .smart_dma_rev = DPU_SMART_DMA_V2, /* TODO: v2.5 */ .ubwc_version = DPU_HW_UBWC_VER_30, .has_src_split = true, .has_dim_layer = true, @@ -189,7 +189,7 @@ static const struct dpu_caps sm8250_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .qseed_type = DPU_SSPP_SCALER_QSEED3LITE, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ + .smart_dma_rev = DPU_SMART_DMA_V2, /* TODO: v2.5 */ .ubwc_version = DPU_HW_UBWC_VER_40, .has_src_split = true, .has_dim_layer = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 08864f0addc4..1202a82918eb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -70,6 +70,18 @@ enum { DPU_HW_UBWC_VER_40 = 0x400, };

+/** + * SmartDMA support + * @DPU_SMART_DMA_UNSUPPORTED, SmartDMA not support + * @DPU_SMART_DMA_V1, SmartDMA 1.0 support + * @DPU_SMART_DMA_V2, SmartDMA 2.0 support + */ +enum { + DPU_SMART_DMA_UNSUPPORTED, + DPU_SMART_DMA_V1, + DPU_SMART_DMA_V2, +}; + /** * MDP TOP BLOCK features * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be be done per pipe @@ -104,8 +116,6 @@ enum { * @DPU_SSPP_QOS, SSPP support QoS control, danger/safe/creq * @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control * @DPU_SSPP_EXCL_RECT, SSPP supports exclusion rect - * @DPU_SSPP_SMART_DMA_V1, SmartDMA 1.0 support - * @DPU_SSPP_SMART_DMA_V2, SmartDMA 2.0 support * @DPU_SSPP_TS_PREFILL Supports prefill with traffic shaper * @DPU_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec * @DPU_SSPP_CDP Supports client driven prefetch @@ -124,8 +134,6 @@ enum { DPU_SSPP_QOS, DPU_SSPP_QOS_8LVL, DPU_SSPP_EXCL_RECT, - DPU_SSPP_SMART_DMA_V1, - DPU_SSPP_SMART_DMA_V2, DPU_SSPP_TS_PREFILL, DPU_SSPP_TS_PREFILL_REC1, DPU_SSPP_CDP, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index 8734a47040aa..4165ff2d7a3c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -647,7 +647,8 @@ static void dpu_hw_sspp_setup_cdp(struct dpu_hw_pipe *ctx, }

static void _setup_layer_ops(struct dpu_hw_pipe *c, - unsigned long features) + unsigned long features, + int smart_dma_rev) { if (test_bit(DPU_SSPP_SRC, &features)) { c->ops.setup_format = dpu_hw_sspp_setup_format; @@ -668,8 +669,8 @@ static void _setup_layer_ops(struct dpu_hw_pipe *c, test_bit(DPU_SSPP_CSC_10BIT, &features)) c->ops.setup_csc = dpu_hw_sspp_setup_csc;

- if (test_bit(DPU_SSPP_SMART_DMA_V1, &c->cap->features) || - test_bit(DPU_SSPP_SMART_DMA_V2, &c->cap->features)) + if (smart_dma_rev == DPU_SMART_DMA_V1 || + smart_dma_rev == DPU_SMART_DMA_V2) c->ops.setup_multirect = dpu_hw_sspp_setup_multirect;

if (test_bit(DPU_SSPP_SCALER_QSEED3, &features) || @@ -731,7 +732,7 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, hw_pipe->mdp = &catalog->mdp[0]; hw_pipe->idx = idx; hw_pipe->cap = cfg; - _setup_layer_ops(hw_pipe, hw_pipe->cap->features); + _setup_layer_ops(hw_pipe, hw_pipe->cap->features, catalog->caps->smart_dma_rev);

dpu_hw_blk_init(&hw_pipe->base, DPU_HW_BLK_SSPP, idx);