Hi Philippe,

when you did the dd the dw-dsi generalization, dw_mipi_dsi_dphy_timing_config() did end up with static values and a comment stating "data & clock lane timers should be computed according to panel blankings and to the automatic clock lane control mode...".

Especially with the PHY_HS2LP_TIME(0x60) I ran into problems. On the Google-Gru-Scarlet (ChromeOS tablet with a highres display) everything works nicely (panel clock 229MHz) but on the device I'm on right now (panel clock 64MHz) I end up with broken output (pixel garbage).

When I set it to the value found in the Rockchip vendor kernel PHY_HS2LP_TIME(0x14) that display works as expected.

The Rockchip SoC manual is pretty sparse on what this value should actually be, so I'm hoping that you may have some insights ;-) .

So far I have found https://github.com/surdupetru/huawei-p6/blob/master/kernel/huawei/hwp6_u06/d... and https://github.com/torvalds/linux/blob/master/drivers/gpu/drm/hisilicon/kiri...

but simply copying strange calculatons seems wrong, similarly to just swapping the hardcoded value from 0x40 to my needed 0x14 ;-) .

So if you have some insights I would be most grateful :-D .

Thanks Heiko