RZ/G2L SoC embeds Mali-G31 bifrost GPU. This patch series aims to add support for the same
It is tested with latest drm-misc-next + mesa 21.3.0 + out of tree patch for (du + DSI) + platfrom mesa configuration for RZ/G2L.
Tested the kmscube application.
test logs:- root@smarc-rzg2l:~# kmscube Using display 0xaaaadb6e7d30 with EGL version 1.4 =================================== EGL information: version: "1.4" vendor: "Mesa Project" ..... =================================== OpenGL ES 2.x information: version: "OpenGL ES 3.1 Mesa 21.3.0" shading language version: "OpenGL ES GLSL ES 3.10" vendor: "Panfrost" renderer: "Mali-G31 (Panfrost)" .... =================================== ^C
root@smarc-rzg2l:~# cat /proc/interrupts | grep panfrost 82: 587287 0 GICv3 186 Level panfrost-job 83: 2 0 GICv3 187 Level panfrost-mmu 84: 8 0 GICv3 185 Level panfrost-gpu
root@smarc-rzg2l:~# cat /sys/class/devfreq/11840000.gpu/trans_stat From : To : 50000000 62500000 100000000 125000000 200000000 250000000 400000000 500000000 time(ms) * 50000000: 0 0 0 0 0 0 0 0 72 62500000: 0 0 0 0 0 0 0 0 0 100000000: 0 0 0 0 0 0 0 0 0 125000000: 0 0 0 0 0 0 0 1 68 200000000: 0 0 0 0 0 0 0 1 68 250000000: 1 0 0 0 0 0 0 0 84 400000000: 0 0 0 0 0 0 0 0 0 500000000: 0 0 0 1 1 1 0 0 736 Total transition : 6 root@smarc-rzg2l:~# kmscube Using display 0xaaaaf7a421b0 with EGL version 1.4 =================================== EGL information: version: "1.4" vendor: "Mesa Project" ..... =================================== OpenGL ES 2.x information: version: "OpenGL ES 3.1 Mesa 21.3.0" shading language version: "OpenGL ES GLSL ES 3.10" vendor: "Panfrost" renderer: "Mali-G31 (Panfrost)" ...... ===================================
root@smarc-rzg2l:~# root@smarc-rzg2l:~# root@smarc-rzg2l:~# cat /sys/class/devfreq/11840000.gpu/trans_stat From : To : 50000000 62500000 100000000 125000000 200000000 250000000 400000000 500000000 time(ms) * 50000000: 0 0 0 0 0 0 0 1 144 62500000: 0 0 0 0 0 0 0 0 0 100000000: 0 0 0 0 0 0 0 9 524 125000000: 0 0 9 0 0 0 0 3 2544 200000000: 0 0 0 11 0 0 0 46 3304 250000000: 1 0 0 0 33 0 0 0 7496 400000000: 0 0 0 0 16 19 0 0 2024 500000000: 1 0 0 1 8 15 35 0 4032 Total transition : 208
Platform specific Mesa patch for RZ/G2L --------------------- src/gallium/targets/dri/meson.build + 'rcar-du_dri.so', src/gallium/targets/dri/target.c +DEFINE_LOADER_DRM_ENTRYPOINT(rcar_du)
V1->V2: * Removed clock patches from this seies, as it is accepted for 5.17 * Added Rb tag from Geert * Added reset-names required property for RZ/G2L and updated the board dtsi.
Biju Das (3): dt-bindings: gpu: mali-bifrost: Document RZ/G2L support arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU node arm64: dts: renesas: rzg2l-smarc-som: Add vdd core regulator
.../bindings/gpu/arm,mali-bifrost.yaml | 39 ++++++++++- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 65 +++++++++++++++++++ .../boot/dts/renesas/rzg2l-smarc-som.dtsi | 13 ++++ 3 files changed, 115 insertions(+), 2 deletions(-)
The Renesas RZ/G2{L, LC} SoC (a.k.a R9A07G044) has a Bifrost Mali-G31 GPU, add a compatible string for it.
Signed-off-by: Biju Das biju.das.jz@bp.renesas.com Reviewed-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com --- v1->v2: * Updated minItems for resets as 2 * Documented optional property reset-names * Documented reset-names as required property for RZ/G2L SoC. --- .../bindings/gpu/arm,mali-bifrost.yaml | 39 ++++++++++++++++++- 1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index 6f98dd55fb4c..c3b2f4ddd520 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -19,6 +19,7 @@ properties: - amlogic,meson-g12a-mali - mediatek,mt8183-mali - realtek,rtd1619-mali + - renesas,r9a07g044-mali - rockchip,px30-mali - rockchip,rk3568-mali - const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable @@ -27,19 +28,30 @@ properties: maxItems: 1
interrupts: + minItems: 3 items: - description: Job interrupt - description: MMU interrupt - description: GPU interrupt + - description: EVENT interrupt
interrupt-names: + minItems: 3 items: - const: job - const: mmu - const: gpu + - const: event
clocks: - maxItems: 1 + minItems: 1 + maxItems: 3 + + clock-names: + items: + - const: gpu + - const: bus + - const: bus_ace
mali-supply: true
@@ -52,7 +64,14 @@ properties: maxItems: 3
resets: - maxItems: 2 + minItems: 2 + maxItems: 3 + + reset-names: + items: + - const: rst + - const: axi_rst + - const: ace_rst
"#cooling-cells": const: 2 @@ -113,6 +132,22 @@ allOf: - sram-supply - power-domains - power-domain-names + - if: + properties: + compatible: + contains: + const: renesas,r9a07g044-mali + then: + properties: + interrupt-names: + minItems: 4 + clock-names: + minItems: 3 + required: + - clock-names + - power-domains + - resets + - reset-names else: properties: power-domains:
On 2021-12-06 15:00, Biju Das wrote:
The Renesas RZ/G2{L, LC} SoC (a.k.a R9A07G044) has a Bifrost Mali-G31 GPU, add a compatible string for it.
Signed-off-by: Biju Das biju.das.jz@bp.renesas.com Reviewed-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com
v1->v2:
- Updated minItems for resets as 2
- Documented optional property reset-names
- Documented reset-names as required property for RZ/G2L SoC.
.../bindings/gpu/arm,mali-bifrost.yaml | 39 ++++++++++++++++++- 1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index 6f98dd55fb4c..c3b2f4ddd520 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -19,6 +19,7 @@ properties: - amlogic,meson-g12a-mali - mediatek,mt8183-mali - realtek,rtd1619-mali
- renesas,r9a07g044-mali - rockchip,px30-mali - rockchip,rk3568-mali - const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable@@ -27,19 +28,30 @@ properties: maxItems: 1
interrupts:
- minItems: 3 items:
- description: Job interrupt
- description: MMU interrupt
- description: GPU interrupt
- description: EVENT interrupt
I believe we haven't bothered with the "Event" interrupt so far since there's no real meaningful use for it - it seems the downstream binding for Arm's kbase driver doesn't mention it either.
interrupt-names:
minItems: 3 items:
- const: job
- const: mmu
- const: gpu
- const: eventclocks:
- maxItems: 1
- minItems: 1
- maxItems: 3
- clock-names:
- items:
- const: gpu- const: bus- const: bus_ace
Note that the Bifrost GPUs themselves all only have a single external clock and reset (unexcitingly named "CLK" and "RESETn" respectively, FWIW). I can't help feeling wary that defining additional names for vendor integration details in the core binding may quickly grow into a mess of mutually-incompatible sets of values, for no great benefit. At the very least, it would seem more sensible to put them in the SoC-specific conditional schemas.
Robin.
mali-supply: true@@ -52,7 +64,14 @@ properties: maxItems: 3
resets:
- maxItems: 2
minItems: 2
maxItems: 3
reset-names:
items:
- const: rst- const: axi_rst- const: ace_rst"#cooling-cells": const: 2
@@ -113,6 +132,22 @@ allOf: - sram-supply - power-domains - power-domain-names
- if:
properties:compatible:contains:const: renesas,r9a07g044-mali- then:
properties:interrupt-names:minItems: 4clock-names:minItems: 3required:- clock-names- power-domains- resets- reset-names else: properties: power-domains:
Hi Robin,
Thanks for the feedback.
Subject: Re: [PATCH v2 1/3] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
On 2021-12-06 15:00, Biju Das wrote:
The Renesas RZ/G2{L, LC} SoC (a.k.a R9A07G044) has a Bifrost Mali-G31 GPU, add a compatible string for it.
Signed-off-by: Biju Das biju.das.jz@bp.renesas.com Reviewed-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com
v1->v2:
- Updated minItems for resets as 2
- Documented optional property reset-names
- Documented reset-names as required property for RZ/G2L SoC.
.../bindings/gpu/arm,mali-bifrost.yaml | 39 ++++++++++++++++++- 1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index 6f98dd55fb4c..c3b2f4ddd520 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -19,6 +19,7 @@ properties: - amlogic,meson-g12a-mali - mediatek,mt8183-mali - realtek,rtd1619-mali
- renesas,r9a07g044-mali - rockchip,px30-mali - rockchip,rk3568-mali - const: arm,mali-bifrost # Mali Bifrost GPU model/revision isfully discoverable @@ -27,19 +28,30 @@ properties: maxItems: 1
interrupts:
- minItems: 3 items:
- description: Job interrupt
- description: MMU interrupt
- description: GPU interrupt
- description: EVENT interruptI believe we haven't bothered with the "Event" interrupt so far since there's no real meaningful use for it - it seems the downstream binding for Arm's kbase driver doesn't mention it either.
I agree. But DT binding describes the H/W. Our SoC, mention about Event interrupt. That is the reason I have documented it.
I am ok for keeping it or removing it. Please let me know.
interrupt-names:
minItems: 3 items:
- const: job
- const: mmu
- const: gpu
- const: eventclocks:
- maxItems: 1
- minItems: 1
- maxItems: 3
- clock-names:
- items:
- const: gpu- const: bus- const: bus_aceNote that the Bifrost GPUs themselves all only have a single external clock and reset (unexcitingly named "CLK" and "RESETn" respectively, FWIW). I can't help feeling wary that defining additional names for vendor integration details in the core binding may quickly grow into a mess of mutually-incompatible sets of values, for no great benefit. At the very least, it would seem more sensible to put them in the SoC-specific conditional schemas.
Initially GPU was not working on our platform. Then after debugging found that it needs, bus clock to make it work. This information is missing in dt binding and I need to find this info from source code.
That is the reason, even if it is optional, I have documented with same name here.
Regards, Biju
Robin.
mali-supply: true@@ -52,7 +64,14 @@ properties: maxItems: 3
resets:
- maxItems: 2
minItems: 2
maxItems: 3
reset-names:
items:
- const: rst- const: axi_rst- const: ace_rst"#cooling-cells": const: 2
@@ -113,6 +132,22 @@ allOf: - sram-supply - power-domains - power-domain-names
- if:
properties:compatible:contains:const: renesas,r9a07g044-mali- then:
properties:interrupt-names:minItems: 4clock-names:minItems: 3required:- clock-names- power-domains- resets- reset-names else: properties: power-domains:
Hi,
Subject: RE: [PATCH v2 1/3] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
Hi Robin,
Thanks for the feedback.
Subject: Re: [PATCH v2 1/3] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
On 2021-12-06 15:00, Biju Das wrote:
The Renesas RZ/G2{L, LC} SoC (a.k.a R9A07G044) has a Bifrost Mali-G31 GPU, add a compatible string for it.
Signed-off-by: Biju Das biju.das.jz@bp.renesas.com Reviewed-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com
v1->v2:
- Updated minItems for resets as 2
- Documented optional property reset-names
- Documented reset-names as required property for RZ/G2L SoC.
.../bindings/gpu/arm,mali-bifrost.yaml | 39
++++++++++++++++++-
1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index 6f98dd55fb4c..c3b2f4ddd520 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -19,6 +19,7 @@ properties: - amlogic,meson-g12a-mali - mediatek,mt8183-mali - realtek,rtd1619-mali
- renesas,r9a07g044-mali - rockchip,px30-mali - rockchip,rk3568-mali - const: arm,mali-bifrost # Mali Bifrost GPU model/revisionis fully discoverable @@ -27,19 +28,30 @@ properties: maxItems: 1
interrupts:
- minItems: 3 items:
- description: Job interrupt
- description: MMU interrupt
- description: GPU interrupt
- description: EVENT interruptI believe we haven't bothered with the "Event" interrupt so far since there's no real meaningful use for it - it seems the downstream binding for Arm's kbase driver doesn't mention it either.
I agree. But DT binding describes the H/W. Our SoC, mention about Event interrupt. That is the reason I have documented it.
interrupt-names:
minItems: 3 items:
- const: job
- const: mmu
- const: gpu
- const: eventclocks:
- maxItems: 1
- minItems: 1
- maxItems: 3
- clock-names:
- items:
- const: gpu- const: bus- const: bus_aceNote that the Bifrost GPUs themselves all only have a single external clock and reset (unexcitingly named "CLK" and "RESETn" respectively, FWIW). I can't help feeling wary that defining additional names for vendor integration details in the core binding may quickly grow into a mess of mutually-incompatible sets of values, for no great benefit. At the very least, it would seem more sensible to put them in the SoC-specific conditional schemas.
I agree, All optional properties like clock-names and reset-names should go in the SoC-specific conditional schemas. I will make clock-names and reset-names to true and handle it in the SoC-specific conditional schemas.
I will send V3, incorporating the above.
Regards, Biju
Robin.
mali-supply: true@@ -52,7 +64,14 @@ properties: maxItems: 3
resets:
- maxItems: 2
minItems: 2
maxItems: 3
reset-names:
items:
- const: rst- const: axi_rst- const: ace_rst"#cooling-cells": const: 2
@@ -113,6 +132,22 @@ allOf: - sram-supply - power-domains - power-domain-names
- if:
properties:compatible:contains:const: renesas,r9a07g044-mali- then:
properties:interrupt-names:minItems: 4clock-names:minItems: 3required:- clock-names- power-domains- resets- reset-names else: properties: power-domains:
dri-devel@lists.freedesktop.org
-
Biju Das -
Robin Murphy