Should work with the legacy handling in of, but we shouldn't rely on that.
Signed-off-by: Sean Paul seanpaul@chromium.org --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index 035a5fbe1435..e6d02c6947b4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -424,7 +424,7 @@ static void dpu_encoder_phys_cmd_tearcheck_config( * vsync_count is ratio of MDP VSYNC clock frequency to LCD panel * frequency divided by the no. of rows (lines) in the LCDpanel. */ - vsync_hz = dpu_kms_get_clk_rate(dpu_kms, "vsync_clk"); + vsync_hz = dpu_kms_get_clk_rate(dpu_kms, "vsync"); if (vsync_hz <= 0) { DPU_DEBUG_CMDENC(cmd_enc, "invalid - vsync_hz %u\n", vsync_hz);
In these cases, we want to enumerate _all_ clocks, not just the ones that are assigned a rate.
Signed-off-by: Sean Paul seanpaul@chromium.org --- drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c index 8d907faa7496..c1d7eac4fa25 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c @@ -147,8 +147,7 @@ int msm_dss_parse_clock(struct platform_device *pdev, return -EINVAL;
mp->num_clk = 0; - num_clk = of_property_count_strings(pdev->dev.of_node, - "assigned-clock-names"); + num_clk = of_property_count_strings(pdev->dev.of_node, "clock-names"); if (num_clk <= 0) { pr_debug("clocks are not defined\n"); return 0; @@ -162,7 +161,7 @@ int msm_dss_parse_clock(struct platform_device *pdev,
for (i = 0; i < num_clk; i++) { rc = of_property_read_string_index(pdev->dev.of_node, - "assigned-clock-names", i, + "clock-names", i, &clock_name); if (rc) { dev_err(&pdev->dev, "Failed to get clock name for %d\n",
This fixes up a collision between introducing dual-channel support and the dsi refactors. This patch applies the same dual-channel considerations and pclk calculations to both v2 and 6G, with a bit of abstracting for good measure.
Signed-off-by: Sean Paul seanpaul@chromium.org --- drivers/gpu/drm/msm/dsi/dsi_host.c | 72 +++++++++++++++--------------- 1 file changed, 35 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 319501dcc083..96fb5f635314 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -664,11 +664,9 @@ void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host) clk_disable_unprepare(msm_host->byte_clk); }
-int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_dual_dsi) +static u32 dsi_get_pclk_rate(struct msm_dsi_host *msm_host, bool is_dual_dsi) { struct drm_display_mode *mode = msm_host->mode; - u8 lanes = msm_host->lanes; - u32 bpp = dsi_get_bpp(msm_host->format); u32 pclk_rate;
pclk_rate = mode->clock * 1000; @@ -676,61 +674,61 @@ int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_dual_dsi) /* * For dual DSI mode, the current DRM mode has the complete width of the * panel. Since, the complete panel is driven by two DSI controllers, - * theclock rates have to be split between the two dsi controllers. + * the clock rates have to be split between the two dsi controllers. * Adjust the byte and pixel clock rates for each dsi host accordingly. */ if (is_dual_dsi) pclk_rate /= 2;
- if (lanes > 0) { - msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes); - } else { + return pclk_rate; +} + +static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_dual_dsi) +{ + u8 lanes = msm_host->lanes; + u32 bpp = dsi_get_bpp(msm_host->format); + u32 pclk_rate = dsi_get_pclk_rate(msm_host, is_dual_dsi); + u64 pclk_bpp = (u64)pclk_rate * bpp; + + if (lanes == 0) { pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__); - msm_host->byte_clk_rate = (pclk_rate * bpp) / 8; + lanes = 1; }
- DBG("pclk=%d, bclk=%d", pclk_rate, msm_host->byte_clk_rate); + do_div(pclk_bpp, (8 * lanes));
- msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk); + msm_host->pixel_clk_rate = pclk_rate; + msm_host->byte_clk_rate = pclk_bpp; + + DBG("pclk=%d, bclk=%d", msm_host->pixel_clk_rate, + msm_host->byte_clk_rate); + +} + +int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_dual_dsi) +{ + if (!msm_host->mode) { + pr_err("%s: mode not set\n", __func__); + return -EINVAL; + }
+ dsi_calc_pclk(msm_host, is_dual_dsi); + msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk); return 0; }
int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_dual_dsi) { - struct drm_display_mode *mode = msm_host->mode; - u8 lanes = msm_host->lanes; u32 bpp = dsi_get_bpp(msm_host->format); - u32 pclk_rate; u64 pclk_bpp; unsigned int esc_mhz, esc_div; unsigned long byte_mhz;
- pclk_rate = mode->clock * 1000; - - /* - * For dual DSI mode, the current DRM mode has the complete width of the - * panel. Since, the complete panel is driven by two DSI controllers, - * theclock rates have to be split between the two dsi controllers. - * Adjust the byte and pixel clock rates for each dsi host accordingly. - */ - if (is_dual_dsi) - pclk_rate /= 2; - - pclk_bpp = pclk_rate * bpp; - if (lanes > 0) { - do_div(pclk_bpp, (8 * lanes)); - } else { - pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__); - do_div(pclk_bpp, 8); - } - msm_host->pixel_clk_rate = pclk_rate; - msm_host->byte_clk_rate = pclk_bpp; - - DBG("pclk=%d, bclk=%d", msm_host->pixel_clk_rate, - msm_host->byte_clk_rate); + dsi_calc_pclk(msm_host, is_dual_dsi);
- msm_host->src_clk_rate = (pclk_rate * bpp) / 8; + pclk_bpp = (u64)dsi_get_pclk_rate(msm_host, is_dual_dsi) * bpp; + do_div(pclk_bpp, 8); + msm_host->src_clk_rate = pclk_bpp;
/* * esc clock is byte clock followed by a 4 bit divider,
dri-devel@lists.freedesktop.org
-
Sean Paul