Factor out register programming to configure the chip video RX side for reception of video data from DSI or DPI. This is particularly useful in the (e)DP output mode, where the video data can be received from either DPI or DSI. While only the former is supported in (e)DP output mode so far, this patch is added in preparation for addition of the later.
There is a change in the order or register programming in case of the DSI-to-DPI mode. The DSI RX side is now programmed and enabled all in one place after the output mode has been configured. Before this change, the DSI RX has been programmed before the output mode has been set and only enabled afterward. The order makes no difference however, since the DSI RX is only enabled at the end either way.
Signed-off-by: Marek Vasut marex@denx.de Cc: Jonas Karlman jonas@kwiboo.se Cc: Laurent Pinchart Laurent.pinchart@ideasonboard.com Cc: Lucas Stach l.stach@pengutronix.de Cc: Marek Vasut marex@denx.de Cc: Maxime Ripard maxime@cerno.tech Cc: Neil Armstrong narmstrong@baylibre.com Cc: Robert Foss robert.foss@linaro.org Cc: Sam Ravnborg sam@ravnborg.org --- drivers/gpu/drm/bridge/tc358767.c | 94 +++++++++++++++++-------------- 1 file changed, 53 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c index 485717c8f0b4..e72dd5cd9700 100644 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@ -1247,11 +1247,60 @@ static int tc_main_link_disable(struct tc_data *tc) return regmap_write(tc->regmap, DP0CTL, 0); }
-static int tc_dpi_stream_enable(struct tc_data *tc) +static int tc_dsi_rx_enable(struct tc_data *tc) { + u32 value; int ret; + + regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 3); + regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 3); + regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 3); + regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 3); + regmap_write(tc->regmap, PPI_D0S_ATMR, 0); + regmap_write(tc->regmap, PPI_D1S_ATMR, 0); + regmap_write(tc->regmap, PPI_TX_RX_TA, TTA_GET | TTA_SURE); + regmap_write(tc->regmap, PPI_LPTXTIMECNT, LPX_PERIOD); + + value = ((LANEENABLE_L0EN << tc->dsi_lanes) - LANEENABLE_L0EN) | + LANEENABLE_CLEN; + regmap_write(tc->regmap, PPI_LANEENABLE, value); + regmap_write(tc->regmap, DSI_LANEENABLE, value); + + /* Set input interface */ + value = DP0_AUDSRC_NO_INPUT; + if (tc_test_pattern) + value |= DP0_VIDSRC_COLOR_BAR; + else + value |= DP0_VIDSRC_DSI_RX; + ret = regmap_write(tc->regmap, SYSCTRL, value); + if (ret) + return ret; + + usleep_range(120, 150); + + regmap_write(tc->regmap, PPI_STARTPPI, PPI_START_FUNCTION); + regmap_write(tc->regmap, DSI_STARTDSI, DSI_RX_START); + + return 0; +} + +static int tc_dpi_rx_enable(struct tc_data *tc) +{ u32 value;
+ /* Set input interface */ + value = DP0_AUDSRC_NO_INPUT; + if (tc_test_pattern) + value |= DP0_VIDSRC_COLOR_BAR; + else + value |= DP0_VIDSRC_DPI_RX; + return regmap_write(tc->regmap, SYSCTRL, value); +} + +static int tc_dpi_stream_enable(struct tc_data *tc) +{ + int ret; + dev_dbg(tc->dev, "enable video stream\n");
/* Setup PLL */ @@ -1277,20 +1326,6 @@ static int tc_dpi_stream_enable(struct tc_data *tc) if (ret) return ret;
- regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 3); - regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 3); - regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 3); - regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 3); - regmap_write(tc->regmap, PPI_D0S_ATMR, 0); - regmap_write(tc->regmap, PPI_D1S_ATMR, 0); - regmap_write(tc->regmap, PPI_TX_RX_TA, TTA_GET | TTA_SURE); - regmap_write(tc->regmap, PPI_LPTXTIMECNT, LPX_PERIOD); - - value = ((LANEENABLE_L0EN << tc->dsi_lanes) - LANEENABLE_L0EN) | - LANEENABLE_CLEN; - regmap_write(tc->regmap, PPI_LANEENABLE, value); - regmap_write(tc->regmap, DSI_LANEENABLE, value); - ret = tc_set_common_video_mode(tc, &tc->mode); if (ret) return ret; @@ -1299,22 +1334,7 @@ static int tc_dpi_stream_enable(struct tc_data *tc) if (ret) return ret;
- /* Set input interface */ - value = DP0_AUDSRC_NO_INPUT; - if (tc_test_pattern) - value |= DP0_VIDSRC_COLOR_BAR; - else - value |= DP0_VIDSRC_DSI_RX; - ret = regmap_write(tc->regmap, SYSCTRL, value); - if (ret) - return ret; - - usleep_range(120, 150); - - regmap_write(tc->regmap, PPI_STARTPPI, PPI_START_FUNCTION); - regmap_write(tc->regmap, DSI_STARTDSI, DSI_RX_START); - - return 0; + return tc_dsi_rx_enable(tc); }
static int tc_dpi_stream_disable(struct tc_data *tc) @@ -1370,19 +1390,11 @@ static int tc_edp_stream_enable(struct tc_data *tc) usleep_range(500, 1000); value |= VID_EN; ret = regmap_write(tc->regmap, DP0CTL, value); - if (ret) - return ret; - /* Set input interface */ - value = DP0_AUDSRC_NO_INPUT; - if (tc_test_pattern) - value |= DP0_VIDSRC_COLOR_BAR; - else - value |= DP0_VIDSRC_DPI_RX; - ret = regmap_write(tc->regmap, SYSCTRL, value); if (ret) return ret;
- return 0; + /* Set input interface */ + return tc_dpi_rx_enable(tc); }
static int tc_edp_stream_disable(struct tc_data *tc)
Implement DSI-to-e(DP) mode, which is a mix of currently supported DSI-to-DPI and DPI-to-(e)DP modes. The input side is configured as either DSI or DPI, the DP AUX channel is registered for both input side options, and the DSI host is attached for both DPI and (e)DP output side options.
One notable detail is that the DSI-to-(e)DP mode requires the Pixel PLL to be always enabled, which is not needed for DPI-to-(e)DP mode which gets the matching clock direct from DPI Pixel Clock instead.
Signed-off-by: Marek Vasut marex@denx.de Cc: Jonas Karlman jonas@kwiboo.se Cc: Laurent Pinchart Laurent.pinchart@ideasonboard.com Cc: Lucas Stach l.stach@pengutronix.de Cc: Marek Vasut marex@denx.de Cc: Maxime Ripard maxime@cerno.tech Cc: Neil Armstrong narmstrong@baylibre.com Cc: Robert Foss robert.foss@linaro.org Cc: Sam Ravnborg sam@ravnborg.org --- drivers/gpu/drm/bridge/tc358767.c | 40 +++++++++++++++++++++++-------- 1 file changed, 30 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c index e72dd5cd9700..798da0e4d086 100644 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@ -309,6 +309,9 @@ struct tc_data { /* do we have IRQ */ bool have_irq;
+ /* Input connector type, DSI and not DPI. */ + bool input_connector_dsi; + /* HPD pin number (0 or 1) or -ENODEV */ int hpd_pin; }; @@ -1353,8 +1356,18 @@ static int tc_edp_stream_enable(struct tc_data *tc)
dev_dbg(tc->dev, "enable video stream\n");
- /* PXL PLL setup */ - if (tc_test_pattern) { + /* + * Pixel PLL must be enabled for DSI input mode and test pattern. + * + * Per TC9595XBG datasheet Revision 0.1 2018-12-27 Figure 4.18 + * "Clock Mode Selection and Clock Sources", either Pixel PLL + * or DPI_PCLK supplies StrmClk. DPI_PCLK is only available in + * case valid Pixel Clock are supplied to the chip DPI input. + * In case built-in test pattern is desired OR DSI input mode + * is used, DPI_PCLK is not available and thus Pixel PLL must + * be used instead. + */ + if (tc->input_connector_dsi || tc_test_pattern) { ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk), 1000 * tc->mode.clock); if (ret) @@ -1394,7 +1407,10 @@ static int tc_edp_stream_enable(struct tc_data *tc) return ret;
/* Set input interface */ - return tc_dpi_rx_enable(tc); + if (tc->input_connector_dsi) + return tc_dsi_rx_enable(tc); + else + return tc_dpi_rx_enable(tc); }
static int tc_edp_stream_disable(struct tc_data *tc) @@ -2004,14 +2020,18 @@ static int tc_probe_bridge_endpoint(struct tc_data *tc) mode |= BIT(endpoint.port); }
- if (mode == mode_dpi_to_edp || mode == mode_dpi_to_dp) + if (mode == mode_dpi_to_edp || mode == mode_dpi_to_dp) { + tc->input_connector_dsi = false; return tc_probe_edp_bridge_endpoint(tc); - else if (mode == mode_dsi_to_dpi) + } else if (mode == mode_dsi_to_dpi) { + tc->input_connector_dsi = true; return tc_probe_dpi_bridge_endpoint(tc); - else if (mode == mode_dsi_to_edp || mode == mode_dsi_to_dp) - dev_warn(dev, "The mode DSI-to-(e)DP is not supported!\n"); - else - dev_warn(dev, "Invalid mode (0x%x) is not supported!\n", mode); + } else if (mode == mode_dsi_to_edp || mode == mode_dsi_to_dp) { + tc->input_connector_dsi = true; + return tc_probe_edp_bridge_endpoint(tc); + } + + dev_warn(dev, "Invalid mode (0x%x) is not supported!\n", mode);
return -EINVAL; } @@ -2149,7 +2169,7 @@ static int tc_probe(struct i2c_client *client, const struct i2c_device_id *id)
i2c_set_clientdata(client, tc);
- if (tc->bridge.type == DRM_MODE_CONNECTOR_DPI) { /* DPI output */ + if (tc->input_connector_dsi) { /* DSI input */ ret = tc_mipi_dsi_host_attach(tc); if (ret) { drm_bridge_remove(&tc->bridge);
On Fri, 29 Apr 2022 at 22:56, Marek Vasut marex@denx.de wrote:
Implement DSI-to-e(DP) mode, which is a mix of currently supported DSI-to-DPI and DPI-to-(e)DP modes. The input side is configured as either DSI or DPI, the DP AUX channel is registered for both input side options, and the DSI host is attached for both DPI and (e)DP output side options.
One notable detail is that the DSI-to-(e)DP mode requires the Pixel PLL to be always enabled, which is not needed for DPI-to-(e)DP mode which gets the matching clock direct from DPI Pixel Clock instead.
Signed-off-by: Marek Vasut marex@denx.de Cc: Jonas Karlman jonas@kwiboo.se Cc: Laurent Pinchart Laurent.pinchart@ideasonboard.com Cc: Lucas Stach l.stach@pengutronix.de Cc: Marek Vasut marex@denx.de Cc: Maxime Ripard maxime@cerno.tech Cc: Neil Armstrong narmstrong@baylibre.com Cc: Robert Foss robert.foss@linaro.org Cc: Sam Ravnborg sam@ravnborg.org
drivers/gpu/drm/bridge/tc358767.c | 40 +++++++++++++++++++++++-------- 1 file changed, 30 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c index e72dd5cd9700..798da0e4d086 100644 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@ -309,6 +309,9 @@ struct tc_data { /* do we have IRQ */ bool have_irq;
/* Input connector type, DSI and not DPI. */bool input_connector_dsi;/* HPD pin number (0 or 1) or -ENODEV */ int hpd_pin;}; @@ -1353,8 +1356,18 @@ static int tc_edp_stream_enable(struct tc_data *tc)
dev_dbg(tc->dev, "enable video stream\n");
/* PXL PLL setup */if (tc_test_pattern) {
/** Pixel PLL must be enabled for DSI input mode and test pattern.** Per TC9595XBG datasheet Revision 0.1 2018-12-27 Figure 4.18* "Clock Mode Selection and Clock Sources", either Pixel PLL* or DPI_PCLK supplies StrmClk. DPI_PCLK is only available in* case valid Pixel Clock are supplied to the chip DPI input.* In case built-in test pattern is desired OR DSI input mode* is used, DPI_PCLK is not available and thus Pixel PLL must* be used instead.*/if (tc->input_connector_dsi || tc_test_pattern) { ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk), 1000 * tc->mode.clock); if (ret)@@ -1394,7 +1407,10 @@ static int tc_edp_stream_enable(struct tc_data *tc) return ret;
/* Set input interface */
return tc_dpi_rx_enable(tc);
if (tc->input_connector_dsi)return tc_dsi_rx_enable(tc);elsereturn tc_dpi_rx_enable(tc);}
static int tc_edp_stream_disable(struct tc_data *tc) @@ -2004,14 +2020,18 @@ static int tc_probe_bridge_endpoint(struct tc_data *tc) mode |= BIT(endpoint.port); }
if (mode == mode_dpi_to_edp || mode == mode_dpi_to_dp)
if (mode == mode_dpi_to_edp || mode == mode_dpi_to_dp) {tc->input_connector_dsi = false; return tc_probe_edp_bridge_endpoint(tc);
else if (mode == mode_dsi_to_dpi)
} else if (mode == mode_dsi_to_dpi) {tc->input_connector_dsi = true; return tc_probe_dpi_bridge_endpoint(tc);
else if (mode == mode_dsi_to_edp || mode == mode_dsi_to_dp)dev_warn(dev, "The mode DSI-to-(e)DP is not supported!\n");elsedev_warn(dev, "Invalid mode (0x%x) is not supported!\n", mode);
} else if (mode == mode_dsi_to_edp || mode == mode_dsi_to_dp) {tc->input_connector_dsi = true;return tc_probe_edp_bridge_endpoint(tc);}dev_warn(dev, "Invalid mode (0x%x) is not supported!\n", mode); return -EINVAL;} @@ -2149,7 +2169,7 @@ static int tc_probe(struct i2c_client *client, const struct i2c_device_id *id)
i2c_set_clientdata(client, tc);
if (tc->bridge.type == DRM_MODE_CONNECTOR_DPI) { /* DPI output */
if (tc->input_connector_dsi) { /* DSI input */ ret = tc_mipi_dsi_host_attach(tc); if (ret) { drm_bridge_remove(&tc->bridge);
Reviewed-by: Robert Foss robert.foss@linaro.org
On Fri, 29 Apr 2022 at 22:56, Marek Vasut marex@denx.de wrote:
Factor out register programming to configure the chip video RX side for reception of video data from DSI or DPI. This is particularly useful in the (e)DP output mode, where the video data can be received from either DPI or DSI. While only the former is supported in (e)DP output mode so far, this patch is added in preparation for addition of the later.
There is a change in the order or register programming in case of the DSI-to-DPI mode. The DSI RX side is now programmed and enabled all in one place after the output mode has been configured. Before this change, the DSI RX has been programmed before the output mode has been set and only enabled afterward. The order makes no difference however, since the DSI RX is only enabled at the end either way.
Signed-off-by: Marek Vasut marex@denx.de Cc: Jonas Karlman jonas@kwiboo.se Cc: Laurent Pinchart Laurent.pinchart@ideasonboard.com Cc: Lucas Stach l.stach@pengutronix.de Cc: Marek Vasut marex@denx.de Cc: Maxime Ripard maxime@cerno.tech Cc: Neil Armstrong narmstrong@baylibre.com Cc: Robert Foss robert.foss@linaro.org Cc: Sam Ravnborg sam@ravnborg.org
drivers/gpu/drm/bridge/tc358767.c | 94 +++++++++++++++++-------------- 1 file changed, 53 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c index 485717c8f0b4..e72dd5cd9700 100644 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@ -1247,11 +1247,60 @@ static int tc_main_link_disable(struct tc_data *tc) return regmap_write(tc->regmap, DP0CTL, 0); }
-static int tc_dpi_stream_enable(struct tc_data *tc) +static int tc_dsi_rx_enable(struct tc_data *tc) {
u32 value; int ret;regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 3);regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 3);regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 3);regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 3);regmap_write(tc->regmap, PPI_D0S_ATMR, 0);regmap_write(tc->regmap, PPI_D1S_ATMR, 0);regmap_write(tc->regmap, PPI_TX_RX_TA, TTA_GET | TTA_SURE);regmap_write(tc->regmap, PPI_LPTXTIMECNT, LPX_PERIOD);value = ((LANEENABLE_L0EN << tc->dsi_lanes) - LANEENABLE_L0EN) |LANEENABLE_CLEN;regmap_write(tc->regmap, PPI_LANEENABLE, value);regmap_write(tc->regmap, DSI_LANEENABLE, value);/* Set input interface */value = DP0_AUDSRC_NO_INPUT;if (tc_test_pattern)value |= DP0_VIDSRC_COLOR_BAR;elsevalue |= DP0_VIDSRC_DSI_RX;ret = regmap_write(tc->regmap, SYSCTRL, value);if (ret)return ret;usleep_range(120, 150);regmap_write(tc->regmap, PPI_STARTPPI, PPI_START_FUNCTION);regmap_write(tc->regmap, DSI_STARTDSI, DSI_RX_START);return 0;+}
+static int tc_dpi_rx_enable(struct tc_data *tc) +{ u32 value;
/* Set input interface */value = DP0_AUDSRC_NO_INPUT;if (tc_test_pattern)value |= DP0_VIDSRC_COLOR_BAR;elsevalue |= DP0_VIDSRC_DPI_RX;return regmap_write(tc->regmap, SYSCTRL, value);+}
+static int tc_dpi_stream_enable(struct tc_data *tc) +{
int ret;dev_dbg(tc->dev, "enable video stream\n"); /* Setup PLL */@@ -1277,20 +1326,6 @@ static int tc_dpi_stream_enable(struct tc_data *tc) if (ret) return ret;
regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 3);regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 3);regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 3);regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 3);regmap_write(tc->regmap, PPI_D0S_ATMR, 0);regmap_write(tc->regmap, PPI_D1S_ATMR, 0);regmap_write(tc->regmap, PPI_TX_RX_TA, TTA_GET | TTA_SURE);regmap_write(tc->regmap, PPI_LPTXTIMECNT, LPX_PERIOD);value = ((LANEENABLE_L0EN << tc->dsi_lanes) - LANEENABLE_L0EN) |LANEENABLE_CLEN;regmap_write(tc->regmap, PPI_LANEENABLE, value);regmap_write(tc->regmap, DSI_LANEENABLE, value);ret = tc_set_common_video_mode(tc, &tc->mode); if (ret) return ret;@@ -1299,22 +1334,7 @@ static int tc_dpi_stream_enable(struct tc_data *tc) if (ret) return ret;
/* Set input interface */value = DP0_AUDSRC_NO_INPUT;if (tc_test_pattern)value |= DP0_VIDSRC_COLOR_BAR;elsevalue |= DP0_VIDSRC_DSI_RX;ret = regmap_write(tc->regmap, SYSCTRL, value);if (ret)return ret;usleep_range(120, 150);regmap_write(tc->regmap, PPI_STARTPPI, PPI_START_FUNCTION);regmap_write(tc->regmap, DSI_STARTDSI, DSI_RX_START);return 0;
return tc_dsi_rx_enable(tc);}
static int tc_dpi_stream_disable(struct tc_data *tc) @@ -1370,19 +1390,11 @@ static int tc_edp_stream_enable(struct tc_data *tc) usleep_range(500, 1000); value |= VID_EN; ret = regmap_write(tc->regmap, DP0CTL, value);
if (ret)return ret;/* Set input interface */value = DP0_AUDSRC_NO_INPUT;if (tc_test_pattern)value |= DP0_VIDSRC_COLOR_BAR;elsevalue |= DP0_VIDSRC_DPI_RX;ret = regmap_write(tc->regmap, SYSCTRL, value); if (ret) return ret;return 0;
/* Set input interface */return tc_dpi_rx_enable(tc);}
static int tc_edp_stream_disable(struct tc_data *tc)
2.35.1
Reviewed-by: Robert Foss robert.foss@linaro.org
On Thu, 12 May 2022 at 18:02, Robert Foss robert.foss@linaro.org wrote:
On Fri, 29 Apr 2022 at 22:56, Marek Vasut marex@denx.de wrote:
Factor out register programming to configure the chip video RX side for reception of video data from DSI or DPI. This is particularly useful in the (e)DP output mode, where the video data can be received from either DPI or DSI. While only the former is supported in (e)DP output mode so far, this patch is added in preparation for addition of the later.
There is a change in the order or register programming in case of the DSI-to-DPI mode. The DSI RX side is now programmed and enabled all in one place after the output mode has been configured. Before this change, the DSI RX has been programmed before the output mode has been set and only enabled afterward. The order makes no difference however, since the DSI RX is only enabled at the end either way.
Signed-off-by: Marek Vasut marex@denx.de Cc: Jonas Karlman jonas@kwiboo.se Cc: Laurent Pinchart Laurent.pinchart@ideasonboard.com Cc: Lucas Stach l.stach@pengutronix.de Cc: Marek Vasut marex@denx.de Cc: Maxime Ripard maxime@cerno.tech Cc: Neil Armstrong narmstrong@baylibre.com Cc: Robert Foss robert.foss@linaro.org Cc: Sam Ravnborg sam@ravnborg.org
drivers/gpu/drm/bridge/tc358767.c | 94 +++++++++++++++++-------------- 1 file changed, 53 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c index 485717c8f0b4..e72dd5cd9700 100644 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@ -1247,11 +1247,60 @@ static int tc_main_link_disable(struct tc_data *tc) return regmap_write(tc->regmap, DP0CTL, 0); }
-static int tc_dpi_stream_enable(struct tc_data *tc) +static int tc_dsi_rx_enable(struct tc_data *tc) {
u32 value; int ret;regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 3);regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 3);regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 3);regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 3);regmap_write(tc->regmap, PPI_D0S_ATMR, 0);regmap_write(tc->regmap, PPI_D1S_ATMR, 0);regmap_write(tc->regmap, PPI_TX_RX_TA, TTA_GET | TTA_SURE);regmap_write(tc->regmap, PPI_LPTXTIMECNT, LPX_PERIOD);value = ((LANEENABLE_L0EN << tc->dsi_lanes) - LANEENABLE_L0EN) |LANEENABLE_CLEN;regmap_write(tc->regmap, PPI_LANEENABLE, value);regmap_write(tc->regmap, DSI_LANEENABLE, value);/* Set input interface */value = DP0_AUDSRC_NO_INPUT;if (tc_test_pattern)value |= DP0_VIDSRC_COLOR_BAR;elsevalue |= DP0_VIDSRC_DSI_RX;ret = regmap_write(tc->regmap, SYSCTRL, value);if (ret)return ret;usleep_range(120, 150);regmap_write(tc->regmap, PPI_STARTPPI, PPI_START_FUNCTION);regmap_write(tc->regmap, DSI_STARTDSI, DSI_RX_START);return 0;+}
+static int tc_dpi_rx_enable(struct tc_data *tc) +{ u32 value;
/* Set input interface */value = DP0_AUDSRC_NO_INPUT;if (tc_test_pattern)value |= DP0_VIDSRC_COLOR_BAR;elsevalue |= DP0_VIDSRC_DPI_RX;return regmap_write(tc->regmap, SYSCTRL, value);+}
+static int tc_dpi_stream_enable(struct tc_data *tc) +{
int ret;dev_dbg(tc->dev, "enable video stream\n"); /* Setup PLL */@@ -1277,20 +1326,6 @@ static int tc_dpi_stream_enable(struct tc_data *tc) if (ret) return ret;
regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 3);regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 3);regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 3);regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 3);regmap_write(tc->regmap, PPI_D0S_ATMR, 0);regmap_write(tc->regmap, PPI_D1S_ATMR, 0);regmap_write(tc->regmap, PPI_TX_RX_TA, TTA_GET | TTA_SURE);regmap_write(tc->regmap, PPI_LPTXTIMECNT, LPX_PERIOD);value = ((LANEENABLE_L0EN << tc->dsi_lanes) - LANEENABLE_L0EN) |LANEENABLE_CLEN;regmap_write(tc->regmap, PPI_LANEENABLE, value);regmap_write(tc->regmap, DSI_LANEENABLE, value);ret = tc_set_common_video_mode(tc, &tc->mode); if (ret) return ret;@@ -1299,22 +1334,7 @@ static int tc_dpi_stream_enable(struct tc_data *tc) if (ret) return ret;
/* Set input interface */value = DP0_AUDSRC_NO_INPUT;if (tc_test_pattern)value |= DP0_VIDSRC_COLOR_BAR;elsevalue |= DP0_VIDSRC_DSI_RX;ret = regmap_write(tc->regmap, SYSCTRL, value);if (ret)return ret;usleep_range(120, 150);regmap_write(tc->regmap, PPI_STARTPPI, PPI_START_FUNCTION);regmap_write(tc->regmap, DSI_STARTDSI, DSI_RX_START);return 0;
return tc_dsi_rx_enable(tc);}
static int tc_dpi_stream_disable(struct tc_data *tc) @@ -1370,19 +1390,11 @@ static int tc_edp_stream_enable(struct tc_data *tc) usleep_range(500, 1000); value |= VID_EN; ret = regmap_write(tc->regmap, DP0CTL, value);
if (ret)return ret;/* Set input interface */value = DP0_AUDSRC_NO_INPUT;if (tc_test_pattern)value |= DP0_VIDSRC_COLOR_BAR;elsevalue |= DP0_VIDSRC_DPI_RX;ret = regmap_write(tc->regmap, SYSCTRL, value); if (ret) return ret;return 0;
/* Set input interface */return tc_dpi_rx_enable(tc);}
static int tc_edp_stream_disable(struct tc_data *tc)
2.35.1
Reviewed-by: Robert Foss robert.foss@linaro.org
Applied to drm-misc-next.
dri-devel@lists.freedesktop.org
-
Marek Vasut -
Robert Foss