Hi

2013/2/25 Rodrigo Vivi rodrigo.vivi@gmail.com:

While old platforms had 3 transcoders and 3 pipes (1:1), HSW has 4 transcoders and 3 pipes. These regs were being used only by HDMI code where pipe is always the same thing as cpu_transcoder. This patch allow us to use them for DP, specially for TRANSCODER_EDP.

v2: Adding HSW_TVIDEO_DIP_VSC_DATA to transmit vsc to eDP.

Signed-off-by: Rodrigo Vivi rodrigo.vivi@gmail.com

Reviewed-by: Paulo Zanoni paulo.r.zanoni@intel.com

---

drivers/gpu/drm/i915/i915_reg.h | 18 ++++++++++-------- drivers/gpu/drm/i915/intel_hdmi.c | 13 +++++++------ 2 files changed, 17 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 527b664..b715ecd 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3754,14 +3754,16 @@ #define HSW_VIDEO_DIP_VSC_ECC_B 0x61344 #define HSW_VIDEO_DIP_GCP_B 0x61210

-#define HSW_TVIDEO_DIP_CTL(pipe) \

•    _PIPE(pipe, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B)
  

-#define HSW_TVIDEO_DIP_AVI_DATA(pipe) \

•    _PIPE(pipe, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B)
  

-#define HSW_TVIDEO_DIP_SPD_DATA(pipe) \

•    _PIPE(pipe, HSW_VIDEO_DIP_SPD_DATA_A, HSW_VIDEO_DIP_SPD_DATA_B)
  

-#define HSW_TVIDEO_DIP_GCP(pipe) \

•   _PIPE(pipe, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B)
  

+#define HSW_TVIDEO_DIP_CTL(trans) \

•    _TRANSCODER(trans, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B)
  

+#define HSW_TVIDEO_DIP_AVI_DATA(trans) \

•    _TRANSCODER(trans, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B)
  

+#define HSW_TVIDEO_DIP_SPD_DATA(trans) \

•    _TRANSCODER(trans, HSW_VIDEO_DIP_SPD_DATA_A, HSW_VIDEO_DIP_SPD_DATA_B)
  

+#define HSW_TVIDEO_DIP_GCP(trans) \

•   _TRANSCODER(trans, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B)
  

+#define HSW_TVIDEO_DIP_VSC_DATA(trans) \

•    _TRANSCODER(trans, HSW_VIDEO_DIP_VSC_DATA_A, HSW_VIDEO_DIP_VSC_DATA_B)
  
  

#define _TRANS_HTOTAL_B 0xe1000 #define _TRANS_HBLANK_B 0xe1004 diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 5a6138c..26290c1 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -120,13 +120,14 @@ static u32 hsw_infoframe_enable(struct dip_infoframe *frame) } }

-static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe) +static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame,

•                             enum transcoder cpu_transcoder)
  

{ switch (frame->type) { case DIP_TYPE_AVI:

•           return HSW_TVIDEO_DIP_AVI_DATA(pipe);
  

•           return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
    case DIP_TYPE_SPD:
  

•           return HSW_TVIDEO_DIP_SPD_DATA(pipe);
  

•           return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
    default:
            DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
            return 0;
  

@@ -293,8 +294,8 @@ static void hsw_write_infoframe(struct drm_encoder *encoder, struct drm_device *dev = encoder->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);

•   u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
  

•   u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe);
  

•   u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->cpu_transcoder);
  

•   u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->cpu_transcoder);
    unsigned int i, len = DIP_HEADER_SIZE + frame->len;
    u32 val = I915_READ(ctl_reg);
  
  

@@ -568,7 +569,7 @@ static void hsw_set_infoframes(struct drm_encoder *encoder, struct drm_i915_private *dev_priv = encoder->dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);

•   u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
  

•   u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->cpu_transcoder);
    u32 val = I915_READ(reg);
  
    assert_hdmi_port_disabled(intel_hdmi);
  

-- 1.8.1.2

---

Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

On Mon, Feb 25, 2013 at 07:55:17PM -0300, Rodrigo Vivi wrote:

From: Shobhit Kumar shobhit.kumar@intel.com

Signed-off-by: Sateesh Kavuri sateesh.kavuri@intel.com

v2: Modified and corrected the structures to be more in line for kernel coding guidelines and rebased the code on Paulo's DP patchset

Signed-off-by: Shobhit Kumar shobhit.kumar@intel.com

v3: removing unecessary identation at DP_RECEIVER_CAP_SIZE v4: moving them to include/drm/drm_dp_helper.h and also already icluding EDP_PSR_RECEIVER_CAP_SIZE to add everything needed for PSR at once at drm_dp_helper.h

Signed-off-by: Rodrigo Vivi rodrigo.vivi@gmail.com

Bikeshed for your patch headlines: You still have drm/i915 there, despite that the #defines and structures are now moved to the drm core dp helpers. Non-Intel people might simply ignore the patches in that case. -Daniel

---

include/drm/drm_dp_helper.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index e8e1417..06c5060 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -343,12 +343,34 @@ u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE], int lane);

#define DP_RECEIVER_CAP_SIZE 0xf +#define EDP_PSR_RECEIVER_CAP_SIZE 2

void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]); void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]);

u8 drm_dp_link_rate_to_bw_code(int link_rate); int drm_dp_bw_code_to_link_rate(u8 link_bw);

+/* SDP header as per eDP 1.3 spec, section 3.6 */ +struct edp_sdp_header {

• u8 id;
• u8 type;
• u8 revision;
• u8 valid_payload_bytes;

+} __attribute__((packed));

+/* SDP VSC header as per eDP 1.3 spec, section 3.6 */ +struct edp_vsc_psr {

• struct edp_sdp_header sdp_header;
• u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid*/
• u8 DB2; /* CRC value bits 7:0 of the R or Cr component */
• u8 DB3; /* CRC value bits 15:8 of the R or Cr component */
• u8 DB4; /* CRC value bits 7:0 of the G or Y component */
• u8 DB5; /* CRC value bits 15:8 of the G or Y component */
• u8 DB6; /* CRC value bits 7:0 of the B or Cb component */
• u8 DB7; /* CRC value bits 15:8 of the B or Cb component */

+} __attribute__((packed));

static inline int drm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE]) { -- 1.8.1.2

---

Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

On Mon, Feb 25, 2013 at 07:55:18PM -0300, Rodrigo Vivi wrote:

From: Shobhit Kumar shobhit.kumar@intel.com

Signed-off-by: Shobhit Kumar shobhit.kumar@intel.com

v2: reuse of just created is_edp_psr and put it at right place.

Signed-off-by: Rodrigo Vivi rodrigo.vivi@gmail.com Reviewed-by: Jani Nikula jani.nikula@intel.com

---

drivers/gpu/drm/i915/intel_dp.c | 13 +++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 1 + 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index b4494a2..5cfa9f4 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1437,6 +1437,12 @@ static void intel_post_disable_dp(struct intel_encoder *encoder) } }

+static bool is_edp_psr(struct intel_dp *intel_dp) +{

• return (is_edp(intel_dp) &&

• (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED));
  

This should probably also check the setup time vs. vblank restriction.

+}

static void intel_enable_dp(struct intel_encoder *encoder) { struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); @@ -2117,6 +2123,13 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) if (intel_dp->dpcd[DP_DPCD_REV] == 0) return false; /* DPCD not present */

• /* Check if the panel supports PSR */
• memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
• intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,

• 		       intel_dp->psr_dpcd,
  

• 		       sizeof(intel_dp->psr_dpcd));
  

• if (is_edp_psr(intel_dp))

• DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
  

  if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) return true; /* native DP sink */

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 005a91f..865ede6 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -375,6 +375,7 @@ struct intel_dp { uint8_t link_bw; uint8_t lane_count; uint8_t dpcd[DP_RECEIVER_CAP_SIZE];

• uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; struct i2c_adapter adapter; struct i2c_algo_dp_aux_data algo;

-- 1.8.1.2

---

dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel

On Mon, Feb 25, 2013 at 07:55:20PM -0300, Rodrigo Vivi wrote:

Adding Enable and Disable PSR functionalities. This includes setting the PSR configuration over AUX, sending SDP VSC DIP over the eDP PIPE config, enabling PSR in the sink via DPCD register and finally enabling PSR on the host.

This patch is heavily based on initial PSR code by Sateesh Kavuri and Kumar Shobhit but in a different implementation.

Credits-by: Sateesh Kavuri sateesh.kavuri@intel.com Credits-by: Shobhit Kumar shobhit.kumar@intel.com Signed-off-by: Rodrigo Vivi rodrigo.vivi@gmail.com

---

drivers/gpu/drm/i915/i915_reg.h | 40 +++++++++ drivers/gpu/drm/i915/intel_dp.c | 183 +++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 3 + 3 files changed, 226 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b715ecd..1e31f23 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -844,6 +844,8 @@ #define SNB_CPU_FENCE_ENABLE (1<<29) #define DPFC_CPU_FENCE_OFFSET 0x100104

+/* Framebuffer compression for Haswell */ +#define HSW_FBC_CONTROL 0x43208

/*

• GPIO regs

@@ -1580,6 +1582,44 @@ #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B) #define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)

+/* HSW eDP PSR registers */ +#define EDP_PSR_CTL 0x64800 +#define EDP_PSR_ENABLE (1<<31) +#define EDP_PSR_LINK_DISABLE (0<<27) +#define EDP_PSR_LINK_STANDBY (1<<27) +#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25) +#define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25) +#define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25) +#define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25) +#define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25) +#define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20 +#define EDP_PSR_SKIP_AUX_EXIT (1<<12) +#define EDP_PSR_TP1_TP2_SEL (0<<11) +#define EDP_PSR_TP1_TP3_SEL (1<<11) +#define EDP_PSR_TP2_TP3_TIME_500us (0<<8) +#define EDP_PSR_TP2_TP3_TIME_100us (1<<8) +#define EDP_PSR_TP2_TP3_TIME_2500us (2<<8) +#define EDP_PSR_TP2_TP3_TIME_0us (3<<8) +#define EDP_PSR_TP1_TIME_500us (0<<4) +#define EDP_PSR_TP1_TIME_100us (1<<4) +#define EDP_PSR_TP1_TIME_2500us (2<<4) +#define EDP_PSR_TP1_TIME_0us (3<<4) +#define EDP_PSR_IDLE_FRAME_SHIFT 0

+#define EDP_PSR_AUX_CTL 0x64810 +#define EDP_PSR_AUX_DATA1 0x64814 +#define EDP_PSR_AUX_DATA2 0x64818 +#define EDP_PSR_AUX_DATA3 0x6481c +#define EDP_PSR_AUX_DATA4 0x64820 +#define EDP_PSR_AUX_DATA5 0x64824

+#define EDP_PSR_STATUS_CTL 0x64840 +#define EDP_PSR_STATUS_STATE_MASK (7<<29)

+#define EDP_PSR_DEBUG_CTL 0x64860 +#define EDP_PSR_DEBUG_MASK_MEMUP (1<<26) +#define EDP_PSR_DEBUG_MASK_HPD (1<<25)

/* VGA port control */ #define ADPA 0x61100 #define PCH_ADPA 0xe1100 diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 5cfa9f4..a420f0d 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -83,6 +83,13 @@ static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) return intel_dig_port->base.base.dev; }

+static struct drm_crtc *intel_dp_to_crtc(struct intel_dp *intel_dp) +{

• struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
• return intel_dig_port->base.base.crtc;

+}

static struct intel_dp *intel_attached_dp(struct drm_connector *connector) { return enc_to_intel_dp(&intel_attached_encoder(connector)->base); @@ -1443,6 +1450,182 @@ static bool is_edp_psr(struct intel_dp *intel_dp) (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED)); }

+static bool +intel_edp_is_psr_enabled(struct intel_dp* intel_dp) +{

• struct drm_device *dev = intel_dp_to_dev(intel_dp);
• struct drm_i915_private *dev_priv = dev->dev_private;
• return I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;

+}

+static void +intel_edp_psr_enable_src(struct intel_dp *intel_dp) +{

• struct drm_device *dev = intel_dp_to_dev(intel_dp);
• struct drm_i915_private *dev_priv = dev->dev_private;
• uint32_t max_sleep_time = 0x1f;
• uint32_t val = 0x0;
• if (dev_priv->vbt.psr_idle_frames)

•    val |= dev_priv->vbt.psr_idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
  

• else

•    val |= 1 << EDP_PSR_IDLE_FRAME_SHIFT;
  

• if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {

• val |= EDP_PSR_LINK_STANDBY;
  

There were some WAs for link standby not working on all revisions. Do we care?

• val |= EDP_PSR_TP2_TP3_TIME_0us;
  

• val |= EDP_PSR_TP1_TIME_0us;
  

• val |= EDP_PSR_SKIP_AUX_EXIT;
  

• } else {

• val |= EDP_PSR_LINK_DISABLE;
  

• /* Use these Values from VBT
  

•  * Case values are timings for HSW as of now
  

•  * in multiple of 100us
  

•  */
  

• switch(dev_priv->vbt.psr_wakeup_tp1) {
  

• 	case 1:
  

• 		val |= EDP_PSR_TP1_TIME_100us;
  

• 		break;
  

• 	case 5:
  

• 		val |= EDP_PSR_TP1_TIME_500us;
  

• 		break;
  

• 	case 25:
  

• 		val |= EDP_PSR_TP1_TIME_2500us;
  

• 		break;
  

• 	default:
  

• 		val |= EDP_PSR_TP1_TIME_500us;
  

• 		break;
  

• };
  

• switch(dev_priv->vbt.psr_wakeup_tp2_tp3) {
  

• 	case 1:
  

• 		val |= EDP_PSR_TP2_TP3_TIME_100us;
  

• 		break;
  

• 	case 5:
  

• 		val |= EDP_PSR_TP2_TP3_TIME_500us;
  

• 		break;
  

• 	case 25:
  

• 		val |= EDP_PSR_TP2_TP3_TIME_2500us;
  

• 		break;
  

• 	default:
  

• 		val |= EDP_PSR_TP2_TP3_TIME_500us;
  

• 		break;
  

• };
  

• }
• I915_WRITE(EDP_PSR_CTL, val |

•    EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES |
  

•    max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
  

•    EDP_PSR_ENABLE);
  

+}

+void intel_edp_write_vsc_psr(struct intel_dp* intel_dp,

• 	     struct edp_vsc_psr *vsc_psr)
  

+{

• struct drm_device *dev = intel_dp_to_dev(intel_dp);
• struct drm_i915_private *dev_priv = dev->dev_private;
• struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp_to_crtc(intel_dp));
• u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->cpu_transcoder);
• u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(intel_crtc->cpu_transcoder);
• uint32_t *data = (uint32_t *)vsc_psr;
• unsigned int i;
• u32 val = I915_READ(ctl_reg);
• if (data_reg == 0)

• return;
  

• /* As per eDP spec, wait for vblank to send SDP VSC packet */
• intel_wait_for_vblank(dev, intel_crtc->pipe);

Is this really needed? Isn't the SDP stuff sent out during vblank by definition?

• mmiowb();
• for (i = 0; i < sizeof(struct edp_vsc_psr); i += 4) {

• I915_WRITE(data_reg + i, *data);
  

• data++;
  

• }
• /* Write every possible data byte to force correct ECC calculation. */
• for (; i < VIDEO_DIP_DATA_SIZE; i += 4)

• I915_WRITE(data_reg + i, 0);
  

• mmiowb();
• val |= VIDEO_DIP_ENABLE_VSC_HSW;
• I915_WRITE(ctl_reg, val);
• POSTING_READ(ctl_reg);

+}

+void intel_edp_enable_psr(struct intel_dp* intel_dp) +{

• struct drm_device *dev = intel_dp_to_dev(intel_dp);
• struct drm_i915_private *dev_priv = dev->dev_private;
• struct edp_vsc_psr psr_vsc;
• int msg_size = 5; /* Header(4) + Message(1) */
• if (!is_edp_psr(intel_dp) || intel_edp_is_psr_enabled(intel_dp))

• return;
  

• /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
• memset(&psr_vsc, 0, sizeof(psr_vsc));
• psr_vsc.sdp_header.id = 0;
• psr_vsc.sdp_header.type = 0x7;
• psr_vsc.sdp_header.revision = 0x2;
• psr_vsc.sdp_header.valid_payload_bytes = 0x8;
• intel_edp_write_vsc_psr(intel_dp, &psr_vsc);
• /* Enable PSR in sink by setting bit 0 in DPCD config reg

• * along with the transmitter state during PSR active
  

• * Transmitter state later can be ready from VBT. As of now
  

• * program the full link down
  

• *
  

• */
  

• intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,

• 		    DP_PSR_ENABLE);
  

• /* Setup AUX registers */
• /* Write command on DPCD 0x0600 */
• I915_WRITE(EDP_PSR_AUX_DATA1, 0x80060000);
• /* Set the state to normal operation D0 in DPCD 0x0600 */
• I915_WRITE(EDP_PSR_AUX_DATA2, 0x01000000);
• I915_WRITE(EDP_PSR_AUX_CTL,

•    msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT |
  

•    I915_READ(DPA_AUX_CH_CTL));
  

Would it be possible to make this stuff a bit more like the normal aux stuff? Maybe even share some code to set up the data? But then again it's just these few writes here, so I'm not sure it's worth the effort.

• /* Enable PSR on the host */
• intel_edp_psr_enable_src(intel_dp);
• /* WA: FBC/PSR Underrun/Corruption Workaround */
• I915_WRITE(HSW_FBC_CONTROL, ~FBC_CTL_EN);

Are we expecting that BIOS left FBC enabled? Shouldn't we then disable it during resume?

• /* WA: Continuous PSR exit Workaround */
• I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP);

Shouldn't this be done before enabling PSR?

• I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);

I can't find anything about this in bspec or WA db.

+}

+void intel_edp_disable_psr(struct intel_dp* intel_dp) +{

• struct drm_device *dev = intel_dp_to_dev(intel_dp);
• struct drm_i915_private *dev_priv = dev->dev_private;
• struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp_to_crtc(intel_dp));
• uint32_t reg = HSW_TVIDEO_DIP_CTL(intel_crtc->cpu_transcoder);
• uint32_t val;
• if (!intel_edp_is_psr_enabled(intel_dp))

• return;
  

• val = I915_READ(EDP_PSR_CTL);
• I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
• /* Wait till PSR is idle */
• if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL) &

•        EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
  

• DRM_ERROR("Timed out waiting for PSR Idle State\n");
  

• intel_wait_for_vblank(dev, intel_crtc->pipe);
• val = I915_READ(reg);
• I915_WRITE(reg, val & ~VIDEO_DIP_ENABLE_VSC_HSW);

+}

static void intel_enable_dp(struct intel_encoder *encoder) { struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 865ede6..cfda739 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -696,4 +696,7 @@ extern bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);

+extern void intel_edp_enable_psr(struct intel_dp* intel_dp); +extern void intel_edp_disable_psr(struct intel_dp* intel_dp);

#endif /* __INTEL_DRV_H__ */

1.8.1.2

---

dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel

Hi

So now I finally have the correct spec in hands!

2013/2/25 Rodrigo Vivi rodrigo.vivi@gmail.com:

Adding Enable and Disable PSR functionalities. This includes setting the PSR configuration over AUX, sending SDP VSC DIP over the eDP PIPE config, enabling PSR in the sink via DPCD register and finally enabling PSR on the host.

This patch is heavily based on initial PSR code by Sateesh Kavuri and Kumar Shobhit but in a different implementation.

Credits-by: Sateesh Kavuri sateesh.kavuri@intel.com Credits-by: Shobhit Kumar shobhit.kumar@intel.com Signed-off-by: Rodrigo Vivi rodrigo.vivi@gmail.com

---

drivers/gpu/drm/i915/i915_reg.h | 40 +++++++++ drivers/gpu/drm/i915/intel_dp.c | 183 +++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 3 + 3 files changed, 226 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b715ecd..1e31f23 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -844,6 +844,8 @@ #define SNB_CPU_FENCE_ENABLE (1<<29) #define DPFC_CPU_FENCE_OFFSET 0x100104

+/* Framebuffer compression for Haswell */ +#define HSW_FBC_CONTROL 0x43208

/*

• GPIO regs

@@ -1580,6 +1582,44 @@ #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B) #define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)

+/* HSW eDP PSR registers */ +#define EDP_PSR_CTL 0x64800 +#define EDP_PSR_ENABLE (1<<31) +#define EDP_PSR_LINK_DISABLE (0<<27) +#define EDP_PSR_LINK_STANDBY (1<<27) +#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25) +#define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25) +#define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25) +#define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25) +#define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25) +#define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20 +#define EDP_PSR_SKIP_AUX_EXIT (1<<12) +#define EDP_PSR_TP1_TP2_SEL (0<<11) +#define EDP_PSR_TP1_TP3_SEL (1<<11) +#define EDP_PSR_TP2_TP3_TIME_500us (0<<8) +#define EDP_PSR_TP2_TP3_TIME_100us (1<<8) +#define EDP_PSR_TP2_TP3_TIME_2500us (2<<8) +#define EDP_PSR_TP2_TP3_TIME_0us (3<<8) +#define EDP_PSR_TP1_TIME_500us (0<<4) +#define EDP_PSR_TP1_TIME_100us (1<<4) +#define EDP_PSR_TP1_TIME_2500us (2<<4) +#define EDP_PSR_TP1_TIME_0us (3<<4) +#define EDP_PSR_IDLE_FRAME_SHIFT 0

+#define EDP_PSR_AUX_CTL 0x64810 +#define EDP_PSR_AUX_DATA1 0x64814 +#define EDP_PSR_AUX_DATA2 0x64818 +#define EDP_PSR_AUX_DATA3 0x6481c +#define EDP_PSR_AUX_DATA4 0x64820 +#define EDP_PSR_AUX_DATA5 0x64824

+#define EDP_PSR_STATUS_CTL 0x64840 +#define EDP_PSR_STATUS_STATE_MASK (7<<29)

+#define EDP_PSR_DEBUG_CTL 0x64860 +#define EDP_PSR_DEBUG_MASK_MEMUP (1<<26) +#define EDP_PSR_DEBUG_MASK_HPD (1<<25)

/* VGA port control */ #define ADPA 0x61100 #define PCH_ADPA 0xe1100 diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 5cfa9f4..a420f0d 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -83,6 +83,13 @@ static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) return intel_dig_port->base.base.dev; }

+static struct drm_crtc *intel_dp_to_crtc(struct intel_dp *intel_dp) +{

•   struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  

•   return intel_dig_port->base.base.crtc;
  

+}

static struct intel_dp *intel_attached_dp(struct drm_connector *connector) { return enc_to_intel_dp(&intel_attached_encoder(connector)->base); @@ -1443,6 +1450,182 @@ static bool is_edp_psr(struct intel_dp *intel_dp) (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED)); }

+static bool +intel_edp_is_psr_enabled(struct intel_dp* intel_dp) +{

•   struct drm_device *dev = intel_dp_to_dev(intel_dp);
  

•   struct drm_i915_private *dev_priv = dev->dev_private;
  

•   return I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
  

+}

+static void +intel_edp_psr_enable_src(struct intel_dp *intel_dp) +{

•   struct drm_device *dev = intel_dp_to_dev(intel_dp);
  

•   struct drm_i915_private *dev_priv = dev->dev_private;
  

•   uint32_t max_sleep_time = 0x1f;
  

•   uint32_t val = 0x0;
  

•   if (dev_priv->vbt.psr_idle_frames)
  

•       val |= dev_priv->vbt.psr_idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
  

•   else
  

•       val |= 1 << EDP_PSR_IDLE_FRAME_SHIFT;
  

•   if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
  

•           val |= EDP_PSR_LINK_STANDBY;
  

If we set this bit, shouldn't we also set DPCD 0x170 bit 1 to 1?

•           val |= EDP_PSR_TP2_TP3_TIME_0us;
  

•           val |= EDP_PSR_TP1_TIME_0us;
  

•           val |= EDP_PSR_SKIP_AUX_EXIT;
  

•   } else {
  

•           val |= EDP_PSR_LINK_DISABLE;
  

•           /* Use these Values from VBT
  

•            * Case values are timings for HSW as of now
  

•            * in multiple of 100us
  

•            */
  

•           switch(dev_priv->vbt.psr_wakeup_tp1) {
  

•                   case 1:
  

•                           val |= EDP_PSR_TP1_TIME_100us;
  

•                           break;
  

•                   case 5:
  

•                           val |= EDP_PSR_TP1_TIME_500us;
  

•                           break;
  

•                   case 25:
  

•                           val |= EDP_PSR_TP1_TIME_2500us;
  

•                           break;
  

•                   default:
  

•                           val |= EDP_PSR_TP1_TIME_500us;
  

•                           break;
  

•           };
  

•           switch(dev_priv->vbt.psr_wakeup_tp2_tp3) {
  

•                   case 1:
  

•                           val |= EDP_PSR_TP2_TP3_TIME_100us;
  

•                           break;
  

•                   case 5:
  

•                           val |= EDP_PSR_TP2_TP3_TIME_500us;
  

•                           break;
  

•                   case 25:
  

•                           val |= EDP_PSR_TP2_TP3_TIME_2500us;
  

•                           break;
  

•                   default:
  

•                           val |= EDP_PSR_TP2_TP3_TIME_500us;
  

•                           break;
  

•           };
  

•   }
  

•   I915_WRITE(EDP_PSR_CTL, val |
  

•              EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES |
  

•              max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
  

•              EDP_PSR_ENABLE);
  

+}

+void intel_edp_write_vsc_psr(struct intel_dp* intel_dp,

•                        struct edp_vsc_psr *vsc_psr)
  

+{

•   struct drm_device *dev =  intel_dp_to_dev(intel_dp);
  

•   struct drm_i915_private *dev_priv = dev->dev_private;
  

•   struct intel_crtc *intel_crtc =  to_intel_crtc(intel_dp_to_crtc(intel_dp));
  

I'd reorganize the declarations to avoid calling both intel_dp_to_crtc and intel_dp_to_dev :)

•   u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->cpu_transcoder);
  

Please don't preserve the register contents here. We don't use this register anywhere else for DP yet.

•   u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(intel_crtc->cpu_transcoder);
  

•   uint32_t *data = (uint32_t *)vsc_psr;
  

•   unsigned int i;
  

•   u32 val = I915_READ(ctl_reg);
  

•   if (data_reg == 0)
  

•           return;
  

I don't think this is ever expected, so you could probably WARN() or BUG() here. I see this statement comes from hsw_write_infoframe (intel_hdmi.c), we should probably try to do the WARN/BUG there too.

•   /* As per eDP spec, wait for vblank to send SDP VSC packet */
  

•   intel_wait_for_vblank(dev, intel_crtc->pipe);
  

Please see BSpec page "Pipe Video Data Island Packet". After waiting the vsync you need to disable the DIP first, then write the data.

•   mmiowb();
  

•   for (i = 0; i < sizeof(struct edp_vsc_psr); i += 4) {
  

•           I915_WRITE(data_reg + i, *data);
  

•           data++;
  

•   }
  

•   /* Write every possible data byte to force correct ECC calculation. */
  

•   for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
  

•           I915_WRITE(data_reg + i, 0);
  

•   mmiowb();
  

•   val |= VIDEO_DIP_ENABLE_VSC_HSW;
  

•   I915_WRITE(ctl_reg, val);
  

•   POSTING_READ(ctl_reg);
  

According to the PSR enabling guide, "HW also enables VSC DIP when required", so I guess the 3 lines above are not needed.

+}

+void intel_edp_enable_psr(struct intel_dp* intel_dp) +{

•   struct drm_device *dev = intel_dp_to_dev(intel_dp);
  

•   struct drm_i915_private *dev_priv = dev->dev_private;
  

•   struct edp_vsc_psr psr_vsc;
  

•   int msg_size = 5;       /* Header(4) + Message(1) */
  

•   if (!is_edp_psr(intel_dp) || intel_edp_is_psr_enabled(intel_dp))
  

Is it possible to have intel_edp_is_psr_enable here? If not, maybe WARN it.

•           return;
  

•   /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
  

•   memset(&psr_vsc, 0, sizeof(psr_vsc));
  

•   psr_vsc.sdp_header.id = 0;
  

•   psr_vsc.sdp_header.type = 0x7;
  

•   psr_vsc.sdp_header.revision = 0x2;
  

•   psr_vsc.sdp_header.valid_payload_bytes = 0x8;
  

•   intel_edp_write_vsc_psr(intel_dp, &psr_vsc);
  

•   /* Enable PSR in sink by setting bit 0 in DPCD config reg
  

•    * along with the transmitter state during PSR active
  

•    * Transmitter state later can be ready from VBT. As of now
  

•    * program the full link down
  

This comment is probably missing a few periods.

•    *
  

•    */
  

•   intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
  

•                               DP_PSR_ENABLE);
  

•   /* Setup AUX registers */
  

•   /* Write command on DPCD 0x0600 */
  

•   I915_WRITE(EDP_PSR_AUX_DATA1, 0x80060000);
  

•   /* Set the state to normal operation D0 in DPCD 0x0600 */
  

•   I915_WRITE(EDP_PSR_AUX_DATA2, 0x01000000);
  

I see the lines above match our spec, but I still think Jani's comment from patch "drm/i915: Setup EDP PSR AUX Registers" is applicable here.

•   I915_WRITE(EDP_PSR_AUX_CTL,
  

•              msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT |
  

•              I915_READ(DPA_AUX_CH_CTL));
  

I don't think this is safe, especially since we're not erasing the original msg size bits from DPA_AUX_CH_CTL. I think we should try to set all the bits of this register without reading DPA_AUX_CH_CTL (maybe extract some code from intel_dp_aux_ch into new functions and call from both here and intel_dp_aux_ch).

Also, I still think you should patch intel_dp_aux_ch to put a WARN in case EDP_PSR_CTL bit 31 is 1.

•   /* Enable PSR on the host */
  

•   intel_edp_psr_enable_src(intel_dp);
  

•   /* WA: FBC/PSR Underrun/Corruption Workaround */
  

•   I915_WRITE(HSW_FBC_CONTROL, ~FBC_CTL_EN);
  

This FBC WA won't be needed on real world Hardware.

•   /* WA: Continuous PSR exit Workaround */
  

•   I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP);
  

•   I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
  

All they ask is to "disabled unused interrupts", not "disable all interrupts".

+}

+void intel_edp_disable_psr(struct intel_dp* intel_dp) +{

•   struct drm_device *dev = intel_dp_to_dev(intel_dp);
  

•   struct drm_i915_private *dev_priv = dev->dev_private;
  

•   struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp_to_crtc(intel_dp));
  

•   uint32_t reg = HSW_TVIDEO_DIP_CTL(intel_crtc->cpu_transcoder);
  

•   uint32_t val;
  

•   if (!intel_edp_is_psr_enabled(intel_dp))
  

Is this possible? Should we WARN here?

•           return;
  

•   val = I915_READ(EDP_PSR_CTL);
  

•   I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
  

•   /* Wait till PSR is idle */
  

•   if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
  

•                  EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
  

Some big sleeps here. Can't we make them faster?

•           DRM_ERROR("Timed out waiting for PSR Idle State\n");
  

•   intel_wait_for_vblank(dev, intel_crtc->pipe);
  

•   val = I915_READ(reg);
  

•   I915_WRITE(reg, val & ~VIDEO_DIP_ENABLE_VSC_HSW);
  

So, based on this and on the spec, it means the HW will automagically do the link training for us if it's needed?

+}

static void intel_enable_dp(struct intel_encoder *encoder) { struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 865ede6..cfda739 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -696,4 +696,7 @@ extern bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);

+extern void intel_edp_enable_psr(struct intel_dp* intel_dp); +extern void intel_edp_disable_psr(struct intel_dp* intel_dp);

#endif /* __INTEL_DRV_H__ */

1.8.1.2

---

dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel

Hi

2013/2/25 Rodrigo Vivi rodrigo.vivi@gmail.com:

Adding support for PSR Status, PSR entry counter and performance counters. Heavily based on initial work from Shobhit.

Credits-by: Shobhit Kumar shobhit.kumar@intel.com Signed-off-by: Rodrigo Vivi rodrigo.vivi@gmail.com

---

drivers/gpu/drm/i915/i915_debugfs.c | 92 +++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 24 ++++++++++ 2 files changed, 116 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 7c65ab8..01021f6 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1680,6 +1680,97 @@ static int i915_dpio_info(struct seq_file *m, void *data) return 0; }

+static int i915_edp_psr_status(struct seq_file *m, void *data) +{

•   struct drm_info_node *node = m->private;
  

•   struct drm_device *dev = node->minor->dev;
  

•   struct drm_i915_private *dev_priv = dev->dev_private;
  

•   unsigned int count;
  

•   u32 psrctl, psrstat, psrperf;
  

•   psrctl = I915_READ(EDP_PSR_CTL);
  

•   seq_printf(m, "PSR Enabled: %s\n",
  

•              yesno(psrctl & EDP_PSR_ENABLE));
  

•   psrstat = I915_READ(EDP_PSR_STATUS_CTL);
  

•   seq_printf(m, "PSR Current State: ");
  

•   switch (psrstat & EDP_PSR_STATUS_STATE_MASK) {
  

•   case EDP_PSR_STATUS_STATE_IDLE:
  

•           seq_printf(m, "Reset state\n");
  

•           break;
  

•   case EDP_PSR_STATUS_STATE_SRDONACK:
  

•           seq_printf(m, "Wait for TG/Stream to send on frame of data after SRD conditions are met\n");
  

•           break;
  

•   case EDP_PSR_STATUS_STATE_SRDENT:
  

•           seq_printf(m, "SRD entry\n");
  

•           break;
  

•   case EDP_PSR_STATUS_STATE_BUFOFF:
  

•           seq_printf(m, "Wait for buffer turn off\n");
  

•           break;
  

•   case EDP_PSR_STATUS_STATE_BUFON:
  

•                   seq_printf(m, "Wait for buffer turn on\n");
  

•           break;
  

•   case EDP_PSR_STATUS_STATE_AUXACK:
  

•                   seq_printf(m, "Wait for AUX to acknowledge on SRD exit\n");
  

•           break;
  

•   case EDP_PSR_STATUS_STATE_SRDOFFACK:
  

•                   seq_printf(m, "Wait for TG/Stream to acknowledge the SRD VDM exit\n");
  

•           break;
  

•   default:
  

•           seq_printf(m, "Unknown\n");
  

•           break;
  

•   }
  

•   seq_printf(m, "Link Status: ");
  

•   switch (psrstat & EDP_PSR_STATUS_LINK_MASK) {
  

•   case EDP_PSR_STATUS_LINK_FULL_OFF:
  

•           seq_printf(m, "Link is fully off\n");
  

•           break;
  

•   case EDP_PSR_STATUS_LINK_FULL_ON:
  

•           seq_printf(m, "Link is fully on\n");
  

•           break;
  

•   case EDP_PSR_STATUS_LINK_STANDBY:
  

•           seq_printf(m, "Link is in standby\n");
  

•           break;
  

•   default:
  

•           seq_printf(m, "Unknown\n");
  

•           break;
  

•   }
  

•   seq_printf(m, "PSR Entry Count: %u\n",
  

•              psrstat >> EDP_PSR_STATUS_COUNT_SHIFT &
  

•              EDP_PSR_STATUS_COUNT_MASK);
  

•   seq_printf(m, "Max Sleep Timer Counter: %u\n",
  

•              psrstat >> EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT &
  

•              EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK);
  

•   seq_printf(m, "Had AUX error: %s\n",
  

•              yesno(psrstat & EDP_PSR_STATUS_AUX_ERROR));
  

•   seq_printf(m, "Sending AUX: %s\n",
  

•              yesno(psrstat & EDP_PSR_STATUS_AUX_SENDING));
  

•   seq_printf(m, "Sending Idle: %s\n",
  

•              yesno(psrstat & EDP_PSR_STATUS_SENDING_IDLE));
  

•   seq_printf(m, "Sending TP2 TP3: %s\n",
  

•              yesno(psrstat & EDP_PSR_STATUS_SENDING_TP2_TP3));
  

•   seq_printf(m, "Sending TP1: %s\n",
  

•              yesno(psrstat & EDP_PSR_STATUS_SENDING_TP1));
  

•   seq_printf(m, "Idle Count: %u\n",
  

•              psrstat & EDP_PSR_STATUS_IDLE_MASK);
  

•   psrperf = (I915_READ(EDP_PSR_PERF_CNT)) & EDP_PSR_PERF_CNT_MASK;
  

•   seq_printf(m, "Performance Counter: %u\n", psrperf);
  

•   return 0;
  

+}

static ssize_t i915_wedged_read(struct file *filp, char __user *ubuf, @@ -2249,6 +2340,7 @@ static struct drm_info_list i915_debugfs_list[] = { {"i915_swizzle_info", i915_swizzle_info, 0}, {"i915_ppgtt_info", i915_ppgtt_info, 0}, {"i915_dpio", i915_dpio_info, 0},

•   {"i915_edp_psr_status", i915_edp_psr_status, 0},
  

}; #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1e31f23..1f7e666 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1615,6 +1615,30 @@

#define EDP_PSR_STATUS_CTL 0x64840 #define EDP_PSR_STATUS_STATE_MASK (7<<29) +#define EDP_PSR_STATUS_STATE_IDLE (0<<29) +#define EDP_PSR_STATUS_STATE_SRDONACK (1<<29) +#define EDP_PSR_STATUS_STATE_SRDENT (2<<29) +#define EDP_PSR_STATUS_STATE_BUFOFF (3<<29) +#define EDP_PSR_STATUS_STATE_BUFON (4<<29) +#define EDP_PSR_STATUS_STATE_AUXACK (5<<29) +#define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29) +#define EDP_PSR_STATUS_LINK_MASK (3<<29) +#define EDP_PSR_STATUS_LINK_FULL_OFF (0<<29) +#define EDP_PSR_STATUS_LINK_FULL_ON (1<<29) +#define EDP_PSR_STATUS_LINK_STANDBY (2<<29)

The 4 lines above are wrong. It's (x<<26).

+#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20 +#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f +#define EDP_PSR_STATUS_COUNT_SHIFT 16 +#define EDP_PSR_STATUS_COUNT_MASK 0xf +#define EDP_PSR_STATUS_AUX_ERROR (1<<15) +#define EDP_PSR_STATUS_AUX_SENDING (1<<12) +#define EDP_PSR_STATUS_SENDING_IDLE (1<<9) +#define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8) +#define EDP_PSR_STATUS_SENDING_TP1 (1<<4) +#define EDP_PSR_STATUS_IDLE_MASK 0xf

+#define EDP_PSR_PERF_CNT 0x64844 +#define EDP_PSR_PERF_CNT_MASK 0xffffff

#define EDP_PSR_DEBUG_CTL 0x64860

#define EDP_PSR_DEBUG_MASK_MEMUP (1<<26)

1.8.1.2

---

Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Hi

2013/2/25 Rodrigo Vivi rodrigo.vivi@gmail.com:

PSR must be enabled after transcoder and port are running. And it is only available for HSW.

v2: move enable/disable to intel_ddi

Signed-off-by: Rodrigo Vivi rodrigo.vivi@gmail.com

drivers/gpu/drm/i915/intel_ddi.c | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 816c45c..bbfdcfd 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1321,6 +1321,7 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder) struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

            ironlake_edp_backlight_on(intel_dp);

•           intel_edp_enable_psr(intel_dp);
    }
  
    if (intel_crtc->eld_vld) {
  

@@ -1345,6 +1346,7 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder) struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

            ironlake_edp_backlight_off(intel_dp);

•           intel_edp_disable_psr(intel_dp);
  

The spec suggests PSR should be disabled even before backlight (it also suggests audio should be disabled before backlight, and I notice this seems to be wrong in our code).

    }

    tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);

-- 1.8.1.2

---

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