Instead of using _PAGE_RW and _PAGE_PRESENT to check for 0 and 1 bits, this series replaces them with GEN6_PTE_VALID and BYT_PTE_WRITEABLE. We should be using macros defined for i915 to check these bits, instead of macros defined by the mmu. Some arch does not have these macros defined, thus leading to compilation errors.
v2: Corrected sender's email.
v3: Corrected spelling error.
v4: Clean up a few other macros that are checking 0 and 1 bits.
v5: Instead of introducing new macros for checking 0 and 1 bits, re-use already defined macros for i915.
Michael Cheng (1): drm/i915: Re-use i915 macros for checking PTEs
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 6 +++--- drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +- drivers/gpu/drm/i915/gvt/gtt.c | 12 ++++++------ 3 files changed, 10 insertions(+), 10 deletions(-)
Certain gen8 ppgtt/gtt functions are using _PAGE_RW and _PAGE_PRESENT to check bits 0 and 1 for PTEs. These macros are defined per architectures, and some architectures do not have these defined (like arm64). This patch replaces these two macros with their i915 equivalent implementation.
Signed-off-by: Michael Cheng michael.cheng@intel.com --- drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 6 +++--- drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +- drivers/gpu/drm/i915/gvt/gtt.c | 12 ++++++------ 3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c index 9966e9dc5218..cc484cc6c26f 100644 --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c @@ -18,7 +18,7 @@ static u64 gen8_pde_encode(const dma_addr_t addr, const enum i915_cache_level level) { - u64 pde = addr | _PAGE_PRESENT | _PAGE_RW; + u64 pde = addr | GEN6_PTE_VALID | BYT_PTE_WRITEABLE;
if (level != I915_CACHE_NONE) pde |= PPAT_CACHED_PDE; @@ -32,10 +32,10 @@ static u64 gen8_pte_encode(dma_addr_t addr, enum i915_cache_level level, u32 flags) { - gen8_pte_t pte = addr | _PAGE_PRESENT | _PAGE_RW; + gen8_pte_t pte = addr | GEN6_PTE_VALID | BYT_PTE_WRITEABLE;
if (unlikely(flags & PTE_READ_ONLY)) - pte &= ~_PAGE_RW; + pte &= ~BYT_PTE_WRITEABLE;
if (flags & PTE_LM) pte |= GEN12_PPGTT_PTE_LM; diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index 555111c3bee5..76495deaddc2 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -209,7 +209,7 @@ u64 gen8_ggtt_pte_encode(dma_addr_t addr, enum i915_cache_level level, u32 flags) { - gen8_pte_t pte = addr | _PAGE_PRESENT; + gen8_pte_t pte = addr | GEN6_PTE_VALID;
if (flags & PTE_LM) pte |= GEN12_GGTT_PTE_LM; diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c index 53d0cb327539..e481b639ba0a 100644 --- a/drivers/gpu/drm/i915/gvt/gtt.c +++ b/drivers/gpu/drm/i915/gvt/gtt.c @@ -446,17 +446,17 @@ static bool gen8_gtt_test_present(struct intel_gvt_gtt_entry *e) || e->type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY) return (e->val64 != 0); else - return (e->val64 & _PAGE_PRESENT); + return (e->val64 & GEN6_PTE_VALID); }
static void gtt_entry_clear_present(struct intel_gvt_gtt_entry *e) { - e->val64 &= ~_PAGE_PRESENT; + e->val64 &= ~GEN6_PTE_VALID; }
static void gtt_entry_set_present(struct intel_gvt_gtt_entry *e) { - e->val64 |= _PAGE_PRESENT; + e->val64 |= GEN6_PTE_VALID; }
static bool gen8_gtt_test_64k_splited(struct intel_gvt_gtt_entry *e) @@ -2439,7 +2439,7 @@ static int alloc_scratch_pages(struct intel_vgpu *vgpu, /* The entry parameters like present/writeable/cache type * set to the same as i915's scratch page tree. */ - se.val64 |= _PAGE_PRESENT | _PAGE_RW; + se.val64 |= GEN6_PTE_VALID | BYT_PTE_WRITEABLE; if (type == GTT_TYPE_PPGTT_PDE_PT) se.val64 |= PPAT_CACHED;
@@ -2896,7 +2896,7 @@ void intel_gvt_restore_ggtt(struct intel_gvt *gvt) offset = vgpu_aperture_gmadr_base(vgpu) >> PAGE_SHIFT; for (idx = 0; idx < num_low; idx++) { pte = mm->ggtt_mm.host_ggtt_aperture[idx]; - if (pte & _PAGE_PRESENT) + if (pte & GEN6_PTE_VALID) write_pte64(vgpu->gvt->gt->ggtt, offset + idx, pte); }
@@ -2904,7 +2904,7 @@ void intel_gvt_restore_ggtt(struct intel_gvt *gvt) offset = vgpu_hidden_gmadr_base(vgpu) >> PAGE_SHIFT; for (idx = 0; idx < num_hi; idx++) { pte = mm->ggtt_mm.host_ggtt_hidden[idx]; - if (pte & _PAGE_PRESENT) + if (pte & GEN6_PTE_VALID) write_pte64(vgpu->gvt->gt->ggtt, offset + idx, pte); } }
On Thu, Nov 18, 2021 at 12:54:32PM -0800, Michael Cheng wrote:
Certain gen8 ppgtt/gtt functions are using _PAGE_RW and _PAGE_PRESENT to check bits 0 and 1 for PTEs. These macros are defined per architectures, and some architectures do not have these defined (like arm64). This patch replaces these two macros with their i915 equivalent implementation.
Signed-off-by: Michael Cheng michael.cheng@intel.com
Reviewed-by: Lucas De Marchi lucas.demarchi@intel.com
thanks Lucas De Marchi
dri-devel@lists.freedesktop.org
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Lucas De Marchi -
Michael Cheng