On 2018-05-11 20:58, Sean Paul wrote:

On Fri, May 11, 2018 at 08:19:29PM +0530, Rajesh Yadav wrote:

...

SoCs containing dpu have a MDSS top level wrapper which includes sub-blocks as dpu, dsi, phy, dp etc. MDSS top level wrapper manages common resources like common clocks, power and irq for its sub-blocks.

Currently, in dpu driver, all the power resource management is part of power_handle which manages these resources via a custom implementation. And the resource relationships are not modelled properly in dt. Moreover the irq domain handling code is part of dpu device (which is a child device) due to lack of a dedicated driver for MDSS top level wrapper device.

This change adds dpu_mdss top level driver to handle common clock like - core clock, ahb clock (for register access), main power supply (i.e. gdsc) and irq management. The top level mdss device/driver acts as an interrupt controller and manage hwirq mapping for its child devices.

It implements runtime_pm support for resource management. Child nodes can control these resources via runtime_pm get/put calls on their corresponding devices due to parent child relationship defined in dt.

Changes in v2:

• merge _dpu_mdss_hw_rev_init to dpu_mdss_init (Sean Paul)
• merge _dpu_mdss_get_intr_sources to dpu_mdss_irq (Sean Paul)
• fix indentation for irq_find_mapping call (Sean Paul)
• remove unnecessary goto statements from dpu_mdss_irq (Sean Paul)
• remove redundant param checks from dpu_mdss_irq_mask/unmask (Sean Paul/Jordan Crouse)
• remove redundant param checks from dpu_mdss_irqdomain_map (Sean Paul/Jordan Crouse)
• return error code from dpu_mdss_enable/disable (Sean Paul/Jordan

Crouse)

• remove redundant param check from dpu_mdss_destroy (Sean Paul)
• remove explicit calls to devm_kfree (Sean Paul/Jordan Crouse)
• remove compatibility check from dpu_mdss_init as it is conditionally called from msm_drv (Sean Paul)
• reworked msm_dss_parse_clock() to add return checks for of_property_read_* calls, fix log message and fix alignment issues (Sean Paul/Jordan Crouse)
• remove extra line before dpu_mdss_init (Sean Paul)
• remove redundant param checks from __intr_offset and make it a void function to avoid unnecessary error handling from caller (Jordan Crouse)
• remove redundant param check from dpu_mdss_irq (Jordan Crouse)
• change mdss address space log message to debug and use %pK for kernel pointers (Jordan Crouse)
• remove unnecessary log message from msm_dss_parse_clock (Jordan

Crouse)

• don't export msm_dss_parse_clock since it is used only by dpu driver (Jordan Crouse)

Signed-off-by: Rajesh Yadav ryadav@codeaurora.org

drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 97 --------- drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h | 14 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 9 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 7 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 28 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 11 - drivers/gpu/drm/msm/disp/dpu1/dpu_irq.c | 48 +--- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 6 - drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 2 - drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 254 ++++++++++++++++++++++ drivers/gpu/drm/msm/dpu_io_util.c | 57 +++++ drivers/gpu/drm/msm/msm_drv.c | 26 ++- drivers/gpu/drm/msm/msm_drv.h | 2 +- drivers/gpu/drm/msm/msm_kms.h | 1 + include/linux/dpu_io_util.h | 2 + 16 files changed, 339 insertions(+), 226 deletions(-) create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c

/snip

...

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c new file mode 100644 index 0000000..ce680ea --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c

/snip

...

+int dpu_mdss_init(struct drm_device *dev) +{

• struct platform_device *pdev = to_platform_device(dev->dev);
• struct msm_drm_private *priv = dev->dev_private;
• struct dpu_mdss *dpu_mdss;
• struct dss_module_power *mp;
• int ret = 0;
• dpu_mdss = devm_kzalloc(dev->dev, sizeof(*dpu_mdss), GFP_KERNEL);
• if (!dpu_mdss)

• return -ENOMEM;
  

• dpu_mdss->mmio = msm_ioremap(pdev, "mdss_phys", "mdss_phys");
• if (IS_ERR(dpu_mdss->mmio)) {

• ret = PTR_ERR(dpu_mdss->mmio);
  

remove this ...

...

• DPU_ERROR("mdss register memory map failed: %d\n", ret);
  

• dpu_mdss->mmio = NULL;
  

• return ret;
  

... and replace with return PTR_ERR(dpu_mdss->mmio);

Sure, I'll update in v3.

...

• }
• DRM_DEBUG("mapped mdss address space @%pK\n", dpu_mdss->mmio);
• dpu_mdss->mmio_len = msm_iomap_size(pdev, "mdss_phys");
• mp = &dpu_mdss->mp;
• ret = msm_dss_parse_clock(pdev, mp);
• if (ret) {

• DPU_ERROR("failed to parse clocks, ret=%d\n", ret);
  

• goto clk_parse_err;
  

• }
• ret = msm_dss_get_clk(&pdev->dev, mp->clk_config, mp->num_clk);
• if (ret) {

• DPU_ERROR("failed to get clocks, ret=%d\n", ret);
  

• goto clk_get_error;
  

• }
• ret = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk);
• if (ret) {

• DPU_ERROR("failed to set clock rate, ret=%d\n", ret);
  

• goto clk_rate_error;
  

• }
• dpu_mdss->base.dev = dev;
• dpu_mdss->base.funcs = &mdss_funcs;
• ret = _dpu_mdss_irq_domain_add(dpu_mdss);
• if (ret)

• goto irq_domain_error;
  

• ret = devm_request_irq(dev->dev, platform_get_irq(pdev, 0),

• 	dpu_mdss_irq, 0, "dpu_mdss_isr", dpu_mdss);
  

• if (ret) {

• DPU_ERROR("failed to init irq: %d\n", ret);
  

• goto irq_error;
  

• }
• pm_runtime_enable(dev->dev);
• pm_runtime_get_sync(dev->dev);
• dpu_mdss->hwversion = readl_relaxed(dpu_mdss->mmio);
• pm_runtime_put_sync(dev->dev);
• priv->mdss = &dpu_mdss->base;
• return ret;

+irq_error:

• _dpu_mdss_irq_domain_fini(dpu_mdss);

+irq_domain_error: +clk_rate_error:

• msm_dss_put_clk(mp->clk_config, mp->num_clk);

+clk_get_error:

• devm_kfree(&pdev->dev, mp->clk_config);

+clk_parse_err:

• if (dpu_mdss->mmio)

• msm_iounmap(pdev, dpu_mdss->mmio);
  

• dpu_mdss->mmio = NULL;
• return ret;

+} diff --git a/drivers/gpu/drm/msm/dpu_io_util.c b/drivers/gpu/drm/msm/dpu_io_util.c index a18bc99..c44f33f 100644 --- a/drivers/gpu/drm/msm/dpu_io_util.c +++ b/drivers/gpu/drm/msm/dpu_io_util.c @@ -448,6 +448,63 @@ int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable) } /* msm_dss_enable_clk */ EXPORT_SYMBOL(msm_dss_enable_clk);

+int msm_dss_parse_clock(struct platform_device *pdev,

• struct dss_module_power *mp)
  

+{

• u32 i, rc = 0;
• const char *clock_name;
• u32 rate = 0, max_rate = 0;
• int num_clk = 0;
• if (!pdev || !mp)

• return -EINVAL;
  

• mp->num_clk = 0;
• num_clk = of_property_count_strings(pdev->dev.of_node,

"clock-names");

• if (num_clk <= 0) {

• pr_debug("clocks are not defined\n");
  

• return 0;
  

• }
• mp->clk_config = devm_kzalloc(&pdev->dev,

• 		      sizeof(struct dss_clk) * num_clk,
  

• 		      GFP_KERNEL);
  

• if (!mp->clk_config)

• return -ENOMEM;
  

• for (i = 0; i < num_clk; i++) {

• rc = of_property_read_string_index(pdev->dev.of_node,
  

• 				   "clock-names", i,
  

• 				   &clock_name);
  

• if (rc)
  

• 	break;
  

• strlcpy(mp->clk_config[i].clk_name, clock_name,
  

• 	sizeof(mp->clk_config[i].clk_name));
  

• rc = of_property_read_u32_index(pdev->dev.of_node,
  

• 				"clock-rate", i,
  

• 				&rate);
  

• if (rc)
  

• 	break;
  

• mp->clk_config[i].rate = rate;
  

• if (!mp->clk_config[i].rate)
  

• 	mp->clk_config[i].type = DSS_CLK_AHB;
  

• else
  

• 	mp->clk_config[i].type = DSS_CLK_PCLK;
  

• rc = of_property_read_u32_index(pdev->dev.of_node,
  

• 				"clock-max-rate", i,
  

• 				&max_rate);
  

Hmm, I missed these in my first review, these need new dt bindings. I'm far from an expert on dt bindings, but I think you'll be asked to define these are clocks, and get the rate/max rate information from the clock subsystem instead of breaking it all out like this.

Sean

I have checked the clock-bindings.txt and in the clock consumers example I can see that clock-frequency binding is used, so I'll rename "clock-rate" to "clock-frequency". Regarding max-rate/frequency, I have not see any references for it in clock-bindings.txt. This properties is mainly used in downstream driver, i'll remove it.

Thanks, Rajesh

...

• if (rc)
  

• 	break;
  

• mp->clk_config[i].max_rate = max_rate;
  

• }
• if (!rc)

• mp->num_clk = num_clk;
  

• return rc;

+}

int dpu_i2c_byte_read(struct i2c_client *client, uint8_t slave_addr, uint8_t reg_offset, uint8_t *read_buf) diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 5d8f1b6..a0e73ea 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -503,7 +503,18 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv) ddev->dev_private = priv; priv->dev = ddev;

• ret = mdp5_mdss_init(ddev);

• switch (get_mdp_ver(pdev)) {
• case KMS_MDP5:

• ret = mdp5_mdss_init(ddev);
  

• break;
  

• case KMS_DPU:

• ret = dpu_mdss_init(ddev);
  

• break;
  

• default:

• ret = 0;
  

• break;
  

• }
• if (ret) goto mdss_init_fail;

@@ -1539,12 +1550,13 @@ static int add_display_components(struct device *dev, int ret;

/*

• * MDP5 based devices don't have a flat hierarchy. There is a top 
  

level

• * parent: MDSS, and children: MDP5, DSI, HDMI, eDP etc. Populate 
  

the

• * children devices, find the MDP5 node, and then add the interfaces
  

• * to our components list.
  

• * MDP5/DPU based devices don't have a flat hierarchy. There is a 
  

top

• * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
  

• * Populate the children devices, find the MDP5/DPU node, and then 
  

add

• * the interfaces to our components list.
  

  */

• if (of_device_is_compatible(dev->of_node, "qcom,mdss")) {

• if (of_device_is_compatible(dev->of_node, "qcom,mdss") ||

• of_device_is_compatible(dev->of_node, "qcom,dpu-mdss")) {
  

  ret = of_platform_populate(dev->of_node, NULL, NULL, dev); if (ret) { dev_err(dev, "failed to populate children devices\n");

@@ -1686,7 +1698,7 @@ static int msm_pdev_remove(struct platform_device *pdev) { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 }, { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 }, #ifdef CONFIG_DRM_MSM_DPU

• { .compatible = "qcom,dpu-kms", .data = (void *)KMS_DPU },

• { .compatible = "qcom,dpu-mdss", .data = (void *)KMS_DPU },

#endif {} }; diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 90a2521..e8e5e73 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -381,7 +381,7 @@ struct msm_drm_private { /* subordinate devices, if present: */ struct platform_device *gpu_pdev;

• /* top level MDSS wrapper device (for MDP5 only) */

• /* top level MDSS wrapper device (for MDP5/DPU only) */ struct msm_mdss *mdss;

  /* possibly this should be in the kms component, but it is

diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h index 9a7bc7d..5e1de85 100644 --- a/drivers/gpu/drm/msm/msm_kms.h +++ b/drivers/gpu/drm/msm/msm_kms.h @@ -144,6 +144,7 @@ struct msm_mdss { };

int mdp5_mdss_init(struct drm_device *dev); +int dpu_mdss_init(struct drm_device *dev);

/**

• Mode Set Utility Functions

diff --git a/include/linux/dpu_io_util.h b/include/linux/dpu_io_util.h index 7c73899..45e606f 100644 --- a/include/linux/dpu_io_util.h +++ b/include/linux/dpu_io_util.h @@ -104,6 +104,8 @@ int msm_dss_config_vreg(struct device *dev, struct dss_vreg *in_vreg, void msm_dss_put_clk(struct dss_clk *clk_arry, int num_clk); int msm_dss_clk_set_rate(struct dss_clk *clk_arry, int num_clk); int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable); +int msm_dss_parse_clock(struct platform_device *pdev,

• struct dss_module_power *mp);
  
  

int dpu_i2c_byte_read(struct i2c_client *client, uint8_t slave_addr, uint8_t reg_offset, uint8_t *read_buf); -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

On Fri, May 11, 2018 at 11:05:24AM -0600, Jordan Crouse wrote:

On Fri, May 11, 2018 at 08:19:29PM +0530, Rajesh Yadav wrote:

...

SoCs containing dpu have a MDSS top level wrapper which includes sub-blocks as dpu, dsi, phy, dp etc. MDSS top level wrapper manages common resources like common clocks, power and irq for its sub-blocks.

Currently, in dpu driver, all the power resource management is part of power_handle which manages these resources via a custom implementation. And the resource relationships are not modelled properly in dt. Moreover the irq domain handling code is part of dpu device (which is a child device) due to lack of a dedicated driver for MDSS top level wrapper device.

This change adds dpu_mdss top level driver to handle common clock like - core clock, ahb clock (for register access), main power supply (i.e. gdsc) and irq management. The top level mdss device/driver acts as an interrupt controller and manage hwirq mapping for its child devices.

It implements runtime_pm support for resource management. Child nodes can control these resources via runtime_pm get/put calls on their corresponding devices due to parent child relationship defined in dt.

Changes in v2:

• merge _dpu_mdss_hw_rev_init to dpu_mdss_init (Sean Paul)
• merge _dpu_mdss_get_intr_sources to dpu_mdss_irq (Sean Paul)
• fix indentation for irq_find_mapping call (Sean Paul)
• remove unnecessary goto statements from dpu_mdss_irq (Sean Paul)
• remove redundant param checks from dpu_mdss_irq_mask/unmask (Sean Paul/Jordan Crouse)
• remove redundant param checks from dpu_mdss_irqdomain_map (Sean Paul/Jordan Crouse)
• return error code from dpu_mdss_enable/disable (Sean Paul/Jordan Crouse)
• remove redundant param check from dpu_mdss_destroy (Sean Paul)
• remove explicit calls to devm_kfree (Sean Paul/Jordan Crouse)
• remove compatibility check from dpu_mdss_init as it is conditionally called from msm_drv (Sean Paul)
• reworked msm_dss_parse_clock() to add return checks for of_property_read_* calls, fix log message and fix alignment issues (Sean Paul/Jordan Crouse)
• remove extra line before dpu_mdss_init (Sean Paul)
• remove redundant param checks from __intr_offset and make it a void function to avoid unnecessary error handling from caller (Jordan Crouse)
• remove redundant param check from dpu_mdss_irq (Jordan Crouse)
• change mdss address space log message to debug and use %pK for kernel pointers (Jordan Crouse)
• remove unnecessary log message from msm_dss_parse_clock (Jordan Crouse)
• don't export msm_dss_parse_clock since it is used only by dpu driver (Jordan Crouse)

Signed-off-by: Rajesh Yadav ryadav@codeaurora.org

Reviewed-by: Jordan Crouse jcrouse@codeaurora.org

I know you'll get a hundred different opinions from a hundred different people

I'll interpret this as solicitation of my opinion :-)

I find this level of detail _extremely_ useful when reviewing, especially on sets as big as this one.

It's a pretty good strategy to make reviews go as smoothly as possible, since it's generally more difficult to read code than to write it.

Sean

/opinion

but you don't need to credit me for every change - just a single line "fixed bugs" works for me.

...

---

drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 97 --------- drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h | 14 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 9 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 7 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 28 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 11 - drivers/gpu/drm/msm/disp/dpu1/dpu_irq.c | 48 +--- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 6 - drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 2 - drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 254 ++++++++++++++++++++++ drivers/gpu/drm/msm/dpu_io_util.c | 57 +++++ drivers/gpu/drm/msm/msm_drv.c | 26 ++- drivers/gpu/drm/msm/msm_drv.h | 2 +- drivers/gpu/drm/msm/msm_kms.h | 1 + include/linux/dpu_io_util.h | 2 + 16 files changed, 339 insertions(+), 226 deletions(-) create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index d7558ed..d9826c1 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -81,6 +81,7 @@ msm-y := \ disp/dpu1/dpu_reg_dma.o \ disp/dpu1/dpu_rm.o \ disp/dpu1/dpu_vbif.o \

• disp/dpu1/dpu_mdss.o \ dpu_dbg.o \ dpu_io_util.o \ dpu_dbg_evtlog.o \

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c index fe33013..977adc4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c @@ -515,103 +515,6 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms) dpu_kms->irq_obj.total_irqs = 0; }

-static void dpu_core_irq_mask(struct irq_data *irqd) -{

• struct dpu_kms *dpu_kms;
• if (!irqd || !irq_data_get_irq_chip_data(irqd)) {

• DPU_ERROR("invalid parameters irqd %d\n", irqd != NULL);
  

• return;
  

• }
• dpu_kms = irq_data_get_irq_chip_data(irqd);
• /* memory barrier */
• smp_mb__before_atomic();
• clear_bit(irqd->hwirq, &dpu_kms->irq_controller.enabled_mask);
• /* memory barrier */
• smp_mb__after_atomic();

-}

-static void dpu_core_irq_unmask(struct irq_data *irqd) -{

• struct dpu_kms *dpu_kms;
• if (!irqd || !irq_data_get_irq_chip_data(irqd)) {

• DPU_ERROR("invalid parameters irqd %d\n", irqd != NULL);
  

• return;
  

• }
• dpu_kms = irq_data_get_irq_chip_data(irqd);
• /* memory barrier */
• smp_mb__before_atomic();
• set_bit(irqd->hwirq, &dpu_kms->irq_controller.enabled_mask);
• /* memory barrier */
• smp_mb__after_atomic();

-}

-static struct irq_chip dpu_core_irq_chip = {

• .name = "dpu",
• .irq_mask = dpu_core_irq_mask,
• .irq_unmask = dpu_core_irq_unmask,

-};

-static int dpu_core_irqdomain_map(struct irq_domain *domain,

• unsigned int irq, irq_hw_number_t hwirq)
  

-{

• struct dpu_kms *dpu_kms;
• int rc;
• if (!domain || !domain->host_data) {

• DPU_ERROR("invalid parameters domain %d\n", domain != NULL);
  

• return -EINVAL;
  

• }
• dpu_kms = domain->host_data;
• irq_set_chip_and_handler(irq, &dpu_core_irq_chip, handle_level_irq);
• rc = irq_set_chip_data(irq, dpu_kms);
• return rc;

-}

-static const struct irq_domain_ops dpu_core_irqdomain_ops = {

• .map = dpu_core_irqdomain_map,
• .xlate = irq_domain_xlate_onecell,

-};

-int dpu_core_irq_domain_add(struct dpu_kms *dpu_kms) -{

• struct device *dev;
• struct irq_domain *domain;
• if (!dpu_kms->dev || !dpu_kms->dev->dev) {

• pr_err("invalid device handles\n");
  

• return -EINVAL;
  

• }
• dev = dpu_kms->dev->dev;
• domain = irq_domain_add_linear(dev->of_node, 32,

• 	&dpu_core_irqdomain_ops, dpu_kms);
  

• if (!domain) {

• pr_err("failed to add irq_domain\n");
  

• return -EINVAL;
  

• }
• dpu_kms->irq_controller.enabled_mask = 0;
• dpu_kms->irq_controller.domain = domain;
• return 0;

-}

-int dpu_core_irq_domain_fini(struct dpu_kms *dpu_kms) -{

• if (dpu_kms->irq_controller.domain) {

• irq_domain_remove(dpu_kms->irq_controller.domain);
  

• dpu_kms->irq_controller.domain = NULL;
  

• }
• return 0;

-}

irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms) { /* diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h index 64a54fe..8fa59db 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h @@ -38,20 +38,6 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms);

/**

• • dpu_core_irq_domain_add - Add core IRQ domain for DPU
• • @dpu_kms: DPU handle
• • @return: none
• */

-int dpu_core_irq_domain_add(struct dpu_kms *dpu_kms);

-/**

• • dpu_core_irq_domain_fini - uninstall core IRQ domain
• • @dpu_kms: DPU handle
• • @return: 0 if success; error code otherwise
• */

-int dpu_core_irq_domain_fini(struct dpu_kms *dpu_kms);

-/**

• dpu_core_irq - core IRQ handler
• @dpu_kms: DPU handle
• @return: interrupt handling status

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 8e779c0..c5b370f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -77,13 +77,6 @@ .has_idle_pc = true, };

-static struct dpu_mdss_base_cfg sdm845_mdss[] = {

• {
• .name = "mdss_0", .id = MDP_TOP,
• .base = 0x0, .features = 0
• },

-};

static struct dpu_mdp_cfg sdm845_mdp[] = { { .name = "top_0", .id = MDP_TOP, @@ -550,8 +543,6 @@ void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg) { *dpu_cfg = (struct dpu_mdss_cfg){ .caps = &sdm845_dpu_caps,

• .mdss_count = ARRAY_SIZE(sdm845_mdss),
  

• .mdss = sdm845_mdss,
  

  .mdp_count = ARRAY_SIZE(sdm845_mdp), .mdp = sdm845_mdp, .ctl_count = ARRAY_SIZE(sdm845_ctl),

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 39bec0a..7084643 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -492,10 +492,6 @@ struct dpu_wb_sub_blocks { u32 maxlinewidth; };

-struct dpu_mdss_base_cfg {

• DPU_HW_BLK_INFO;

-};

/**

• dpu_clk_ctrl_type - Defines top level clock control signals

*/ @@ -875,9 +871,6 @@ struct dpu_mdss_cfg {

const struct dpu_caps *caps;

• u32 mdss_count;
• struct dpu_mdss_base_cfg *mdss;
• u32 mdp_count; struct dpu_mdp_cfg *mdp;

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c index 9767cc8..73f084c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c @@ -22,7 +22,6 @@

• Register offsets in MDSS register file for the interrupt registers
• w.r.t. to the MDSS base

*/ -#define HW_INTR_STATUS 0x0010 #define MDP_SSPP_TOP0_OFF 0x1000 #define MDP_INTF_0_OFF 0x6B000 #define MDP_INTF_1_OFF 0x6B800 @@ -1017,17 +1016,6 @@ static int dpu_hw_intr_get_valid_interrupts(struct dpu_hw_intr *intr, return 0; }

-static int dpu_hw_intr_get_interrupt_sources(struct dpu_hw_intr *intr,

• uint32_t *sources)
  

-{

• if (!intr || !sources)

• return -EINVAL;
  

• *sources = DPU_REG_READ(&intr->hw, HW_INTR_STATUS);
• return 0;

-}

static void dpu_hw_intr_get_interrupt_statuses(struct dpu_hw_intr *intr) { int i; @@ -1162,7 +1150,6 @@ static void __setup_intr_ops(struct dpu_hw_intr_ops *ops) ops->clear_all_irqs = dpu_hw_intr_clear_irqs; ops->disable_all_irqs = dpu_hw_intr_disable_irqs; ops->get_valid_interrupts = dpu_hw_intr_get_valid_interrupts;

• ops->get_interrupt_sources = dpu_hw_intr_get_interrupt_sources; ops->get_interrupt_statuses = dpu_hw_intr_get_interrupt_statuses; ops->clear_interrupt_status = dpu_hw_intr_clear_interrupt_status; ops->clear_intr_status_nolock = dpu_hw_intr_clear_intr_status_nolock;

@@ -1170,23 +1157,18 @@ static void __setup_intr_ops(struct dpu_hw_intr_ops *ops) ops->get_intr_status_nolock = dpu_hw_intr_get_intr_status_nolock; }

-static struct dpu_mdss_base_cfg *__intr_offset(struct dpu_mdss_cfg *m, +static void __intr_offset(struct dpu_mdss_cfg *m, void __iomem *addr, struct dpu_hw_blk_reg_map *hw) {

• if (!m || !addr || !hw || m->mdp_count == 0)

• return NULL;
  

• hw->base_off = addr;
• hw->blk_off = m->mdss[0].base;

• hw->blk_off = m->mdp[0].base; hw->hwversion = m->hwversion;

• return &m->mdss[0];

}

struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr, struct dpu_mdss_cfg *m) { struct dpu_hw_intr *intr;

• struct dpu_mdss_base_cfg *cfg;

  if (!addr || !m) return ERR_PTR(-EINVAL);

@@ -1195,11 +1177,7 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr, if (!intr) return ERR_PTR(-ENOMEM);

• cfg = __intr_offset(m, addr, &intr->hw);
• if (!cfg) {

• kfree(intr);
  

• return ERR_PTR(-EINVAL);
  

• }

• __intr_offset(m, addr, &intr->hw); __setup_intr_ops(&intr->ops);

  intr->irq_idx_tbl_size = ARRAY_SIZE(dpu_irq_map);

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h index 2f1a828..b52cdca 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h @@ -242,17 +242,6 @@ struct dpu_hw_intr_ops { int (*get_valid_interrupts)( struct dpu_hw_intr *intr, uint32_t *mask);

• /**

• * get_interrupt_sources - Gets the bitmask of the DPU interrupt
  

• *                         source that are currently fired.
  

• * @intr:	HW interrupt handle
  

• * @sources:	Returning the DPU interrupt source status bit mask
  

• * @return:	0 for success, otherwise failure
  

• */
  

• int (*get_interrupt_sources)(

• 	struct dpu_hw_intr *intr,
  

• 	uint32_t *sources);
  

};

/** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_irq.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_irq.c index 19c0929..d5e6ce0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_irq.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_irq.c @@ -19,56 +19,11 @@ #include "dpu_irq.h" #include "dpu_core_irq.h"

-static uint32_t g_dpu_irq_status;

irqreturn_t dpu_irq(struct msm_kms *kms) { struct dpu_kms *dpu_kms = to_dpu_kms(kms);

• u32 interrupts;
• dpu_kms->hw_intr->ops.get_interrupt_sources(dpu_kms->hw_intr,

• 	&interrupts);
  

• /* store irq status in case of irq-storm debugging */
• g_dpu_irq_status = interrupts;
• /*

• * Taking care of MDP interrupt
  

• */
  

• if (interrupts & IRQ_SOURCE_MDP) {

• interrupts &= ~IRQ_SOURCE_MDP;
  

• dpu_core_irq(dpu_kms);
  

• }
• /*

• * Routing all other interrupts to external drivers
  

• */
  

• while (interrupts) {

• irq_hw_number_t hwirq = fls(interrupts) - 1;
  

• unsigned int mapping;
  

• int rc;
  

• mapping = irq_find_mapping(dpu_kms->irq_controller.domain,
  

• 		hwirq);
  

• if (mapping == 0) {
  

• 	DPU_EVT32(hwirq, DPU_EVTLOG_ERROR);
  

• 	goto error;
  

• }
  

• rc = generic_handle_irq(mapping);
  

• if (rc < 0) {
  

• 	DPU_EVT32(hwirq, mapping, rc, DPU_EVTLOG_ERROR);
  

• 	goto error;
  

• }
  

• interrupts &= ~(1 << hwirq);
  

• }
• return IRQ_HANDLED;

-error:

• /* bad situation, inform irq system, it may disable overall MDSS irq */
• return IRQ_NONE;

• return dpu_core_irq(dpu_kms);

}

void dpu_irq_preinstall(struct msm_kms *kms) @@ -108,5 +63,4 @@ void dpu_irq_uninstall(struct msm_kms *kms) }

dpu_core_irq_uninstall(dpu_kms);

• dpu_core_irq_domain_fini(dpu_kms);

} diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 06adb38..e4ab753 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -636,10 +636,6 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms) priv = dev->dev_private; catalog = dpu_kms->catalog;

• ret = dpu_core_irq_domain_add(dpu_kms);
• if (ret)

• goto fail_irq;
  

• /*
  • Create encoder and query display drivers to create
  • bridges and connectors

@@ -716,8 +712,6 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms) return 0; fail: _dpu_kms_drm_obj_destroy(dpu_kms); -fail_irq:

• dpu_core_irq_domain_fini(dpu_kms); return ret;

}

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index 5b0c081..a1c0910 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -184,8 +184,6 @@ struct dpu_kms { struct regulator *mmagic; struct regulator *venus;

• struct dpu_irq_controller irq_controller;
• struct dpu_hw_intr *hw_intr; struct dpu_irq irq_obj;

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c new file mode 100644 index 0000000..ce680ea --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c @@ -0,0 +1,254 @@ +/*

• • SPDX-License-Identifier: GPL-2.0
• • Copyright (c) 2018, The Linux Foundation
• */

+#include "dpu_kms.h"

+#define to_dpu_mdss(x) container_of(x, struct dpu_mdss, base)

+#define HW_INTR_STATUS 0x0010

+struct dpu_mdss {

• struct msm_mdss base;
• void __iomem *mmio;
• unsigned long mmio_len;
• u32 hwversion;
• struct dss_module_power mp;
• struct dpu_irq_controller irq_controller;

+};

+static irqreturn_t dpu_mdss_irq(int irq, void *arg) +{

• struct dpu_mdss *dpu_mdss = arg;
• u32 interrupts;
• interrupts = readl_relaxed(dpu_mdss->mmio + HW_INTR_STATUS);
• while (interrupts) {

• irq_hw_number_t hwirq = fls(interrupts) - 1;
  

• unsigned int mapping;
  

• int rc;
  

• mapping = irq_find_mapping(dpu_mdss->irq_controller.domain,
  

• 			   hwirq);
  

• if (mapping == 0) {
  

• 	DPU_EVT32(hwirq, DPU_EVTLOG_ERROR);
  

• 	return IRQ_NONE;
  

• }
  

• rc = generic_handle_irq(mapping);
  

• if (rc < 0) {
  

• 	DPU_EVT32(hwirq, mapping, rc, DPU_EVTLOG_ERROR);
  

• 	return IRQ_NONE;
  

• }
  

• interrupts &= ~(1 << hwirq);
  

• }
• return IRQ_HANDLED;

+}

+static void dpu_mdss_irq_mask(struct irq_data *irqd) +{

• struct dpu_mdss *dpu_mdss = irq_data_get_irq_chip_data(irqd);
• /* memory barrier */
• smp_mb__before_atomic();
• clear_bit(irqd->hwirq, &dpu_mdss->irq_controller.enabled_mask);
• /* memory barrier */
• smp_mb__after_atomic();

+}

+static void dpu_mdss_irq_unmask(struct irq_data *irqd) +{

• struct dpu_mdss *dpu_mdss = irq_data_get_irq_chip_data(irqd);
• /* memory barrier */
• smp_mb__before_atomic();
• set_bit(irqd->hwirq, &dpu_mdss->irq_controller.enabled_mask);
• /* memory barrier */
• smp_mb__after_atomic();

+}

+static struct irq_chip dpu_mdss_irq_chip = {

• .name = "dpu_mdss",
• .irq_mask = dpu_mdss_irq_mask,
• .irq_unmask = dpu_mdss_irq_unmask,

+};

+static int dpu_mdss_irqdomain_map(struct irq_domain *domain,

• unsigned int irq, irq_hw_number_t hwirq)
  

+{

• struct dpu_mdss *dpu_mdss = domain->host_data;
• int ret;
• irq_set_chip_and_handler(irq, &dpu_mdss_irq_chip, handle_level_irq);
• ret = irq_set_chip_data(irq, dpu_mdss);
• return ret;

+}

+static const struct irq_domain_ops dpu_mdss_irqdomain_ops = {

• .map = dpu_mdss_irqdomain_map,
• .xlate = irq_domain_xlate_onecell,

+};

+static int _dpu_mdss_irq_domain_add(struct dpu_mdss *dpu_mdss) +{

• struct device *dev;
• struct irq_domain *domain;
• dev = dpu_mdss->base.dev->dev;
• domain = irq_domain_add_linear(dev->of_node, 32,

• 	&dpu_mdss_irqdomain_ops, dpu_mdss);
  

• if (!domain) {

• DPU_ERROR("failed to add irq_domain\n");
  

• return -EINVAL;
  

• }
• dpu_mdss->irq_controller.enabled_mask = 0;
• dpu_mdss->irq_controller.domain = domain;
• return 0;

+}

+int _dpu_mdss_irq_domain_fini(struct dpu_mdss *dpu_mdss) +{

• if (dpu_mdss->irq_controller.domain) {

• irq_domain_remove(dpu_mdss->irq_controller.domain);
  

• dpu_mdss->irq_controller.domain = NULL;
  

• }
• return 0;

+} +static int dpu_mdss_enable(struct msm_mdss *mdss) +{

• struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
• struct dss_module_power *mp = &dpu_mdss->mp;
• int ret;
• ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true);
• if (ret)

• DPU_ERROR("clock enable failed, ret:%d\n", ret);
  

• return ret;

+}

+static int dpu_mdss_disable(struct msm_mdss *mdss) +{

• struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
• struct dss_module_power *mp = &dpu_mdss->mp;
• int ret;
• ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false);
• if (ret)

• DPU_ERROR("clock disable failed, ret:%d\n", ret);
  

• return ret;

+}

+static void dpu_mdss_destroy(struct drm_device *dev) +{

• struct platform_device *pdev = to_platform_device(dev->dev);
• struct msm_drm_private *priv = dev->dev_private;
• struct dpu_mdss *dpu_mdss = to_dpu_mdss(priv->mdss);
• struct dss_module_power *mp = &dpu_mdss->mp;
• _dpu_mdss_irq_domain_fini(dpu_mdss);
• msm_dss_put_clk(mp->clk_config, mp->num_clk);
• devm_kfree(&pdev->dev, mp->clk_config);
• if (dpu_mdss->mmio)

• msm_iounmap(pdev, dpu_mdss->mmio);
  

• dpu_mdss->mmio = NULL;
• pm_runtime_disable(dev->dev);
• priv->mdss = NULL;

+}

+static const struct msm_mdss_funcs mdss_funcs = {

• .enable = dpu_mdss_enable,
• .disable = dpu_mdss_disable,
• .destroy = dpu_mdss_destroy,

+};

+int dpu_mdss_init(struct drm_device *dev) +{

• struct platform_device *pdev = to_platform_device(dev->dev);
• struct msm_drm_private *priv = dev->dev_private;
• struct dpu_mdss *dpu_mdss;
• struct dss_module_power *mp;
• int ret = 0;
• dpu_mdss = devm_kzalloc(dev->dev, sizeof(*dpu_mdss), GFP_KERNEL);
• if (!dpu_mdss)

• return -ENOMEM;
  

• dpu_mdss->mmio = msm_ioremap(pdev, "mdss_phys", "mdss_phys");
• if (IS_ERR(dpu_mdss->mmio)) {

• ret = PTR_ERR(dpu_mdss->mmio);
  

• DPU_ERROR("mdss register memory map failed: %d\n", ret);
  

• dpu_mdss->mmio = NULL;
  

• return ret;
  

• }
• DRM_DEBUG("mapped mdss address space @%pK\n", dpu_mdss->mmio);
• dpu_mdss->mmio_len = msm_iomap_size(pdev, "mdss_phys");
• mp = &dpu_mdss->mp;
• ret = msm_dss_parse_clock(pdev, mp);
• if (ret) {

• DPU_ERROR("failed to parse clocks, ret=%d\n", ret);
  

• goto clk_parse_err;
  

• }
• ret = msm_dss_get_clk(&pdev->dev, mp->clk_config, mp->num_clk);
• if (ret) {

• DPU_ERROR("failed to get clocks, ret=%d\n", ret);
  

• goto clk_get_error;
  

• }
• ret = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk);
• if (ret) {

• DPU_ERROR("failed to set clock rate, ret=%d\n", ret);
  

• goto clk_rate_error;
  

• }
• dpu_mdss->base.dev = dev;
• dpu_mdss->base.funcs = &mdss_funcs;
• ret = _dpu_mdss_irq_domain_add(dpu_mdss);
• if (ret)

• goto irq_domain_error;
  

• ret = devm_request_irq(dev->dev, platform_get_irq(pdev, 0),

• 	dpu_mdss_irq, 0, "dpu_mdss_isr", dpu_mdss);
  

• if (ret) {

• DPU_ERROR("failed to init irq: %d\n", ret);
  

• goto irq_error;
  

• }
• pm_runtime_enable(dev->dev);
• pm_runtime_get_sync(dev->dev);
• dpu_mdss->hwversion = readl_relaxed(dpu_mdss->mmio);
• pm_runtime_put_sync(dev->dev);
• priv->mdss = &dpu_mdss->base;
• return ret;

+irq_error:

• _dpu_mdss_irq_domain_fini(dpu_mdss);

+irq_domain_error: +clk_rate_error:

• msm_dss_put_clk(mp->clk_config, mp->num_clk);

+clk_get_error:

• devm_kfree(&pdev->dev, mp->clk_config);

+clk_parse_err:

• if (dpu_mdss->mmio)

• msm_iounmap(pdev, dpu_mdss->mmio);
  

• dpu_mdss->mmio = NULL;
• return ret;

+} diff --git a/drivers/gpu/drm/msm/dpu_io_util.c b/drivers/gpu/drm/msm/dpu_io_util.c index a18bc99..c44f33f 100644 --- a/drivers/gpu/drm/msm/dpu_io_util.c +++ b/drivers/gpu/drm/msm/dpu_io_util.c @@ -448,6 +448,63 @@ int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable) } /* msm_dss_enable_clk */ EXPORT_SYMBOL(msm_dss_enable_clk);

+int msm_dss_parse_clock(struct platform_device *pdev,

• struct dss_module_power *mp)
  

+{

• u32 i, rc = 0;
• const char *clock_name;
• u32 rate = 0, max_rate = 0;
• int num_clk = 0;
• if (!pdev || !mp)

• return -EINVAL;
  

• mp->num_clk = 0;
• num_clk = of_property_count_strings(pdev->dev.of_node, "clock-names");
• if (num_clk <= 0) {

• pr_debug("clocks are not defined\n");
  

• return 0;
  

• }
• mp->clk_config = devm_kzalloc(&pdev->dev,

• 		      sizeof(struct dss_clk) * num_clk,
  

• 		      GFP_KERNEL);
  

• if (!mp->clk_config)

• return -ENOMEM;
  

• for (i = 0; i < num_clk; i++) {

• rc = of_property_read_string_index(pdev->dev.of_node,
  

• 				   "clock-names", i,
  

• 				   &clock_name);
  

• if (rc)
  

• 	break;
  

• strlcpy(mp->clk_config[i].clk_name, clock_name,
  

• 	sizeof(mp->clk_config[i].clk_name));
  

• rc = of_property_read_u32_index(pdev->dev.of_node,
  

• 				"clock-rate", i,
  

• 				&rate);
  

• if (rc)
  

• 	break;
  

• mp->clk_config[i].rate = rate;
  

• if (!mp->clk_config[i].rate)
  

• 	mp->clk_config[i].type = DSS_CLK_AHB;
  

• else
  

• 	mp->clk_config[i].type = DSS_CLK_PCLK;
  

• rc = of_property_read_u32_index(pdev->dev.of_node,
  

• 				"clock-max-rate", i,
  

• 				&max_rate);
  

• if (rc)
  

• 	break;
  

• mp->clk_config[i].max_rate = max_rate;
  

• }
• if (!rc)

• mp->num_clk = num_clk;
  

• return rc;

+}

int dpu_i2c_byte_read(struct i2c_client *client, uint8_t slave_addr, uint8_t reg_offset, uint8_t *read_buf) diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 5d8f1b6..a0e73ea 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -503,7 +503,18 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv) ddev->dev_private = priv; priv->dev = ddev;

• ret = mdp5_mdss_init(ddev);

• switch (get_mdp_ver(pdev)) {
• case KMS_MDP5:

• ret = mdp5_mdss_init(ddev);
  

• break;
  

• case KMS_DPU:

• ret = dpu_mdss_init(ddev);
  

• break;
  

• default:

• ret = 0;
  

• break;
  

• }
• if (ret) goto mdss_init_fail;

@@ -1539,12 +1550,13 @@ static int add_display_components(struct device *dev, int ret;

/*

• * MDP5 based devices don't have a flat hierarchy. There is a top level
  

• * parent: MDSS, and children: MDP5, DSI, HDMI, eDP etc. Populate the
  

• * children devices, find the MDP5 node, and then add the interfaces
  

• * to our components list.
  

• * MDP5/DPU based devices don't have a flat hierarchy. There is a top
  

• * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
  

• * Populate the children devices, find the MDP5/DPU node, and then add
  

• * the interfaces to our components list.
  

  */

• if (of_device_is_compatible(dev->of_node, "qcom,mdss")) {

• if (of_device_is_compatible(dev->of_node, "qcom,mdss") ||

• of_device_is_compatible(dev->of_node, "qcom,dpu-mdss")) {
  

  ret = of_platform_populate(dev->of_node, NULL, NULL, dev); if (ret) { dev_err(dev, "failed to populate children devices\n");

@@ -1686,7 +1698,7 @@ static int msm_pdev_remove(struct platform_device *pdev) { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 }, { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 }, #ifdef CONFIG_DRM_MSM_DPU

• { .compatible = "qcom,dpu-kms", .data = (void *)KMS_DPU },

• { .compatible = "qcom,dpu-mdss", .data = (void *)KMS_DPU },

#endif {} }; diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 90a2521..e8e5e73 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -381,7 +381,7 @@ struct msm_drm_private { /* subordinate devices, if present: */ struct platform_device *gpu_pdev;

• /* top level MDSS wrapper device (for MDP5 only) */

• /* top level MDSS wrapper device (for MDP5/DPU only) */ struct msm_mdss *mdss;

  /* possibly this should be in the kms component, but it is

diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h index 9a7bc7d..5e1de85 100644 --- a/drivers/gpu/drm/msm/msm_kms.h +++ b/drivers/gpu/drm/msm/msm_kms.h @@ -144,6 +144,7 @@ struct msm_mdss { };

int mdp5_mdss_init(struct drm_device *dev); +int dpu_mdss_init(struct drm_device *dev);

/**

• Mode Set Utility Functions

diff --git a/include/linux/dpu_io_util.h b/include/linux/dpu_io_util.h index 7c73899..45e606f 100644 --- a/include/linux/dpu_io_util.h +++ b/include/linux/dpu_io_util.h @@ -104,6 +104,8 @@ int msm_dss_config_vreg(struct device *dev, struct dss_vreg *in_vreg, void msm_dss_put_clk(struct dss_clk *clk_arry, int num_clk); int msm_dss_clk_set_rate(struct dss_clk *clk_arry, int num_clk); int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable); +int msm_dss_parse_clock(struct platform_device *pdev,

• struct dss_module_power *mp);
  
  

int dpu_i2c_byte_read(struct i2c_client *client, uint8_t slave_addr, uint8_t reg_offset, uint8_t *read_buf); -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

---

Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno

-- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project

On Fri, May 11, 2018 at 08:19:30PM +0530, Rajesh Yadav wrote:

Current MSM display controller HW matches a tree like hierarchy where MDSS top level wrapper is parent device and mdp5/dpu, dsi, dp are child devices.

Each child device like mdp5, dsi etc. have a separate driver, but currently dpu handling is tied to a single driver which was managing both mdss and dpu resources.

Inorder to have the cleaner one to one device and driver association, this change adds a new platform_driver for dpu child device node which implements the kms functionality.

The dpu driver implements runtime_pm support for managing clocks and bus bandwidth etc.

Changes in v2:

• remove redundant param check from _dpu_kms_hw_destroy (Sean Paul)
• remove explicit calls to devm_kfree (Sean Paul)
• merge dpu_init into dpu_bind (Sean Paul)
• merge dpu_destroy into dpu_unbind (Sean Paul)
• use %pK for kernel pointer printing (Jordan Crouse)
• remove explicit devm allocation failure message (Jordan Crouse)

Signed-off-by: Rajesh Yadav ryadav@codeaurora.org

Reviewed-by: Sean Paul seanpaul@chromium.org

---

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 238 +++++++++++++++++++++++++------- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 4 + drivers/gpu/drm/msm/msm_drv.c | 2 + drivers/gpu/drm/msm/msm_drv.h | 3 + 4 files changed, 196 insertions(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index e4ab753..85f3dbc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1030,16 +1030,12 @@ static long dpu_kms_round_pixclk(struct msm_kms *kms, unsigned long rate, return rate; }

-static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms,

• struct platform_device *pdev)
  

+static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms) { struct drm_device *dev; struct msm_drm_private *priv; int i;

• if (!dpu_kms || !pdev)

• return;
  

• dev = dpu_kms->dev; if (!dev) return;

@@ -1091,15 +1087,15 @@ static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms, dpu_kms->core_client = NULL;

if (dpu_kms->vbif[VBIF_NRT])

• msm_iounmap(pdev, dpu_kms->vbif[VBIF_NRT]);
  

• msm_iounmap(dpu_kms->pdev, dpu_kms->vbif[VBIF_NRT]);
  

  dpu_kms->vbif[VBIF_NRT] = NULL;

  if (dpu_kms->vbif[VBIF_RT])

• msm_iounmap(pdev, dpu_kms->vbif[VBIF_RT]);
  

• msm_iounmap(dpu_kms->pdev, dpu_kms->vbif[VBIF_RT]);
  

  dpu_kms->vbif[VBIF_RT] = NULL;

  if (dpu_kms->mmio)

• msm_iounmap(pdev, dpu_kms->mmio);
  

• msm_iounmap(dpu_kms->pdev, dpu_kms->mmio);
  

  dpu_kms->mmio = NULL;

  dpu_reg_dma_deinit();

@@ -1172,8 +1168,6 @@ int dpu_kms_mmu_attach(struct dpu_kms *dpu_kms, bool secure_only) static void dpu_kms_destroy(struct msm_kms *kms) { struct dpu_kms *dpu_kms;

• struct drm_device *dev;

• struct platform_device *platformdev;

  if (!kms) { DPU_ERROR("invalid kms\n");

@@ -1181,20 +1175,7 @@ static void dpu_kms_destroy(struct msm_kms *kms) }

dpu_kms = to_dpu_kms(kms);

• dev = dpu_kms->dev;
• if (!dev) {

• DPU_ERROR("invalid device\n");
  

• return;
  

• }
• platformdev = to_platform_device(dev->dev);
• if (!platformdev) {

• DPU_ERROR("invalid platform device\n");
  

• return;
  

• }
• _dpu_kms_hw_destroy(dpu_kms, platformdev);
• kfree(dpu_kms);

• _dpu_kms_hw_destroy(dpu_kms);

}

static void dpu_kms_preclose(struct msm_kms *kms, struct drm_file *file) @@ -1550,7 +1531,6 @@ static int dpu_kms_hw_init(struct msm_kms *kms) struct dpu_kms *dpu_kms; struct drm_device *dev; struct msm_drm_private *priv;

• struct platform_device *platformdev; int i, rc = -EINVAL;

  if (!kms) {

@@ -1565,34 +1545,28 @@ static int dpu_kms_hw_init(struct msm_kms *kms) goto end; }

• platformdev = to_platform_device(dev->dev);

• if (!platformdev) {

• DPU_ERROR("invalid platform device\n");
  

• goto end;
  

• }
  

• priv = dev->dev_private; if (!priv) { DPU_ERROR("invalid private data\n"); goto end; }

• dpu_kms->mmio = msm_ioremap(platformdev, "mdp_phys", "mdp_phys");

• dpu_kms->mmio = msm_ioremap(dpu_kms->pdev, "mdp_phys", "mdp_phys"); if (IS_ERR(dpu_kms->mmio)) { rc = PTR_ERR(dpu_kms->mmio); DPU_ERROR("mdp register memory map failed: %d\n", rc); dpu_kms->mmio = NULL; goto error; }

• DRM_INFO("mapped mdp address space @%p\n", dpu_kms->mmio);
• dpu_kms->mmio_len = msm_iomap_size(platformdev, "mdp_phys");

• DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio);

• dpu_kms->mmio_len = msm_iomap_size(dpu_kms->pdev, "mdp_phys");

  rc = dpu_dbg_reg_register_base(DPU_DBG_NAME, dpu_kms->mmio, dpu_kms->mmio_len); if (rc) DPU_ERROR("dbg base register kms failed: %d\n", rc);

• dpu_kms->vbif[VBIF_RT] = msm_ioremap(platformdev, "vbif_phys",

• dpu_kms->vbif[VBIF_RT] = msm_ioremap(dpu_kms->pdev, "vbif_phys", "vbif_phys"); if (IS_ERR(dpu_kms->vbif[VBIF_RT])) { rc = PTR_ERR(dpu_kms->vbif[VBIF_RT]);

@@ -1600,20 +1574,20 @@ static int dpu_kms_hw_init(struct msm_kms *kms) dpu_kms->vbif[VBIF_RT] = NULL; goto error; }

• dpu_kms->vbif_len[VBIF_RT] = msm_iomap_size(platformdev,

• dpu_kms->vbif_len[VBIF_RT] = msm_iomap_size(dpu_kms->pdev, "vbif_phys"); rc = dpu_dbg_reg_register_base("vbif_rt", dpu_kms->vbif[VBIF_RT], dpu_kms->vbif_len[VBIF_RT]); if (rc) DPU_ERROR("dbg base register vbif_rt failed: %d\n", rc);

• dpu_kms->vbif[VBIF_NRT] = msm_ioremap(platformdev, "vbif_nrt_phys",

• dpu_kms->vbif[VBIF_NRT] = msm_ioremap(dpu_kms->pdev, "vbif_nrt_phys", "vbif_nrt_phys"); if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) { dpu_kms->vbif[VBIF_NRT] = NULL; DPU_DEBUG("VBIF NRT is not defined"); } else {

• dpu_kms->vbif_len[VBIF_NRT] = msm_iomap_size(platformdev,
  

• dpu_kms->vbif_len[VBIF_NRT] = msm_iomap_size(dpu_kms->pdev,
  				"vbif_nrt_phys");
  

  rc = dpu_dbg_reg_register_base("vbif_nrt", dpu_kms->vbif[VBIF_NRT],

@@ -1624,13 +1598,13 @@ static int dpu_kms_hw_init(struct msm_kms *kms) }

#ifdef CONFIG_CHROME_REGDMA

• dpu_kms->reg_dma = msm_ioremap(platformdev, "regdma_phys",

• dpu_kms->reg_dma = msm_ioremap(dpu_kms->pdev, "regdma_phys", "regdma_phys"); if (IS_ERR(dpu_kms->reg_dma)) { dpu_kms->reg_dma = NULL; DPU_DEBUG("REG_DMA is not defined"); } else {

• dpu_kms->reg_dma_len = msm_iomap_size(platformdev,
  

• dpu_kms->reg_dma_len = msm_iomap_size(dpu_kms->pdev,
  					"regdma_phys");
  

  rc = dpu_dbg_reg_register_base("reg_dma", dpu_kms->reg_dma,

@@ -1804,14 +1778,13 @@ static int dpu_kms_hw_init(struct msm_kms *kms) dpu_power_resource_enable(&priv->phandle, dpu_kms->core_client, false); pm_runtime_put_sync(dev->dev); error:

• _dpu_kms_hw_destroy(dpu_kms, platformdev);

• _dpu_kms_hw_destroy(dpu_kms);

end: return rc; }

struct msm_kms *dpu_kms_init(struct drm_device *dev) {

• struct platform_device *pdev = to_platform_device(dev->dev); struct msm_drm_private *priv; struct dpu_kms *dpu_kms; int irq;

@@ -1821,24 +1794,187 @@ struct msm_kms *dpu_kms_init(struct drm_device *dev) return ERR_PTR(-EINVAL); }

• irq = platform_get_irq(pdev, 0);

• priv = dev->dev_private;
• dpu_kms = to_dpu_kms(priv->kms);
• irq = irq_of_parse_and_map(dpu_kms->pdev->dev.of_node, 0); if (irq < 0) { DPU_ERROR("failed to get irq: %d\n", irq); return ERR_PTR(irq); }
• dpu_kms->base.irq = irq;

• priv = dev->dev_private;

• return &dpu_kms->base;

+}

• dpu_kms = kzalloc(sizeof(*dpu_kms), GFP_KERNEL);
• if (!dpu_kms) {

• DPU_ERROR("failed to allocate dpu kms\n");
  

• return ERR_PTR(-ENOMEM);
  

+static int dpu_bind(struct device *dev, struct device *master, void *data) +{

• struct drm_device *ddev = dev_get_drvdata(master);

• struct platform_device *pdev = to_platform_device(dev);

• struct msm_drm_private *priv = ddev->dev_private;

• struct dpu_kms *dpu_kms;

• struct dss_module_power *mp;

• int ret = 0;

• dpu_kms = devm_kzalloc(&pdev->dev, sizeof(*dpu_kms), GFP_KERNEL);

• if (!dpu_kms)

• return -ENOMEM;
  

• mp = &dpu_kms->mp;

• ret = msm_dss_parse_clock(pdev, mp);

• if (ret) {

• DPU_ERROR("failed to parse clocks, ret=%d\n", ret);
  

• return ret;
  

• }

• ret = msm_dss_get_clk(&pdev->dev, mp->clk_config, mp->num_clk);

• if (ret) {

• pr_err("failed to get clocks, ret=%d\n", ret);
  

• goto clk_get_error;
  

• }

• ret = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk);

• if (ret) {

• pr_err("failed to set clock rate, ret=%d\n", ret);
  

• goto clk_rate_error;
  

  }

• platform_set_drvdata(pdev, dpu_kms);

• msm_kms_init(&dpu_kms->base, &kms_funcs);

• dpu_kms->dev = dev;
• dpu_kms->base.irq = irq;

• dpu_kms->dev = ddev;
• dpu_kms->pdev = pdev;

• return &dpu_kms->base;

• pm_runtime_enable(&pdev->dev);
• dpu_kms->rpm_enabled = true;
• priv->kms = &dpu_kms->base;
• return ret;

+clk_rate_error:

• msm_dss_put_clk(mp->clk_config, mp->num_clk);

+clk_get_error:

• devm_kfree(&pdev->dev, mp->clk_config);
• mp->num_clk = 0;
• return ret;

}

+static void dpu_unbind(struct device *dev, struct device *master, void *data) +{

• struct platform_device *pdev = to_platform_device(dev);
• struct dpu_kms *dpu_kms = platform_get_drvdata(pdev);
• struct dss_module_power *mp = &dpu_kms->mp;
• msm_dss_put_clk(mp->clk_config, mp->num_clk);
• devm_kfree(&pdev->dev, mp->clk_config);
• mp->num_clk = 0;
• if (dpu_kms->rpm_enabled)

• pm_runtime_disable(&pdev->dev);
  

+}

+static const struct component_ops dpu_ops = {

• .bind = dpu_bind,
• .unbind = dpu_unbind,

+};

+static int dpu_dev_probe(struct platform_device *pdev) +{

• return component_add(&pdev->dev, &dpu_ops);

+}

+static int dpu_dev_remove(struct platform_device *pdev) +{

• component_del(&pdev->dev, &dpu_ops);
• return 0;

+}

+static int dpu_runtime_suspend(struct device *dev) +{

• int rc = -1;
• struct platform_device *pdev = to_platform_device(dev);
• struct dpu_kms *dpu_kms = platform_get_drvdata(pdev);
• struct drm_device *ddev;
• struct msm_drm_private *priv;
• struct dss_module_power *mp = &dpu_kms->mp;
• ddev = dpu_kms->dev;
• if (!ddev) {

• DPU_ERROR("invalid drm_device\n");
  

• goto exit;
  

• }
• priv = ddev->dev_private;
• rc = dpu_power_resource_enable(&priv->phandle,

• dpu_kms->core_client, false);
  

• if (rc)

• DPU_ERROR("resource disable failed: %d\n", rc);
  

• rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false);
• if (rc)

• DPU_ERROR("clock disable failed rc:%d\n", rc);
  

+exit:

• return rc;

+}

+static int dpu_runtime_resume(struct device *dev) +{

• int rc = -1;
• struct platform_device *pdev = to_platform_device(dev);
• struct dpu_kms *dpu_kms = platform_get_drvdata(pdev);
• struct drm_device *ddev;
• struct msm_drm_private *priv;
• struct dss_module_power *mp = &dpu_kms->mp;
• ddev = dpu_kms->dev;
• if (!ddev) {

• DPU_ERROR("invalid drm_device\n");
  

• goto exit;
  

• }
• priv = ddev->dev_private;
• rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true);
• if (rc) {

• DPU_ERROR("clock enable failed rc:%d\n", rc);
  

• goto exit;
  

• }
• rc = dpu_power_resource_enable(&priv->phandle, dpu_kms->core_client,

• true);
  

• if (rc)

• DPU_ERROR("resource enable failed: %d\n", rc);
  

+exit:

• return rc;

+}

+static const struct dev_pm_ops dpu_pm_ops = {

• SET_RUNTIME_PM_OPS(dpu_runtime_suspend, dpu_runtime_resume, NULL)

+};

+static const struct of_device_id dpu_dt_match[] = {

• { .compatible = "qcom,dpu", },
• {}

+}; +MODULE_DEVICE_TABLE(of, dpu_dt_match);

+static struct platform_driver dpu_driver = {

• .probe = dpu_dev_probe,
• .remove = dpu_dev_remove,
• .driver = {

• .name = "msm_dpu",
  

• .of_match_table = dpu_dt_match,
  

• .pm = &dpu_pm_ops,
  

• },

+};

+void __init msm_dpu_register(void) +{

• platform_driver_register(&dpu_driver);

+}

+void __exit msm_dpu_unregister(void) +{

• platform_driver_unregister(&dpu_driver);

+} diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index a1c0910..3c69921 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -200,6 +200,10 @@ struct dpu_kms { struct dpu_hw_mdp *hw_mdp;

bool has_danger_ctrl;

• struct platform_device *pdev;
• bool rpm_enabled;
• struct dss_module_power mp;

};

struct vsync_info { diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index a0e73ea..5470529 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -1731,6 +1731,7 @@ static int __init msm_drm_register(void)

DBG("init"); msm_mdp_register();

• msm_dpu_register(); msm_dsi_register(); msm_edp_register(); msm_hdmi_register();

@@ -1747,6 +1748,7 @@ static void __exit msm_drm_unregister(void) msm_edp_unregister(); msm_dsi_unregister(); msm_mdp_unregister();

• msm_dpu_unregister();

}

module_init(msm_drm_register); diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index e8e5e73..22a3096 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -682,6 +682,9 @@ static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, void __init msm_mdp_register(void); void __exit msm_mdp_unregister(void);

+void __init msm_dpu_register(void); +void __exit msm_dpu_unregister(void);

#ifdef CONFIG_DEBUG_FS void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m); void msm_gem_describe_objects(struct list_head *list, struct seq_file *m); -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

On Fri, May 11, 2018 at 08:19:36PM +0530, Rajesh Yadav wrote:

Currently, msm_drv was creating dpu_power_handle client which was used by dpu_dbg module to enable power resources before register debug dumping.

Now since, the mdss core power resource handling is implemented via runtime_pm and same has been removed from dpu_power_handle. Remove dpu_power_handle dependency from msm_drv and use pm_runtime_get/put_sync calls from dpu_dbg module on dpu_mdss top level device for core, ahb clock and power resource management (for register access).

Changes in v2:

• resolved conflict in dpu_core_perf_init
• dropped (Reviewed-by: Sean Paul) due to above change

Reviewed-by: Sean Paul seanpaul@chromium.org

Signed-off-by: Rajesh Yadav ryadav@codeaurora.org

drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 7 ------- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +-- drivers/gpu/drm/msm/dpu_dbg.c | 18 +++++++----------- drivers/gpu/drm/msm/dpu_dbg.h | 13 ++----------- drivers/gpu/drm/msm/msm_drv.c | 27 +-------------------------- drivers/gpu/drm/msm/msm_drv.h | 1 - 7 files changed, 11 insertions(+), 62 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c index 5b79077..2cf3fca 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c @@ -673,18 +673,11 @@ int dpu_core_perf_init(struct dpu_core_perf *perf, struct drm_device *dev, struct dpu_mdss_cfg *catalog, struct dpu_power_handle *phandle,

• struct dpu_power_client *pclient,
  

  struct dss_clk *core_clk)

{

• if (!pclient) {

• DPU_ERROR("invalid parameters\n");
  

• return -EINVAL;
  

• }

• perf->dev = dev; perf->catalog = catalog; perf->phandle = phandle;

• perf->pclient = pclient; perf->core_clk = core_clk;

  perf->max_core_clk_rate = core_clk->max_rate;

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h index 9c1a719..cde48df 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h @@ -53,7 +53,6 @@ struct dpu_core_perf_tune {

• @debugfs_root: top level debug folder
• @catalog: Pointer to catalog configuration
• @phandle: Pointer to power handler

• • @pclient: Pointer to power client
  • @core_clk: Pointer to core clock structure
  • @core_clk_rate: current core clock rate
  • @max_core_clk_rate: maximum allowable core clock rate

@@ -68,7 +67,6 @@ struct dpu_core_perf { struct dentry *debugfs_root; struct dpu_mdss_cfg *catalog; struct dpu_power_handle *phandle;

• struct dpu_power_client *pclient; struct dss_clk *core_clk; u64 core_clk_rate; u64 max_core_clk_rate;

@@ -115,14 +113,12 @@ void dpu_core_perf_crtc_update(struct drm_crtc *crtc,

• @dev: Pointer to drm device
• @catalog: Pointer to catalog
• @phandle: Pointer to power handle

• • @pclient: Pointer to power client
  • @core_clk: pointer to core clock
  */

int dpu_core_perf_init(struct dpu_core_perf *perf, struct drm_device *dev, struct dpu_mdss_cfg *catalog, struct dpu_power_handle *phandle,

• struct dpu_power_client *pclient,
  

  struct dss_clk *core_clk);

/** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 349bda5..9c3b220 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1721,8 +1721,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms) #endif

rc = dpu_core_perf_init(&dpu_kms->perf, dev, dpu_kms->catalog,

• 	&priv->phandle, priv->pclient,
  

• 	_dpu_kms_get_clk(dpu_kms, "core_clk"));
  

• 	&priv->phandle, _dpu_kms_get_clk(dpu_kms, "core_clk"));
  

  if (rc) { DPU_ERROR("failed to init perf %d\n", rc); goto perf_err;

diff --git a/drivers/gpu/drm/msm/dpu_dbg.c b/drivers/gpu/drm/msm/dpu_dbg.c index 4a39b82..27538bc 100644 --- a/drivers/gpu/drm/msm/dpu_dbg.c +++ b/drivers/gpu/drm/msm/dpu_dbg.c @@ -20,6 +20,7 @@ #include <linux/dma-buf.h> #include <linux/slab.h> #include <linux/list_sort.h> +#include <linux/pm_runtime.h>

#include "dpu_dbg.h" #include "disp/dpu1/dpu_hw_catalog.h" @@ -167,7 +168,6 @@ struct dpu_dbg_vbif_debug_bus {

• @evtlog: event log instance
• @reg_base_list: list of register dumping regions
• @dev: device pointer

• • @power_ctrl: callback structure for enabling power for reading hw registers
  • @req_dump_blks: list of blocks requested for dumping
  • @panic_on_err: whether to kernel panic after triggering dump via debugfs
  • @dump_work: work struct for deferring register dump work to separate thread

@@ -182,7 +182,6 @@ struct dpu_dbg_vbif_debug_bus { struct dpu_dbg_evtlog *evtlog; struct list_head reg_base_list; struct device *dev;

• struct dpu_dbg_power_ctrl power_ctrl;

  struct dpu_dbg_reg_base *req_dump_blks[DPU_DBG_BASE_MAX];

@@ -2008,12 +2007,10 @@ static void _dpu_debug_bus_ppb1_dump(void __iomem *mem_base, */ static inline void _dpu_dbg_enable_power(int enable) {

• if (!dpu_dbg_base.power_ctrl.enable_fn)

• return;
  

• dpu_dbg_base.power_ctrl.enable_fn(

• 	dpu_dbg_base.power_ctrl.handle,
  

• 	dpu_dbg_base.power_ctrl.client,
  

• 	enable);
  

• if (enable)

• pm_runtime_get_sync(dpu_dbg_base.dev);
  

• else

• pm_runtime_put_sync(dpu_dbg_base.dev);
  

}

/** @@ -3099,16 +3096,15 @@ void dpu_dbg_init_dbg_buses(u32 hwversion) } }

-int dpu_dbg_init(struct device *dev, struct dpu_dbg_power_ctrl *power_ctrl) +int dpu_dbg_init(struct device *dev) {

• if (!dev || !power_ctrl) {

• if (!dev) { pr_err("invalid params\n"); return -EINVAL; }

  INIT_LIST_HEAD(&dpu_dbg_base.reg_base_list); dpu_dbg_base.dev = dev;

• dpu_dbg_base.power_ctrl = *power_ctrl;

  dpu_dbg_base.evtlog = dpu_evtlog_init(); if (IS_ERR_OR_NULL(dpu_dbg_base.evtlog))

diff --git a/drivers/gpu/drm/msm/dpu_dbg.h b/drivers/gpu/drm/msm/dpu_dbg.h index e79b5aa..283dbbc 100644 --- a/drivers/gpu/drm/msm/dpu_dbg.h +++ b/drivers/gpu/drm/msm/dpu_dbg.h @@ -71,12 +71,6 @@ enum dpu_dbg_dump_flag { #define DPU_EVTLOG_BUF_MAX 512 #define DPU_EVTLOG_BUF_ALIGN 32

-struct dpu_dbg_power_ctrl {

• void *handle;
• void *client;
• int (*enable_fn)(void *handle, void *client, bool enable);

-};

struct dpu_dbg_evtlog_log { s64 time; const char *name; @@ -211,11 +205,9 @@ ssize_t dpu_evtlog_dump_to_buffer(struct dpu_dbg_evtlog *evtlog, /**

• dpu_dbg_init - initialize global dpu debug facilities: evtlog, regdump
• @dev: device handle

• • @power_ctrl: power control callback structure for enabling clocks

• • 	during register dumping
    

  • Returns: 0 or -ERROR
  */

-int dpu_dbg_init(struct device *dev, struct dpu_dbg_power_ctrl *power_ctrl); +int dpu_dbg_init(struct device *dev);

/**

• dpu_dbg_debugfs_register - register entries at the given debugfs dir

@@ -359,8 +351,7 @@ static inline void dpu_dbg_init_dbg_buses(u32 hwversion) { }

-static inline int dpu_dbg_init(struct device *dev,

• struct dpu_dbg_power_ctrl *power_ctrl)
  

+static inline int dpu_dbg_init(struct device *dev) { return 0; } diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 5470529..5c267cd 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -340,7 +340,6 @@ static int msm_drm_uninit(struct device *dev) component_unbind_all(dev, ddev);

#ifdef CONFIG_DRM_MSM_DPU

• dpu_power_client_destroy(&priv->phandle, priv->pclient); dpu_power_resource_deinit(pdev, &priv->phandle); dpu_dbg_destroy();

#endif @@ -464,13 +463,6 @@ static int msm_component_bind_all(struct device *dev, } #endif

-#ifdef CONFIG_DRM_MSM_DPU -static int msm_power_enable_wrapper(void *handle, void *client, bool enable) -{

• return dpu_power_resource_enable(handle, client, enable);

-} -#endif

static int msm_drm_init(struct device *dev, struct drm_driver *drv) { struct platform_device *pdev = to_platform_device(dev); @@ -479,10 +471,6 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv) struct msm_kms *kms; struct msm_mdss *mdss;

-#ifdef CONFIG_DRM_MSM_DPU

• struct dpu_dbg_power_ctrl dbg_power_ctrl = { 0 };

-#endif

• int ret, i; struct sched_param param;

@@ -537,18 +525,7 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv) goto power_init_fail; }

• priv->pclient = dpu_power_client_create(&priv->phandle, "dpu");
• if (IS_ERR_OR_NULL(priv->pclient)) {

• pr_err("dpu power client create failed\n");
  

• ret = -EINVAL;
  

• goto power_client_fail;
  

• }
• dbg_power_ctrl.handle = &priv->phandle;
• dbg_power_ctrl.client = priv->pclient;
• dbg_power_ctrl.enable_fn = msm_power_enable_wrapper;
• ret = dpu_dbg_init(&pdev->dev, &dbg_power_ctrl);

• ret = dpu_dbg_init(&pdev->dev); if (ret) { dev_err(dev, "failed to init dpu dbg: %d\n", ret); goto dbg_init_fail;

@@ -756,8 +733,6 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv) #ifdef CONFIG_DRM_MSM_DPU dpu_dbg_destroy(); dbg_init_fail:

• dpu_power_client_destroy(&priv->phandle, priv->pclient);

-power_client_fail: dpu_power_resource_deinit(pdev, &priv->phandle); power_init_fail: #endif diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 22a3096..f9ae96f 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -376,7 +376,6 @@ struct msm_drm_private { struct msm_kms *kms;

struct dpu_power_handle phandle;

• struct dpu_power_client *pclient;

  /* subordinate devices, if present: */ struct platform_device *gpu_pdev;

-- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

On Fri, May 11, 2018 at 08:19:37PM +0530, Rajesh Yadav wrote:

Now, since dpu_power_handle manages only bus scaling and power enable/disable notifications which are restricted to dpu driver, move dpu_power_handle to dpu folder.

Changes in v2:

• resolved conflict in dpu_unbind
• dropped (Reviewed-by: Sean Paul) due to above change

Reviewed-by: Sean Paul seanpaul@chromium.org

Signed-off-by: Rajesh Yadav ryadav@codeaurora.org

drivers/gpu/drm/msm/Makefile | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 5 +- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 7 +- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 2 + drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 39 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c | 693 +++++++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h | 288 ++++++++++ drivers/gpu/drm/msm/dpu_power_handle.c | 693 ----------------------- drivers/gpu/drm/msm/dpu_power_handle.h | 288 ---------- drivers/gpu/drm/msm/msm_drv.c | 9 - drivers/gpu/drm/msm/msm_drv.h | 4 - 14 files changed, 1013 insertions(+), 1020 deletions(-) create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h delete mode 100644 drivers/gpu/drm/msm/dpu_power_handle.c delete mode 100644 drivers/gpu/drm/msm/dpu_power_handle.h

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index d9826c1..f578d5a 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -82,10 +82,10 @@ msm-y := \ disp/dpu1/dpu_rm.o \ disp/dpu1/dpu_vbif.o \ disp/dpu1/dpu_mdss.o \

• disp/dpu1/dpu_power_handle.o \ dpu_dbg.o \ dpu_io_util.o \ dpu_dbg_evtlog.o \

• dpu_power_handle.o \ msm_prop.o \ msm_atomic.o \ msm_debugfs.o \

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c index 5c5cc56..33ab2ac 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c @@ -18,7 +18,6 @@ #include <linux/kthread.h>

#include "dpu_core_irq.h" -#include "dpu_power_handle.h"

/**

• dpu_core_irq_callback_handler - dispatch core interrupts

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c index 2cf3fca..d3a1ed9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c @@ -257,7 +257,6 @@ static void _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms, = dpu_crtc_get_client_type(crtc); struct drm_crtc *tmp_crtc; struct dpu_crtc_state *dpu_cstate;

• struct msm_drm_private *priv = kms->dev->dev_private;

  drm_for_each_crtc(tmp_crtc, crtc->dev) { if (_dpu_core_perf_crtc_is_power_on(tmp_crtc) &&

@@ -287,7 +286,7 @@ static void _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms,

switch (curr_client_type) { case NRT_CLIENT:

• dpu_power_data_bus_set_quota(&priv->phandle, kms->core_client,
  

• dpu_power_data_bus_set_quota(&kms->phandle, kms->core_client,
  	DPU_POWER_HANDLE_DATA_BUS_CLIENT_NRT,
  	bus_id, bus_ab_quota, bus_ib_quota);
  

  DPU_DEBUG("client:%s bus_id=%d ab=%llu ib=%llu\n", "nrt",

@@ -295,7 +294,7 @@ static void _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms, break;

case RT_CLIENT:

• dpu_power_data_bus_set_quota(&priv->phandle, kms->core_client,
  

• dpu_power_data_bus_set_quota(&kms->phandle, kms->core_client,
  	DPU_POWER_HANDLE_DATA_BUS_CLIENT_RT,
  	bus_id, bus_ab_quota, bus_ib_quota);
  

  DPU_DEBUG("client:%s bus_id=%d ab=%llu ib=%llu\n", "rt",

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index e2d2e32..99c5e75 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -598,6 +598,7 @@ static void dpu_crtc_destroy(struct drm_crtc *crtc) _dpu_crtc_destroy_dest_scaler(dpu_crtc);

_dpu_crtc_deinit_events(dpu_crtc);

• dpu_crtc->phandle = NULL;

  drm_crtc_cleanup(crtc); mutex_destroy(&dpu_crtc->crtc_lock);

@@ -2572,7 +2573,7 @@ static void dpu_crtc_disable(struct drm_crtc *crtc) }

if (dpu_crtc->power_event)

• dpu_power_handle_unregister_event(&priv->phandle,
  

• dpu_power_handle_unregister_event(dpu_crtc->phandle,
  	dpu_crtc->power_event);
  
  
  

@@ -2643,7 +2644,7 @@ static void dpu_crtc_enable(struct drm_crtc *crtc, mutex_unlock(&dpu_crtc->crtc_lock);

dpu_crtc->power_event = dpu_power_handle_register_event(

• &priv->phandle,
  

• dpu_crtc->phandle,
  

  DPU_POWER_EVENT_POST_ENABLE | DPU_POWER_EVENT_POST_DISABLE | DPU_POWER_EVENT_PRE_DISABLE, dpu_crtc_handle_power_event, crtc, dpu_crtc->name);

@@ -3938,6 +3939,8 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane) dpu_cp_crtc_init(crtc); dpu_cp_crtc_install_properties(crtc);

• dpu_crtc->phandle = &kms->phandle;
• DPU_DEBUG("%s: successfully initialized crtc\n", dpu_crtc->name); return crtc;

} diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h index 9304058..671d909 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h @@ -184,6 +184,7 @@ struct dpu_crtc_event {

• @misr_enable : boolean entry indicates misr enable/disable status.
• @misr_frame_count : misr frame count provided by client
• @misr_data : store misr data before turning off the clocks.

• • @phandle: Pointer to power handler
  • @power_event : registered power event handle
  • @cur_perf : current performance committed to clock/bandwidth driver
  • @rp_lock : serialization lock for resource pool

@@ -240,6 +241,7 @@ struct dpu_crtc { u32 misr_frame_count; u32 misr_data[CRTC_DUAL_MIXERS];

• struct dpu_power_handle *phandle; struct dpu_power_event *power_event;

  struct dpu_core_perf_params cur_perf;

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 298a6ef..11ae6cc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -31,7 +31,6 @@ #include "dpu_hw_ctl.h" #include "dpu_formats.h" #include "dpu_encoder_phys.h" -#include "dpu_power_handle.h" #include "dpu_crtc.h" #include "dpu_trace.h" #include "dpu_core_irq.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 9c3b220..0598cfb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1017,24 +1017,19 @@ static long dpu_kms_round_pixclk(struct msm_kms *kms, unsigned long rate, static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms) { struct drm_device *dev;

• struct msm_drm_private *priv; int i;

  dev = dpu_kms->dev; if (!dev) return;

• priv = dev->dev_private;

• if (!priv)

• return;
  

• if (dpu_kms->hw_intr) dpu_hw_intr_destroy(dpu_kms->hw_intr); dpu_kms->hw_intr = NULL;

  if (dpu_kms->power_event) dpu_power_handle_unregister_event(

• 		&priv->phandle, dpu_kms->power_event);
  

• 		&dpu_kms->phandle, dpu_kms->power_event);
  
  

  /* safe to call these more than once during shutdown */ _dpu_debugfs_destroy(dpu_kms);

@@ -1067,7 +1062,8 @@ static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms) dpu_kms->catalog = NULL;

if (dpu_kms->core_client)

• dpu_power_client_destroy(&priv->phandle, dpu_kms->core_client);
  

• dpu_power_client_destroy(&dpu_kms->phandle,
  

• 	dpu_kms->core_client);
  

  dpu_kms->core_client = NULL;

  if (dpu_kms->vbif[VBIF_NRT])

@@ -1624,7 +1620,8 @@ static int dpu_kms_hw_init(struct msm_kms *kms) } #endif

• dpu_kms->core_client = dpu_power_client_create(&priv->phandle, "core");

• dpu_kms->core_client = dpu_power_client_create(&dpu_kms->phandle,

• 			"core");
  

  if (IS_ERR_OR_NULL(dpu_kms->core_client)) { rc = PTR_ERR(dpu_kms->core_client); if (!dpu_kms->core_client)

@@ -1721,7 +1718,8 @@ static int dpu_kms_hw_init(struct msm_kms *kms) #endif

rc = dpu_core_perf_init(&dpu_kms->perf, dev, dpu_kms->catalog,

• 	&priv->phandle, _dpu_kms_get_clk(dpu_kms, "core_clk"));
  

• 	&dpu_kms->phandle,
  

• 	_dpu_kms_get_clk(dpu_kms, "core_clk"));
  

  if (rc) { DPU_ERROR("failed to init perf %d\n", rc); goto perf_err;

@@ -1765,7 +1763,8 @@ static int dpu_kms_hw_init(struct msm_kms *kms) * Handle (re)initializations during power enable */ dpu_kms_handle_power_event(DPU_POWER_EVENT_POST_ENABLE, dpu_kms);

• dpu_kms->power_event = dpu_power_handle_register_event(&priv->phandle,

• dpu_kms->power_event = dpu_power_handle_register_event(

• 	&dpu_kms->phandle,
  DPU_POWER_EVENT_POST_ENABLE,
  dpu_kms_handle_power_event, dpu_kms, "kms");
  
  

@@ -1841,6 +1840,12 @@ static int dpu_bind(struct device *dev, struct device *master, void *data) goto clk_rate_error; }

• ret = dpu_power_resource_init(pdev, &dpu_kms->phandle);

• if (ret) {

• pr_err("dpu power resource init failed\n");
  

• goto power_init_fail;
  

• }

• platform_set_drvdata(pdev, dpu_kms);

  msm_kms_init(&dpu_kms->base, &kms_funcs);

@@ -1853,6 +1858,7 @@ static int dpu_bind(struct device *dev, struct device *master, void *data) priv->kms = &dpu_kms->base; return ret;

+power_init_fail: clk_rate_error: msm_dss_put_clk(mp->clk_config, mp->num_clk); clk_get_error: @@ -1867,6 +1873,7 @@ static void dpu_unbind(struct device *dev, struct device *master, void *data) struct dpu_kms *dpu_kms = platform_get_drvdata(pdev); struct dss_module_power *mp = &dpu_kms->mp;

• dpu_power_resource_deinit(pdev, &dpu_kms->phandle); msm_dss_put_clk(mp->clk_config, mp->num_clk); devm_kfree(&pdev->dev, mp->clk_config); mp->num_clk = 0;

@@ -1897,7 +1904,6 @@ static int dpu_runtime_suspend(struct device *dev) struct platform_device *pdev = to_platform_device(dev); struct dpu_kms *dpu_kms = platform_get_drvdata(pdev); struct drm_device *ddev;

• struct msm_drm_private *priv; struct dss_module_power *mp = &dpu_kms->mp;

  ddev = dpu_kms->dev;

@@ -1905,10 +1911,9 @@ static int dpu_runtime_suspend(struct device *dev) DPU_ERROR("invalid drm_device\n"); goto exit; }

• priv = ddev->dev_private;

• rc = dpu_power_resource_enable(&priv->phandle,

• dpu_kms->core_client, false);
  

• rc = dpu_power_resource_enable(&dpu_kms->phandle,

• 	dpu_kms->core_client, false);
  

  if (rc) DPU_ERROR("resource disable failed: %d\n", rc);

@@ -1926,7 +1931,6 @@ static int dpu_runtime_resume(struct device *dev) struct platform_device *pdev = to_platform_device(dev); struct dpu_kms *dpu_kms = platform_get_drvdata(pdev); struct drm_device *ddev;

• struct msm_drm_private *priv; struct dss_module_power *mp = &dpu_kms->mp;

  ddev = dpu_kms->dev;

@@ -1934,7 +1938,6 @@ static int dpu_runtime_resume(struct device *dev) DPU_ERROR("invalid drm_device\n"); goto exit; }

• priv = ddev->dev_private;

  rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true); if (rc) {

@@ -1942,8 +1945,8 @@ static int dpu_runtime_resume(struct device *dev) goto exit; }

• rc = dpu_power_resource_enable(&priv->phandle, dpu_kms->core_client,

• true);
  

• rc = dpu_power_resource_enable(&dpu_kms->phandle,

• 	dpu_kms->core_client, true);
  

  if (rc) DPU_ERROR("resource enable failed: %d\n", rc);

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index a8255fe..c48ed4e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -164,6 +164,7 @@ struct dpu_kms { struct dpu_mdss_cfg *catalog;

struct msm_gem_address_space *aspace[MSM_SMMU_DOMAIN_MAX];

• struct dpu_power_handle phandle; struct dpu_power_client *core_client;

#ifdef CONFIG_ION struct ion_client *iclient; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c new file mode 100644 index 0000000..77be106 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c @@ -0,0 +1,693 @@ +/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.

• • This program is free software; you can redistribute it and/or modify
• • it under the terms of the GNU General Public License version 2 and
• • only version 2 as published by the Free Software Foundation.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• */

+#define pr_fmt(fmt) "[drm:%s:%d]: " fmt, __func__, __LINE__

+#include <linux/kernel.h> +#include <linux/of.h> +#include <linux/string.h> +#include <linux/of_address.h> +#include <linux/slab.h> +#include <linux/mutex.h> +#include <linux/of_platform.h> +#ifdef CONFIG_QCOM_BUS_SCALING +#include <linux/msm-bus.h> +#include <linux/msm-bus-board.h> +#endif +#include <linux/dpu_io_util.h>

+#include "dpu_power_handle.h" +#include "dpu_trace.h"

+static const char *data_bus_name[DPU_POWER_HANDLE_DBUS_ID_MAX] = {

• [DPU_POWER_HANDLE_DBUS_ID_MNOC] = "qcom,dpu-data-bus",
• [DPU_POWER_HANDLE_DBUS_ID_LLCC] = "qcom,dpu-llcc-bus",
• [DPU_POWER_HANDLE_DBUS_ID_EBI] = "qcom,dpu-ebi-bus",

+};

+const char *dpu_power_handle_get_dbus_name(u32 bus_id) +{

• if (bus_id < DPU_POWER_HANDLE_DBUS_ID_MAX)

• return data_bus_name[bus_id];
  

• return NULL;

+}

+static void dpu_power_event_trigger_locked(struct dpu_power_handle *phandle,

• u32 event_type)
  

+{

• struct dpu_power_event *event;
• list_for_each_entry(event, &phandle->event_list, list) {

• if (event->event_type & event_type)
  

• 	event->cb_fnc(event_type, event->usr);
  

• }

+}

+struct dpu_power_client *dpu_power_client_create(

• struct dpu_power_handle *phandle, char *client_name)

+{

• struct dpu_power_client *client;
• static u32 id;
• if (!client_name || !phandle) {

• pr_err("client name is null or invalid power data\n");
  

• return ERR_PTR(-EINVAL);
  

• }
• client = kzalloc(sizeof(struct dpu_power_client), GFP_KERNEL);
• if (!client)

• return ERR_PTR(-ENOMEM);
  

• mutex_lock(&phandle->phandle_lock);
• strlcpy(client->name, client_name, MAX_CLIENT_NAME_LEN);
• client->usecase_ndx = VOTE_INDEX_DISABLE;
• client->id = id;
• client->active = true;
• pr_debug("client %s created:%pK id :%d\n", client_name,

• client, id);
  

• id++;
• list_add(&client->list, &phandle->power_client_clist);
• mutex_unlock(&phandle->phandle_lock);
• return client;

+}

+void dpu_power_client_destroy(struct dpu_power_handle *phandle,

• struct dpu_power_client *client)

+{

• if (!client || !phandle) {

• pr_err("reg bus vote: invalid client handle\n");
  

• } else if (!client->active) {

• pr_err("dpu power deinit already done\n");
  

• kfree(client);
  

• } else {

• pr_debug("bus vote client %s destroyed:%pK id:%u\n",
  

• 	client->name, client, client->id);
  

• mutex_lock(&phandle->phandle_lock);
  

• list_del_init(&client->list);
  

• mutex_unlock(&phandle->phandle_lock);
  

• kfree(client);
  

• }

+}

+#ifdef CONFIG_QCOM_BUS_SCALING

+#define MAX_AXI_PORT_COUNT 3

+static int _dpu_power_data_bus_set_quota(

• struct dpu_power_data_bus_handle *pdbus,
  

• u64 ab_quota_rt, u64 ab_quota_nrt,
  

• u64 ib_quota_rt, u64 ib_quota_nrt)
  

+{

• int new_uc_idx;
• u64 ab_quota[MAX_AXI_PORT_COUNT] = {0, 0};
• u64 ib_quota[MAX_AXI_PORT_COUNT] = {0, 0};
• int rc;
• if (pdbus->data_bus_hdl < 1) {

• pr_err("invalid bus handle %d\n", pdbus->data_bus_hdl);
  

• return -EINVAL;
  

• }
• pdbus->ab_rt = ab_quota_rt;
• pdbus->ib_rt = ib_quota_rt;
• pdbus->ab_nrt = ab_quota_nrt;
• pdbus->ib_nrt = ib_quota_nrt;
• if (pdbus->enable) {

• ab_quota_rt = max_t(u64, ab_quota_rt,
  

• 		DPU_POWER_HANDLE_ENABLE_BUS_AB_QUOTA);
  

• ib_quota_rt = max_t(u64, ib_quota_rt,
  

• 		DPU_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  

• ab_quota_nrt = max_t(u64, ab_quota_nrt,
  

• 		DPU_POWER_HANDLE_ENABLE_BUS_AB_QUOTA);
  

• ib_quota_nrt = max_t(u64, ib_quota_nrt,
  

• 		DPU_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  

• } else {

• ab_quota_rt = min_t(u64, ab_quota_rt,
  

• 		DPU_POWER_HANDLE_DISABLE_BUS_AB_QUOTA);
  

• ib_quota_rt = min_t(u64, ib_quota_rt,
  

• 		DPU_POWER_HANDLE_DISABLE_BUS_IB_QUOTA);
  

• ab_quota_nrt = min_t(u64, ab_quota_nrt,
  

• 		DPU_POWER_HANDLE_DISABLE_BUS_AB_QUOTA);
  

• ib_quota_nrt = min_t(u64, ib_quota_nrt,
  

• 		DPU_POWER_HANDLE_DISABLE_BUS_IB_QUOTA);
  

• }
• if (!ab_quota_rt && !ab_quota_nrt && !ib_quota_rt && !ib_quota_nrt) {

• new_uc_idx = 0;
  

• } else {

• int i;
  

• struct msm_bus_vectors *vect = NULL;
  

• struct msm_bus_scale_pdata *bw_table =
  

• 	pdbus->data_bus_scale_table;
  

• u32 nrt_axi_port_cnt = pdbus->nrt_axi_port_cnt;
  

• u32 total_axi_port_cnt = pdbus->axi_port_cnt;
  

• u32 rt_axi_port_cnt = total_axi_port_cnt - nrt_axi_port_cnt;
  

• if (!bw_table || !total_axi_port_cnt ||
  

•     total_axi_port_cnt > MAX_AXI_PORT_COUNT) {
  

• 	pr_err("invalid input\n");
  

• 	return -EINVAL;
  

• }
  

• if (pdbus->bus_channels) {
  

• 	ib_quota_rt = div_u64(ib_quota_rt,
  

• 				pdbus->bus_channels);
  

• 	ib_quota_nrt = div_u64(ib_quota_nrt,
  

• 				pdbus->bus_channels);
  

• }
  

• if (nrt_axi_port_cnt) {
  

• 	ab_quota_rt = div_u64(ab_quota_rt, rt_axi_port_cnt);
  

• 	ab_quota_nrt = div_u64(ab_quota_nrt, nrt_axi_port_cnt);
  

• 	for (i = 0; i < total_axi_port_cnt; i++) {
  

• 		if (i < rt_axi_port_cnt) {
  

• 			ab_quota[i] = ab_quota_rt;
  

• 			ib_quota[i] = ib_quota_rt;
  

• 		} else {
  

• 			ab_quota[i] = ab_quota_nrt;
  

• 			ib_quota[i] = ib_quota_nrt;
  

• 		}
  

• 	}
  

• } else {
  

• 	ab_quota[0] = div_u64(ab_quota_rt + ab_quota_nrt,
  

• 			total_axi_port_cnt);
  

• 	ib_quota[0] = ib_quota_rt + ib_quota_nrt;
  

• 	for (i = 1; i < total_axi_port_cnt; i++) {
  

• 		ab_quota[i] = ab_quota[0];
  

• 		ib_quota[i] = ib_quota[0];
  

• 	}
  

• }
  

• new_uc_idx = (pdbus->curr_bw_uc_idx %
  

• 	(bw_table->num_usecases - 1)) + 1;
  

• for (i = 0; i < total_axi_port_cnt; i++) {
  

• 	vect = &bw_table->usecase[new_uc_idx].vectors[i];
  

• 	vect->ab = ab_quota[i];
  

• 	vect->ib = ib_quota[i];
  

• 	pr_debug(
  

• 		"%s uc_idx=%d %s path idx=%d ab=%llu ib=%llu\n",
  

• 		bw_table->name,
  

• 		new_uc_idx, (i < rt_axi_port_cnt) ? "rt" : "nrt"
  

• 		, i, vect->ab, vect->ib);
  

• }
  

• }
• pdbus->curr_bw_uc_idx = new_uc_idx;
• pdbus->ao_bw_uc_idx = new_uc_idx;
• DPU_ATRACE_BEGIN("msm_bus_scale_req");
• rc = msm_bus_scale_client_update_request(pdbus->data_bus_hdl,

• 	new_uc_idx);
  

• DPU_ATRACE_END("msm_bus_scale_req");
• return rc;

+}

+int dpu_power_data_bus_set_quota(struct dpu_power_handle *phandle,

• struct dpu_power_client *pclient,
  

• int bus_client, u32 bus_id,
  

• u64 ab_quota, u64 ib_quota)
  

+{

• int rc = 0;
• int i;
• u64 total_ab_rt = 0, total_ib_rt = 0;
• u64 total_ab_nrt = 0, total_ib_nrt = 0;
• struct dpu_power_client *client;
• if (!phandle || !pclient ||

• 	bus_client >= DPU_POWER_HANDLE_DATA_BUS_CLIENT_MAX ||
  

• 	bus_id >= DPU_POWER_HANDLE_DBUS_ID_MAX) {
  

• pr_err("invalid parameters\n");
  

• return -EINVAL;
  

• }
• mutex_lock(&phandle->phandle_lock);
• pclient->ab[bus_client] = ab_quota;
• pclient->ib[bus_client] = ib_quota;
• trace_dpu_perf_update_bus(bus_client, ab_quota, ib_quota);
• list_for_each_entry(client, &phandle->power_client_clist, list) {

• for (i = 0; i < DPU_POWER_HANDLE_DATA_BUS_CLIENT_MAX; i++) {
  

• 	if (i == DPU_POWER_HANDLE_DATA_BUS_CLIENT_NRT) {
  

• 		total_ab_nrt += client->ab[i];
  

• 		total_ib_nrt += client->ib[i];
  

• 	} else {
  

• 		total_ab_rt += client->ab[i];
  

• 		total_ib_rt = max(total_ib_rt, client->ib[i]);
  

• 	}
  

• }
  

• }
• if (phandle->data_bus_handle[bus_id].data_bus_hdl)

• rc = _dpu_power_data_bus_set_quota(
  

• 	&phandle->data_bus_handle[bus_id],
  

• 	total_ab_rt, total_ab_nrt,
  

• 	total_ib_rt, total_ib_nrt);
  

• mutex_unlock(&phandle->phandle_lock);
• return rc;

+}

+static void dpu_power_data_bus_unregister(

• struct dpu_power_data_bus_handle *pdbus)
  

+{

• if (pdbus->data_bus_hdl) {

• msm_bus_scale_unregister_client(pdbus->data_bus_hdl);
  

• pdbus->data_bus_hdl = 0;
  

• }

+}

+static int dpu_power_data_bus_parse(struct platform_device *pdev,

• struct dpu_power_data_bus_handle *pdbus, const char *name)

+{

• struct device_node *node;
• int rc = 0;
• int paths;
• pdbus->bus_channels = 1;
• rc = of_property_read_u32(pdev->dev.of_node,

• "qcom,dpu-dram-channels", &pdbus->bus_channels);
  

• if (rc) {

• pr_debug("number of channels property not specified\n");
  

• rc = 0;
  

• }
• pdbus->nrt_axi_port_cnt = 0;
• rc = of_property_read_u32(pdev->dev.of_node,

• 	"qcom,dpu-num-nrt-paths",
  

• 	&pdbus->nrt_axi_port_cnt);
  

• if (rc) {

• pr_debug("number of axi port property not specified\n");
  

• rc = 0;
  

• }
• node = of_get_child_by_name(pdev->dev.of_node, name);
• if (node) {

• rc = of_property_read_u32(node,
  

• 		"qcom,msm-bus,num-paths", &paths);
  

• if (rc) {
  

• 	pr_err("Error. qcom,msm-bus,num-paths not found\n");
  

• 	return rc;
  

• }
  

• pdbus->axi_port_cnt = paths;
  

• pdbus->data_bus_scale_table =
  

• 		msm_bus_pdata_from_node(pdev, node);
  

• if (IS_ERR_OR_NULL(pdbus->data_bus_scale_table)) {
  

• 	pr_err("reg bus handle parsing failed\n");
  

• 	rc = PTR_ERR(pdbus->data_bus_scale_table);
  

• 	if (!pdbus->data_bus_scale_table)
  

• 		rc = -EINVAL;
  

• 	goto end;
  

• }
  

• pdbus->data_bus_hdl = msm_bus_scale_register_client(
  

• 		pdbus->data_bus_scale_table);
  

• if (!pdbus->data_bus_hdl) {
  

• 	pr_err("data_bus_client register failed\n");
  

• 	rc = -EINVAL;
  

• 	goto end;
  

• }
  

• pr_debug("register %s data_bus_hdl=%x\n", name,
  

• 		pdbus->data_bus_hdl);
  

• }

+end:

• return rc;

+}

+static int dpu_power_reg_bus_parse(struct platform_device *pdev,

• struct dpu_power_handle *phandle)

+{

• struct device_node *node;
• struct msm_bus_scale_pdata *bus_scale_table;
• int rc = 0;
• node = of_get_child_by_name(pdev->dev.of_node, "qcom,dpu-reg-bus");
• if (node) {

• bus_scale_table = msm_bus_pdata_from_node(pdev, node);
  

• if (IS_ERR_OR_NULL(bus_scale_table)) {
  

• 	pr_err("reg bus handle parsing failed\n");
  

• 	rc = PTR_ERR(bus_scale_table);
  

• 	if (!bus_scale_table)
  

• 		rc = -EINVAL;
  

• 	goto end;
  

• }
  

• phandle->reg_bus_hdl = msm_bus_scale_register_client(
  

• 	      bus_scale_table);
  

• if (!phandle->reg_bus_hdl) {
  

• 	pr_err("reg_bus_client register failed\n");
  

• 	rc = -EINVAL;
  

• 	goto end;
  

• }
  

• pr_debug("register reg_bus_hdl=%x\n", phandle->reg_bus_hdl);
  

• }

+end:

• return rc;

+}

+static void dpu_power_reg_bus_unregister(u32 reg_bus_hdl) +{

• if (reg_bus_hdl)

• msm_bus_scale_unregister_client(reg_bus_hdl);
  

+}

+int dpu_power_data_bus_state_update(struct dpu_power_handle *phandle,

• 					bool enable)
  

+{

• int i;
• if (!phandle) {

• pr_err("invalid param\n");
  

• return -EINVAL;
  

• }
• for (i = DPU_POWER_HANDLE_DBUS_ID_MNOC;

• 	i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++)
  

• phandle->data_bus_handle[i].enable = enable;
  

• return 0;

+}

+static int dpu_power_data_bus_update(struct dpu_power_data_bus_handle *pdbus,

• 					bool enable)
  

+{

• int rc = 0;
• pdbus->enable = enable;
• if (pdbus->data_bus_hdl)

• rc = _dpu_power_data_bus_set_quota(pdbus, pdbus->ab_rt,
  

• 		pdbus->ab_nrt, pdbus->ib_rt, pdbus->ib_nrt);
  

• if (rc)

• pr_err("failed to set data bus vote rc=%d enable:%d\n",
  

• 					rc, enable);
  

• return rc;

+}

+static int dpu_power_reg_bus_update(u32 reg_bus_hdl, u32 usecase_ndx) +{

• int rc = 0;
• if (reg_bus_hdl)

• rc = msm_bus_scale_client_update_request(reg_bus_hdl,
  

• 						usecase_ndx);
  

• if (rc)

• pr_err("failed to set reg bus vote rc=%d\n", rc);
  

• return rc;

+} +#else +static int dpu_power_data_bus_parse(struct platform_device *pdev,

• struct dpu_power_data_bus_handle *pdbus, const char *name)
  

+{

• return 0;

+}

+static void dpu_power_data_bus_unregister(

• struct dpu_power_data_bus_handle *pdbus)
  

+{ +}

+int dpu_power_data_bus_set_quota(struct dpu_power_handle *phandle,

• struct dpu_power_client *pclient,
  

• int bus_client, u32 bus_id,
  

• u64 ab_quota, u64 ib_quota)
  

+{

• return 0;

+}

+static int dpu_power_reg_bus_parse(struct platform_device *pdev,

• struct dpu_power_handle *phandle)

+{

• return 0;

+}

+static void dpu_power_reg_bus_unregister(u32 reg_bus_hdl) +{ +}

+static int dpu_power_reg_bus_update(u32 reg_bus_hdl, u32 usecase_ndx) +{

• return 0;

+}

+static int dpu_power_data_bus_update(struct dpu_power_data_bus_handle *pdbus,

• 					bool enable)
  

+{

• return 0;

+}

+int dpu_power_data_bus_state_update(struct dpu_power_handle *phandle,

• 					bool enable)
  

+{

• return 0;

+} +#endif

+int dpu_power_resource_init(struct platform_device *pdev,

• struct dpu_power_handle *phandle)

+{

• int rc = 0, i;
• if (!phandle || !pdev) {

• pr_err("invalid input param\n");
  

• return -EINVAL;
  

• }
• phandle->dev = &pdev->dev;
• rc = dpu_power_reg_bus_parse(pdev, phandle);
• if (rc) {

• pr_err("register bus parse failed rc=%d\n", rc);
  

• return rc;
  

• }
• for (i = DPU_POWER_HANDLE_DBUS_ID_MNOC;

• 	i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
  

• rc = dpu_power_data_bus_parse(pdev,
  

• 		&phandle->data_bus_handle[i],
  

• 		data_bus_name[i]);
  

• if (rc) {
  

• 	pr_err("register data bus parse failed id=%d rc=%d\n",
  

• 			i, rc);
  

• 	goto data_bus_err;
  

• }
  

• }
• INIT_LIST_HEAD(&phandle->power_client_clist);
• INIT_LIST_HEAD(&phandle->event_list);
• mutex_init(&phandle->phandle_lock);
• return rc;

+data_bus_err:

• for (i--; i >= 0; i--)

• dpu_power_data_bus_unregister(&phandle->data_bus_handle[i]);
  

• dpu_power_reg_bus_unregister(phandle->reg_bus_hdl);
• return rc;

+}

+void dpu_power_resource_deinit(struct platform_device *pdev,

• struct dpu_power_handle *phandle)

+{

• struct dpu_power_client *curr_client, *next_client;
• struct dpu_power_event *curr_event, *next_event;
• int i;
• if (!phandle || !pdev) {

• pr_err("invalid input param\n");
  

• return;
  

• }
• mutex_lock(&phandle->phandle_lock);
• list_for_each_entry_safe(curr_client, next_client,

• 	&phandle->power_client_clist, list) {
  

• pr_err("cliend:%s-%d still registered with refcount:%d\n",
  

• 		curr_client->name, curr_client->id,
  

• 		curr_client->refcount);
  

• curr_client->active = false;
  

• list_del(&curr_client->list);
  

• }
• list_for_each_entry_safe(curr_event, next_event,

• 	&phandle->event_list, list) {
  

• pr_err("event:%d, client:%s still registered\n",
  

• 		curr_event->event_type,
  

• 		curr_event->client_name);
  

• curr_event->active = false;
  

• list_del(&curr_event->list);
  

• }
• mutex_unlock(&phandle->phandle_lock);
• for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++)

• dpu_power_data_bus_unregister(&phandle->data_bus_handle[i]);
  

• dpu_power_reg_bus_unregister(phandle->reg_bus_hdl);

+}

+int dpu_power_resource_enable(struct dpu_power_handle *phandle,

• struct dpu_power_client *pclient, bool enable)

+{

• int rc = 0, i;
• bool changed = false;
• u32 max_usecase_ndx = VOTE_INDEX_DISABLE, prev_usecase_ndx;
• struct dpu_power_client *client;
• if (!phandle || !pclient) {

• pr_err("invalid input argument\n");
  

• return -EINVAL;
  

• }
• mutex_lock(&phandle->phandle_lock);
• if (enable)

• pclient->refcount++;
  

• else if (pclient->refcount)

• pclient->refcount--;
  

• if (pclient->refcount)

• pclient->usecase_ndx = VOTE_INDEX_LOW;
  

• else

• pclient->usecase_ndx = VOTE_INDEX_DISABLE;
  

• list_for_each_entry(client, &phandle->power_client_clist, list) {

• if (client->usecase_ndx < VOTE_INDEX_MAX &&
  

•     client->usecase_ndx > max_usecase_ndx)
  

• 	max_usecase_ndx = client->usecase_ndx;
  

• }
• if (phandle->current_usecase_ndx != max_usecase_ndx) {

• changed = true;
  

• prev_usecase_ndx = phandle->current_usecase_ndx;
  

• phandle->current_usecase_ndx = max_usecase_ndx;
  

• }
• pr_debug("%pS: changed=%d current idx=%d request client %s id:%u enable:%d refcount:%d\n",

• __builtin_return_address(0), changed, max_usecase_ndx,
  

• pclient->name, pclient->id, enable, pclient->refcount);
  

• if (!changed)

• goto end;
  

• if (enable) {

• dpu_power_event_trigger_locked(phandle,
  

• 		DPU_POWER_EVENT_PRE_ENABLE);
  

• for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
  

• 	rc = dpu_power_data_bus_update(
  

• 			&phandle->data_bus_handle[i], enable);
  

• 	if (rc) {
  

• 		pr_err("failed to set data bus vote id=%d rc=%d\n",
  

• 				i, rc);
  

• 		goto data_bus_hdl_err;
  

• 	}
  

• }
  

• rc = dpu_power_reg_bus_update(phandle->reg_bus_hdl,
  

• 					max_usecase_ndx);
  

• if (rc) {
  

• 	pr_err("failed to set reg bus vote rc=%d\n", rc);
  

• 	goto reg_bus_hdl_err;
  

• }
  

• dpu_power_event_trigger_locked(phandle,
  

• 		DPU_POWER_EVENT_POST_ENABLE);
  

• } else {

• dpu_power_event_trigger_locked(phandle,
  

• 		DPU_POWER_EVENT_PRE_DISABLE);
  

• dpu_power_reg_bus_update(phandle->reg_bus_hdl,
  

• 					max_usecase_ndx);
  

• for (i = 0 ; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++)
  

• 	dpu_power_data_bus_update(&phandle->data_bus_handle[i],
  

• 			enable);
  

• dpu_power_event_trigger_locked(phandle,
  

• 		DPU_POWER_EVENT_POST_DISABLE);
  

• }

+end:

• mutex_unlock(&phandle->phandle_lock);
• return rc;

+reg_bus_hdl_err:

• for (i = 0 ; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++)

• dpu_power_data_bus_update(&phandle->data_bus_handle[i], 0);
  

+data_bus_hdl_err:

• phandle->current_usecase_ndx = prev_usecase_ndx;
• mutex_unlock(&phandle->phandle_lock);
• return rc;

+}

+struct dpu_power_event *dpu_power_handle_register_event(

• struct dpu_power_handle *phandle,
  

• u32 event_type, void (*cb_fnc)(u32 event_type, void *usr),
  

• void *usr, char *client_name)
  

+{

• struct dpu_power_event *event;
• if (!phandle) {

• pr_err("invalid power handle\n");
  

• return ERR_PTR(-EINVAL);
  

• } else if (!cb_fnc || !event_type) {

• pr_err("no callback fnc or event type\n");
  

• return ERR_PTR(-EINVAL);
  

• }
• event = kzalloc(sizeof(struct dpu_power_event), GFP_KERNEL);
• if (!event)

• return ERR_PTR(-ENOMEM);
  

• event->event_type = event_type;
• event->cb_fnc = cb_fnc;
• event->usr = usr;
• strlcpy(event->client_name, client_name, MAX_CLIENT_NAME_LEN);
• event->active = true;
• mutex_lock(&phandle->phandle_lock);
• list_add(&event->list, &phandle->event_list);
• mutex_unlock(&phandle->phandle_lock);
• return event;

+}

+void dpu_power_handle_unregister_event(

• struct dpu_power_handle *phandle,
  

• struct dpu_power_event *event)
  

+{

• if (!phandle || !event) {

• pr_err("invalid phandle or event\n");
  

• } else if (!event->active) {

• pr_err("power handle deinit already done\n");
  

• kfree(event);
  

• } else {

• mutex_lock(&phandle->phandle_lock);
  

• list_del_init(&event->list);
  

• mutex_unlock(&phandle->phandle_lock);
  

• kfree(event);
  

• }

+} diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h new file mode 100644 index 0000000..9a6d4b9 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h @@ -0,0 +1,288 @@ +/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.

• • This program is free software; you can redistribute it and/or modify
• • it under the terms of the GNU General Public License version 2 and
• • only version 2 as published by the Free Software Foundation.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• */

+#ifndef _DPU_POWER_HANDLE_H_ +#define _DPU_POWER_HANDLE_H_

+#define MAX_CLIENT_NAME_LEN 128

+#define DPU_POWER_HANDLE_ENABLE_BUS_AB_QUOTA 0 +#define DPU_POWER_HANDLE_DISABLE_BUS_AB_QUOTA 0 +#define DPU_POWER_HANDLE_ENABLE_BUS_IB_QUOTA 1600000000 +#define DPU_POWER_HANDLE_DISABLE_BUS_IB_QUOTA 0

+#include <linux/dpu_io_util.h>

+/* event will be triggered before power handler disable */ +#define DPU_POWER_EVENT_PRE_DISABLE 0x1

+/* event will be triggered after power handler disable */ +#define DPU_POWER_EVENT_POST_DISABLE 0x2

+/* event will be triggered before power handler enable */ +#define DPU_POWER_EVENT_PRE_ENABLE 0x4

+/* event will be triggered after power handler enable */ +#define DPU_POWER_EVENT_POST_ENABLE 0x8

+/**

• • mdss_bus_vote_type: register bus vote type
• • VOTE_INDEX_DISABLE: removes the client vote
• • VOTE_INDEX_LOW: keeps the lowest vote for register bus
• • VOTE_INDEX_MAX: invalid
• */

+enum mdss_bus_vote_type {

• VOTE_INDEX_DISABLE,
• VOTE_INDEX_LOW,
• VOTE_INDEX_MAX,

+};

+/**

• • enum dpu_power_handle_data_bus_client - type of axi bus clients
• • @DPU_POWER_HANDLE_DATA_BUS_CLIENT_RT: core real-time bus client
• • @DPU_POWER_HANDLE_DATA_BUS_CLIENT_NRT: core non-real-time bus client
• • @DPU_POWER_HANDLE_DATA_BUS_CLIENT_MAX: maximum number of bus client type
• */

+enum dpu_power_handle_data_bus_client {

• DPU_POWER_HANDLE_DATA_BUS_CLIENT_RT,
• DPU_POWER_HANDLE_DATA_BUS_CLIENT_NRT,
• DPU_POWER_HANDLE_DATA_BUS_CLIENT_MAX

+};

+/**

• • enum DPU_POWER_HANDLE_DBUS_ID - data bus identifier
• • @DPU_POWER_HANDLE_DBUS_ID_MNOC: DPU/MNOC data bus
• • @DPU_POWER_HANDLE_DBUS_ID_LLCC: MNOC/LLCC data bus
• • @DPU_POWER_HANDLE_DBUS_ID_EBI: LLCC/EBI data bus
• */

+enum DPU_POWER_HANDLE_DBUS_ID {

• DPU_POWER_HANDLE_DBUS_ID_MNOC,
• DPU_POWER_HANDLE_DBUS_ID_LLCC,
• DPU_POWER_HANDLE_DBUS_ID_EBI,
• DPU_POWER_HANDLE_DBUS_ID_MAX,

+};

+/**

• • struct dpu_power_client: stores the power client for dpu driver
• • @name: name of the client
• • @usecase_ndx: current regs bus vote type
• • @refcount: current refcount if multiple modules are using same

• •          same client for enable/disable. Power module will
    

• •          aggregate the refcount and vote accordingly for this
    

• •          client.
    

• • @id: assigned during create. helps for debugging.
• • @list: list to attach power handle master list
• • @ab: arbitrated bandwidth for each bus client
• • @ib: instantaneous bandwidth for each bus client
• • @active: inidcates the state of dpu power handle
• */

+struct dpu_power_client {

• char name[MAX_CLIENT_NAME_LEN];
• short usecase_ndx;
• short refcount;
• u32 id;
• struct list_head list;
• u64 ab[DPU_POWER_HANDLE_DATA_BUS_CLIENT_MAX];
• u64 ib[DPU_POWER_HANDLE_DATA_BUS_CLIENT_MAX];
• bool active;

+};

+/**

• • struct dpu_power_data_handle: power handle struct for data bus
• • @data_bus_scale_table: pointer to bus scaling table
• • @data_bus_hdl: current data bus handle
• • @axi_port_cnt: number of rt axi ports
• • @nrt_axi_port_cnt: number of nrt axi ports
• • @bus_channels: number of memory bus channels
• • @curr_bw_uc_idx: current use case index of data bus
• • @ao_bw_uc_idx: active only use case index of data bus
• • @ab_rt: realtime ab quota
• • @ib_rt: realtime ib quota
• • @ab_nrt: non-realtime ab quota
• • @ib_nrt: non-realtime ib quota
• • @enable: true if bus is enabled
• */

+struct dpu_power_data_bus_handle {

• struct msm_bus_scale_pdata *data_bus_scale_table;
• u32 data_bus_hdl;
• u32 axi_port_cnt;
• u32 nrt_axi_port_cnt;
• u32 bus_channels;
• u32 curr_bw_uc_idx;
• u32 ao_bw_uc_idx;
• u64 ab_rt;
• u64 ib_rt;
• u64 ab_nrt;
• u64 ib_nrt;
• bool enable;

+};

+/*

• • struct dpu_power_event - local event registration structure
• • @client_name: name of the client registering
• • @cb_fnc: pointer to desired callback function
• • @usr: user pointer to pass to callback event trigger
• • @event: refer to DPU_POWER_HANDLE_EVENT_*
• • @list: list to attach event master list
• • @active: indicates the state of dpu power handle
• */

+struct dpu_power_event {

• char client_name[MAX_CLIENT_NAME_LEN];
• void (*cb_fnc)(u32 event_type, void *usr);
• void *usr;
• u32 event_type;
• struct list_head list;
• bool active;

+};

+/**

• • struct dpu_power_handle: power handle main struct
• • @client_clist: master list to store all clients
• • @phandle_lock: lock to synchronize the enable/disable
• • @dev: pointer to device structure
• • @usecase_ndx: current usecase index
• • @reg_bus_hdl: current register bus handle
• • @data_bus_handle: context structure for data bus control
• • @event_list: current power handle event list
• */

+struct dpu_power_handle {

• struct list_head power_client_clist;
• struct mutex phandle_lock;
• struct device *dev;
• u32 current_usecase_ndx;
• u32 reg_bus_hdl;
• struct dpu_power_data_bus_handle data_bus_handle

• [DPU_POWER_HANDLE_DBUS_ID_MAX];
  

• struct list_head event_list;

+};

+/**

• • dpu_power_resource_init() - initializes the dpu power handle
• • @pdev: platform device to search the power resources
• • @pdata: power handle to store the power resources
• • Return: error code.
• */

+int dpu_power_resource_init(struct platform_device *pdev,

• struct dpu_power_handle *pdata);

+/**

• • dpu_power_resource_deinit() - release the dpu power handle
• • @pdev: platform device for power resources
• • @pdata: power handle containing the resources
• • Return: error code.
• */

+void dpu_power_resource_deinit(struct platform_device *pdev,

• struct dpu_power_handle *pdata);

+/**

• • dpu_power_client_create() - create the client on power handle
• • @pdata: power handle containing the resources
• • @client_name: new client name for registration
• • Return: error code.
• */

+struct dpu_power_client *dpu_power_client_create(struct dpu_power_handle *pdata,

• char *client_name);

+/**

• • dpu_power_client_destroy() - destroy the client on power handle
• • @pdata: power handle containing the resources
• • @client_name: new client name for registration
• • Return: none
• */

+void dpu_power_client_destroy(struct dpu_power_handle *phandle,

• struct dpu_power_client *client);

+/**

• • dpu_power_resource_enable() - enable/disable the power resources
• • @pdata: power handle containing the resources
• • @client: client information to enable/disable its vote
• • @enable: boolean request for enable/disable
• • Return: error code.
• */

+int dpu_power_resource_enable(struct dpu_power_handle *pdata,

• struct dpu_power_client *pclient, bool enable);

+/**

• • dpu_power_data_bus_state_update() - update data bus state
• • @pdata: power handle containing the resources
• • @enable: take enable vs disable path
• • Return: error code.
• */

+int dpu_power_data_bus_state_update(struct dpu_power_handle *phandle,

• 					bool enable);
  

+/**

• • dpu_power_data_bus_set_quota() - set data bus quota for power client
• • @phandle: power handle containing the resources
• • @client: client information to set quota
• • @bus_client: real-time or non-real-time bus client
• • @bus_id: identifier of data bus, see DPU_POWER_HANDLE_DBUS_ID
• • @ab_quota: arbitrated bus bandwidth
• • @ib_quota: instantaneous bus bandwidth
• • Return: zero if success, or error code otherwise
• */

+int dpu_power_data_bus_set_quota(struct dpu_power_handle *phandle,

• struct dpu_power_client *pclient,
  

• int bus_client, u32 bus_id,
  

• u64 ab_quota, u64 ib_quota);
  

+/**

• • dpu_power_data_bus_bandwidth_ctrl() - control data bus bandwidth enable
• • @phandle: power handle containing the resources
• • @client: client information to bandwidth control
• • @enable: true to enable bandwidth for data base
• • Return: none
• */

+void dpu_power_data_bus_bandwidth_ctrl(struct dpu_power_handle *phandle,

• struct dpu_power_client *pclient, int enable);
  

+/**

• • dpu_power_handle_register_event - register a callback function for an event.
• • Clients can register for multiple events with a single register.
• • Any block with access to phandle can register for the event
• • notification.
• • @phandle: power handle containing the resources
• • @event_type: event type to register; refer DPU_POWER_HANDLE_EVENT_*
• • @cb_fnc: pointer to desired callback function
• • @usr: user pointer to pass to callback on event trigger
• • Return: event pointer if success, or error code otherwise
• */

+struct dpu_power_event *dpu_power_handle_register_event(

• struct dpu_power_handle *phandle,
  

• u32 event_type, void (*cb_fnc)(u32 event_type, void *usr),
  

• void *usr, char *client_name);
  

+/**

• • dpu_power_handle_unregister_event - unregister callback for event(s)
• • @phandle: power handle containing the resources
• • @event: event pointer returned after power handle register
• */

+void dpu_power_handle_unregister_event(struct dpu_power_handle *phandle,

• struct dpu_power_event *event);
  

+/**

• • dpu_power_handle_get_dbus_name - get name of given data bus identifier
• • @bus_id: data bus identifier
• • Return: Pointer to name string if success; NULL otherwise
• */

+const char *dpu_power_handle_get_dbus_name(u32 bus_id);

+#endif /* _DPU_POWER_HANDLE_H_ */ diff --git a/drivers/gpu/drm/msm/dpu_power_handle.c b/drivers/gpu/drm/msm/dpu_power_handle.c deleted file mode 100644 index 77be106..0000000 --- a/drivers/gpu/drm/msm/dpu_power_handle.c +++ /dev/null @@ -1,693 +0,0 @@ -/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.

• • This program is free software; you can redistribute it and/or modify
• • it under the terms of the GNU General Public License version 2 and
• • only version 2 as published by the Free Software Foundation.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• */

-#define pr_fmt(fmt) "[drm:%s:%d]: " fmt, __func__, __LINE__

-#include <linux/kernel.h> -#include <linux/of.h> -#include <linux/string.h> -#include <linux/of_address.h> -#include <linux/slab.h> -#include <linux/mutex.h> -#include <linux/of_platform.h> -#ifdef CONFIG_QCOM_BUS_SCALING -#include <linux/msm-bus.h> -#include <linux/msm-bus-board.h> -#endif -#include <linux/dpu_io_util.h>

-#include "dpu_power_handle.h" -#include "dpu_trace.h"

-static const char *data_bus_name[DPU_POWER_HANDLE_DBUS_ID_MAX] = {

• [DPU_POWER_HANDLE_DBUS_ID_MNOC] = "qcom,dpu-data-bus",
• [DPU_POWER_HANDLE_DBUS_ID_LLCC] = "qcom,dpu-llcc-bus",
• [DPU_POWER_HANDLE_DBUS_ID_EBI] = "qcom,dpu-ebi-bus",

-};

-const char *dpu_power_handle_get_dbus_name(u32 bus_id) -{

• if (bus_id < DPU_POWER_HANDLE_DBUS_ID_MAX)

• return data_bus_name[bus_id];
  

• return NULL;

-}

-static void dpu_power_event_trigger_locked(struct dpu_power_handle *phandle,

• u32 event_type)
  

-{

• struct dpu_power_event *event;
• list_for_each_entry(event, &phandle->event_list, list) {

• if (event->event_type & event_type)
  

• 	event->cb_fnc(event_type, event->usr);
  

• }

-}

-struct dpu_power_client *dpu_power_client_create(

• struct dpu_power_handle *phandle, char *client_name)

-{

• struct dpu_power_client *client;
• static u32 id;
• if (!client_name || !phandle) {

• pr_err("client name is null or invalid power data\n");
  

• return ERR_PTR(-EINVAL);
  

• }
• client = kzalloc(sizeof(struct dpu_power_client), GFP_KERNEL);
• if (!client)

• return ERR_PTR(-ENOMEM);
  

• mutex_lock(&phandle->phandle_lock);
• strlcpy(client->name, client_name, MAX_CLIENT_NAME_LEN);
• client->usecase_ndx = VOTE_INDEX_DISABLE;
• client->id = id;
• client->active = true;
• pr_debug("client %s created:%pK id :%d\n", client_name,

• client, id);
  

• id++;
• list_add(&client->list, &phandle->power_client_clist);
• mutex_unlock(&phandle->phandle_lock);
• return client;

-}

-void dpu_power_client_destroy(struct dpu_power_handle *phandle,

• struct dpu_power_client *client)

-{

• if (!client || !phandle) {

• pr_err("reg bus vote: invalid client handle\n");
  

• } else if (!client->active) {

• pr_err("dpu power deinit already done\n");
  

• kfree(client);
  

• } else {

• pr_debug("bus vote client %s destroyed:%pK id:%u\n",
  

• 	client->name, client, client->id);
  

• mutex_lock(&phandle->phandle_lock);
  

• list_del_init(&client->list);
  

• mutex_unlock(&phandle->phandle_lock);
  

• kfree(client);
  

• }

-}

-#ifdef CONFIG_QCOM_BUS_SCALING

-#define MAX_AXI_PORT_COUNT 3

-static int _dpu_power_data_bus_set_quota(

• struct dpu_power_data_bus_handle *pdbus,
  

• u64 ab_quota_rt, u64 ab_quota_nrt,
  

• u64 ib_quota_rt, u64 ib_quota_nrt)
  

-{

• int new_uc_idx;
• u64 ab_quota[MAX_AXI_PORT_COUNT] = {0, 0};
• u64 ib_quota[MAX_AXI_PORT_COUNT] = {0, 0};
• int rc;
• if (pdbus->data_bus_hdl < 1) {

• pr_err("invalid bus handle %d\n", pdbus->data_bus_hdl);
  

• return -EINVAL;
  

• }
• pdbus->ab_rt = ab_quota_rt;
• pdbus->ib_rt = ib_quota_rt;
• pdbus->ab_nrt = ab_quota_nrt;
• pdbus->ib_nrt = ib_quota_nrt;
• if (pdbus->enable) {

• ab_quota_rt = max_t(u64, ab_quota_rt,
  

• 		DPU_POWER_HANDLE_ENABLE_BUS_AB_QUOTA);
  

• ib_quota_rt = max_t(u64, ib_quota_rt,
  

• 		DPU_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  

• ab_quota_nrt = max_t(u64, ab_quota_nrt,
  

• 		DPU_POWER_HANDLE_ENABLE_BUS_AB_QUOTA);
  

• ib_quota_nrt = max_t(u64, ib_quota_nrt,
  

• 		DPU_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  

• } else {

• ab_quota_rt = min_t(u64, ab_quota_rt,
  

• 		DPU_POWER_HANDLE_DISABLE_BUS_AB_QUOTA);
  

• ib_quota_rt = min_t(u64, ib_quota_rt,
  

• 		DPU_POWER_HANDLE_DISABLE_BUS_IB_QUOTA);
  

• ab_quota_nrt = min_t(u64, ab_quota_nrt,
  

• 		DPU_POWER_HANDLE_DISABLE_BUS_AB_QUOTA);
  

• ib_quota_nrt = min_t(u64, ib_quota_nrt,
  

• 		DPU_POWER_HANDLE_DISABLE_BUS_IB_QUOTA);
  

• }
• if (!ab_quota_rt && !ab_quota_nrt && !ib_quota_rt && !ib_quota_nrt) {

• new_uc_idx = 0;
  

• } else {

• int i;
  

• struct msm_bus_vectors *vect = NULL;
  

• struct msm_bus_scale_pdata *bw_table =
  

• 	pdbus->data_bus_scale_table;
  

• u32 nrt_axi_port_cnt = pdbus->nrt_axi_port_cnt;
  

• u32 total_axi_port_cnt = pdbus->axi_port_cnt;
  

• u32 rt_axi_port_cnt = total_axi_port_cnt - nrt_axi_port_cnt;
  

• if (!bw_table || !total_axi_port_cnt ||
  

•     total_axi_port_cnt > MAX_AXI_PORT_COUNT) {
  

• 	pr_err("invalid input\n");
  

• 	return -EINVAL;
  

• }
  

• if (pdbus->bus_channels) {
  

• 	ib_quota_rt = div_u64(ib_quota_rt,
  

• 				pdbus->bus_channels);
  

• 	ib_quota_nrt = div_u64(ib_quota_nrt,
  

• 				pdbus->bus_channels);
  

• }
  

• if (nrt_axi_port_cnt) {
  

• 	ab_quota_rt = div_u64(ab_quota_rt, rt_axi_port_cnt);
  

• 	ab_quota_nrt = div_u64(ab_quota_nrt, nrt_axi_port_cnt);
  

• 	for (i = 0; i < total_axi_port_cnt; i++) {
  

• 		if (i < rt_axi_port_cnt) {
  

• 			ab_quota[i] = ab_quota_rt;
  

• 			ib_quota[i] = ib_quota_rt;
  

• 		} else {
  

• 			ab_quota[i] = ab_quota_nrt;
  

• 			ib_quota[i] = ib_quota_nrt;
  

• 		}
  

• 	}
  

• } else {
  

• 	ab_quota[0] = div_u64(ab_quota_rt + ab_quota_nrt,
  

• 			total_axi_port_cnt);
  

• 	ib_quota[0] = ib_quota_rt + ib_quota_nrt;
  

• 	for (i = 1; i < total_axi_port_cnt; i++) {
  

• 		ab_quota[i] = ab_quota[0];
  

• 		ib_quota[i] = ib_quota[0];
  

• 	}
  

• }
  

• new_uc_idx = (pdbus->curr_bw_uc_idx %
  

• 	(bw_table->num_usecases - 1)) + 1;
  

• for (i = 0; i < total_axi_port_cnt; i++) {
  

• 	vect = &bw_table->usecase[new_uc_idx].vectors[i];
  

• 	vect->ab = ab_quota[i];
  

• 	vect->ib = ib_quota[i];
  

• 	pr_debug(
  

• 		"%s uc_idx=%d %s path idx=%d ab=%llu ib=%llu\n",
  

• 		bw_table->name,
  

• 		new_uc_idx, (i < rt_axi_port_cnt) ? "rt" : "nrt"
  

• 		, i, vect->ab, vect->ib);
  

• }
  

• }
• pdbus->curr_bw_uc_idx = new_uc_idx;
• pdbus->ao_bw_uc_idx = new_uc_idx;
• DPU_ATRACE_BEGIN("msm_bus_scale_req");
• rc = msm_bus_scale_client_update_request(pdbus->data_bus_hdl,

• 	new_uc_idx);
  

• DPU_ATRACE_END("msm_bus_scale_req");
• return rc;

-}

-int dpu_power_data_bus_set_quota(struct dpu_power_handle *phandle,

• struct dpu_power_client *pclient,
  

• int bus_client, u32 bus_id,
  

• u64 ab_quota, u64 ib_quota)
  

-{

• int rc = 0;
• int i;
• u64 total_ab_rt = 0, total_ib_rt = 0;
• u64 total_ab_nrt = 0, total_ib_nrt = 0;
• struct dpu_power_client *client;
• if (!phandle || !pclient ||

• 	bus_client >= DPU_POWER_HANDLE_DATA_BUS_CLIENT_MAX ||
  

• 	bus_id >= DPU_POWER_HANDLE_DBUS_ID_MAX) {
  

• pr_err("invalid parameters\n");
  

• return -EINVAL;
  

• }
• mutex_lock(&phandle->phandle_lock);
• pclient->ab[bus_client] = ab_quota;
• pclient->ib[bus_client] = ib_quota;
• trace_dpu_perf_update_bus(bus_client, ab_quota, ib_quota);
• list_for_each_entry(client, &phandle->power_client_clist, list) {

• for (i = 0; i < DPU_POWER_HANDLE_DATA_BUS_CLIENT_MAX; i++) {
  

• 	if (i == DPU_POWER_HANDLE_DATA_BUS_CLIENT_NRT) {
  

• 		total_ab_nrt += client->ab[i];
  

• 		total_ib_nrt += client->ib[i];
  

• 	} else {
  

• 		total_ab_rt += client->ab[i];
  

• 		total_ib_rt = max(total_ib_rt, client->ib[i]);
  

• 	}
  

• }
  

• }
• if (phandle->data_bus_handle[bus_id].data_bus_hdl)

• rc = _dpu_power_data_bus_set_quota(
  

• 	&phandle->data_bus_handle[bus_id],
  

• 	total_ab_rt, total_ab_nrt,
  

• 	total_ib_rt, total_ib_nrt);
  

• mutex_unlock(&phandle->phandle_lock);
• return rc;

-}

-static void dpu_power_data_bus_unregister(

• struct dpu_power_data_bus_handle *pdbus)
  

-{

• if (pdbus->data_bus_hdl) {

• msm_bus_scale_unregister_client(pdbus->data_bus_hdl);
  

• pdbus->data_bus_hdl = 0;
  

• }

-}

-static int dpu_power_data_bus_parse(struct platform_device *pdev,

• struct dpu_power_data_bus_handle *pdbus, const char *name)

-{

• struct device_node *node;
• int rc = 0;
• int paths;
• pdbus->bus_channels = 1;
• rc = of_property_read_u32(pdev->dev.of_node,

• "qcom,dpu-dram-channels", &pdbus->bus_channels);
  

• if (rc) {

• pr_debug("number of channels property not specified\n");
  

• rc = 0;
  

• }
• pdbus->nrt_axi_port_cnt = 0;
• rc = of_property_read_u32(pdev->dev.of_node,

• 	"qcom,dpu-num-nrt-paths",
  

• 	&pdbus->nrt_axi_port_cnt);
  

• if (rc) {

• pr_debug("number of axi port property not specified\n");
  

• rc = 0;
  

• }
• node = of_get_child_by_name(pdev->dev.of_node, name);
• if (node) {

• rc = of_property_read_u32(node,
  

• 		"qcom,msm-bus,num-paths", &paths);
  

• if (rc) {
  

• 	pr_err("Error. qcom,msm-bus,num-paths not found\n");
  

• 	return rc;
  

• }
  

• pdbus->axi_port_cnt = paths;
  

• pdbus->data_bus_scale_table =
  

• 		msm_bus_pdata_from_node(pdev, node);
  

• if (IS_ERR_OR_NULL(pdbus->data_bus_scale_table)) {
  

• 	pr_err("reg bus handle parsing failed\n");
  

• 	rc = PTR_ERR(pdbus->data_bus_scale_table);
  

• 	if (!pdbus->data_bus_scale_table)
  

• 		rc = -EINVAL;
  

• 	goto end;
  

• }
  

• pdbus->data_bus_hdl = msm_bus_scale_register_client(
  

• 		pdbus->data_bus_scale_table);
  

• if (!pdbus->data_bus_hdl) {
  

• 	pr_err("data_bus_client register failed\n");
  

• 	rc = -EINVAL;
  

• 	goto end;
  

• }
  

• pr_debug("register %s data_bus_hdl=%x\n", name,
  

• 		pdbus->data_bus_hdl);
  

• }

-end:

• return rc;

-}

-static int dpu_power_reg_bus_parse(struct platform_device *pdev,

• struct dpu_power_handle *phandle)

-{

• struct device_node *node;
• struct msm_bus_scale_pdata *bus_scale_table;
• int rc = 0;
• node = of_get_child_by_name(pdev->dev.of_node, "qcom,dpu-reg-bus");
• if (node) {

• bus_scale_table = msm_bus_pdata_from_node(pdev, node);
  

• if (IS_ERR_OR_NULL(bus_scale_table)) {
  

• 	pr_err("reg bus handle parsing failed\n");
  

• 	rc = PTR_ERR(bus_scale_table);
  

• 	if (!bus_scale_table)
  

• 		rc = -EINVAL;
  

• 	goto end;
  

• }
  

• phandle->reg_bus_hdl = msm_bus_scale_register_client(
  

• 	      bus_scale_table);
  

• if (!phandle->reg_bus_hdl) {
  

• 	pr_err("reg_bus_client register failed\n");
  

• 	rc = -EINVAL;
  

• 	goto end;
  

• }
  

• pr_debug("register reg_bus_hdl=%x\n", phandle->reg_bus_hdl);
  

• }

-end:

• return rc;

-}

-static void dpu_power_reg_bus_unregister(u32 reg_bus_hdl) -{

• if (reg_bus_hdl)

• msm_bus_scale_unregister_client(reg_bus_hdl);
  

-}

-int dpu_power_data_bus_state_update(struct dpu_power_handle *phandle,

• 					bool enable)
  

-{

• int i;
• if (!phandle) {

• pr_err("invalid param\n");
  

• return -EINVAL;
  

• }
• for (i = DPU_POWER_HANDLE_DBUS_ID_MNOC;

• 	i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++)
  

• phandle->data_bus_handle[i].enable = enable;
  

• return 0;

-}

-static int dpu_power_data_bus_update(struct dpu_power_data_bus_handle *pdbus,

• 					bool enable)
  

-{

• int rc = 0;
• pdbus->enable = enable;
• if (pdbus->data_bus_hdl)

• rc = _dpu_power_data_bus_set_quota(pdbus, pdbus->ab_rt,
  

• 		pdbus->ab_nrt, pdbus->ib_rt, pdbus->ib_nrt);
  

• if (rc)

• pr_err("failed to set data bus vote rc=%d enable:%d\n",
  

• 					rc, enable);
  

• return rc;

-}

-static int dpu_power_reg_bus_update(u32 reg_bus_hdl, u32 usecase_ndx) -{

• int rc = 0;
• if (reg_bus_hdl)

• rc = msm_bus_scale_client_update_request(reg_bus_hdl,
  

• 						usecase_ndx);
  

• if (rc)

• pr_err("failed to set reg bus vote rc=%d\n", rc);
  

• return rc;

-} -#else -static int dpu_power_data_bus_parse(struct platform_device *pdev,

• struct dpu_power_data_bus_handle *pdbus, const char *name)
  

-{

• return 0;

-}

-static void dpu_power_data_bus_unregister(

• struct dpu_power_data_bus_handle *pdbus)
  

-{ -}

-int dpu_power_data_bus_set_quota(struct dpu_power_handle *phandle,

• struct dpu_power_client *pclient,
  

• int bus_client, u32 bus_id,
  

• u64 ab_quota, u64 ib_quota)
  

-{

• return 0;

-}

-static int dpu_power_reg_bus_parse(struct platform_device *pdev,

• struct dpu_power_handle *phandle)

-{

• return 0;

-}

-static void dpu_power_reg_bus_unregister(u32 reg_bus_hdl) -{ -}

-static int dpu_power_reg_bus_update(u32 reg_bus_hdl, u32 usecase_ndx) -{

• return 0;

-}

-static int dpu_power_data_bus_update(struct dpu_power_data_bus_handle *pdbus,

• 					bool enable)
  

-{

• return 0;

-}

-int dpu_power_data_bus_state_update(struct dpu_power_handle *phandle,

• 					bool enable)
  

-{

• return 0;

-} -#endif

-int dpu_power_resource_init(struct platform_device *pdev,

• struct dpu_power_handle *phandle)

-{

• int rc = 0, i;
• if (!phandle || !pdev) {

• pr_err("invalid input param\n");
  

• return -EINVAL;
  

• }
• phandle->dev = &pdev->dev;
• rc = dpu_power_reg_bus_parse(pdev, phandle);
• if (rc) {

• pr_err("register bus parse failed rc=%d\n", rc);
  

• return rc;
  

• }
• for (i = DPU_POWER_HANDLE_DBUS_ID_MNOC;

• 	i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
  

• rc = dpu_power_data_bus_parse(pdev,
  

• 		&phandle->data_bus_handle[i],
  

• 		data_bus_name[i]);
  

• if (rc) {
  

• 	pr_err("register data bus parse failed id=%d rc=%d\n",
  

• 			i, rc);
  

• 	goto data_bus_err;
  

• }
  

• }
• INIT_LIST_HEAD(&phandle->power_client_clist);
• INIT_LIST_HEAD(&phandle->event_list);
• mutex_init(&phandle->phandle_lock);
• return rc;

-data_bus_err:

• for (i--; i >= 0; i--)

• dpu_power_data_bus_unregister(&phandle->data_bus_handle[i]);
  

• dpu_power_reg_bus_unregister(phandle->reg_bus_hdl);
• return rc;

-}

-void dpu_power_resource_deinit(struct platform_device *pdev,

• struct dpu_power_handle *phandle)

-{

• struct dpu_power_client *curr_client, *next_client;
• struct dpu_power_event *curr_event, *next_event;
• int i;
• if (!phandle || !pdev) {

• pr_err("invalid input param\n");
  

• return;
  

• }
• mutex_lock(&phandle->phandle_lock);
• list_for_each_entry_safe(curr_client, next_client,

• 	&phandle->power_client_clist, list) {
  

• pr_err("cliend:%s-%d still registered with refcount:%d\n",
  

• 		curr_client->name, curr_client->id,
  

• 		curr_client->refcount);
  

• curr_client->active = false;
  

• list_del(&curr_client->list);
  

• }
• list_for_each_entry_safe(curr_event, next_event,

• 	&phandle->event_list, list) {
  

• pr_err("event:%d, client:%s still registered\n",
  

• 		curr_event->event_type,
  

• 		curr_event->client_name);
  

• curr_event->active = false;
  

• list_del(&curr_event->list);
  

• }
• mutex_unlock(&phandle->phandle_lock);
• for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++)

• dpu_power_data_bus_unregister(&phandle->data_bus_handle[i]);
  

• dpu_power_reg_bus_unregister(phandle->reg_bus_hdl);

-}

-int dpu_power_resource_enable(struct dpu_power_handle *phandle,

• struct dpu_power_client *pclient, bool enable)

-{

• int rc = 0, i;
• bool changed = false;
• u32 max_usecase_ndx = VOTE_INDEX_DISABLE, prev_usecase_ndx;
• struct dpu_power_client *client;
• if (!phandle || !pclient) {

• pr_err("invalid input argument\n");
  

• return -EINVAL;
  

• }
• mutex_lock(&phandle->phandle_lock);
• if (enable)

• pclient->refcount++;
  

• else if (pclient->refcount)

• pclient->refcount--;
  

• if (pclient->refcount)

• pclient->usecase_ndx = VOTE_INDEX_LOW;
  

• else

• pclient->usecase_ndx = VOTE_INDEX_DISABLE;
  

• list_for_each_entry(client, &phandle->power_client_clist, list) {

• if (client->usecase_ndx < VOTE_INDEX_MAX &&
  

•     client->usecase_ndx > max_usecase_ndx)
  

• 	max_usecase_ndx = client->usecase_ndx;
  

• }
• if (phandle->current_usecase_ndx != max_usecase_ndx) {

• changed = true;
  

• prev_usecase_ndx = phandle->current_usecase_ndx;
  

• phandle->current_usecase_ndx = max_usecase_ndx;
  

• }
• pr_debug("%pS: changed=%d current idx=%d request client %s id:%u enable:%d refcount:%d\n",

• __builtin_return_address(0), changed, max_usecase_ndx,
  

• pclient->name, pclient->id, enable, pclient->refcount);
  

• if (!changed)

• goto end;
  

• if (enable) {

• dpu_power_event_trigger_locked(phandle,
  

• 		DPU_POWER_EVENT_PRE_ENABLE);
  

• for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
  

• 	rc = dpu_power_data_bus_update(
  

• 			&phandle->data_bus_handle[i], enable);
  

• 	if (rc) {
  

• 		pr_err("failed to set data bus vote id=%d rc=%d\n",
  

• 				i, rc);
  

• 		goto data_bus_hdl_err;
  

• 	}
  

• }
  

• rc = dpu_power_reg_bus_update(phandle->reg_bus_hdl,
  

• 					max_usecase_ndx);
  

• if (rc) {
  

• 	pr_err("failed to set reg bus vote rc=%d\n", rc);
  

• 	goto reg_bus_hdl_err;
  

• }
  

• dpu_power_event_trigger_locked(phandle,
  

• 		DPU_POWER_EVENT_POST_ENABLE);
  

• } else {

• dpu_power_event_trigger_locked(phandle,
  

• 		DPU_POWER_EVENT_PRE_DISABLE);
  

• dpu_power_reg_bus_update(phandle->reg_bus_hdl,
  

• 					max_usecase_ndx);
  

• for (i = 0 ; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++)
  

• 	dpu_power_data_bus_update(&phandle->data_bus_handle[i],
  

• 			enable);
  

• dpu_power_event_trigger_locked(phandle,
  

• 		DPU_POWER_EVENT_POST_DISABLE);
  

• }

-end:

• mutex_unlock(&phandle->phandle_lock);
• return rc;

-reg_bus_hdl_err:

• for (i = 0 ; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++)

• dpu_power_data_bus_update(&phandle->data_bus_handle[i], 0);
  

-data_bus_hdl_err:

• phandle->current_usecase_ndx = prev_usecase_ndx;
• mutex_unlock(&phandle->phandle_lock);
• return rc;

-}

-struct dpu_power_event *dpu_power_handle_register_event(

• struct dpu_power_handle *phandle,
  

• u32 event_type, void (*cb_fnc)(u32 event_type, void *usr),
  

• void *usr, char *client_name)
  

-{

• struct dpu_power_event *event;
• if (!phandle) {

• pr_err("invalid power handle\n");
  

• return ERR_PTR(-EINVAL);
  

• } else if (!cb_fnc || !event_type) {

• pr_err("no callback fnc or event type\n");
  

• return ERR_PTR(-EINVAL);
  

• }
• event = kzalloc(sizeof(struct dpu_power_event), GFP_KERNEL);
• if (!event)

• return ERR_PTR(-ENOMEM);
  

• event->event_type = event_type;
• event->cb_fnc = cb_fnc;
• event->usr = usr;
• strlcpy(event->client_name, client_name, MAX_CLIENT_NAME_LEN);
• event->active = true;
• mutex_lock(&phandle->phandle_lock);
• list_add(&event->list, &phandle->event_list);
• mutex_unlock(&phandle->phandle_lock);
• return event;

-}

-void dpu_power_handle_unregister_event(

• struct dpu_power_handle *phandle,
  

• struct dpu_power_event *event)
  

-{

• if (!phandle || !event) {

• pr_err("invalid phandle or event\n");
  

• } else if (!event->active) {

• pr_err("power handle deinit already done\n");
  

• kfree(event);
  

• } else {

• mutex_lock(&phandle->phandle_lock);
  

• list_del_init(&event->list);
  

• mutex_unlock(&phandle->phandle_lock);
  

• kfree(event);
  

• }

-} diff --git a/drivers/gpu/drm/msm/dpu_power_handle.h b/drivers/gpu/drm/msm/dpu_power_handle.h deleted file mode 100644 index 9a6d4b9..0000000 --- a/drivers/gpu/drm/msm/dpu_power_handle.h +++ /dev/null @@ -1,288 +0,0 @@ -/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.

• • This program is free software; you can redistribute it and/or modify
• • it under the terms of the GNU General Public License version 2 and
• • only version 2 as published by the Free Software Foundation.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• */

-#ifndef _DPU_POWER_HANDLE_H_ -#define _DPU_POWER_HANDLE_H_

-#define MAX_CLIENT_NAME_LEN 128

-#define DPU_POWER_HANDLE_ENABLE_BUS_AB_QUOTA 0 -#define DPU_POWER_HANDLE_DISABLE_BUS_AB_QUOTA 0 -#define DPU_POWER_HANDLE_ENABLE_BUS_IB_QUOTA 1600000000 -#define DPU_POWER_HANDLE_DISABLE_BUS_IB_QUOTA 0

-#include <linux/dpu_io_util.h>

-/* event will be triggered before power handler disable */ -#define DPU_POWER_EVENT_PRE_DISABLE 0x1

-/* event will be triggered after power handler disable */ -#define DPU_POWER_EVENT_POST_DISABLE 0x2

-/* event will be triggered before power handler enable */ -#define DPU_POWER_EVENT_PRE_ENABLE 0x4

-/* event will be triggered after power handler enable */ -#define DPU_POWER_EVENT_POST_ENABLE 0x8

-/**

• • mdss_bus_vote_type: register bus vote type
• • VOTE_INDEX_DISABLE: removes the client vote
• • VOTE_INDEX_LOW: keeps the lowest vote for register bus
• • VOTE_INDEX_MAX: invalid
• */

-enum mdss_bus_vote_type {

• VOTE_INDEX_DISABLE,
• VOTE_INDEX_LOW,
• VOTE_INDEX_MAX,

-};

-/**

• • enum dpu_power_handle_data_bus_client - type of axi bus clients
• • @DPU_POWER_HANDLE_DATA_BUS_CLIENT_RT: core real-time bus client
• • @DPU_POWER_HANDLE_DATA_BUS_CLIENT_NRT: core non-real-time bus client
• • @DPU_POWER_HANDLE_DATA_BUS_CLIENT_MAX: maximum number of bus client type
• */

-enum dpu_power_handle_data_bus_client {

• DPU_POWER_HANDLE_DATA_BUS_CLIENT_RT,
• DPU_POWER_HANDLE_DATA_BUS_CLIENT_NRT,
• DPU_POWER_HANDLE_DATA_BUS_CLIENT_MAX

-};

-/**

• • enum DPU_POWER_HANDLE_DBUS_ID - data bus identifier
• • @DPU_POWER_HANDLE_DBUS_ID_MNOC: DPU/MNOC data bus
• • @DPU_POWER_HANDLE_DBUS_ID_LLCC: MNOC/LLCC data bus
• • @DPU_POWER_HANDLE_DBUS_ID_EBI: LLCC/EBI data bus
• */

-enum DPU_POWER_HANDLE_DBUS_ID {

• DPU_POWER_HANDLE_DBUS_ID_MNOC,
• DPU_POWER_HANDLE_DBUS_ID_LLCC,
• DPU_POWER_HANDLE_DBUS_ID_EBI,
• DPU_POWER_HANDLE_DBUS_ID_MAX,

-};

-/**

• • struct dpu_power_client: stores the power client for dpu driver
• • @name: name of the client
• • @usecase_ndx: current regs bus vote type
• • @refcount: current refcount if multiple modules are using same

• •          same client for enable/disable. Power module will
    

• •          aggregate the refcount and vote accordingly for this
    

• •          client.
    

• • @id: assigned during create. helps for debugging.
• • @list: list to attach power handle master list
• • @ab: arbitrated bandwidth for each bus client
• • @ib: instantaneous bandwidth for each bus client
• • @active: inidcates the state of dpu power handle
• */

-struct dpu_power_client {

• char name[MAX_CLIENT_NAME_LEN];
• short usecase_ndx;
• short refcount;
• u32 id;
• struct list_head list;
• u64 ab[DPU_POWER_HANDLE_DATA_BUS_CLIENT_MAX];
• u64 ib[DPU_POWER_HANDLE_DATA_BUS_CLIENT_MAX];
• bool active;

-};

-/**

• • struct dpu_power_data_handle: power handle struct for data bus
• • @data_bus_scale_table: pointer to bus scaling table
• • @data_bus_hdl: current data bus handle
• • @axi_port_cnt: number of rt axi ports
• • @nrt_axi_port_cnt: number of nrt axi ports
• • @bus_channels: number of memory bus channels
• • @curr_bw_uc_idx: current use case index of data bus
• • @ao_bw_uc_idx: active only use case index of data bus
• • @ab_rt: realtime ab quota
• • @ib_rt: realtime ib quota
• • @ab_nrt: non-realtime ab quota
• • @ib_nrt: non-realtime ib quota
• • @enable: true if bus is enabled
• */

-struct dpu_power_data_bus_handle {

• struct msm_bus_scale_pdata *data_bus_scale_table;
• u32 data_bus_hdl;
• u32 axi_port_cnt;
• u32 nrt_axi_port_cnt;
• u32 bus_channels;
• u32 curr_bw_uc_idx;
• u32 ao_bw_uc_idx;
• u64 ab_rt;
• u64 ib_rt;
• u64 ab_nrt;
• u64 ib_nrt;
• bool enable;

-};

-/*

• • struct dpu_power_event - local event registration structure
• • @client_name: name of the client registering
• • @cb_fnc: pointer to desired callback function
• • @usr: user pointer to pass to callback event trigger
• • @event: refer to DPU_POWER_HANDLE_EVENT_*
• • @list: list to attach event master list
• • @active: indicates the state of dpu power handle
• */

-struct dpu_power_event {

• char client_name[MAX_CLIENT_NAME_LEN];
• void (*cb_fnc)(u32 event_type, void *usr);
• void *usr;
• u32 event_type;
• struct list_head list;
• bool active;

-};

-/**

• • struct dpu_power_handle: power handle main struct
• • @client_clist: master list to store all clients
• • @phandle_lock: lock to synchronize the enable/disable
• • @dev: pointer to device structure
• • @usecase_ndx: current usecase index
• • @reg_bus_hdl: current register bus handle
• • @data_bus_handle: context structure for data bus control
• • @event_list: current power handle event list
• */

-struct dpu_power_handle {

• struct list_head power_client_clist;
• struct mutex phandle_lock;
• struct device *dev;
• u32 current_usecase_ndx;
• u32 reg_bus_hdl;
• struct dpu_power_data_bus_handle data_bus_handle

• [DPU_POWER_HANDLE_DBUS_ID_MAX];
  

• struct list_head event_list;

-};

-/**

• • dpu_power_resource_init() - initializes the dpu power handle
• • @pdev: platform device to search the power resources
• • @pdata: power handle to store the power resources
• • Return: error code.
• */

-int dpu_power_resource_init(struct platform_device *pdev,

• struct dpu_power_handle *pdata);

-/**

• • dpu_power_resource_deinit() - release the dpu power handle
• • @pdev: platform device for power resources
• • @pdata: power handle containing the resources
• • Return: error code.
• */

-void dpu_power_resource_deinit(struct platform_device *pdev,

• struct dpu_power_handle *pdata);

-/**

• • dpu_power_client_create() - create the client on power handle
• • @pdata: power handle containing the resources
• • @client_name: new client name for registration
• • Return: error code.
• */

-struct dpu_power_client *dpu_power_client_create(struct dpu_power_handle *pdata,

• char *client_name);

-/**

• • dpu_power_client_destroy() - destroy the client on power handle
• • @pdata: power handle containing the resources
• • @client_name: new client name for registration
• • Return: none
• */

-void dpu_power_client_destroy(struct dpu_power_handle *phandle,

• struct dpu_power_client *client);

-/**

• • dpu_power_resource_enable() - enable/disable the power resources
• • @pdata: power handle containing the resources
• • @client: client information to enable/disable its vote
• • @enable: boolean request for enable/disable
• • Return: error code.
• */

-int dpu_power_resource_enable(struct dpu_power_handle *pdata,

• struct dpu_power_client *pclient, bool enable);

-/**

• • dpu_power_data_bus_state_update() - update data bus state
• • @pdata: power handle containing the resources
• • @enable: take enable vs disable path
• • Return: error code.
• */

-int dpu_power_data_bus_state_update(struct dpu_power_handle *phandle,

• 					bool enable);
  

-/**

• • dpu_power_data_bus_set_quota() - set data bus quota for power client
• • @phandle: power handle containing the resources
• • @client: client information to set quota
• • @bus_client: real-time or non-real-time bus client
• • @bus_id: identifier of data bus, see DPU_POWER_HANDLE_DBUS_ID
• • @ab_quota: arbitrated bus bandwidth
• • @ib_quota: instantaneous bus bandwidth
• • Return: zero if success, or error code otherwise
• */

-int dpu_power_data_bus_set_quota(struct dpu_power_handle *phandle,

• struct dpu_power_client *pclient,
  

• int bus_client, u32 bus_id,
  

• u64 ab_quota, u64 ib_quota);
  

-/**

• • dpu_power_data_bus_bandwidth_ctrl() - control data bus bandwidth enable
• • @phandle: power handle containing the resources
• • @client: client information to bandwidth control
• • @enable: true to enable bandwidth for data base
• • Return: none
• */

-void dpu_power_data_bus_bandwidth_ctrl(struct dpu_power_handle *phandle,

• struct dpu_power_client *pclient, int enable);
  

-/**

• • dpu_power_handle_register_event - register a callback function for an event.
• • Clients can register for multiple events with a single register.
• • Any block with access to phandle can register for the event
• • notification.
• • @phandle: power handle containing the resources
• • @event_type: event type to register; refer DPU_POWER_HANDLE_EVENT_*
• • @cb_fnc: pointer to desired callback function
• • @usr: user pointer to pass to callback on event trigger
• • Return: event pointer if success, or error code otherwise
• */

-struct dpu_power_event *dpu_power_handle_register_event(

• struct dpu_power_handle *phandle,
  

• u32 event_type, void (*cb_fnc)(u32 event_type, void *usr),
  

• void *usr, char *client_name);
  

-/**

• • dpu_power_handle_unregister_event - unregister callback for event(s)
• • @phandle: power handle containing the resources
• • @event: event pointer returned after power handle register
• */

-void dpu_power_handle_unregister_event(struct dpu_power_handle *phandle,

• struct dpu_power_event *event);
  

-/**

• • dpu_power_handle_get_dbus_name - get name of given data bus identifier
• • @bus_id: data bus identifier
• • Return: Pointer to name string if success; NULL otherwise
• */

-const char *dpu_power_handle_get_dbus_name(u32 bus_id);

-#endif /* _DPU_POWER_HANDLE_H_ */ diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 5c267cd..60b6919 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -340,7 +340,6 @@ static int msm_drm_uninit(struct device *dev) component_unbind_all(dev, ddev);

#ifdef CONFIG_DRM_MSM_DPU

• dpu_power_resource_deinit(pdev, &priv->phandle); dpu_dbg_destroy();

#endif

@@ -519,12 +518,6 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv) drm_mode_config_init(ddev);

#ifdef CONFIG_DRM_MSM_DPU

• ret = dpu_power_resource_init(pdev, &priv->phandle);
• if (ret) {

• pr_err("dpu power resource init failed\n");
  

• goto power_init_fail;
  

• }
• ret = dpu_dbg_init(&pdev->dev); if (ret) { dev_err(dev, "failed to init dpu dbg: %d\n", ret);

@@ -733,8 +726,6 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv) #ifdef CONFIG_DRM_MSM_DPU dpu_dbg_destroy(); dbg_init_fail:

• dpu_power_resource_deinit(pdev, &priv->phandle);

-power_init_fail: #endif if (mdss && mdss->funcs) mdss->funcs->destroy(ddev); diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index f9ae96f..27a73a8 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -46,8 +46,6 @@ #include <drm/msm_drm.h> #include <drm/drm_gem.h>

-#include "dpu_power_handle.h"

#define GET_MAJOR_REV(rev) ((rev) >> 28) #define GET_MINOR_REV(rev) (((rev) >> 16) & 0xFFF) #define GET_STEP_REV(rev) ((rev) & 0xFFFF) @@ -375,8 +373,6 @@ struct msm_drm_private {

struct msm_kms *kms;

• struct dpu_power_handle phandle;
• /* subordinate devices, if present: */ struct platform_device *gpu_pdev;

-- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project