From: Xinlei Lee xinlei.lee@mediatek.com
Changes since v3: 1. Add dsi port property. 2. Fix some formatting.
Changes since v2: 1. Added #address-cells, #size-cells two properties. 2. Fix some formatting issues.
Changes since v1: 1. Delete the mediatek,dsi.txt & Add the mediatek,dsi.yaml. 2. Ignore the Move the getting bridge node function patch for V1.
Xinlei Lee (3): dt-bindings: display: mediatek: dsi: Convert dsi_dtbinding to .yaml dt-bindings: display: mediatek: dsi: Add compatible for MediaTek MT8186 drm/mediatek: Add mt8186 dsi compatible to mtk_dsi.c
.../display/mediatek/mediatek,dsi.txt | 62 --------- .../display/mediatek/mediatek,dsi.yaml | 119 ++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_dsi.c | 8 ++ 3 files changed, 127 insertions(+), 62 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
From: Xinlei Lee xinlei.lee@mediatek.com
Convert mediatek,dsi.txt to mediatek,dsi.yaml format
Signed-off-by: Xinlei Lee xinlei.lee@mediatek.com --- .../display/mediatek/mediatek,dsi.txt | 62 --------- .../display/mediatek/mediatek,dsi.yaml | 118 ++++++++++++++++++ 2 files changed, 118 insertions(+), 62 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt deleted file mode 100644 index 36b01458f45c..000000000000 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt +++ /dev/null @@ -1,62 +0,0 @@ -Mediatek DSI Device -=================== - -The Mediatek DSI function block is a sink of the display subsystem and can -drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual- -channel output. - -Required properties: -- compatible: "mediatek,<chip>-dsi" -- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183. -- reg: Physical base address and length of the controller's registers -- interrupts: The interrupt signal from the function block. -- clocks: device clocks - See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. -- clock-names: must contain "engine", "digital", and "hs" -- phys: phandle link to the MIPI D-PHY controller. -- phy-names: must contain "dphy" -- port: Output port node with endpoint definitions as described in - Documentation/devicetree/bindings/graph.txt. This port should be connected - to the input port of an attached DSI panel or DSI-to-eDP encoder chip. - -Optional properties: -- resets: list of phandle + reset specifier pair, as described in [1]. - -[1] Documentation/devicetree/bindings/reset/reset.txt - -MIPI TX Configuration Module -============================ - -See phy/mediatek,dsi-phy.yaml - -Example: - -mipi_tx0: mipi-dphy@10215000 { - compatible = "mediatek,mt8173-mipi-tx"; - reg = <0 0x10215000 0 0x1000>; - clocks = <&clk26m>; - clock-output-names = "mipi_tx0_pll"; - #clock-cells = <0>; - #phy-cells = <0>; - drive-strength-microamp = <4600>; - nvmem-cells= <&mipi_tx_calibration>; - nvmem-cell-names = "calibration-data"; -}; - -dsi0: dsi@1401b000 { - compatible = "mediatek,mt8173-dsi"; - reg = <0 0x1401b000 0 0x1000>; - interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; - clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>, - <&mipi_tx0>; - clock-names = "engine", "digital", "hs"; - resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>; - phys = <&mipi_tx0>; - phy-names = "dphy"; - - port { - dsi0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml new file mode 100644 index 000000000000..431bb981394f --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek DSI Controller Device Tree Bindings + +maintainers: + - CK Hu ck.hu@mediatek.com + - Jitao Shi jitao.shi@mediatek.com + - Xinlei Lee xinlei.lee@mediatek.com + +description: | + The MediaTek DSI function block is a sink of the display subsystem and can + drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual- + channel output. + +properties: + compatible: + enum: + - mediatek,mt2701-dsi + - mediatek,mt7623-dsi + - mediatek,mt8167-dsi + - mediatek,mt8173-dsi + - mediatek,mt8183-dsi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + items: + - description: Engine Clock + - description: Digital Clock + - description: HS Clock + + clock-names: + items: + - const: engine + - const: digital + - const: hs + + resets: + maxItems: 1 + + phys: + maxItems: 1 + + phy-names: + items: + - const: dphy + + port: + $ref: /schemas/graph.yaml#/properties/port + description: + Output port node. This port should be connected to the input + port of an attached DSI panel or DSI-to-eDP encoder chip. + + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + +required: + - compatible + - reg + - interrupts + - power-domains + - clocks + - clock-names + - phys + - phy-names + - port + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt8183-clk.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/power/mt8183-power.h> + #include <dt-bindings/phy/phy.h> + #include <dt-bindings/reset/mt8183-resets.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + dsi0: dsi@14014000 { + compatible = "mediatek,mt8183-dsi"; + reg = <0 0x14014000 0 0x1000>; + interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DSI0_MM>, + <&mmsys CLK_MM_DSI0_IF>, + <&mipi_tx0>; + clock-names = "engine", "digital", "hs"; + resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>; + phys = <&mipi_tx0>; + phy-names = "dphy"; + port { + dsi0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; + +...
Hi, Xinlei:
On Sat, 2022-04-09 at 17:11 +0800, xinlei.lee@mediatek.com wrote:
From: Xinlei Lee xinlei.lee@mediatek.com
Convert mediatek,dsi.txt to mediatek,dsi.yaml format
Signed-off-by: Xinlei Lee xinlei.lee@mediatek.com
.../display/mediatek/mediatek,dsi.txt | 62 --------- .../display/mediatek/mediatek,dsi.yaml | 118 ++++++++++++++++++ 2 files changed, 118 insertions(+), 62 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt deleted file mode 100644 index 36b01458f45c..000000000000
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt +++ /dev/null @@ -1,62 +0,0 @@
-Mediatek DSI Device
-The Mediatek DSI function block is a sink of the display subsystem and can -drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual- -channel output.
-Required properties: -- compatible: "mediatek,<chip>-dsi" -- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183. -- reg: Physical base address and length of the controller's registers -- interrupts: The interrupt signal from the function block. -- clocks: device clocks
- See Documentation/devicetree/bindings/clock/clock-bindings.txt for
details. -- clock-names: must contain "engine", "digital", and "hs" -- phys: phandle link to the MIPI D-PHY controller. -- phy-names: must contain "dphy" -- port: Output port node with endpoint definitions as described in
- Documentation/devicetree/bindings/graph.txt. This port should be
connected
- to the input port of an attached DSI panel or DSI-to-eDP encoder
chip.
-Optional properties: -- resets: list of phandle + reset specifier pair, as described in [1].
-[1] Documentation/devicetree/bindings/reset/reset.txt
-MIPI TX Configuration Module
-See phy/mediatek,dsi-phy.yaml
-Example:
-mipi_tx0: mipi-dphy@10215000 {
- compatible = "mediatek,mt8173-mipi-tx";
- reg = <0 0x10215000 0 0x1000>;
- clocks = <&clk26m>;
- clock-output-names = "mipi_tx0_pll";
- #clock-cells = <0>;
- #phy-cells = <0>;
- drive-strength-microamp = <4600>;
- nvmem-cells= <&mipi_tx_calibration>;
- nvmem-cell-names = "calibration-data";
-};
-dsi0: dsi@1401b000 {
- compatible = "mediatek,mt8173-dsi";
- reg = <0 0x1401b000 0 0x1000>;
- interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>,
<&mipi_tx0>;- clock-names = "engine", "digital", "hs";
- resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
- phys = <&mipi_tx0>;
- phy-names = "dphy";
- port {
dsi0_out: endpoint {remote-endpoint = <&panel_in>;};- };
-}; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yam l b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yam l new file mode 100644 index 000000000000..431bb981394f --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yam l @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/m...
+$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;...
+title: MediaTek DSI Controller Device Tree Bindings
+maintainers:
- CK Hu ck.hu@mediatek.com
Replace 'CK Hu' with MediaTek DRM driver maintainer:
Chun-Kuang Hu chunkuang.hu@kernel.org Philipp Zabel p.zabel@pengutronix.de
- Jitao Shi jitao.shi@mediatek.com
- Xinlei Lee xinlei.lee@mediatek.com
+description: |
- The MediaTek DSI function block is a sink of the display subsystem
and can
- drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized
for dual-
- channel output.
+properties:
- compatible:
- enum:
- mediatek,mt2701-dsi- mediatek,mt7623-dsi- mediatek,mt8167-dsi- mediatek,mt8173-dsi- mediatek,mt8183-dsi- reg:
- maxItems: 1
- interrupts:
- maxItems: 1
- power-domains:
- maxItems: 1
- clocks:
- items:
- description: Engine Clock- description: Digital Clock- description: HS Clock- clock-names:
- items:
- const: engine- const: digital- const: hs- resets:
- maxItems: 1
- phys:
- maxItems: 1
- phy-names:
- items:
- const: dphy- port:
- $ref: /schemas/graph.yaml#/properties/port
- description:
Output port node. This port should be connected to the inputport of an attached DSI panel or DSI-to-eDP encoder chip.- "#address-cells":
- const: 2
- "#size-cells":
- const: 2
+required:
- compatible
- reg
- interrupts
- power-domains
- clocks
- clock-names
- phys
- phy-names
- port
+additionalProperties: false
+examples:
- |
- #include <dt-bindings/clock/mt8183-clk.h>
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/interrupt-controller/irq.h>
- #include <dt-bindings/power/mt8183-power.h>
- #include <dt-bindings/phy/phy.h>
- #include <dt-bindings/reset/mt8183-resets.h>
- soc {
#address-cells = <2>;#size-cells = <2>;dsi0: dsi@14014000 {compatible = "mediatek,mt8183-dsi";reg = <0 0x14014000 0 0x1000>;interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;clocks = <&mmsys CLK_MM_DSI0_MM>,<&mmsys CLK_MM_DSI0_IF>,<&mipi_tx0>;clock-names = "engine", "digital", "hs";resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;phys = <&mipi_tx0>;phy-names = "dphy";port {dsi0_out: endpoint {remote-endpoint = <&panel_in>;};};};- };
+...
On Tue, 2022-04-12 at 17:17 +0800, CK Hu wrote:
Hi, Xinlei:
On Sat, 2022-04-09 at 17:11 +0800, xinlei.lee@mediatek.com wrote:
From: Xinlei Lee xinlei.lee@mediatek.com
Convert mediatek,dsi.txt to mediatek,dsi.yaml format
Signed-off-by: Xinlei Lee xinlei.lee@mediatek.com
.../display/mediatek/mediatek,dsi.txt | 62 --------- .../display/mediatek/mediatek,dsi.yaml | 118 ++++++++++++++++++ 2 files changed, 118 insertions(+), 62 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yam l
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.t xt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.t xt deleted file mode 100644 index 36b01458f45c..000000000000
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.t xt +++ /dev/null @@ -1,62 +0,0 @@
-Mediatek DSI Device
-The Mediatek DSI function block is a sink of the display subsystem and can -drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual- -channel output.
-Required properties: -- compatible: "mediatek,<chip>-dsi" -- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183. -- reg: Physical base address and length of the controller's registers -- interrupts: The interrupt signal from the function block. -- clocks: device clocks
- See Documentation/devicetree/bindings/clock/clock-bindings.txt
for details. -- clock-names: must contain "engine", "digital", and "hs" -- phys: phandle link to the MIPI D-PHY controller. -- phy-names: must contain "dphy" -- port: Output port node with endpoint definitions as described in
- Documentation/devicetree/bindings/graph.txt. This port should be
connected
- to the input port of an attached DSI panel or DSI-to-eDP encoder
chip.
-Optional properties: -- resets: list of phandle + reset specifier pair, as described in [1].
-[1] Documentation/devicetree/bindings/reset/reset.txt
-MIPI TX Configuration Module
-See phy/mediatek,dsi-phy.yaml
-Example:
-mipi_tx0: mipi-dphy@10215000 {
- compatible = "mediatek,mt8173-mipi-tx";
- reg = <0 0x10215000 0 0x1000>;
- clocks = <&clk26m>;
- clock-output-names = "mipi_tx0_pll";
- #clock-cells = <0>;
- #phy-cells = <0>;
- drive-strength-microamp = <4600>;
- nvmem-cells= <&mipi_tx_calibration>;
- nvmem-cell-names = "calibration-data";
-};
-dsi0: dsi@1401b000 {
- compatible = "mediatek,mt8173-dsi";
- reg = <0 0x1401b000 0 0x1000>;
- interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>,
<&mipi_tx0>;- clock-names = "engine", "digital", "hs";
- resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
- phys = <&mipi_tx0>;
- phy-names = "dphy";
- port {
dsi0_out: endpoint {remote-endpoint = <&panel_in>;};- };
-}; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.y am l b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.y am l new file mode 100644 index 000000000000..431bb981394f --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.y am l @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id:
https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/m...
+$schema:
https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;...
+title: MediaTek DSI Controller Device Tree Bindings
+maintainers:
- CK Hu ck.hu@mediatek.com
Replace 'CK Hu' with MediaTek DRM driver maintainer:
Chun-Kuang Hu chunkuang.hu@kernel.org Philipp Zabel p.zabel@pengutronix.de
- Jitao Shi jitao.shi@mediatek.com
- Xinlei Lee xinlei.lee@mediatek.com
+description: |
- The MediaTek DSI function block is a sink of the display
subsystem and can
- drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized
for dual-
- channel output.
+properties:
- compatible:
- enum:
- mediatek,mt2701-dsi- mediatek,mt7623-dsi- mediatek,mt8167-dsi- mediatek,mt8173-dsi- mediatek,mt8183-dsi- reg:
- maxItems: 1
- interrupts:
- maxItems: 1
- power-domains:
- maxItems: 1
- clocks:
- items:
- description: Engine Clock- description: Digital Clock- description: HS Clock- clock-names:
- items:
- const: engine- const: digital- const: hs- resets:
- maxItems: 1
- phys:
- maxItems: 1
- phy-names:
- items:
- const: dphy- port:
- $ref: /schemas/graph.yaml#/properties/port
- description:
Output port node. This port should be connected to the inputport of an attached DSI panel or DSI-to-eDP encoder chip.- "#address-cells":
- const: 2
- "#size-cells":
- const: 2
+required:
- compatible
- reg
- interrupts
- power-domains
- clocks
- clock-names
- phys
- phy-names
- port
+additionalProperties: false
+examples:
- |
- #include <dt-bindings/clock/mt8183-clk.h>
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/interrupt-controller/irq.h>
- #include <dt-bindings/power/mt8183-power.h>
- #include <dt-bindings/phy/phy.h>
- #include <dt-bindings/reset/mt8183-resets.h>
- soc {
#address-cells = <2>;#size-cells = <2>;dsi0: dsi@14014000 {compatible = "mediatek,mt8183-dsi";reg = <0 0x14014000 0 0x1000>;interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;clocks = <&mmsys CLK_MM_DSI0_MM>,<&mmsys CLK_MM_DSI0_IF>,<&mipi_tx0>;clock-names = "engine", "digital", "hs";resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;phys = <&mipi_tx0>;phy-names = "dphy";port {dsi0_out: endpoint {remote-endpoint = <&panel_in>;};};};- };
+...
Hi CK:
Thanks for your review. I will replace in the next version.
Best Regards! xinlei
On Sat, Apr 09, 2022 at 05:11:52PM +0800, xinlei.lee@mediatek.com wrote:
From: Xinlei Lee xinlei.lee@mediatek.com
Convert mediatek,dsi.txt to mediatek,dsi.yaml format
Signed-off-by: Xinlei Lee xinlei.lee@mediatek.com
.../display/mediatek/mediatek,dsi.txt | 62 --------- .../display/mediatek/mediatek,dsi.yaml | 118 ++++++++++++++++++ 2 files changed, 118 insertions(+), 62 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml new file mode 100644 index 000000000000..431bb981394f --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: MediaTek DSI Controller Device Tree Bindings
+maintainers:
- CK Hu ck.hu@mediatek.com
- Jitao Shi jitao.shi@mediatek.com
- Xinlei Lee xinlei.lee@mediatek.com
+description: |
- The MediaTek DSI function block is a sink of the display subsystem and can
- drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
- channel output.
allOf: - $ref: /schemas/display/dsi-controller.yaml#
+properties:
- compatible:
- enum:
- mediatek,mt2701-dsi- mediatek,mt7623-dsi- mediatek,mt8167-dsi- mediatek,mt8173-dsi- mediatek,mt8183-dsi- reg:
- maxItems: 1
- interrupts:
- maxItems: 1
- power-domains:
- maxItems: 1
- clocks:
- items:
- description: Engine Clock- description: Digital Clock- description: HS Clock- clock-names:
- items:
- const: engine- const: digital- const: hs- resets:
- maxItems: 1
- phys:
- maxItems: 1
- phy-names:
- items:
- const: dphy- port:
- $ref: /schemas/graph.yaml#/properties/port
- description:
Output port node. This port should be connected to the inputport of an attached DSI panel or DSI-to-eDP encoder chip.- "#address-cells":
- const: 2
- "#size-cells":
- const: 2
+required:
- compatible
- reg
- interrupts
- power-domains
- clocks
- clock-names
- phys
- phy-names
- port
+additionalProperties: false
with the above,
unevaluatedProperties: false
+examples:
- |
- #include <dt-bindings/clock/mt8183-clk.h>
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/interrupt-controller/irq.h>
- #include <dt-bindings/power/mt8183-power.h>
- #include <dt-bindings/phy/phy.h>
- #include <dt-bindings/reset/mt8183-resets.h>
- soc {
#address-cells = <2>;#size-cells = <2>;dsi0: dsi@14014000 {compatible = "mediatek,mt8183-dsi";reg = <0 0x14014000 0 0x1000>;interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;clocks = <&mmsys CLK_MM_DSI0_MM>,<&mmsys CLK_MM_DSI0_IF>,<&mipi_tx0>;clock-names = "engine", "digital", "hs";resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;phys = <&mipi_tx0>;phy-names = "dphy";port {dsi0_out: endpoint {remote-endpoint = <&panel_in>;};};};- };
+...
2.18.0
On Wed, 2022-04-13 at 16:20 -0500, Rob Herring wrote:
On Sat, Apr 09, 2022 at 05:11:52PM +0800, xinlei.lee@mediatek.com wrote:
From: Xinlei Lee xinlei.lee@mediatek.com
Convert mediatek,dsi.txt to mediatek,dsi.yaml format
Signed-off-by: Xinlei Lee xinlei.lee@mediatek.com
.../display/mediatek/mediatek,dsi.txt | 62 --------- .../display/mediatek/mediatek,dsi.yaml | 118 ++++++++++++++++++ 2 files changed, 118 insertions(+), 62 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yam l
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.y aml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.y aml new file mode 100644 index 000000000000..431bb981394f --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.y aml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: MediaTek DSI Controller Device Tree Bindings
+maintainers:
- CK Hu ck.hu@mediatek.com
- Jitao Shi jitao.shi@mediatek.com
- Xinlei Lee xinlei.lee@mediatek.com
+description: |
- The MediaTek DSI function block is a sink of the display
subsystem and can
- drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized
for dual-
- channel output.
allOf:
- $ref: /schemas/display/dsi-controller.yaml#
Hello Rob,
Thanks for your review.
I will help Xinlei to push next version. I will add this in next version.
+properties:
- compatible:
- enum:
- mediatek,mt2701-dsi- mediatek,mt7623-dsi- mediatek,mt8167-dsi- mediatek,mt8173-dsi- mediatek,mt8183-dsi- reg:
- maxItems: 1
- interrupts:
- maxItems: 1
- power-domains:
- maxItems: 1
- clocks:
- items:
- description: Engine Clock- description: Digital Clock- description: HS Clock- clock-names:
- items:
- const: engine- const: digital- const: hs- resets:
- maxItems: 1
- phys:
- maxItems: 1
- phy-names:
- items:
- const: dphy- port:
- $ref: /schemas/graph.yaml#/properties/port
- description:
Output port node. This port should be connected to the inputport of an attached DSI panel or DSI-to-eDP encoder chip.- "#address-cells":
- const: 2
- "#size-cells":
- const: 2
+required:
- compatible
- reg
- interrupts
- power-domains
- clocks
- clock-names
- phys
- phy-names
- port
+additionalProperties: false
with the above,
unevaluatedProperties: false
OK, I will modify additionalProperties to unevaluatedProperties in next version.
BRs, Rex
+examples:
- |
- #include <dt-bindings/clock/mt8183-clk.h>
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/interrupt-controller/irq.h>
- #include <dt-bindings/power/mt8183-power.h>
- #include <dt-bindings/phy/phy.h>
- #include <dt-bindings/reset/mt8183-resets.h>
- soc {
#address-cells = <2>;#size-cells = <2>;dsi0: dsi@14014000 {compatible = "mediatek,mt8183-dsi";reg = <0 0x14014000 0 0x1000>;interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;clocks = <&mmsys CLK_MM_DSI0_MM>,<&mmsys CLK_MM_DSI0_IF>,<&mipi_tx0>;clock-names = "engine", "digital", "hs";resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;phys = <&mipi_tx0>;phy-names = "dphy";port {dsi0_out: endpoint {remote-endpoint = <&panel_in>;};};};- };
+...
2.18.0
From: Xinlei Lee xinlei.lee@mediatek.com
Add dt-binding documentation of dsi for MediaTek MT8186 SoC.
Signed-off-by: Xinlei Lee xinlei.lee@mediatek.com Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com Reviewed-by: Rex-BC Chen rex-bc.chen@mediatek.com --- .../devicetree/bindings/display/mediatek/mediatek,dsi.yaml | 1 + 1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml index 431bb981394f..4ef0d3bf55ca 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml @@ -24,6 +24,7 @@ properties: - mediatek,mt8167-dsi - mediatek,mt8173-dsi - mediatek,mt8183-dsi + - mediatek,mt8186-dsi
reg: maxItems: 1
On Sat, 09 Apr 2022 17:11:53 +0800, xinlei.lee@mediatek.com wrote:
From: Xinlei Lee xinlei.lee@mediatek.com
Add dt-binding documentation of dsi for MediaTek MT8186 SoC.
Signed-off-by: Xinlei Lee xinlei.lee@mediatek.com Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com Reviewed-by: Rex-BC Chen rex-bc.chen@mediatek.com
.../devicetree/bindings/display/mediatek/mediatek,dsi.yaml | 1 + 1 file changed, 1 insertion(+)
Acked-by: Rob Herring robh@kernel.org
From: Xinlei Lee xinlei.lee@mediatek.com
Add the compatible because use different cmdq addresses in mt8186.
Signed-off-by: Xinlei Lee xinlei.lee@mediatek.com Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com Reviewed-by: Rex-BC Chen rex-bc.chen@mediatek.com --- drivers/gpu/drm/mediatek/mtk_dsi.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index ccb0511b9cd5..b13fd0317e96 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -1155,6 +1155,12 @@ static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = { .has_size_ctl = true, };
+static const struct mtk_dsi_driver_data mt8186_dsi_driver_data = { + .reg_cmdq_off = 0xd00, + .has_shadow_ctl = true, + .has_size_ctl = true, +}; + static const struct of_device_id mtk_dsi_of_match[] = { { .compatible = "mediatek,mt2701-dsi", .data = &mt2701_dsi_driver_data }, @@ -1162,6 +1168,8 @@ static const struct of_device_id mtk_dsi_of_match[] = { .data = &mt8173_dsi_driver_data }, { .compatible = "mediatek,mt8183-dsi", .data = &mt8183_dsi_driver_data }, + { .compatible = "mediatek,mt8186-dsi", + .data = &mt8186_dsi_driver_data }, { }, }; MODULE_DEVICE_TABLE(of, mtk_dsi_of_match);
dri-devel@lists.freedesktop.org
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CK Hu -
Rex-BC Chen -
Rob Herring -
xinlei.lee -
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