From: Chris Morgan macromorgan@hotmail.com
This series adds the ability to set the byteswap order in the chrontel ch7033 driver via an optional devicetree node. This is necessary because the HDMI DIP of the NTC CHIP requires a byteswap order that differs from the default value of the driver.
Signed-off-by: Chris Morgan macromorgan@hotmail.com
Chris Morgan (2): dt-bindings: Add byteswap order to chrontel ch7033 drm/bridge: chrontel-ch7033: Add option for setting byteswap order
.../bindings/display/bridge/chrontel,ch7033.yaml | 8 ++++++++ drivers/gpu/drm/bridge/chrontel-ch7033.c | 15 +++++++++++++-- 2 files changed, 21 insertions(+), 2 deletions(-)
From: Chris Morgan macromorgan@hotmail.com
Update dt-binding documentation to add support for setting byteswap of chrontel ch7033.
New property name of chrontel,byteswap added to set the byteswap order. This property is optional.
Signed-off-by: Chris Morgan macromorgan@hotmail.com --- .../bindings/display/bridge/chrontel,ch7033.yaml | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml b/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml index bb6289c7d375..ecd3062c5215 100644 --- a/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml +++ b/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml @@ -14,6 +14,14 @@ properties: compatible: const: chrontel,ch7033
+ chrontel,byteswap: + $ref: /schemas/types.yaml#/definitions/uint8 + enum: [0, 1, 2, 3, 4, 5] + description: | + Set the byteswap value of the bridge. Values 0-5 correspond to + BYTE_SWAP_RGB, BYTE_SWAP_RBG, BYTE_SWAP_GRB, BYTE_SWAP_GBR, + BYTE_SWAP_BRG, and BYTE_SWAP_BGR respectively. + reg: maxItems: 1 description: I2C address of the device
From: Chris Morgan macromorgan@hotmail.com
Add the option to set the byteswap order in the devicetree. For the official HDMI DIP for the NTC CHIP the byteswap order needs to be RGB, however the driver sets it as BGR. With this patch the driver will remain at BGR unless manually specified via devicetree.
Signed-off-by: Chris Morgan macromorgan@hotmail.com --- drivers/gpu/drm/bridge/chrontel-ch7033.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/chrontel-ch7033.c b/drivers/gpu/drm/bridge/chrontel-ch7033.c index 486f405c2e16..88175b7e80d4 100644 --- a/drivers/gpu/drm/bridge/chrontel-ch7033.c +++ b/drivers/gpu/drm/bridge/chrontel-ch7033.c @@ -67,6 +67,7 @@ enum { BYTE_SWAP_GBR = 3, BYTE_SWAP_BRG = 4, BYTE_SWAP_BGR = 5, + BYTE_SWAP_MAX = 6, };
/* Page 0, Register 0x19 */ @@ -354,6 +355,8 @@ static void ch7033_bridge_mode_set(struct drm_bridge *bridge, int hsynclen = mode->hsync_end - mode->hsync_start; int vbporch = mode->vsync_start - mode->vdisplay; int vsynclen = mode->vsync_end - mode->vsync_start; + u8 byte_swap; + int ret;
/* * Page 4 @@ -397,8 +400,16 @@ static void ch7033_bridge_mode_set(struct drm_bridge *bridge, regmap_write(priv->regmap, 0x15, vbporch); regmap_write(priv->regmap, 0x16, vsynclen);
- /* Input color swap. */ - regmap_update_bits(priv->regmap, 0x18, SWAP, BYTE_SWAP_BGR); + /* Input color swap. Byte order is optional and will default to + * BYTE_SWAP_BGR to preserve backwards compatibility with existing + * driver. + */ + ret = of_property_read_u8(priv->bridge.of_node, "chrontel,byteswap", + &byte_swap); + if (!ret && byte_swap < BYTE_SWAP_MAX) + regmap_update_bits(priv->regmap, 0x18, SWAP, byte_swap); + else + regmap_update_bits(priv->regmap, 0x18, SWAP, BYTE_SWAP_BGR);
/* Input clock and sync polarity. */ regmap_update_bits(priv->regmap, 0x19, 0x1, mode->clock >> 16);
dri-devel@lists.freedesktop.org
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Chris Morgan