From: Frank Wunderlich frank-w@public-files.de
This Patch-Series adds missing Patches/Bugfixes to get hdmi working on BPI-R2
v3->v4: - fix removed const in "add ddp routing for mt7623" - change subjects to "drm/mediatek:..." - add documentation for mt7623-* compatibles - dropped redundant display_components node (mmsys compatible) - add reviewd-by collected in v3 v2->v3: - use own mmsys-routing for mt7623 instead of code getting different routing from dts - remove ddp routing bls -> dpi from bpir2/rfb dts - updated some commit-Messages as suggested by CK Hu v1->v2: - using get_possible_crtc API instead of hardcoded - drop unused dts-nodes - refine commit-messages as far as i can :) "config component output by device node port" is needed to fix a WARN_ON() "fix boot up for 720 and 480 but 1080" fixes flickering, which may cause also some resolutions not working on some TFT (had some pr>
Frank Wunderlich (2): dt-bindings: mediatek: add mt7623 display-nodes drm/mediatek: add ddp routing for mt7623
Jitao Shi (1): drm/mediatek: dpi/dsi: change the getting possible_crtc way
Ryder Lee (1): arm: dts: mt7623: add display subsystem related device nodes
Stu Hsieh (1): drm/mediatek: Add get_possible_crtc API for dpi, dsi
chunhui dai (1): drm/mediatek: disable tmds on mt2701
.../display/mediatek/mediatek,disp.txt | 2 +- .../display/mediatek/mediatek,dpi.txt | 2 +- .../display/mediatek/mediatek,dsi.txt | 4 +- .../display/mediatek/mediatek,hdmi.txt | 4 + arch/arm/boot/dts/mt7623.dtsi | 170 ++++++++++++++++++ arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts | 72 ++++++++ arch/arm/boot/dts/mt7623n-rfb-emmc.dts | 72 ++++++++ drivers/gpu/drm/mediatek/mtk_dpi.c | 3 +- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 42 +++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 23 +++ drivers/gpu/drm/mediatek/mtk_dsi.c | 3 +- drivers/gpu/drm/mediatek/mtk_hdmi_phy.c | 3 + drivers/gpu/drm/mediatek/mtk_hdmi_phy.h | 1 + .../gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 1 + 15 files changed, 398 insertions(+), 6 deletions(-)
From: Frank Wunderlich frank-w@public-files.de
mt7623 uses mt2701/mt8173 for drm, but have own compatibles
Signed-off-by: Frank Wunderlich frank-w@public-files.de --- .../devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +- .../devicetree/bindings/display/mediatek/mediatek,dpi.txt | 2 +- .../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 4 ++-- .../devicetree/bindings/display/mediatek/mediatek,hdmi.txt | 4 ++++ 4 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt index b91e709db7a4..121220745d46 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt @@ -43,7 +43,7 @@ Required properties (all function blocks): "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt "mediatek,<chip>-disp-mutex" - display mutex "mediatek,<chip>-disp-od" - overdrive - the supported chips are mt2701, mt2712 and mt8173. + the supported chips are mt2701, mt7623, mt2712 and mt8173. - reg: Physical base address and length of the function block register space - interrupts: The interrupt signal from the function block (required, except for merge and split function blocks). diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt index 77def4456706..dc1ebd13cc88 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt @@ -7,7 +7,7 @@ output bus.
Required properties: - compatible: "mediatek,<chip>-dpi" - the supported chips are mt2701 , mt8173 and mt8183. + the supported chips are mt2701, mt7623, mt8173 and mt8183. - reg: Physical base address and length of the controller's registers - interrupts: The interrupt signal from the function block. - clocks: device clocks diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt index 8e4729de8c85..f06f24d405a5 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt @@ -7,7 +7,7 @@ channel output.
Required properties: - compatible: "mediatek,<chip>-dsi" - the supported chips are mt2701, mt8173 and mt8183. +- the supported chips are mt2701, mt7623, mt8173 and mt8183. - reg: Physical base address and length of the controller's registers - interrupts: The interrupt signal from the function block. - clocks: device clocks @@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY.
Required properties: - compatible: "mediatek,<chip>-mipi-tx" - the supported chips are mt2701, mt8173 and mt8183. +- the supported chips are mt2701, 7623, mt8173 and mt8183. - reg: Physical base address and length of the controller's registers - clocks: PLL reference clock - clock-output-names: name of the output clock line to the DSI encoder diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt index 7b124242b0c5..6b1c586403e4 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt @@ -6,6 +6,7 @@ its parallel input.
Required properties: - compatible: Should be "mediatek,<chip>-hdmi". +- the supported chips are mt2701, mt7623 and mt8173 - reg: Physical base address and length of the controller's registers - interrupts: The interrupt signal from the function block. - clocks: device clocks @@ -32,6 +33,7 @@ The HDMI CEC controller handles hotplug detection and CEC communication.
Required properties: - compatible: Should be "mediatek,<chip>-cec" +- the supported chips are mt7623 and mt8173 - reg: Physical base address and length of the controller's registers - interrupts: The interrupt signal from the function block. - clocks: device clock @@ -44,6 +46,7 @@ The Mediatek's I2C controller is used to interface with I2C devices.
Required properties: - compatible: Should be "mediatek,<chip>-hdmi-ddc" +- the supported chips are mt7623 and mt8173 - reg: Physical base address and length of the controller's registers - clocks: device clock - clock-names: Should be "ddc-i2c". @@ -56,6 +59,7 @@ output and drives the HDMI pads.
Required properties: - compatible: "mediatek,<chip>-hdmi-phy" +- the supported chips are mt2701, mt7623 and mt8173 - reg: Physical base address and length of the module's registers - clocks: PLL reference clock - clock-names: must contain "pll_ref"
CC Rob Herring and devicetree-list
Gesendet: Dienstag, 04. August 2020 um 18:55 Uhr Von: "Frank Wunderlich" linux@fw-web.de An: linux-mediatek@lists.infradead.org Cc: "Frank Wunderlich" frank-w@public-files.de, "Chun-Kuang Hu" chunkuang.hu@kernel.org, "Philipp Zabel" p.zabel@pengutronix.de, "David Airlie" airlied@linux.ie, "Daniel Vetter" daniel@ffwll.ch, "Matthias Brugger" matthias.bgg@gmail.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Betreff: [PATCH v4 1/6] dt-bindings: mediatek: add mt7623 display-nodes
From: Frank Wunderlich frank-w@public-files.de
mt7623 uses mt2701/mt8173 for drm, but have own compatibles
Signed-off-by: Frank Wunderlich frank-w@public-files.de
.../devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +- .../devicetree/bindings/display/mediatek/mediatek,dpi.txt | 2 +- .../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 4 ++-- .../devicetree/bindings/display/mediatek/mediatek,hdmi.txt | 4 ++++ 4 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt index b91e709db7a4..121220745d46 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt @@ -43,7 +43,7 @@ Required properties (all function blocks): "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt "mediatek,<chip>-disp-mutex" - display mutex "mediatek,<chip>-disp-od" - overdrive
- the supported chips are mt2701, mt2712 and mt8173.
- the supported chips are mt2701, mt7623, mt2712 and mt8173.
- reg: Physical base address and length of the function block register space
- interrupts: The interrupt signal from the function block (required, except for merge and split function blocks).
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt index 77def4456706..dc1ebd13cc88 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt @@ -7,7 +7,7 @@ output bus.
Required properties:
- compatible: "mediatek,<chip>-dpi"
- the supported chips are mt2701 , mt8173 and mt8183.
- the supported chips are mt2701, mt7623, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clocks
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt index 8e4729de8c85..f06f24d405a5 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt @@ -7,7 +7,7 @@ channel output.
Required properties:
- compatible: "mediatek,<chip>-dsi"
- the supported chips are mt2701, mt8173 and mt8183.
+- the supported chips are mt2701, mt7623, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clocks
@@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY.
Required properties:
- compatible: "mediatek,<chip>-mipi-tx"
- the supported chips are mt2701, mt8173 and mt8183.
+- the supported chips are mt2701, 7623, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- clocks: PLL reference clock
- clock-output-names: name of the output clock line to the DSI encoder
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt index 7b124242b0c5..6b1c586403e4 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt @@ -6,6 +6,7 @@ its parallel input.
Required properties:
- compatible: Should be "mediatek,<chip>-hdmi".
+- the supported chips are mt2701, mt7623 and mt8173
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clocks
@@ -32,6 +33,7 @@ The HDMI CEC controller handles hotplug detection and CEC communication.
Required properties:
- compatible: Should be "mediatek,<chip>-cec"
+- the supported chips are mt7623 and mt8173
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clock
@@ -44,6 +46,7 @@ The Mediatek's I2C controller is used to interface with I2C devices.
Required properties:
- compatible: Should be "mediatek,<chip>-hdmi-ddc"
+- the supported chips are mt7623 and mt8173
- reg: Physical base address and length of the controller's registers
- clocks: device clock
- clock-names: Should be "ddc-i2c".
@@ -56,6 +59,7 @@ output and drives the HDMI pads.
Required properties:
- compatible: "mediatek,<chip>-hdmi-phy"
+- the supported chips are mt2701, mt7623 and mt8173
- reg: Physical base address and length of the module's registers
- clocks: PLL reference clock
- clock-names: must contain "pll_ref"
-- 2.25.1
On Tue, Aug 4, 2020 at 11:19 AM Frank Wunderlich frank-w@public-files.de wrote:
CC Rob Herring and devicetree-list
Resend or it is not in my patchwork queue.
But this is simple enough:
Acked-by: Rob Herring robh@kernel.org
Gesendet: Dienstag, 04. August 2020 um 18:55 Uhr Von: "Frank Wunderlich" linux@fw-web.de An: linux-mediatek@lists.infradead.org Cc: "Frank Wunderlich" frank-w@public-files.de, "Chun-Kuang Hu" chunkuang.hu@kernel.org, "Philipp Zabel" p.zabel@pengutronix.de, "David Airlie" airlied@linux.ie, "Daniel Vetter" daniel@ffwll.ch, "Matthias Brugger" matthias.bgg@gmail.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Betreff: [PATCH v4 1/6] dt-bindings: mediatek: add mt7623 display-nodes
From: Frank Wunderlich frank-w@public-files.de
mt7623 uses mt2701/mt8173 for drm, but have own compatibles
Signed-off-by: Frank Wunderlich frank-w@public-files.de
.../devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +- .../devicetree/bindings/display/mediatek/mediatek,dpi.txt | 2 +- .../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 4 ++-- .../devicetree/bindings/display/mediatek/mediatek,hdmi.txt | 4 ++++ 4 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt index b91e709db7a4..121220745d46 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt @@ -43,7 +43,7 @@ Required properties (all function blocks): "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt "mediatek,<chip>-disp-mutex" - display mutex "mediatek,<chip>-disp-od" - overdrive
- the supported chips are mt2701, mt2712 and mt8173.
- the supported chips are mt2701, mt7623, mt2712 and mt8173.
- reg: Physical base address and length of the function block register space
- interrupts: The interrupt signal from the function block (required, except for merge and split function blocks).
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt index 77def4456706..dc1ebd13cc88 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt @@ -7,7 +7,7 @@ output bus.
Required properties:
- compatible: "mediatek,<chip>-dpi"
- the supported chips are mt2701 , mt8173 and mt8183.
- the supported chips are mt2701, mt7623, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clocks
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt index 8e4729de8c85..f06f24d405a5 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt @@ -7,7 +7,7 @@ channel output.
Required properties:
- compatible: "mediatek,<chip>-dsi"
- the supported chips are mt2701, mt8173 and mt8183.
+- the supported chips are mt2701, mt7623, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clocks
@@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY.
Required properties:
- compatible: "mediatek,<chip>-mipi-tx"
- the supported chips are mt2701, mt8173 and mt8183.
+- the supported chips are mt2701, 7623, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- clocks: PLL reference clock
- clock-output-names: name of the output clock line to the DSI encoder
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt index 7b124242b0c5..6b1c586403e4 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt @@ -6,6 +6,7 @@ its parallel input.
Required properties:
- compatible: Should be "mediatek,<chip>-hdmi".
+- the supported chips are mt2701, mt7623 and mt8173
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clocks
@@ -32,6 +33,7 @@ The HDMI CEC controller handles hotplug detection and CEC communication.
Required properties:
- compatible: Should be "mediatek,<chip>-cec"
+- the supported chips are mt7623 and mt8173
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clock
@@ -44,6 +46,7 @@ The Mediatek's I2C controller is used to interface with I2C devices.
Required properties:
- compatible: Should be "mediatek,<chip>-hdmi-ddc"
+- the supported chips are mt7623 and mt8173
- reg: Physical base address and length of the controller's registers
- clocks: device clock
- clock-names: Should be "ddc-i2c".
@@ -56,6 +59,7 @@ output and drives the HDMI pads.
Required properties:
- compatible: "mediatek,<chip>-hdmi-phy"
+- the supported chips are mt2701, mt7623 and mt8173
- reg: Physical base address and length of the module's registers
- clocks: PLL reference clock
- clock-names: must contain "pll_ref"
-- 2.25.1
Frank Wunderlich linux@fw-web.de 於 2020年8月5日 週三 上午12:56寫道：
From: Frank Wunderlich frank-w@public-files.de
mt7623 uses mt2701/mt8173 for drm, but have own compatibles
Reviewed-by: Chun-Kuang Hu chunkuang.hu@kernel.org
Signed-off-by: Frank Wunderlich frank-w@public-files.de
.../devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +- .../devicetree/bindings/display/mediatek/mediatek,dpi.txt | 2 +- .../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 4 ++-- .../devicetree/bindings/display/mediatek/mediatek,hdmi.txt | 4 ++++ 4 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt index b91e709db7a4..121220745d46 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt @@ -43,7 +43,7 @@ Required properties (all function blocks): "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt "mediatek,<chip>-disp-mutex" - display mutex "mediatek,<chip>-disp-od" - overdrive
- the supported chips are mt2701, mt2712 and mt8173.
- the supported chips are mt2701, mt7623, mt2712 and mt8173.
- reg: Physical base address and length of the function block register space
- interrupts: The interrupt signal from the function block (required, except for merge and split function blocks).
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt index 77def4456706..dc1ebd13cc88 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt @@ -7,7 +7,7 @@ output bus.
Required properties:
- compatible: "mediatek,<chip>-dpi"
- the supported chips are mt2701 , mt8173 and mt8183.
- the supported chips are mt2701, mt7623, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clocks
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt index 8e4729de8c85..f06f24d405a5 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt @@ -7,7 +7,7 @@ channel output.
Required properties:
- compatible: "mediatek,<chip>-dsi"
- the supported chips are mt2701, mt8173 and mt8183.
+- the supported chips are mt2701, mt7623, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clocks
@@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY.
Required properties:
- compatible: "mediatek,<chip>-mipi-tx"
- the supported chips are mt2701, mt8173 and mt8183.
+- the supported chips are mt2701, 7623, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- clocks: PLL reference clock
- clock-output-names: name of the output clock line to the DSI encoder
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt index 7b124242b0c5..6b1c586403e4 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt @@ -6,6 +6,7 @@ its parallel input.
Required properties:
- compatible: Should be "mediatek,<chip>-hdmi".
+- the supported chips are mt2701, mt7623 and mt8173
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clocks
@@ -32,6 +33,7 @@ The HDMI CEC controller handles hotplug detection and CEC communication.
Required properties:
- compatible: Should be "mediatek,<chip>-cec"
+- the supported chips are mt7623 and mt8173
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clock
@@ -44,6 +46,7 @@ The Mediatek's I2C controller is used to interface with I2C devices.
Required properties:
- compatible: Should be "mediatek,<chip>-hdmi-ddc"
+- the supported chips are mt7623 and mt8173
- reg: Physical base address and length of the controller's registers
- clocks: device clock
- clock-names: Should be "ddc-i2c".
@@ -56,6 +59,7 @@ output and drives the HDMI pads.
Required properties:
- compatible: "mediatek,<chip>-hdmi-phy"
+- the supported chips are mt2701, mt7623 and mt8173
- reg: Physical base address and length of the module's registers
- clocks: PLL reference clock
- clock-names: must contain "pll_ref"
-- 2.25.1
From: Landen Chao landen.chao@mediatek.com
in recent kernel versions there are warnings about incorrect MTU size like these:
eth0: mtu greater than device maximum mtk_soc_eth 1b100000.ethernet eth0: error -22 setting MTU to include DSA overhead
Fixes: bfcb813203e6 ("net: dsa: configure the MTU for switch ports") Fixes: 72579e14a1d3 ("net: dsa: don't fail to probe if we couldn't set the MTU") Fixes: 7a4c53bee332 ("net: report invalid mtu value via netlink extack") Signed-off-by: Landen Chao landen.chao@mediatek.com Signed-off-by: Frank Wunderlich frank-w@public-files.de Reviewed-by: Andrew Lunn andrew@lunn.ch --- v3->v4 - fix commit-message (hyphernations,capitalisation) as suggested by Russell - add Signed-off-by Landen - dropped wrong signed-off from rene (because previous v1/2 was from him) --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index 85735d32ecb0..a1c45b39a230 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -2891,6 +2891,8 @@ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) eth->netdev[id]->irq = eth->irq[0]; eth->netdev[id]->dev.of_node = np;
+ eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; + return 0;
free_netdev:
sorry, send this accidentally while posting my hdmi series v4 (have not deleted patch-file) just ignore this...it's already merged
regards Frank
From: Frank Wunderlich frank-w@public-files.de
on BPi-R2/mt7623 main-path have to be routed to DPI0 (hdmi) instead of DSI0 using compatible "mt7623-mmsys" already defined in dts
Signed-off-by: Frank Wunderlich frank-w@public-files.de --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 6bd369434d9d..11e3752c670d 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -74,6 +74,19 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = { DDP_COMPONENT_DPI0, };
+static const enum mtk_ddp_comp_id mt7623_mtk_ddp_main[] = { + DDP_COMPONENT_OVL0, + DDP_COMPONENT_RDMA0, + DDP_COMPONENT_COLOR0, + DDP_COMPONENT_BLS, + DDP_COMPONENT_DPI0, +}; + +static const enum mtk_ddp_comp_id mt7623_mtk_ddp_ext[] = { + DDP_COMPONENT_RDMA1, + DDP_COMPONENT_DSI0, +}; + static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = { DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0, @@ -127,6 +140,14 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .shadow_register = true, };
+static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = { + .main_path = mt7623_mtk_ddp_main, + .main_len = ARRAY_SIZE(mt7623_mtk_ddp_main), + .ext_path = mt7623_mtk_ddp_ext, + .ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext), + .shadow_register = true, +}; + static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { .main_path = mt2712_mtk_ddp_main, .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main), @@ -422,6 +443,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { static const struct of_device_id mtk_drm_of_ids[] = { { .compatible = "mediatek,mt2701-mmsys", .data = &mt2701_mmsys_driver_data}, + { .compatible = "mediatek,mt7623-mmsys", + .data = &mt7623_mmsys_driver_data}, { .compatible = "mediatek,mt2712-mmsys", .data = &mt2712_mmsys_driver_data}, { .compatible = "mediatek,mt8173-mmsys",
Hi, Frank:
Frank Wunderlich linux@fw-web.de 於 2020年8月5日 週三 上午12:56寫道：
From: Frank Wunderlich frank-w@public-files.de
on BPi-R2/mt7623 main-path have to be routed to DPI0 (hdmi) instead of DSI0 using compatible "mt7623-mmsys" already defined in dts
Reviewed-by: Chun-Kuang Hu chunkuang.hu@kernel.org
Signed-off-by: Frank Wunderlich frank-w@public-files.de
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 6bd369434d9d..11e3752c670d 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -74,6 +74,19 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = { DDP_COMPONENT_DPI0, };
+static const enum mtk_ddp_comp_id mt7623_mtk_ddp_main[] = {
DDP_COMPONENT_OVL0,DDP_COMPONENT_RDMA0,DDP_COMPONENT_COLOR0,DDP_COMPONENT_BLS,DDP_COMPONENT_DPI0,+};
+static const enum mtk_ddp_comp_id mt7623_mtk_ddp_ext[] = {
DDP_COMPONENT_RDMA1,DDP_COMPONENT_DSI0,+};
static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = { DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0, @@ -127,6 +140,14 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .shadow_register = true, };
+static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
.main_path = mt7623_mtk_ddp_main,.main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),.ext_path = mt7623_mtk_ddp_ext,.ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),.shadow_register = true,+};
static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { .main_path = mt2712_mtk_ddp_main, .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main), @@ -422,6 +443,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { static const struct of_device_id mtk_drm_of_ids[] = { { .compatible = "mediatek,mt2701-mmsys", .data = &mt2701_mmsys_driver_data},
{ .compatible = "mediatek,mt7623-mmsys",.data = &mt7623_mmsys_driver_data}, { .compatible = "mediatek,mt2712-mmsys", .data = &mt2712_mmsys_driver_data}, { .compatible = "mediatek,mt8173-mmsys",-- 2.25.1
From: chunhui dai chunhui.dai@mediatek.com
disable tmds on phy on mt2701 to support other resolutions like 1280x1024
Signed-off-by: chunhui dai chunhui.dai@mediatek.com Signed-off-by: Frank Wunderlich frank-w@public-files.de Tested-by: Frank Wunderlich frank-w@public-files.de --- drivers/gpu/drm/mediatek/mtk_hdmi_phy.c | 3 +++ drivers/gpu/drm/mediatek/mtk_hdmi_phy.h | 1 + drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 1 + 3 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c index 5223498502c4..edadb7a700f1 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c @@ -184,6 +184,9 @@ static int mtk_hdmi_phy_probe(struct platform_device *pdev) return PTR_ERR(phy_provider); }
+ if (hdmi_phy->conf->pll_default_off) + hdmi_phy->conf->hdmi_phy_disable_tmds(hdmi_phy); + return of_clk_add_provider(dev->of_node, of_clk_src_simple_get, hdmi_phy->pll); } diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h index 2d8b3182470d..f472fdeb63dc 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h @@ -22,6 +22,7 @@ struct mtk_hdmi_phy; struct mtk_hdmi_phy_conf { bool tz_disabled; unsigned long flags; + bool pll_default_off; const struct clk_ops *hdmi_phy_clk_ops; void (*hdmi_phy_enable_tmds)(struct mtk_hdmi_phy *hdmi_phy); void (*hdmi_phy_disable_tmds)(struct mtk_hdmi_phy *hdmi_phy); diff --git a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c index d3cc4022e988..6fbedacfc1e8 100644 --- a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c +++ b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c @@ -239,6 +239,7 @@ static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy) struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf = { .tz_disabled = true, .flags = CLK_SET_RATE_GATE, + .pll_default_off = true, .hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops, .hdmi_phy_enable_tmds = mtk_hdmi_phy_enable_tmds, .hdmi_phy_disable_tmds = mtk_hdmi_phy_disable_tmds,
From: Stu Hsieh stu.hsieh@mediatek.com
For current mediatek dsi encoder, its possible crtc is fixed in crtc 0, and mediatek dpi encoder's possible crtc is fixed in crtc 1. In some SoC the possible crtc is not fixed in this case, so search pipeline information to find out the correct possible crtc.
Signed-off-by: Stu Hsieh stu.hsieh@mediatek.com Signed-off-by: Frank Wunderlich frank-w@public-files.de Reviewed-by: Chun-Kuang Hu chunkuang.hu@kernel.org --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 42 +++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 + 2 files changed, 44 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 57c88de9a329..a5f2ff6bea93 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -13,6 +13,8 @@ #include <linux/of_platform.h> #include <linux/platform_device.h> #include <linux/soc/mediatek/mtk-cmdq.h> +#include <drm/drm_print.h> + #include "mtk_drm_drv.h" #include "mtk_drm_plane.h" #include "mtk_drm_ddp_comp.h" @@ -412,6 +414,22 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, };
+static bool mtk_drm_find_comp_in_ddp(struct mtk_ddp_comp ddp_comp, + const enum mtk_ddp_comp_id *path, + unsigned int path_len) +{ + unsigned int i; + + if (path == NULL) + return false; + + for (i = 0U; i < path_len; i++) + if (ddp_comp.id == path[i]) + return true; + + return false; +} + int mtk_ddp_comp_get_id(struct device_node *node, enum mtk_ddp_comp_type comp_type) { @@ -427,6 +445,30 @@ int mtk_ddp_comp_get_id(struct device_node *node, return -EINVAL; }
+unsigned int mtk_drm_find_possible_crtc_by_comp(struct drm_device *drm, + struct mtk_ddp_comp ddp_comp) +{ + struct mtk_drm_private *private = drm->dev_private; + unsigned int ret; + + if (mtk_drm_find_comp_in_ddp(ddp_comp, private->data->main_path, + private->data->main_len) == true) { + ret = BIT(0); + } else if (mtk_drm_find_comp_in_ddp(ddp_comp, + private->data->ext_path, + private->data->ext_len) == true) { + ret = BIT(1); + } else if (mtk_drm_find_comp_in_ddp(ddp_comp, + private->data->third_path, + private->data->third_len) == true) { + ret = BIT(2); + } else { + DRM_INFO("Failed to find comp in ddp table\n"); + ret = 0; + } + return ret; +} + int mtk_ddp_comp_init(struct device *dev, struct device_node *node, struct mtk_ddp_comp *comp, enum mtk_ddp_comp_id comp_id, const struct mtk_ddp_comp_funcs *funcs) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index debe36395fe7..1d9e00b69462 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -202,6 +202,8 @@ static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp,
int mtk_ddp_comp_get_id(struct device_node *node, enum mtk_ddp_comp_type comp_type); +unsigned int mtk_drm_find_possible_crtc_by_comp(struct drm_device *drm, + struct mtk_ddp_comp ddp_comp); int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node, struct mtk_ddp_comp *comp, enum mtk_ddp_comp_id comp_id, const struct mtk_ddp_comp_funcs *funcs);
From: Jitao Shi jitao.shi@mediatek.com
For current mediatek dsi encoder, its possible crtc is fixed in crtc 0, and mediatek dpi encoder's possible crtc is fixed in crtc 1. In some SoC the possible crtc is not fixed in this case, so call mtk_drm_find_possible_crtc_by_comp() to find out the correct possible crtc.
Signed-off-by: Jitao Shi jitao.shi@mediatek.com Signed-off-by: Frank Wunderlich frank-w@public-files.de Reviewed-by: Chun-Kuang Hu chunkuang.hu@kernel.org --- drivers/gpu/drm/mediatek/mtk_dpi.c | 3 ++- drivers/gpu/drm/mediatek/mtk_dsi.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index d4f0fb7ad312..e43977015843 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -608,7 +608,8 @@ static int mtk_dpi_bind(struct device *dev, struct device *master, void *data) drm_encoder_helper_add(&dpi->encoder, &mtk_dpi_encoder_helper_funcs);
/* Currently DPI0 is fixed to be driven by OVL1 */ - dpi->encoder.possible_crtcs = BIT(1); + dpi->encoder.possible_crtcs = + mtk_drm_find_possible_crtc_by_comp(drm_dev, dpi->ddp_comp);
ret = drm_bridge_attach(&dpi->encoder, dpi->bridge, NULL, 0); if (ret) { diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 270bf22c98fe..c31d9c12d4a9 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -892,7 +892,8 @@ static int mtk_dsi_create_conn_enc(struct drm_device *drm, struct mtk_dsi *dsi) * Currently display data paths are statically assigned to a crtc each. * crtc 0 is OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 */ - dsi->encoder.possible_crtcs = 1; + dsi->encoder.possible_crtcs = + mtk_drm_find_possible_crtc_by_comp(drm, dsi->ddp_comp);
/* If there's a bridge, attach to it and let it create the connector */ if (dsi->bridge) {
From: Ryder Lee ryder.lee@mediatek.com
Add display subsystem related device nodes for MT7623.
Cc: CK Hu ck.hu@mediatek.com Signed-off-by: chunhui dai chunhui.dai@mediatek.com Signed-off-by: Bibby Hsieh bibby.hsieh@mediatek.com Signed-off-by: Ryder Lee ryder.lee@mediatek.com Signed-off-by: Frank Wunderlich frank-w@public-files.de Tested-by: Frank Wunderlich frank-w@public-files.de --- changed v3->v4: drop display_components which is duplicate of existing mmsys v2->v3: drop bls to dpi routing --- arch/arm/boot/dts/mt7623.dtsi | 170 ++++++++++++++++++ arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts | 72 ++++++++ arch/arm/boot/dts/mt7623n-rfb-emmc.dts | 72 ++++++++ 3 files changed, 314 insertions(+)
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index a106c0d90a52..f2cb44a69454 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -24,6 +24,11 @@ / { #address-cells = <2>; #size-cells = <2>;
+ aliases { + rdma0 = &rdma0; + rdma1 = &rdma1; + }; + cpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-shared; @@ -321,6 +326,25 @@ pwrap: pwrap@1000d000 { clock-names = "spi", "wrap"; };
+ mipi_tx0: mipi-dphy@10010000 { + compatible = "mediatek,mt7623-mipi-tx", + "mediatek,mt2701-mipi-tx"; + reg = <0 0x10010000 0 0x90>; + clocks = <&clk26m>; + clock-output-names = "mipi_tx0_pll"; + #clock-cells = <0>; + #phy-cells = <0>; + }; + + cec: cec@10012000 { + compatible = "mediatek,mt7623-cec", + "mediatek,mt8173-cec"; + reg = <0 0x10012000 0 0xbc>; + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_CEC>; + status = "disabled"; + }; + cir: cir@10013000 { compatible = "mediatek,mt7623-cir"; reg = <0 0x10013000 0 0x1000>; @@ -369,6 +393,18 @@ apmixedsys: syscon@10209000 { #clock-cells = <1>; };
+ hdmi_phy: phy@10209100 { + compatible = "mediatek,mt7623-hdmi-phy", + "mediatek,mt2701-hdmi-phy"; + reg = <0 0x10209100 0 0x24>; + clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; + clock-names = "pll_ref"; + clock-output-names = "hdmitx_dig_cts"; + #clock-cells = <0>; + #phy-cells = <0>; + status = "disabled"; + }; + rng: rng@1020f000 { compatible = "mediatek,mt7623-rng"; reg = <0 0x1020f000 0 0x1000>; @@ -568,6 +604,16 @@ bch: ecc@1100e000 { status = "disabled"; };
+ hdmiddc0: i2c@11013000 { + compatible = "mediatek,mt7623-hdmi-ddc", + "mediatek,mt8173-hdmi-ddc"; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; + reg = <0 0x11013000 0 0x1C>; + clocks = <&pericfg CLK_PERI_I2C3>; + clock-names = "ddc-i2c"; + status = "disabled"; + }; + nor_flash: spi@11014000 { compatible = "mediatek,mt7623-nor", "mediatek,mt8173-nor"; @@ -766,6 +812,77 @@ mmsys: syscon@14000000 { #clock-cells = <1>; };
+ ovl@14007000 { + compatible = "mediatek,mt7623-disp-ovl", + "mediatek,mt2701-disp-ovl"; + reg = <0 0x14007000 0 0x1000>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_DISP_OVL>; + iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>; + mediatek,larb = <&larb0>; + }; + + rdma0: rdma@14008000 { + compatible = "mediatek,mt7623-disp-rdma", + "mediatek,mt2701-disp-rdma"; + reg = <0 0x14008000 0 0x1000>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_DISP_RDMA>; + iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>; + mediatek,larb = <&larb0>; + }; + + wdma@14009000 { + compatible = "mediatek,mt7623-disp-wdma", + "mediatek,mt2701-disp-wdma"; + reg = <0 0x14009000 0 0x1000>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_DISP_WDMA>; + iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>; + mediatek,larb = <&larb0>; + }; + + bls: pwm@1400a000 { + compatible = "mediatek,mt7623-disp-pwm", + "mediatek,mt2701-disp-pwm"; + reg = <0 0x1400a000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&mmsys CLK_MM_MDP_BLS_26M>, + <&mmsys CLK_MM_DISP_BLS>; + clock-names = "main", "mm"; + status = "disabled"; + }; + + color@1400b000 { + compatible = "mediatek,mt7623-disp-color", + "mediatek,mt2701-disp-color"; + reg = <0 0x1400b000 0 0x1000>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_DISP_COLOR>; + }; + + dsi: dsi@1400c000 { + compatible = "mediatek,mt7623-dsi", + "mediatek,mt2701-dsi"; + reg = <0 0x1400c000 0 0x1000>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_DSI_ENGINE>, + <&mmsys CLK_MM_DSI_DIG>, + <&mipi_tx0>; + clock-names = "engine", "digital", "hs"; + phys = <&mipi_tx0>; + phy-names = "dphy"; + status = "disabled"; + }; + + mutex: mutex@1400e000 { + compatible = "mediatek,mt7623-disp-mutex", + "mediatek,mt2701-disp-mutex"; + reg = <0 0x1400e000 0 0x1000>; + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_MUTEX_32K>; + }; + larb0: larb@14010000 { compatible = "mediatek,mt7623-smi-larb", "mediatek,mt2701-smi-larb"; @@ -778,6 +895,44 @@ larb0: larb@14010000 { power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; };
+ rdma1: rdma@14012000 { + compatible = "mediatek,mt7623-disp-rdma", + "mediatek,mt2701-disp-rdma"; + reg = <0 0x14012000 0 0x1000>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>; + mediatek,larb = <&larb0>; + }; + + dpi0: dpi@14014000 { + compatible = "mediatek,mt7623-dpi", + "mediatek,mt2701-dpi"; + reg = <0 0x14014000 0 0x1000>; + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_DPI1_DIGL>, + <&mmsys CLK_MM_DPI1_ENGINE>, + <&apmixedsys CLK_APMIXED_TVDPLL>; + clock-names = "pixel", "engine", "pll"; + status = "disabled"; + }; + + hdmi0: hdmi@14015000 { + compatible = "mediatek,mt7623-hdmi", + "mediatek,mt8173-hdmi"; + reg = <0 0x14015000 0 0x400>; + clocks = <&mmsys CLK_MM_HDMI_PIXEL>, + <&mmsys CLK_MM_HDMI_PLL>, + <&mmsys CLK_MM_HDMI_AUDIO>, + <&mmsys CLK_MM_HDMI_SPDIF>; + clock-names = "pixel", "pll", "bclk", "spdif"; + phys = <&hdmi_phy>; + phy-names = "hdmi"; + mediatek,syscon-hdmi = <&mmsys 0x900>; + cec = <&cec>; + status = "disabled"; + }; + imgsys: syscon@15000000 { compatible = "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", @@ -1102,6 +1257,21 @@ pins-cir { }; };
+ hdmi_pins_a: hdmi-default { + pins-hdmi { + pinmux = <MT7623_PIN_123_HTPLG_FUNC_HTPLG>; + input-enable; + bias-pull-down; + }; + }; + + hdmi_ddc_pins_a: hdmi_ddc-default { + pins-hdmi-ddc { + pinmux = <MT7623_PIN_124_GPIO124_FUNC_HDMISCK>, + <MT7623_PIN_125_GPIO125_FUNC_HDMISD>; + }; + }; + i2c0_pins_a: i2c0-default { pins-i2c0 { pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>, diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts index 2b760f90f38c..b1c83e919015 100644 --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts @@ -21,6 +21,19 @@ chosen { stdout-path = "serial2:115200n8"; };
+ connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "d"; + ddc-i2c-bus = <&hdmiddc0>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi0_out>; + }; + }; + }; + cpus { cpu@0 { proc-supply = <&mt6323_vproc_reg>; @@ -114,10 +127,18 @@ memory@80000000 { }; };
+&bls { + status = "okay"; +}; + &btif { status = "okay"; };
+&cec { + status = "okay"; +}; + &cir { pinctrl-names = "default"; pinctrl-0 = <&cir_pins_a>; @@ -128,6 +149,21 @@ &crypto { status = "okay"; };
+&dpi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dpi0_out: endpoint { + remote-endpoint = <&hdmi0_in>; + }; + }; + }; +}; + ð { status = "okay";
@@ -199,6 +235,42 @@ fixed-link { }; };
+&hdmi0 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins_a>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + hdmi0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + + port@1 { + reg = <1>; + hdmi0_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; +}; + +&hdmiddc0 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_ddc_pins_a>; + status = "okay"; +}; + +&hdmi_phy { + mediatek,ibias = <0xa>; + mediatek,ibias_up = <0x1c>; + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; diff --git a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts index 0447748f9fa0..7e3ded7d9e7d 100644 --- a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts +++ b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts @@ -24,6 +24,19 @@ chosen { stdout-path = "serial2:115200n8"; };
+ connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "d"; + ddc-i2c-bus = <&hdmiddc0>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi0_out>; + }; + }; + }; + cpus { cpu@0 { proc-supply = <&mt6323_vproc_reg>; @@ -106,10 +119,18 @@ sound { }; };
+&bls { + status = "okay"; +}; + &btif { status = "okay"; };
+&cec { + status = "okay"; +}; + &cir { pinctrl-names = "default"; pinctrl-0 = <&cir_pins_a>; @@ -120,6 +141,21 @@ &crypto { status = "okay"; };
+&dpi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dpi0_out: endpoint { + remote-endpoint = <&hdmi0_in>; + }; + }; + }; +}; + ð { status = "okay";
@@ -203,6 +239,42 @@ fixed-link { }; };
+&hdmi0 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins_a>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + hdmi0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + + port@1 { + reg = <1>; + hdmi0_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; +}; + +&hdmiddc0 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_ddc_pins_a>; + status = "okay"; +}; + +&hdmi_phy { + mediatek,ibias = <0xa>; + mediatek,ibias_up = <0x1c>; + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>;
On Tue, 2020-08-04 at 18:55 +0200, Frank Wunderlich wrote:
From: Ryder Lee ryder.lee@mediatek.com
Add display subsystem related device nodes for MT7623.
Cc: CK Hu ck.hu@mediatek.com Signed-off-by: chunhui dai chunhui.dai@mediatek.com Signed-off-by: Bibby Hsieh bibby.hsieh@mediatek.com Signed-off-by: Ryder Lee ryder.lee@mediatek.com Signed-off-by: Frank Wunderlich frank-w@public-files.de Tested-by: Frank Wunderlich frank-w@public-files.de
changed v3->v4: drop display_components which is duplicate of existing mmsys v2->v3: drop bls to dpi routing
arch/arm/boot/dts/mt7623.dtsi | 170 ++++++++++++++++++ arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts | 72 ++++++++ arch/arm/boot/dts/mt7623n-rfb-emmc.dts | 72 ++++++++ 3 files changed, 314 insertions(+)
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index a106c0d90a52..f2cb44a69454 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -24,6 +24,11 @@ / { #address-cells = <2>; #size-cells = <2>;
- aliases {
rdma0 = &rdma0;rdma1 = &rdma1;- };
- cpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-shared;
@@ -321,6 +326,25 @@ pwrap: pwrap@1000d000 { clock-names = "spi", "wrap"; };
- mipi_tx0: mipi-dphy@10010000 {
compatible = "mediatek,mt7623-mipi-tx","mediatek,mt2701-mipi-tx";reg = <0 0x10010000 0 0x90>;clocks = <&clk26m>;clock-output-names = "mipi_tx0_pll";#clock-cells = <0>;#phy-cells = <0>;- };
Doesn't this (and some others) also need status="disabled" since they're not present on MT7623A? Or maybe it's time to split mt7623.dtsi into a mt7623n.dtsi which includes mt7623a.dtsi and adds the extra components?
Gesendet: Dienstag, 04. August 2020 um 19:24 Uhr Von: "David Woodhouse" dwmw2@infradead.org
- mipi_tx0: mipi-dphy@10010000 {
compatible = "mediatek,mt7623-mipi-tx","mediatek,mt2701-mipi-tx";reg = <0 0x10010000 0 0x90>;clocks = <&clk26m>;clock-output-names = "mipi_tx0_pll";#clock-cells = <0>;#phy-cells = <0>;- };
Doesn't this (and some others) also need status="disabled" since they're not present on MT7623A? Or maybe it's time to split mt7623.dtsi into a mt7623n.dtsi which includes mt7623a.dtsi and adds the extra components?
do you have a MT7623A board for testing? is there any list which components are existing on mt7623a? or should i disable all of them and re-enable them in bpi-r2 dts?
regards Frank
On Tue, 2020-08-04 at 19:40 +0200, Frank Wunderlich wrote:
Gesendet: Dienstag, 04. August 2020 um 19:24 Uhr Von: "David Woodhouse" dwmw2@infradead.org
- mipi_tx0: mipi-dphy@10010000 {
compatible = "mediatek,mt7623-mipi-tx","mediatek,mt2701-mipi-tx";reg = <0 0x10010000 0 0x90>;clocks = <&clk26m>;clock-output-names = "mipi_tx0_pll";#clock-cells = <0>;#phy-cells = <0>;- };
Doesn't this (and some others) also need status="disabled" since they're not present on MT7623A? Or maybe it's time to split mt7623.dtsi into a mt7623n.dtsi which includes mt7623a.dtsi and adds the extra components?
do you have a MT7623A board for testing? is there any list which components are existing on mt7623a? or should i disable all of them and re-enable them in bpi-r2 dts?
The UniElec U7623 board (which is supported in OpenWrt) is MT7623A.
I was told that MT7623N has GPU and HDMI, while the MT7623A has a built-in mt7530 switch. Does that imply the switch on the MT7623N boards is *external*?
If so, that means that mt7623n.dtsi maybe shouldn't just include mt7623a.dtsi because it's not a strict superset; maybe they should both include a common mt7623.dtsi that has the parts that are truly common?
I also suspect the switch definition from the UniElec U7623 dts should probably move to this new mt7623a.dtsi? That's not upstream yet though.
CC Rob Herring + devicetree List + Sean
Gesendet: Dienstag, 04. August 2020 um 20:02 Uhr Von: "David Woodhouse" dwmw2@infradead.org On Tue, 2020-08-04 at 19:40 +0200, Frank Wunderlich wrote:
Gesendet: Dienstag, 04. August 2020 um 19:24 Uhr Von: "David Woodhouse" dwmw2@infradead.org
- mipi_tx0: mipi-dphy@10010000 {
compatible = "mediatek,mt7623-mipi-tx","mediatek,mt2701-mipi-tx";reg = <0 0x10010000 0 0x90>;clocks = <&clk26m>;clock-output-names = "mipi_tx0_pll";#clock-cells = <0>;#phy-cells = <0>;- };
Doesn't this (and some others) also need status="disabled" since they're not present on MT7623A? Or maybe it's time to split mt7623.dtsi into a mt7623n.dtsi which includes mt7623a.dtsi and adds the extra components?
any opinions about this? should i disable all new nodes and enable them in the dts for specific board (bpi-r2/mt7623n-rfb)?
have prepared it here [1]
do you have a MT7623A board for testing? is there any list which components are existing on mt7623a? or should i disable all of them and re-enable them in bpi-r2 dts?
The UniElec U7623 board (which is supported in OpenWrt) is MT7623A.
I was told that MT7623N has GPU and HDMI, while the MT7623A has a built-in mt7530 switch. Does that imply the switch on the MT7623N boards is *external*?
yes, bananapi r2 has external mt7530 switch connected to gmacs 0+1 with its ports 6+5
If so, that means that mt7623n.dtsi maybe shouldn't just include mt7623a.dtsi because it's not a strict superset; maybe they should both include a common mt7623.dtsi that has the parts that are truly common?
I also suspect the switch definition from the UniElec U7623 dts should probably move to this new mt7623a.dtsi? That's not upstream yet though.
or should we split dtsi to have a common part (mt7623.dtsi), and one for soc (mt7623n.dtsi/mt7623a.dtsi)?
mt7623.dtsi => mt7623n.dtsi => mt7623n-bananapi-bpi-r2.dts mt7623.dtsi => mt7623a.dtsi => mt7623a-unielec-u7623.dts (not existing yet, openwrt seems to use a board-specific dtsi)
regards Frank
[1] https://github.com/frank-w/BPI-R2-4.14/commits/5.8-hdmi4mainline
On Wed, 2020-08-05 at 09:27 +0200, Frank Wunderlich wrote:
or should we split dtsi to have a common part (mt7623.dtsi), and one for soc (mt7623n.dtsi/mt7623a.dtsi)?
mt7623.dtsi => mt7623n.dtsi => mt7623n-bananapi-bpi-r2.dts mt7623.dtsi => mt7623a.dtsi => mt7623a-unielec-u7623.dts (not existing yet, openwrt seems to use a board-specific dtsi)
Yes, I think we should.
I'll create mt7623a.dtsi and upstream the U7623 support; I think that can happen without conflicting with anything you do.
I note that the GPU node has been added to mt7623.dtsi in 5.8 too; that'll want to move to the new mt7623n.dtsi that you create, along with your other new additions.
Does that seem reasonable?
Gesendet: Mittwoch, 05. August 2020 um 10:36 Uhr Von: "David Woodhouse" dwmw2@infradead.org
mt7623.dtsi => mt7623n.dtsi => mt7623n-bananapi-bpi-r2.dts mt7623.dtsi => mt7623a.dtsi => mt7623a-unielec-u7623.dts (not existing yet, openwrt seems to use a board-specific dtsi)
Yes, I think we should.
i want to see what MTK/DT owner says to this... my current way will be still adding the nodes to existing mt7623.dtsi (like ryder lee did it in original patch) but disabling them to not break mt7623a and splitting it afterwards.
I'll create mt7623a.dtsi and upstream the U7623 support; I think that can happen without conflicting with anything you do.
I note that the GPU node has been added to mt7623.dtsi in 5.8 too; that'll want to move to the new mt7623n.dtsi that you create, along with your other new additions.
i guess mali-node also needs to be moved to mt7623n.dtsi, so my current way seems right... but it's decision of MTK/DT owner. if they make a note i squash the disabling-commit into this and post v5
regards Frank
On Wed, 2020-08-05 at 10:49 +0200, Frank Wunderlich wrote:
Gesendet: Mittwoch, 05. August 2020 um 10:36 Uhr Von: "David Woodhouse" dwmw2@infradead.org
mt7623.dtsi => mt7623n.dtsi => mt7623n-bananapi-bpi-r2.dts mt7623.dtsi => mt7623a.dtsi => mt7623a-unielec-u7623.dts (not existing yet, openwrt seems to use a board-specific dtsi)
Yes, I think we should.
i want to see what MTK/DT owner says to this... my current way will be still adding the nodes to existing mt7623.dtsi (like ryder lee did it in original patch) but disabling them to not break mt7623a and splitting it afterwards.
I'll create mt7623a.dtsi and upstream the U7623 support; I think that can happen without conflicting with anything you do.
I note that the GPU node has been added to mt7623.dtsi in 5.8 too; that'll want to move to the new mt7623n.dtsi that you create, along with your other new additions.
i guess mali-node also needs to be moved to mt7623n.dtsi, so my current way seems right... but it's decision of MTK/DT owner. if they make a note i squash the disabling-commit into this and post v5
Yes, the mali node needs moving too. I've pushed an untested series to http://git.infradead.org/users/dwmw2/linux.git/shortlog/refs/heads/mt7623 which does that and adds the UniElec board.
From: David Woodhouse dwmw@amazon.co.uk
This isn't needed in dtsi files.
Signed-off-by: David Woodhouse dwmw@amazon.co.uk --- arch/arm/boot/dts/mt7623a.dtsi | 1 - 1 file changed, 1 deletion(-)
diff --git a/arch/arm/boot/dts/mt7623a.dtsi b/arch/arm/boot/dts/mt7623a.dtsi index 0735a1fb8ad9..a96075206cce 100644 --- a/arch/arm/boot/dts/mt7623a.dtsi +++ b/arch/arm/boot/dts/mt7623a.dtsi @@ -5,7 +5,6 @@ * */
-/dts-v1/; #include <dt-bindings/power/mt7623a-power.h> #include "mt7623.dtsi"
From: David Woodhouse dwmw@amazon.co.uk
The MT7623A doesn't have a GPU; add it only for MT7623N boards.
Fixes: 1f6ed224594 ("arm: dts: mt7623: add Mali-450 device node") Signed-off-by: David Woodhouse dwmw@amazon.co.uk --- arch/arm/boot/dts/mt7623.dtsi | 24 ------------- arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts | 2 +- arch/arm/boot/dts/mt7623n-rfb-emmc.dts | 2 +- arch/arm/boot/dts/mt7623n.dtsi | 35 +++++++++++++++++++ 4 files changed, 37 insertions(+), 26 deletions(-) create mode 100644 arch/arm/boot/dts/mt7623n.dtsi
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index 3a6b856e5b74..dcd2f5ba4e20 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -734,30 +734,6 @@ g3dsys: syscon@13000000 { #reset-cells = <1>; };
- mali: gpu@13040000 { - compatible = "mediatek,mt7623-mali", "arm,mali-450"; - reg = <0 0x13040000 0 0x30000>; - interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 172 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 173 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 178 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 179 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", - "ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3", - "pp"; - clocks = <&topckgen CLK_TOP_MMPLL>, - <&g3dsys CLK_G3DSYS_CORE>; - clock-names = "bus", "core"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>; - resets = <&g3dsys MT2701_G3DSYS_CORE_RST>; - }; - mmsys: syscon@14000000 { compatible = "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts index 2b760f90f38c..344f8c65c4aa 100644 --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts @@ -6,7 +6,7 @@
/dts-v1/; #include <dt-bindings/input/input.h> -#include "mt7623.dtsi" +#include "mt7623n.dtsi" #include "mt6323.dtsi"
/ { diff --git a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts index 0447748f9fa0..f8efcc364bc3 100644 --- a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts +++ b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts @@ -7,7 +7,7 @@
/dts-v1/; #include <dt-bindings/input/input.h> -#include "mt7623.dtsi" +#include "mt7623n.dtsi" #include "mt6323.dtsi"
/ { diff --git a/arch/arm/boot/dts/mt7623n.dtsi b/arch/arm/boot/dts/mt7623n.dtsi new file mode 100644 index 000000000000..7724a4d05b89 --- /dev/null +++ b/arch/arm/boot/dts/mt7623n.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright © 2017-2020 MediaTek Inc. + * Author: Sean Wang sean.wang@mediatek.com + * Ryder Lee ryder.lee@mediatek.com + * + */ + +#include "mt7623.dtsi" + +/ { + mali: gpu@13040000 { + compatible = "mediatek,mt7623-mali", "arm,mali-450"; + reg = <0 0x13040000 0 0x30000>; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 172 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 173 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 178 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 179 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", + "ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3", + "pp"; + clocks = <&topckgen CLK_TOP_MMPLL>, + <&g3dsys CLK_G3DSYS_CORE>; + clock-names = "bus", "core"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>; + resets = <&g3dsys MT2701_G3DSYS_CORE_RST>; + }; +};
Hi David
Gesendet: Mittwoch, 05. August 2020 um 13:30 Uhr Von: "David Woodhouse" dwmw2@infradead.org From: David Woodhouse dwmw@amazon.co.uk
The MT7623A doesn't have a GPU; add it only for MT7623N boards.
Fixes: 1f6ed224594 ("arm: dts: mt7623: add Mali-450 device node") Signed-off-by: David Woodhouse dwmw@amazon.co.uk
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index 3a6b856e5b74..dcd2f5ba4e20 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -734,30 +734,6 @@ g3dsys: syscon@13000000 { #reset-cells = <1>; };
- mali: gpu@13040000 {
compatible = "mediatek,mt7623-mali", "arm,mali-450";
...
clocks = <&topckgen CLK_TOP_MMPLL>,<&g3dsys CLK_G3DSYS_CORE>;clock-names = "bus", "core";power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>;resets = <&g3dsys MT2701_G3DSYS_CORE_RST>;- };
i guess you should to move g3dsys too, and maybe the mmsys which is also drm-related?
I can add this to my series, but before i change my series, i need advice from MTK/DT owners whats the preferred way ;)
regards Frank
From: David Woodhouse dwmw@amazon.co.uk
Based on a patch in OpenWrt from Kristian Evensen kristian.evensen@gmail.com
Signed-off-by: David Woodhouse dwmw@amazon.co.uk --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/mt7623a-unielec-u7623-emmc.dts | 347 ++++++++++++++++++ 2 files changed, 348 insertions(+) create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623-emmc.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4572db3fa5ae..52f3954b600c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1347,6 +1347,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt6580-evbp1.dtb \ mt6589-aquaris5.dtb \ mt6592-evb.dtb \ + mt7623a-unielec-u7623-emmc.dtb \ mt7623a-rfb-emmc.dtb \ mt7623a-rfb-nand.dtb \ mt7623n-rfb-emmc.dtb \ diff --git a/arch/arm/boot/dts/mt7623a-unielec-u7623-emmc.dts b/arch/arm/boot/dts/mt7623a-unielec-u7623-emmc.dts new file mode 100644 index 000000000000..6205a32159ce --- /dev/null +++ b/arch/arm/boot/dts/mt7623a-unielec-u7623-emmc.dts @@ -0,0 +1,347 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright © 2018 Kristian Evensen kristian.evensen@gmail.com + */ + +/dts-v1/; +#include <dt-bindings/input/input.h> +#include "mt7623a.dtsi" +#include "mt6323.dtsi" + +/ { + model = "UniElec U7623 eMMC"; + compatible = "unielec,u7623-emmc", "mediatek,mt7623"; + + memory@80000000 { + device_type = "memory"; + reg = <0 0x80000000 0 0x20000000>; + }; + + aliases { + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + cpus { + cpu@0 { + proc-supply = <&mt6323_vproc_reg>; + }; + + cpu@1 { + proc-supply = <&mt6323_vproc_reg>; + }; + + cpu@2 { + proc-supply = <&mt6323_vproc_reg>; + }; + + cpu@3 { + proc-supply = <&mt6323_vproc_reg>; + }; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key_pins_a>; + + factory { + label = "factory"; + linux,code = <KEY_RESTART>; + gpios = <&pio 256 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_unielec>; + + led3 { + label = "u7623-01:green:led3"; + gpios = <&pio 14 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led4 { + label = "u7623-01:green:led4"; + gpios = <&pio 15 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; +}; + +&crypto { + status = "okay"; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "trgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + mt7530: switch@0 { + compatible = "mediatek,mt7530"; + }; + }; +}; + +&mt7530 { + compatible = "mediatek,mt7530"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + pinctrl-names = "default"; + mediatek,mcm; + resets = <ðsys 2>; + reset-names = "mcm"; + core-supply = <&mt6323_vpa_reg>; + io-supply = <&mt6323_vemc3v3_reg>; + + dsa,mii-bus = <&mdio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + port@0 { + reg = <0>; + label = "lan0"; + cpu = <&cpu_port0>; + }; + + port@1 { + reg = <1>; + label = "lan1"; + cpu = <&cpu_port0>; + }; + + port@2 { + reg = <2>; + label = "lan2"; + cpu = <&cpu_port0>; + }; + + port@3 { + reg = <3>; + label = "lan3"; + cpu = <&cpu_port0>; + }; + + port@4 { + reg = <4>; + label = "wan"; + cpu = <&cpu_port0>; + }; + + cpu_port0: port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "trgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + status = "okay"; + bus-width = <8>; + max-frequency = <50000000>; + cap-mmc-highspeed; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; +}; + +&pio { + key_pins_a: keys-alt { + pins-keys { + pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>, + <MT7623_PIN_257_GPIO257_FUNC_GPIO257>; + input-enable; + }; + }; + + led_pins_unielec: leds-unielec { + pins-leds { + pinmux = <MT7623_PIN_14_GPIO14_FUNC_GPIO14>, + <MT7623_PIN_15_GPIO15_FUNC_GPIO15>; + }; + }; + + mmc0_pins_default: mmc0default { + pins_cmd_dat { + pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>, + <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>, + <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>, + <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>, + <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>, + <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>, + <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>, + <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>, + <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>; + input-enable; + bias-pull-up; + }; + + pins_clk { + pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>; + bias-pull-down; + }; + + pins_rst { + pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>; + bias-pull-up; + }; + }; + + mmc0_pins_uhs: mmc0 { + pins_cmd_dat { + pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>, + <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>, + <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>, + <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>, + <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>, + <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>, + <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>, + <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>, + <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>; + input-enable; + drive-strength = <MTK_DRIVE_2mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins_clk { + pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>; + drive-strength = <MTK_DRIVE_2mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_01>; + }; + + pins_rst { + pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>; + bias-pull-up; + }; + }; + + pcie_default: pcie_pin_default { + pins_cmd_dat { + pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>, + <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>; + bias-disable; + }; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins_a>; + status = "okay"; +}; + +&pwrap { + mt6323 { + mt6323led: led { + compatible = "mediatek,mt6323-led"; + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "led0"; + default-state = "off"; + }; + }; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins_b>; + status = "okay"; +}; + +&usb1 { + vusb33-supply = <®_3p3v>; + vbus-supply = <®_3p3v>; + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&u3phy2 { + status = "okay"; + mediatek,phy-switch = <&hifsys>; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_default>; + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + + pcie@2,0 { + status = "okay"; + }; +}; + +&pcie1_phy { + status = "okay"; +};
dri-devel@lists.freedesktop.org
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Chun-Kuang Hu -
David Woodhouse -
Frank Wunderlich -
Frank Wunderlich -
Rob Herring