Screen flickers on Innolux panel when clock rate 540000 is in use.

According to the panel vendor, though clock rate 540000 is advertised, but the max clock rate it really supports is 270000.

So use slow and wide training for panels with DPCP rev < 1.4 to resolve the issue. User also confirmed the new strategy doesn't introduce regression on XPS 9380.

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/3384 References: https://gitlab.freedesktop.org/drm/intel/-/issues/272 Signed-off-by: Kai-Heng Feng kai.heng.feng@canonical.com --- drivers/gpu/drm/i915/display/intel_dp.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 775d89b6c3fc..ca73e2179659 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1461,12 +1461,12 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, intel_dp_can_bigjoiner(intel_dp)) pipe_config->bigjoiner = true;

- if (intel_dp_is_edp(intel_dp)) + if (intel_dp_is_edp(intel_dp) && intel_dp->dpcd[DP_DPCD_REV] > 0x13) /* - * Optimize for fast and narrow. eDP 1.3 section 3.3 and eDP 1.4 - * section A.1: "It is recommended that the minimum number of - * lanes be used, using the minimum link rate allowed for that - * lane configuration." + * Optimize for fast and narrow on DP 1.4. eDP 1.3 section 3.3 + * and eDP 1.4 section A.1: "It is recommended that the minimum + * number of lanes be used, using the minimum link rate allowed + * for that lane configuration." * * Note that we fall back to the max clock and lane count for eDP * panels that fail with the fast optimal settings (see