This is MT8173 HDMI 4K support PATCH, based on 4.7-rc1.
In order to support HDMI 4K on MT8173, we have to make some modifications. 1) Make sure that mtk_hdmi_send_infoframe is sent successfully. 2) Enhance the HDMI driving current to improve performance. 3) Make sure that pixel clock is 297MHz when resolution is 4K. 4) Adjust VENCPLL clock.
Bibby Hsieh (1): drm/mediatek: adjust VENCPLL clock for 4K HDMI output
Junzhi Zhao (3): drm/mediatek: do mtk_hdmi_send_infoframe after HDMI clock enable drm/mediatek: enhance the HDMI driving current drm/mediatek: fix the wrong pixel clock when resolution is 4K
drivers/gpu/drm/mediatek/mtk_dpi.c | 184 +++++++++++++++++------- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 9 ++ drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + drivers/gpu/drm/mediatek/mtk_hdmi.c | 19 ++- drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 89 ++++++++---- 5 files changed, 216 insertions(+), 86 deletions(-)
From: Junzhi Zhao junzhi.zhao@mediatek.com
The mtk_hdmi_send_infoframe have to be run after PLL and PIXEL clock of HDMI enable. Make sure that HDMI inforframes can be sent successfully.
Signed-off-by: Junzhi Zhao junzhi.zhao@mediatek.com Signed-off-by: Bibby Hsieh bibby.hsieh@mediatek.com --- drivers/gpu/drm/mediatek/mtk_hdmi.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c index ba812ef..d8609f5 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -1133,12 +1133,6 @@ static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi, phy_power_on(hdmi->phy); mtk_hdmi_aud_output_config(hdmi, mode);
- mtk_hdmi_setup_audio_infoframe(hdmi); - mtk_hdmi_setup_avi_infoframe(hdmi, mode); - mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI"); - if (mode->flags & DRM_MODE_FLAG_3D_MASK) - mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode); - mtk_hdmi_hw_vid_black(hdmi, false); mtk_hdmi_hw_aud_unmute(hdmi); mtk_hdmi_hw_send_av_unmute(hdmi); @@ -1401,14 +1395,25 @@ static void mtk_hdmi_bridge_pre_enable(struct drm_bridge *bridge) hdmi->powered = true; }
+static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi, + struct drm_display_mode *mode) +{ + mtk_hdmi_setup_audio_infoframe(hdmi); + mtk_hdmi_setup_avi_infoframe(hdmi, mode); + mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI"); + if (mode->flags & DRM_MODE_FLAG_3D_MASK) + mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode); +} + static void mtk_hdmi_bridge_enable(struct drm_bridge *bridge) { struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
+ phy_power_on(hdmi->phy); mtk_hdmi_output_set_display_mode(hdmi, &hdmi->mode); clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]); clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]); - phy_power_on(hdmi->phy); + mtk_hdmi_send_infoframe(hdmi, &hdmi->mode);
hdmi->enabled = true; }
From: Junzhi Zhao junzhi.zhao@mediatek.com
In order to improve 4K resolution performance, we have to enhance the HDMI driving currend when clock rate is greater than 165MHz.
Signed-off-by: Junzhi Zhao junzhi.zhao@mediatek.com Signed-off-by: Bibby Hsieh bibby.hsieh@mediatek.com --- drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 89 +++++++++++++++++------- 1 file changed, 63 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c index 8a24754..a871c14 100644 --- a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c +++ b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c @@ -298,32 +298,69 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, (0x1 << PLL_BR_SHIFT), RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC | RG_HDMITX_PLL_BR); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_PRD_IMP_EN); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, - (0x3 << PRD_IBIAS_CLK_SHIFT) | - (0x3 << PRD_IBIAS_D2_SHIFT) | - (0x3 << PRD_IBIAS_D1_SHIFT) | - (0x3 << PRD_IBIAS_D0_SHIFT), - RG_HDMITX_PRD_IBIAS_CLK | - RG_HDMITX_PRD_IBIAS_D2 | - RG_HDMITX_PRD_IBIAS_D1 | - RG_HDMITX_PRD_IBIAS_D0); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3, - (0x0 << DRV_IMP_EN_SHIFT), RG_HDMITX_DRV_IMP_EN); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, - (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) | - (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) | - (hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) | - (hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT), - RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 | - RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5, - (hdmi_phy->ibias << DRV_IBIAS_CLK_SHIFT) | - (hdmi_phy->ibias << DRV_IBIAS_D2_SHIFT) | - (hdmi_phy->ibias << DRV_IBIAS_D1_SHIFT) | - (hdmi_phy->ibias << DRV_IBIAS_D0_SHIFT), - RG_HDMITX_DRV_IBIAS_CLK | RG_HDMITX_DRV_IBIAS_D2 | - RG_HDMITX_DRV_IBIAS_D1 | RG_HDMITX_DRV_IBIAS_D0); + if (rate < 165000000) { + mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, + RG_HDMITX_PRD_IMP_EN); + mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, + (0x3 << PRD_IBIAS_CLK_SHIFT) | + (0x3 << PRD_IBIAS_D2_SHIFT) | + (0x3 << PRD_IBIAS_D1_SHIFT) | + (0x3 << PRD_IBIAS_D0_SHIFT), + RG_HDMITX_PRD_IBIAS_CLK | + RG_HDMITX_PRD_IBIAS_D2 | + RG_HDMITX_PRD_IBIAS_D1 | + RG_HDMITX_PRD_IBIAS_D0); + mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3, + (0x0 << DRV_IMP_EN_SHIFT), + RG_HDMITX_DRV_IMP_EN); + mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, + (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) | + (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) | + (hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) | + (hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT), + RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 | + RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0); + mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5, + (hdmi_phy->ibias << DRV_IBIAS_CLK_SHIFT) | + (hdmi_phy->ibias << DRV_IBIAS_D2_SHIFT) | + (hdmi_phy->ibias << DRV_IBIAS_D1_SHIFT) | + (hdmi_phy->ibias << DRV_IBIAS_D0_SHIFT), + RG_HDMITX_DRV_IBIAS_CLK | + RG_HDMITX_DRV_IBIAS_D2 | + RG_HDMITX_DRV_IBIAS_D1 | + RG_HDMITX_DRV_IBIAS_D0); + } else { + mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3, + RG_HDMITX_PRD_IMP_EN); + mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, + (0x6 << PRD_IBIAS_CLK_SHIFT) | + (0x6 << PRD_IBIAS_D2_SHIFT) | + (0x6 << PRD_IBIAS_D1_SHIFT) | + (0x6 << PRD_IBIAS_D0_SHIFT), + RG_HDMITX_PRD_IBIAS_CLK | + RG_HDMITX_PRD_IBIAS_D2 | + RG_HDMITX_PRD_IBIAS_D1 | + RG_HDMITX_PRD_IBIAS_D0); + mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3, + (0xf << DRV_IMP_EN_SHIFT), + RG_HDMITX_DRV_IMP_EN); + mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, + (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) | + (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) | + (hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) | + (hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT), + RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 | + RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0); + mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5, + (hdmi_phy->ibias_up << DRV_IBIAS_CLK_SHIFT) | + (hdmi_phy->ibias_up << DRV_IBIAS_D2_SHIFT) | + (hdmi_phy->ibias_up << DRV_IBIAS_D1_SHIFT) | + (hdmi_phy->ibias_up << DRV_IBIAS_D0_SHIFT), + RG_HDMITX_DRV_IBIAS_CLK | + RG_HDMITX_DRV_IBIAS_D2 | + RG_HDMITX_DRV_IBIAS_D1 | + RG_HDMITX_DRV_IBIAS_D0); + } return 0; }
Hi, Bibby:
One comment inline.
On Wed, 2016-07-20 at 12:03 +0800, Bibby Hsieh wrote:
From: Junzhi Zhao junzhi.zhao@mediatek.com
In order to improve 4K resolution performance, we have to enhance the HDMI driving currend when clock rate is greater than 165MHz.
Signed-off-by: Junzhi Zhao junzhi.zhao@mediatek.com Signed-off-by: Bibby Hsieh bibby.hsieh@mediatek.com
drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 89 +++++++++++++++++------- 1 file changed, 63 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c index 8a24754..a871c14 100644 --- a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c +++ b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c @@ -298,32 +298,69 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, (0x1 << PLL_BR_SHIFT), RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC | RG_HDMITX_PLL_BR);
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_PRD_IMP_EN);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,
(0x3 << PRD_IBIAS_CLK_SHIFT) |(0x3 << PRD_IBIAS_D2_SHIFT) |(0x3 << PRD_IBIAS_D1_SHIFT) |(0x3 << PRD_IBIAS_D0_SHIFT),RG_HDMITX_PRD_IBIAS_CLK |RG_HDMITX_PRD_IBIAS_D2 |RG_HDMITX_PRD_IBIAS_D1 |RG_HDMITX_PRD_IBIAS_D0);- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,
(0x0 << DRV_IMP_EN_SHIFT), RG_HDMITX_DRV_IMP_EN);- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,
(hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) |(hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |(hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) |(hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT),RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0);- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,
(hdmi_phy->ibias << DRV_IBIAS_CLK_SHIFT) |(hdmi_phy->ibias << DRV_IBIAS_D2_SHIFT) |(hdmi_phy->ibias << DRV_IBIAS_D1_SHIFT) |(hdmi_phy->ibias << DRV_IBIAS_D0_SHIFT),RG_HDMITX_DRV_IBIAS_CLK | RG_HDMITX_DRV_IBIAS_D2 |RG_HDMITX_DRV_IBIAS_D1 | RG_HDMITX_DRV_IBIAS_D0);
- if (rate < 165000000) {
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,RG_HDMITX_PRD_IMP_EN);mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,(0x3 << PRD_IBIAS_CLK_SHIFT) |(0x3 << PRD_IBIAS_D2_SHIFT) |(0x3 << PRD_IBIAS_D1_SHIFT) |(0x3 << PRD_IBIAS_D0_SHIFT),RG_HDMITX_PRD_IBIAS_CLK |RG_HDMITX_PRD_IBIAS_D2 |RG_HDMITX_PRD_IBIAS_D1 |RG_HDMITX_PRD_IBIAS_D0);mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,(0x0 << DRV_IMP_EN_SHIFT),RG_HDMITX_DRV_IMP_EN);mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,(hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) |(hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |(hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) |(hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT),RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0);mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,(hdmi_phy->ibias << DRV_IBIAS_CLK_SHIFT) |(hdmi_phy->ibias << DRV_IBIAS_D2_SHIFT) |(hdmi_phy->ibias << DRV_IBIAS_D1_SHIFT) |(hdmi_phy->ibias << DRV_IBIAS_D0_SHIFT),RG_HDMITX_DRV_IBIAS_CLK |RG_HDMITX_DRV_IBIAS_D2 |RG_HDMITX_DRV_IBIAS_D1 |RG_HDMITX_DRV_IBIAS_D0);- } else {
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,RG_HDMITX_PRD_IMP_EN);mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,(0x6 << PRD_IBIAS_CLK_SHIFT) |(0x6 << PRD_IBIAS_D2_SHIFT) |(0x6 << PRD_IBIAS_D1_SHIFT) |(0x6 << PRD_IBIAS_D0_SHIFT),RG_HDMITX_PRD_IBIAS_CLK |RG_HDMITX_PRD_IBIAS_D2 |RG_HDMITX_PRD_IBIAS_D1 |RG_HDMITX_PRD_IBIAS_D0);mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,(0xf << DRV_IMP_EN_SHIFT),RG_HDMITX_DRV_IMP_EN);mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,(hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) |(hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |(hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) |(hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT),RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0);mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,(hdmi_phy->ibias_up << DRV_IBIAS_CLK_SHIFT) |(hdmi_phy->ibias_up << DRV_IBIAS_D2_SHIFT) |(hdmi_phy->ibias_up << DRV_IBIAS_D1_SHIFT) |(hdmi_phy->ibias_up << DRV_IBIAS_D0_SHIFT),RG_HDMITX_DRV_IBIAS_CLK |RG_HDMITX_DRV_IBIAS_D2 |RG_HDMITX_DRV_IBIAS_D1 |RG_HDMITX_DRV_IBIAS_D0);- }
'if' part and 'else' part looks almost the same. Use variable for difference and merge these two part. For example:
if (rate < 165000000) prd_ibias = 0x3; else prd_ibias = 0x6;
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, (prd_ibias << PRD_IBIAS_CLK_SHIFT) | (prd_ibias << PRD_IBIAS_D2_SHIFT) | (prd_ibias << PRD_IBIAS_D1_SHIFT) | (prd_ibias << PRD_IBIAS_D0_SHIFT), RG_HDMITX_PRD_IBIAS_CLK | RG_HDMITX_PRD_IBIAS_D2 | RG_HDMITX_PRD_IBIAS_D1 | RG_HDMITX_PRD_IBIAS_D0);
return 0; }
Regards, CK
Hi, CK,
I'm appreciate your comment.
On Wed, 2016-07-20 at 15:15 +0800, CK Hu wrote:
Hi, Bibby:
One comment inline.
On Wed, 2016-07-20 at 12:03 +0800, Bibby Hsieh wrote:
From: Junzhi Zhao junzhi.zhao@mediatek.com
In order to improve 4K resolution performance, we have to enhance the HDMI driving currend when clock rate is greater than 165MHz.
Signed-off-by: Junzhi Zhao junzhi.zhao@mediatek.com Signed-off-by: Bibby Hsieh bibby.hsieh@mediatek.com
drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 89 +++++++++++++++++------- 1 file changed, 63 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c index 8a24754..a871c14 100644 --- a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c +++ b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c @@ -298,32 +298,69 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, (0x1 << PLL_BR_SHIFT), RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC | RG_HDMITX_PLL_BR);
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_PRD_IMP_EN);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,
(0x3 << PRD_IBIAS_CLK_SHIFT) |(0x3 << PRD_IBIAS_D2_SHIFT) |(0x3 << PRD_IBIAS_D1_SHIFT) |(0x3 << PRD_IBIAS_D0_SHIFT),RG_HDMITX_PRD_IBIAS_CLK |RG_HDMITX_PRD_IBIAS_D2 |RG_HDMITX_PRD_IBIAS_D1 |RG_HDMITX_PRD_IBIAS_D0);- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,
(0x0 << DRV_IMP_EN_SHIFT), RG_HDMITX_DRV_IMP_EN);- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,
(hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) |(hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |(hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) |(hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT),RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0);- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,
(hdmi_phy->ibias << DRV_IBIAS_CLK_SHIFT) |(hdmi_phy->ibias << DRV_IBIAS_D2_SHIFT) |(hdmi_phy->ibias << DRV_IBIAS_D1_SHIFT) |(hdmi_phy->ibias << DRV_IBIAS_D0_SHIFT),RG_HDMITX_DRV_IBIAS_CLK | RG_HDMITX_DRV_IBIAS_D2 |RG_HDMITX_DRV_IBIAS_D1 | RG_HDMITX_DRV_IBIAS_D0);
- if (rate < 165000000) {
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,RG_HDMITX_PRD_IMP_EN);mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,(0x3 << PRD_IBIAS_CLK_SHIFT) |(0x3 << PRD_IBIAS_D2_SHIFT) |(0x3 << PRD_IBIAS_D1_SHIFT) |(0x3 << PRD_IBIAS_D0_SHIFT),RG_HDMITX_PRD_IBIAS_CLK |RG_HDMITX_PRD_IBIAS_D2 |RG_HDMITX_PRD_IBIAS_D1 |RG_HDMITX_PRD_IBIAS_D0);mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,(0x0 << DRV_IMP_EN_SHIFT),RG_HDMITX_DRV_IMP_EN);mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,(hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) |(hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |(hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) |(hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT),RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0);mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,(hdmi_phy->ibias << DRV_IBIAS_CLK_SHIFT) |(hdmi_phy->ibias << DRV_IBIAS_D2_SHIFT) |(hdmi_phy->ibias << DRV_IBIAS_D1_SHIFT) |(hdmi_phy->ibias << DRV_IBIAS_D0_SHIFT),RG_HDMITX_DRV_IBIAS_CLK |RG_HDMITX_DRV_IBIAS_D2 |RG_HDMITX_DRV_IBIAS_D1 |RG_HDMITX_DRV_IBIAS_D0);- } else {
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,RG_HDMITX_PRD_IMP_EN);mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,(0x6 << PRD_IBIAS_CLK_SHIFT) |(0x6 << PRD_IBIAS_D2_SHIFT) |(0x6 << PRD_IBIAS_D1_SHIFT) |(0x6 << PRD_IBIAS_D0_SHIFT),RG_HDMITX_PRD_IBIAS_CLK |RG_HDMITX_PRD_IBIAS_D2 |RG_HDMITX_PRD_IBIAS_D1 |RG_HDMITX_PRD_IBIAS_D0);mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,(0xf << DRV_IMP_EN_SHIFT),RG_HDMITX_DRV_IMP_EN);mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,(hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) |(hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |(hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) |(hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT),RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0);mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,(hdmi_phy->ibias_up << DRV_IBIAS_CLK_SHIFT) |(hdmi_phy->ibias_up << DRV_IBIAS_D2_SHIFT) |(hdmi_phy->ibias_up << DRV_IBIAS_D1_SHIFT) |(hdmi_phy->ibias_up << DRV_IBIAS_D0_SHIFT),RG_HDMITX_DRV_IBIAS_CLK |RG_HDMITX_DRV_IBIAS_D2 |RG_HDMITX_DRV_IBIAS_D1 |RG_HDMITX_DRV_IBIAS_D0);- }
'if' part and 'else' part looks almost the same. Use variable for difference and merge these two part. For example:
if (rate < 165000000) prd_ibias = 0x3; else prd_ibias = 0x6;
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, (prd_ibias << PRD_IBIAS_CLK_SHIFT) | (prd_ibias << PRD_IBIAS_D2_SHIFT) | (prd_ibias << PRD_IBIAS_D1_SHIFT) | (prd_ibias << PRD_IBIAS_D0_SHIFT), RG_HDMITX_PRD_IBIAS_CLK | RG_HDMITX_PRD_IBIAS_D2 | RG_HDMITX_PRD_IBIAS_D1 | RG_HDMITX_PRD_IBIAS_D0);
return 0; }
Ok, I will use variable instead of that.
Regards, CK
From: Junzhi Zhao junzhi.zhao@mediatek.com
Pixel clock should be 297MHz when resolution is 4K.
Signed-off-by: Junzhi Zhao junzhi.zhao@mediatek.com Signed-off-by: Bibby Hsieh bibby.hsieh@mediatek.com --- drivers/gpu/drm/mediatek/mtk_dpi.c | 184 +++++++++++++++++++++++++----------- 1 file changed, 131 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index d05ca79..c0f04d2 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -60,14 +60,35 @@ enum mtk_dpi_out_color_format { MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL };
+enum mtk_dpi_clk_id { + MTK_DPI_CLK_DPI_ENGINE, + MTK_DPI_CLK_DPI_PIXEL, + MTK_DPI_CLK_TVD_PLL, + MTK_DPI_CLK_TVDPLL_MUX, + MTK_DPI_CLK_TVDPLL_D2, + MTK_DPI_CLK_TVDPLL_D4, + MTK_DPI_CLK_TVDPLL_D8, + MTK_DPI_CLK_TVDPLL_D16, + MTK_DPI_CLK_COUNT, +}; + +static const char * const mtk_dpi_clk_names[MTK_DPI_CLK_COUNT] = { + [MTK_DPI_CLK_DPI_ENGINE] = "engine", + [MTK_DPI_CLK_DPI_PIXEL] = "pixel", + [MTK_DPI_CLK_TVD_PLL] = "pll", + [MTK_DPI_CLK_TVDPLL_MUX] = "tvdpll_mux", + [MTK_DPI_CLK_TVDPLL_D2] = "tvdpll_d2", + [MTK_DPI_CLK_TVDPLL_D4] = "tvdpll_d4", + [MTK_DPI_CLK_TVDPLL_D8] = "tvdpll_d8", + [MTK_DPI_CLK_TVDPLL_D16] = "tvdpll_d16", +}; + struct mtk_dpi { struct mtk_ddp_comp ddp_comp; struct drm_encoder encoder; void __iomem *regs; struct device *dev; - struct clk *engine_clk; - struct clk *pixel_clk; - struct clk *tvd_clk; + struct clk *clk[MTK_DPI_CLK_COUNT]; int irq; struct drm_display_mode mode; enum mtk_dpi_out_color_format color_format; @@ -76,6 +97,7 @@ struct mtk_dpi { enum mtk_dpi_out_channel_swap channel_swap; bool power_sta; u8 power_ctl; + void *data; };
static inline struct mtk_dpi *mtk_dpi_from_encoder(struct drm_encoder *e) @@ -114,6 +136,11 @@ struct mtk_dpi_yc_limit { u16 c_bottom; };
+struct mtk_dpi_conf { + int (*parse_clk_from_dt)(struct mtk_dpi *dpi, struct device_node *np); + int (*clk_config)(struct mtk_dpi *dpi, struct drm_display_mode *mode); +}; + static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) { u32 tmp = readl(dpi->regs + offset) & ~mask; @@ -377,8 +404,8 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi, enum mtk_dpi_power_ctl pctl) return;
mtk_dpi_disable(dpi); - clk_disable_unprepare(dpi->pixel_clk); - clk_disable_unprepare(dpi->engine_clk); + clk_disable_unprepare(dpi->clk[MTK_DPI_CLK_DPI_PIXEL]); + clk_disable_unprepare(dpi->clk[MTK_DPI_CLK_DPI_ENGINE]); dpi->power_sta = false; }
@@ -395,13 +422,13 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi, enum mtk_dpi_power_ctl pctl) if (dpi->power_sta) return 0;
- ret = clk_prepare_enable(dpi->engine_clk); + ret = clk_prepare_enable(dpi->clk[MTK_DPI_CLK_DPI_ENGINE]); if (ret) { dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret); goto err_eng; }
- ret = clk_prepare_enable(dpi->pixel_clk); + ret = clk_prepare_enable(dpi->clk[MTK_DPI_CLK_DPI_PIXEL]); if (ret) { dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret); goto err_pixel; @@ -412,7 +439,7 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi, enum mtk_dpi_power_ctl pctl) return 0;
err_pixel: - clk_disable_unprepare(dpi->engine_clk); + clk_disable_unprepare(dpi->clk[MTK_DPI_CLK_DPI_ENGINE]); err_eng: dpi->power_ctl &= ~pctl; return ret; @@ -428,34 +455,16 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, struct mtk_dpi_sync_param vsync_leven = { 0 }; struct mtk_dpi_sync_param vsync_rodd = { 0 }; struct mtk_dpi_sync_param vsync_reven = { 0 }; - unsigned long pix_rate; - unsigned long pll_rate; - unsigned int factor; + struct mtk_dpi_conf *conf; + int ret;
if (!dpi) { dev_err(dpi->dev, "invalid argument\n"); return -EINVAL; }
- pix_rate = 1000UL * mode->clock; - if (mode->clock <= 74000) - factor = 8 * 3; - else - factor = 4 * 3; - pll_rate = pix_rate * factor; - - dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n", - pll_rate, pix_rate); - - clk_set_rate(dpi->tvd_clk, pll_rate); - pll_rate = clk_get_rate(dpi->tvd_clk); - - pix_rate = pll_rate / factor; - clk_set_rate(dpi->pixel_clk, pix_rate); - pix_rate = clk_get_rate(dpi->pixel_clk); - - dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", - pll_rate, pix_rate); + conf = (struct mtk_dpi_conf *)dpi->data; + ret = conf->clk_config(dpi, mode);
limit.c_bottom = 0x0010; limit.c_top = 0x0FE0; @@ -656,20 +665,109 @@ static const struct component_ops mtk_dpi_component_ops = { .unbind = mtk_dpi_unbind, };
+static int mt8173_parse_clk_from_dt(struct mtk_dpi *dpi, struct device_node *np) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(mtk_dpi_clk_names); i++) { + dpi->clk[i] = of_clk_get_by_name(np, + mtk_dpi_clk_names[i]); + if (IS_ERR(dpi->clk[i])) + return PTR_ERR(dpi->clk[i]); + } + return 0; +} + +static int mt8173_clk_config(struct mtk_dpi *dpi, struct drm_display_mode *mode) +{ + unsigned long pix_rate; + unsigned long pll_rate; + unsigned int factor; + struct clk *parent; + int ret; + + if (mode->clock <= 27000) { + factor = 16 * 3; + parent = dpi->clk[MTK_DPI_CLK_TVDPLL_D16]; + } else if (mode->clock <= 74250) { + factor = 8 * 3; + parent = dpi->clk[MTK_DPI_CLK_TVDPLL_D8]; + } else if (mode->clock <= 167000) { + factor = 4 * 3; + parent = dpi->clk[MTK_DPI_CLK_TVDPLL_D4]; + } else { + factor = 2 * 3; + parent = dpi->clk[MTK_DPI_CLK_TVDPLL_D2]; + } + + pix_rate = 1000UL * mode->clock; + pll_rate = pix_rate * factor; + + dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n", + pll_rate, pix_rate); + + ret = clk_prepare_enable(dpi->clk[MTK_DPI_CLK_TVDPLL_MUX]); + if (ret) { + dev_err(dpi->dev, "tvdpll_mux enable fail\n"); + return ret; + } + + ret = clk_set_parent(dpi->clk[MTK_DPI_CLK_TVDPLL_MUX], parent); + if (ret) { + dev_err(dpi->dev, "tvdpll_mux set parent fail\n"); + return ret; + } + clk_disable_unprepare(dpi->clk[MTK_DPI_CLK_TVDPLL_MUX]); + + ret = clk_set_rate(dpi->clk[MTK_DPI_CLK_TVD_PLL], pll_rate); + if (ret) { + dev_err(dpi->dev, "dpi pll_rate set rate fail\n"); + return ret; + } + pll_rate = clk_get_rate(dpi->clk[MTK_DPI_CLK_TVD_PLL]); + pix_rate = clk_get_rate(dpi->clk[MTK_DPI_CLK_DPI_PIXEL]); + + dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", + pll_rate, pix_rate); + + return 0; +} + +static const struct mtk_dpi_conf mt8173_conf = { + .parse_clk_from_dt = mt8173_parse_clk_from_dt, + .clk_config = mt8173_clk_config, +}; + +static const struct of_device_id mtk_dpi_of_ids[] = { + { .compatible = "mediatek,mt8173-dpi", + .data = &mt8173_conf, + }, + {} +}; + static int mtk_dpi_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct mtk_dpi *dpi; struct resource *mem; + struct device_node *np = dev->of_node; struct device_node *ep, *bridge_node = NULL; int comp_id; + const struct of_device_id *match; + struct mtk_dpi_conf *conf; int ret;
+ match = of_match_node(mtk_dpi_of_ids, dev->of_node); + if (!match) + return -ENODEV; + dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL); if (!dpi) return -ENOMEM;
dpi->dev = dev; + dpi->data = (void *)match->data; + conf = (struct mtk_dpi_conf *)match->data;
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); dpi->regs = devm_ioremap_resource(dev, mem); @@ -679,24 +777,9 @@ static int mtk_dpi_probe(struct platform_device *pdev) return ret; }
- dpi->engine_clk = devm_clk_get(dev, "engine"); - if (IS_ERR(dpi->engine_clk)) { - ret = PTR_ERR(dpi->engine_clk); - dev_err(dev, "Failed to get engine clock: %d\n", ret); - return ret; - } - - dpi->pixel_clk = devm_clk_get(dev, "pixel"); - if (IS_ERR(dpi->pixel_clk)) { - ret = PTR_ERR(dpi->pixel_clk); - dev_err(dev, "Failed to get pixel clock: %d\n", ret); - return ret; - } - - dpi->tvd_clk = devm_clk_get(dev, "pll"); - if (IS_ERR(dpi->tvd_clk)) { - ret = PTR_ERR(dpi->tvd_clk); - dev_err(dev, "Failed to get tvdpll clock: %d\n", ret); + ret = conf->parse_clk_from_dt(dpi, np); + if (ret) { + dev_err(dev, "parse tvd div clk failed!"); return ret; }
@@ -754,11 +837,6 @@ static int mtk_dpi_remove(struct platform_device *pdev) return 0; }
-static const struct of_device_id mtk_dpi_of_ids[] = { - { .compatible = "mediatek,mt8173-dpi", }, - {} -}; - struct platform_driver mtk_dpi_driver = { .probe = mtk_dpi_probe, .remove = mtk_dpi_remove,
Hi, Bibby:
Some comments inline.
On Wed, 2016-07-20 at 12:03 +0800, Bibby Hsieh wrote:
From: Junzhi Zhao junzhi.zhao@mediatek.com
Pixel clock should be 297MHz when resolution is 4K.
Signed-off-by: Junzhi Zhao junzhi.zhao@mediatek.com Signed-off-by: Bibby Hsieh bibby.hsieh@mediatek.com
drivers/gpu/drm/mediatek/mtk_dpi.c | 184 +++++++++++++++++++++++++----------- 1 file changed, 131 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index d05ca79..c0f04d2 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -60,14 +60,35 @@ enum mtk_dpi_out_color_format { MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL };
+enum mtk_dpi_clk_id {
- MTK_DPI_CLK_DPI_ENGINE,
- MTK_DPI_CLK_DPI_PIXEL,
- MTK_DPI_CLK_TVD_PLL,
- MTK_DPI_CLK_TVDPLL_MUX,
- MTK_DPI_CLK_TVDPLL_D2,
- MTK_DPI_CLK_TVDPLL_D4,
- MTK_DPI_CLK_TVDPLL_D8,
- MTK_DPI_CLK_TVDPLL_D16,
- MTK_DPI_CLK_COUNT,
+};
+static const char * const mtk_dpi_clk_names[MTK_DPI_CLK_COUNT] = {
- [MTK_DPI_CLK_DPI_ENGINE] = "engine",
- [MTK_DPI_CLK_DPI_PIXEL] = "pixel",
- [MTK_DPI_CLK_TVD_PLL] = "pll",
- [MTK_DPI_CLK_TVDPLL_MUX] = "tvdpll_mux",
- [MTK_DPI_CLK_TVDPLL_D2] = "tvdpll_d2",
- [MTK_DPI_CLK_TVDPLL_D4] = "tvdpll_d4",
- [MTK_DPI_CLK_TVDPLL_D8] = "tvdpll_d8",
- [MTK_DPI_CLK_TVDPLL_D16] = "tvdpll_d16",
+};
struct mtk_dpi { struct mtk_ddp_comp ddp_comp; struct drm_encoder encoder; void __iomem *regs; struct device *dev;
- struct clk *engine_clk;
- struct clk *pixel_clk;
- struct clk *tvd_clk;
- struct clk *clk[MTK_DPI_CLK_COUNT]; int irq; struct drm_display_mode mode; enum mtk_dpi_out_color_format color_format;
@@ -76,6 +97,7 @@ struct mtk_dpi { enum mtk_dpi_out_channel_swap channel_swap; bool power_sta; u8 power_ctl;
- void *data;
};
static inline struct mtk_dpi *mtk_dpi_from_encoder(struct drm_encoder *e) @@ -114,6 +136,11 @@ struct mtk_dpi_yc_limit { u16 c_bottom; };
+struct mtk_dpi_conf {
- int (*parse_clk_from_dt)(struct mtk_dpi *dpi, struct device_node *np);
- int (*clk_config)(struct mtk_dpi *dpi, struct drm_display_mode *mode);
+};
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) { u32 tmp = readl(dpi->regs + offset) & ~mask; @@ -377,8 +404,8 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi, enum mtk_dpi_power_ctl pctl) return;
mtk_dpi_disable(dpi);
- clk_disable_unprepare(dpi->pixel_clk);
- clk_disable_unprepare(dpi->engine_clk);
- clk_disable_unprepare(dpi->clk[MTK_DPI_CLK_DPI_PIXEL]);
- clk_disable_unprepare(dpi->clk[MTK_DPI_CLK_DPI_ENGINE]); dpi->power_sta = false;
}
@@ -395,13 +422,13 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi, enum mtk_dpi_power_ctl pctl) if (dpi->power_sta) return 0;
- ret = clk_prepare_enable(dpi->engine_clk);
- ret = clk_prepare_enable(dpi->clk[MTK_DPI_CLK_DPI_ENGINE]); if (ret) { dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret); goto err_eng; }
- ret = clk_prepare_enable(dpi->pixel_clk);
- ret = clk_prepare_enable(dpi->clk[MTK_DPI_CLK_DPI_PIXEL]); if (ret) { dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret); goto err_pixel;
@@ -412,7 +439,7 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi, enum mtk_dpi_power_ctl pctl) return 0;
err_pixel:
- clk_disable_unprepare(dpi->engine_clk);
- clk_disable_unprepare(dpi->clk[MTK_DPI_CLK_DPI_ENGINE]);
err_eng: dpi->power_ctl &= ~pctl; return ret; @@ -428,34 +455,16 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, struct mtk_dpi_sync_param vsync_leven = { 0 }; struct mtk_dpi_sync_param vsync_rodd = { 0 }; struct mtk_dpi_sync_param vsync_reven = { 0 };
- unsigned long pix_rate;
- unsigned long pll_rate;
- unsigned int factor;
struct mtk_dpi_conf *conf;
int ret;
if (!dpi) { dev_err(dpi->dev, "invalid argument\n"); return -EINVAL; }
- pix_rate = 1000UL * mode->clock;
- if (mode->clock <= 74000)
factor = 8 * 3;- else
factor = 4 * 3;- pll_rate = pix_rate * factor;
- dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n",
pll_rate, pix_rate);- clk_set_rate(dpi->tvd_clk, pll_rate);
- pll_rate = clk_get_rate(dpi->tvd_clk);
- pix_rate = pll_rate / factor;
- clk_set_rate(dpi->pixel_clk, pix_rate);
- pix_rate = clk_get_rate(dpi->pixel_clk);
- dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n",
pll_rate, pix_rate);
- conf = (struct mtk_dpi_conf *)dpi->data;
- ret = conf->clk_config(dpi, mode);
Nothing to do with return error?
limit.c_bottom = 0x0010; limit.c_top = 0x0FE0; @@ -656,20 +665,109 @@ static const struct component_ops mtk_dpi_component_ops = { .unbind = mtk_dpi_unbind, };
+static int mt8173_parse_clk_from_dt(struct mtk_dpi *dpi, struct device_node *np) +{
- int i;
- for (i = 0; i < ARRAY_SIZE(mtk_dpi_clk_names); i++) {
dpi->clk[i] = of_clk_get_by_name(np,mtk_dpi_clk_names[i]);if (IS_ERR(dpi->clk[i]))return PTR_ERR(dpi->clk[i]);- }
- return 0;
+}
I think parsing device tree is a pure SW behavior. Would this vary for different MTK soc?
+static int mt8173_clk_config(struct mtk_dpi *dpi, struct drm_display_mode *mode) +{
- unsigned long pix_rate;
- unsigned long pll_rate;
- unsigned int factor;
- struct clk *parent;
- int ret;
- if (mode->clock <= 27000) {
factor = 16 * 3;parent = dpi->clk[MTK_DPI_CLK_TVDPLL_D16];- } else if (mode->clock <= 74250) {
factor = 8 * 3;parent = dpi->clk[MTK_DPI_CLK_TVDPLL_D8];- } else if (mode->clock <= 167000) {
factor = 4 * 3;parent = dpi->clk[MTK_DPI_CLK_TVDPLL_D4];- } else {
factor = 2 * 3;parent = dpi->clk[MTK_DPI_CLK_TVDPLL_D2];- }
- pix_rate = 1000UL * mode->clock;
- pll_rate = pix_rate * factor;
- dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n",
pll_rate, pix_rate);- ret = clk_prepare_enable(dpi->clk[MTK_DPI_CLK_TVDPLL_MUX]);
- if (ret) {
dev_err(dpi->dev, "tvdpll_mux enable fail\n");return ret;- }
- ret = clk_set_parent(dpi->clk[MTK_DPI_CLK_TVDPLL_MUX], parent);
- if (ret) {
dev_err(dpi->dev, "tvdpll_mux set parent fail\n");
Before return, you may undo something.
return ret;- }
- clk_disable_unprepare(dpi->clk[MTK_DPI_CLK_TVDPLL_MUX]);
- ret = clk_set_rate(dpi->clk[MTK_DPI_CLK_TVD_PLL], pll_rate);
- if (ret) {
dev_err(dpi->dev, "dpi pll_rate set rate fail\n");return ret;- }
- pll_rate = clk_get_rate(dpi->clk[MTK_DPI_CLK_TVD_PLL]);
- pix_rate = clk_get_rate(dpi->clk[MTK_DPI_CLK_DPI_PIXEL]);
- dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n",
pll_rate, pix_rate);- return 0;
+}
+static const struct mtk_dpi_conf mt8173_conf = {
- .parse_clk_from_dt = mt8173_parse_clk_from_dt,
- .clk_config = mt8173_clk_config,
+};
+static const struct of_device_id mtk_dpi_of_ids[] = {
- { .compatible = "mediatek,mt8173-dpi",
.data = &mt8173_conf,- },
- {}
+};
static int mtk_dpi_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct mtk_dpi *dpi; struct resource *mem;
struct device_node *np = dev->of_node; struct device_node *ep, *bridge_node = NULL; int comp_id;
const struct of_device_id *match;
struct mtk_dpi_conf *conf; int ret;
match = of_match_node(mtk_dpi_of_ids, dev->of_node);
if (!match)
return -ENODEV;dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL); if (!dpi) return -ENOMEM;
dpi->dev = dev;
dpi->data = (void *)match->data;
conf = (struct mtk_dpi_conf *)match->data;
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); dpi->regs = devm_ioremap_resource(dev, mem);
@@ -679,24 +777,9 @@ static int mtk_dpi_probe(struct platform_device *pdev) return ret; }
- dpi->engine_clk = devm_clk_get(dev, "engine");
- if (IS_ERR(dpi->engine_clk)) {
ret = PTR_ERR(dpi->engine_clk);dev_err(dev, "Failed to get engine clock: %d\n", ret);return ret;- }
- dpi->pixel_clk = devm_clk_get(dev, "pixel");
- if (IS_ERR(dpi->pixel_clk)) {
ret = PTR_ERR(dpi->pixel_clk);dev_err(dev, "Failed to get pixel clock: %d\n", ret);return ret;- }
- dpi->tvd_clk = devm_clk_get(dev, "pll");
- if (IS_ERR(dpi->tvd_clk)) {
ret = PTR_ERR(dpi->tvd_clk);dev_err(dev, "Failed to get tvdpll clock: %d\n", ret);
- ret = conf->parse_clk_from_dt(dpi, np);
- if (ret) {
dev_err(dev, "parse tvd div clk failed!");@@ -754,11 +837,6 @@ static int mtk_dpi_remove(struct platform_device *pdev) return 0; }
-static const struct of_device_id mtk_dpi_of_ids[] = {
- { .compatible = "mediatek,mt8173-dpi", },
- {}
-};
struct platform_driver mtk_dpi_driver = { .probe = mtk_dpi_probe, .remove = mtk_dpi_remove,
Regards, CK
Hi, CK,
Thanks for your comments.
On Wed, 2016-07-20 at 15:57 +0800, CK Hu wrote:
Hi, Bibby:
Some comments inline.
On Wed, 2016-07-20 at 12:03 +0800, Bibby Hsieh wrote:
From: Junzhi Zhao junzhi.zhao@mediatek.com
Pixel clock should be 297MHz when resolution is 4K.
Signed-off-by: Junzhi Zhao junzhi.zhao@mediatek.com Signed-off-by: Bibby Hsieh bibby.hsieh@mediatek.com
drivers/gpu/drm/mediatek/mtk_dpi.c | 184 +++++++++++++++++++++++++----------- 1 file changed, 131 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index d05ca79..c0f04d2 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -60,14 +60,35 @@ enum mtk_dpi_out_color_format { MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL };
+enum mtk_dpi_clk_id {
- MTK_DPI_CLK_DPI_ENGINE,
- MTK_DPI_CLK_DPI_PIXEL,
- MTK_DPI_CLK_TVD_PLL,
- MTK_DPI_CLK_TVDPLL_MUX,
- MTK_DPI_CLK_TVDPLL_D2,
- MTK_DPI_CLK_TVDPLL_D4,
- MTK_DPI_CLK_TVDPLL_D8,
- MTK_DPI_CLK_TVDPLL_D16,
- MTK_DPI_CLK_COUNT,
+};
+static const char * const mtk_dpi_clk_names[MTK_DPI_CLK_COUNT] = {
- [MTK_DPI_CLK_DPI_ENGINE] = "engine",
- [MTK_DPI_CLK_DPI_PIXEL] = "pixel",
- [MTK_DPI_CLK_TVD_PLL] = "pll",
- [MTK_DPI_CLK_TVDPLL_MUX] = "tvdpll_mux",
- [MTK_DPI_CLK_TVDPLL_D2] = "tvdpll_d2",
- [MTK_DPI_CLK_TVDPLL_D4] = "tvdpll_d4",
- [MTK_DPI_CLK_TVDPLL_D8] = "tvdpll_d8",
- [MTK_DPI_CLK_TVDPLL_D16] = "tvdpll_d16",
+};
struct mtk_dpi { struct mtk_ddp_comp ddp_comp; struct drm_encoder encoder; void __iomem *regs; struct device *dev;
- struct clk *engine_clk;
- struct clk *pixel_clk;
- struct clk *tvd_clk;
- struct clk *clk[MTK_DPI_CLK_COUNT]; int irq; struct drm_display_mode mode; enum mtk_dpi_out_color_format color_format;
@@ -76,6 +97,7 @@ struct mtk_dpi { enum mtk_dpi_out_channel_swap channel_swap; bool power_sta; u8 power_ctl;
- void *data;
};
static inline struct mtk_dpi *mtk_dpi_from_encoder(struct drm_encoder *e) @@ -114,6 +136,11 @@ struct mtk_dpi_yc_limit { u16 c_bottom; };
+struct mtk_dpi_conf {
- int (*parse_clk_from_dt)(struct mtk_dpi *dpi, struct device_node *np);
- int (*clk_config)(struct mtk_dpi *dpi, struct drm_display_mode *mode);
+};
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) { u32 tmp = readl(dpi->regs + offset) & ~mask; @@ -377,8 +404,8 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi, enum mtk_dpi_power_ctl pctl) return;
mtk_dpi_disable(dpi);
- clk_disable_unprepare(dpi->pixel_clk);
- clk_disable_unprepare(dpi->engine_clk);
- clk_disable_unprepare(dpi->clk[MTK_DPI_CLK_DPI_PIXEL]);
- clk_disable_unprepare(dpi->clk[MTK_DPI_CLK_DPI_ENGINE]); dpi->power_sta = false;
}
@@ -395,13 +422,13 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi, enum mtk_dpi_power_ctl pctl) if (dpi->power_sta) return 0;
- ret = clk_prepare_enable(dpi->engine_clk);
- ret = clk_prepare_enable(dpi->clk[MTK_DPI_CLK_DPI_ENGINE]); if (ret) { dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret); goto err_eng; }
- ret = clk_prepare_enable(dpi->pixel_clk);
- ret = clk_prepare_enable(dpi->clk[MTK_DPI_CLK_DPI_PIXEL]); if (ret) { dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret); goto err_pixel;
@@ -412,7 +439,7 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi, enum mtk_dpi_power_ctl pctl) return 0;
err_pixel:
- clk_disable_unprepare(dpi->engine_clk);
- clk_disable_unprepare(dpi->clk[MTK_DPI_CLK_DPI_ENGINE]);
err_eng: dpi->power_ctl &= ~pctl; return ret; @@ -428,34 +455,16 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, struct mtk_dpi_sync_param vsync_leven = { 0 }; struct mtk_dpi_sync_param vsync_rodd = { 0 }; struct mtk_dpi_sync_param vsync_reven = { 0 };
- unsigned long pix_rate;
- unsigned long pll_rate;
- unsigned int factor;
struct mtk_dpi_conf *conf;
int ret;
if (!dpi) { dev_err(dpi->dev, "invalid argument\n"); return -EINVAL; }
- pix_rate = 1000UL * mode->clock;
- if (mode->clock <= 74000)
factor = 8 * 3;- else
factor = 4 * 3;- pll_rate = pix_rate * factor;
- dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n",
pll_rate, pix_rate);- clk_set_rate(dpi->tvd_clk, pll_rate);
- pll_rate = clk_get_rate(dpi->tvd_clk);
- pix_rate = pll_rate / factor;
- clk_set_rate(dpi->pixel_clk, pix_rate);
- pix_rate = clk_get_rate(dpi->pixel_clk);
- dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n",
pll_rate, pix_rate);
- conf = (struct mtk_dpi_conf *)dpi->data;
- ret = conf->clk_config(dpi, mode);
Nothing to do with return error?
Ok, I will fix that.
limit.c_bottom = 0x0010; limit.c_top = 0x0FE0; @@ -656,20 +665,109 @@ static const struct component_ops mtk_dpi_component_ops = { .unbind = mtk_dpi_unbind, };
+static int mt8173_parse_clk_from_dt(struct mtk_dpi *dpi, struct device_node *np) +{
- int i;
- for (i = 0; i < ARRAY_SIZE(mtk_dpi_clk_names); i++) {
dpi->clk[i] = of_clk_get_by_name(np,mtk_dpi_clk_names[i]);if (IS_ERR(dpi->clk[i]))return PTR_ERR(dpi->clk[i]);- }
- return 0;
+}
I think parsing device tree is a pure SW behavior. Would this vary for different MTK soc?
Yes
+static int mt8173_clk_config(struct mtk_dpi *dpi, struct drm_display_mode *mode) +{
- unsigned long pix_rate;
- unsigned long pll_rate;
- unsigned int factor;
- struct clk *parent;
- int ret;
- if (mode->clock <= 27000) {
factor = 16 * 3;parent = dpi->clk[MTK_DPI_CLK_TVDPLL_D16];- } else if (mode->clock <= 74250) {
factor = 8 * 3;parent = dpi->clk[MTK_DPI_CLK_TVDPLL_D8];- } else if (mode->clock <= 167000) {
factor = 4 * 3;parent = dpi->clk[MTK_DPI_CLK_TVDPLL_D4];- } else {
factor = 2 * 3;parent = dpi->clk[MTK_DPI_CLK_TVDPLL_D2];- }
- pix_rate = 1000UL * mode->clock;
- pll_rate = pix_rate * factor;
- dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n",
pll_rate, pix_rate);- ret = clk_prepare_enable(dpi->clk[MTK_DPI_CLK_TVDPLL_MUX]);
- if (ret) {
dev_err(dpi->dev, "tvdpll_mux enable fail\n");return ret;- }
- ret = clk_set_parent(dpi->clk[MTK_DPI_CLK_TVDPLL_MUX], parent);
- if (ret) {
dev_err(dpi->dev, "tvdpll_mux set parent fail\n");Before return, you may undo something.
I think we can remove this function at the new version, because we make some changes here according Philipp' comments.
return ret;- }
- clk_disable_unprepare(dpi->clk[MTK_DPI_CLK_TVDPLL_MUX]);
- ret = clk_set_rate(dpi->clk[MTK_DPI_CLK_TVD_PLL], pll_rate);
- if (ret) {
dev_err(dpi->dev, "dpi pll_rate set rate fail\n");return ret;- }
- pll_rate = clk_get_rate(dpi->clk[MTK_DPI_CLK_TVD_PLL]);
- pix_rate = clk_get_rate(dpi->clk[MTK_DPI_CLK_DPI_PIXEL]);
- dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n",
pll_rate, pix_rate);- return 0;
+}
+static const struct mtk_dpi_conf mt8173_conf = {
- .parse_clk_from_dt = mt8173_parse_clk_from_dt,
- .clk_config = mt8173_clk_config,
+};
+static const struct of_device_id mtk_dpi_of_ids[] = {
- { .compatible = "mediatek,mt8173-dpi",
.data = &mt8173_conf,- },
- {}
+};
static int mtk_dpi_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct mtk_dpi *dpi; struct resource *mem;
struct device_node *np = dev->of_node; struct device_node *ep, *bridge_node = NULL; int comp_id;
const struct of_device_id *match;
struct mtk_dpi_conf *conf; int ret;
match = of_match_node(mtk_dpi_of_ids, dev->of_node);
if (!match)
return -ENODEV;dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL); if (!dpi) return -ENOMEM;
dpi->dev = dev;
dpi->data = (void *)match->data;
conf = (struct mtk_dpi_conf *)match->data;
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); dpi->regs = devm_ioremap_resource(dev, mem);
@@ -679,24 +777,9 @@ static int mtk_dpi_probe(struct platform_device *pdev) return ret; }
- dpi->engine_clk = devm_clk_get(dev, "engine");
- if (IS_ERR(dpi->engine_clk)) {
ret = PTR_ERR(dpi->engine_clk);dev_err(dev, "Failed to get engine clock: %d\n", ret);return ret;- }
- dpi->pixel_clk = devm_clk_get(dev, "pixel");
- if (IS_ERR(dpi->pixel_clk)) {
ret = PTR_ERR(dpi->pixel_clk);dev_err(dev, "Failed to get pixel clock: %d\n", ret);return ret;- }
- dpi->tvd_clk = devm_clk_get(dev, "pll");
- if (IS_ERR(dpi->tvd_clk)) {
ret = PTR_ERR(dpi->tvd_clk);dev_err(dev, "Failed to get tvdpll clock: %d\n", ret);
- ret = conf->parse_clk_from_dt(dpi, np);
- if (ret) {
dev_err(dev, "parse tvd div clk failed!");@@ -754,11 +837,6 @@ static int mtk_dpi_remove(struct platform_device *pdev) return 0; }
-static const struct of_device_id mtk_dpi_of_ids[] = {
- { .compatible = "mediatek,mt8173-dpi", },
- {}
-};
struct platform_driver mtk_dpi_driver = { .probe = mtk_dpi_probe, .remove = mtk_dpi_remove,
Regards, CK
Hi, Bibby:
On Mon, 2016-07-25 at 14:24 +0800, Bibby Hsieh wrote:
Hi, CK,
Thanks for your comments.
On Wed, 2016-07-20 at 15:57 +0800, CK Hu wrote:
Hi, Bibby:
Some comments inline.
On Wed, 2016-07-20 at 12:03 +0800, Bibby Hsieh wrote:
From: Junzhi Zhao junzhi.zhao@mediatek.com
Pixel clock should be 297MHz when resolution is 4K.
Signed-off-by: Junzhi Zhao junzhi.zhao@mediatek.com Signed-off-by: Bibby Hsieh bibby.hsieh@mediatek.com
drivers/gpu/drm/mediatek/mtk_dpi.c | 184 +++++++++++++++++++++++++----------- 1 file changed, 131 insertions(+), 53 deletions(-)
[snip...]
+static int mt8173_parse_clk_from_dt(struct mtk_dpi *dpi, struct device_node *np) +{
- int i;
- for (i = 0; i < ARRAY_SIZE(mtk_dpi_clk_names); i++) {
dpi->clk[i] = of_clk_get_by_name(np,mtk_dpi_clk_names[i]);if (IS_ERR(dpi->clk[i]))return PTR_ERR(dpi->clk[i]);- }
- return 0;
+}
I think parsing device tree is a pure SW behavior. Would this vary for different MTK soc?
Yes
I can not imaging that, so could you give me an example source code of other MTK soc for parse_clk_from_dt()?
+static const struct mtk_dpi_conf mt8173_conf = {
- .parse_clk_from_dt = mt8173_parse_clk_from_dt,
- .clk_config = mt8173_clk_config,
+};
+static const struct of_device_id mtk_dpi_of_ids[] = {
- { .compatible = "mediatek,mt8173-dpi",
.data = &mt8173_conf,- },
- {}
+};
static int mtk_dpi_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct mtk_dpi *dpi; struct resource *mem;
struct device_node *np = dev->of_node; struct device_node *ep, *bridge_node = NULL; int comp_id;
const struct of_device_id *match;
struct mtk_dpi_conf *conf; int ret;
match = of_match_node(mtk_dpi_of_ids, dev->of_node);
if (!match)
return -ENODEV;dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL); if (!dpi) return -ENOMEM;
dpi->dev = dev;
dpi->data = (void *)match->data;
conf = (struct mtk_dpi_conf *)match->data;
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); dpi->regs = devm_ioremap_resource(dev, mem);
@@ -679,24 +777,9 @@ static int mtk_dpi_probe(struct platform_device *pdev) return ret; }
- dpi->engine_clk = devm_clk_get(dev, "engine");
- if (IS_ERR(dpi->engine_clk)) {
ret = PTR_ERR(dpi->engine_clk);dev_err(dev, "Failed to get engine clock: %d\n", ret);return ret;- }
- dpi->pixel_clk = devm_clk_get(dev, "pixel");
- if (IS_ERR(dpi->pixel_clk)) {
ret = PTR_ERR(dpi->pixel_clk);dev_err(dev, "Failed to get pixel clock: %d\n", ret);return ret;- }
- dpi->tvd_clk = devm_clk_get(dev, "pll");
- if (IS_ERR(dpi->tvd_clk)) {
ret = PTR_ERR(dpi->tvd_clk);dev_err(dev, "Failed to get tvdpll clock: %d\n", ret);
- ret = conf->parse_clk_from_dt(dpi, np);
- if (ret) {
dev_err(dev, "parse tvd div clk failed!");@@ -754,11 +837,6 @@ static int mtk_dpi_remove(struct platform_device *pdev) return 0; }
-static const struct of_device_id mtk_dpi_of_ids[] = {
- { .compatible = "mediatek,mt8173-dpi", },
- {}
-};
struct platform_driver mtk_dpi_driver = { .probe = mtk_dpi_probe, .remove = mtk_dpi_remove,
Regards, CK
Regards, CK
Hi, CK,
Thanks for your comments.
On Mon, 2016-07-25 at 14:49 +0800, CK Hu wrote:
Hi, Bibby:
On Mon, 2016-07-25 at 14:24 +0800, Bibby Hsieh wrote:
Hi, CK,
Thanks for your comments.
On Wed, 2016-07-20 at 15:57 +0800, CK Hu wrote:
Hi, Bibby:
Some comments inline.
On Wed, 2016-07-20 at 12:03 +0800, Bibby Hsieh wrote:
From: Junzhi Zhao junzhi.zhao@mediatek.com
Pixel clock should be 297MHz when resolution is 4K.
Signed-off-by: Junzhi Zhao junzhi.zhao@mediatek.com Signed-off-by: Bibby Hsieh bibby.hsieh@mediatek.com
drivers/gpu/drm/mediatek/mtk_dpi.c | 184 +++++++++++++++++++++++++----------- 1 file changed, 131 insertions(+), 53 deletions(-)
[snip...]
+static int mt8173_parse_clk_from_dt(struct mtk_dpi *dpi, struct device_node *np) +{
- int i;
- for (i = 0; i < ARRAY_SIZE(mtk_dpi_clk_names); i++) {
dpi->clk[i] = of_clk_get_by_name(np,mtk_dpi_clk_names[i]);if (IS_ERR(dpi->clk[i]))return PTR_ERR(dpi->clk[i]);- }
- return 0;
+}
I think parsing device tree is a pure SW behavior. Would this vary for different MTK soc?
Yes
I can not imaging that, so could you give me an example source code of other MTK soc for parse_clk_from_dt()?
I will do some changes according to your comments.
+static const struct mtk_dpi_conf mt8173_conf = {
- .parse_clk_from_dt = mt8173_parse_clk_from_dt,
- .clk_config = mt8173_clk_config,
+};
+static const struct of_device_id mtk_dpi_of_ids[] = {
- { .compatible = "mediatek,mt8173-dpi",
.data = &mt8173_conf,- },
- {}
+};
static int mtk_dpi_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct mtk_dpi *dpi; struct resource *mem;
struct device_node *np = dev->of_node; struct device_node *ep, *bridge_node = NULL; int comp_id;
const struct of_device_id *match;
struct mtk_dpi_conf *conf; int ret;
match = of_match_node(mtk_dpi_of_ids, dev->of_node);
if (!match)
return -ENODEV;dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL); if (!dpi) return -ENOMEM;
dpi->dev = dev;
dpi->data = (void *)match->data;
conf = (struct mtk_dpi_conf *)match->data;
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); dpi->regs = devm_ioremap_resource(dev, mem);
@@ -679,24 +777,9 @@ static int mtk_dpi_probe(struct platform_device *pdev) return ret; }
- dpi->engine_clk = devm_clk_get(dev, "engine");
- if (IS_ERR(dpi->engine_clk)) {
ret = PTR_ERR(dpi->engine_clk);dev_err(dev, "Failed to get engine clock: %d\n", ret);return ret;- }
- dpi->pixel_clk = devm_clk_get(dev, "pixel");
- if (IS_ERR(dpi->pixel_clk)) {
ret = PTR_ERR(dpi->pixel_clk);dev_err(dev, "Failed to get pixel clock: %d\n", ret);return ret;- }
- dpi->tvd_clk = devm_clk_get(dev, "pll");
- if (IS_ERR(dpi->tvd_clk)) {
ret = PTR_ERR(dpi->tvd_clk);dev_err(dev, "Failed to get tvdpll clock: %d\n", ret);
- ret = conf->parse_clk_from_dt(dpi, np);
- if (ret) {
dev_err(dev, "parse tvd div clk failed!");@@ -754,11 +837,6 @@ static int mtk_dpi_remove(struct platform_device *pdev) return 0; }
-static const struct of_device_id mtk_dpi_of_ids[] = {
- { .compatible = "mediatek,mt8173-dpi", },
- {}
-};
struct platform_driver mtk_dpi_driver = { .probe = mtk_dpi_probe, .remove = mtk_dpi_remove,
Regards, CK
Regards, CK
Am Mittwoch, den 20.07.2016, 12:03 +0800 schrieb Bibby Hsieh:
From: Junzhi Zhao junzhi.zhao@mediatek.com
Pixel clock should be 297MHz when resolution is 4K.
Signed-off-by: Junzhi Zhao junzhi.zhao@mediatek.com Signed-off-by: Bibby Hsieh bibby.hsieh@mediatek.com
drivers/gpu/drm/mediatek/mtk_dpi.c | 184 +++++++++++++++++++++++++----------- 1 file changed, 131 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index d05ca79..c0f04d2 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -60,14 +60,35 @@ enum mtk_dpi_out_color_format { MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL };
+enum mtk_dpi_clk_id {
- MTK_DPI_CLK_DPI_ENGINE,
- MTK_DPI_CLK_DPI_PIXEL,
- MTK_DPI_CLK_TVD_PLL,
- MTK_DPI_CLK_TVDPLL_MUX,
- MTK_DPI_CLK_TVDPLL_D2,
- MTK_DPI_CLK_TVDPLL_D4,
- MTK_DPI_CLK_TVDPLL_D8,
- MTK_DPI_CLK_TVDPLL_D16,
- MTK_DPI_CLK_COUNT,
+};
I think this is going in the wrong direction. If the pixel clock output isn't correct after a clk_set_rate(dpi->pixel_clk, rate), the clock drivers should be fixed, not worked around in the dpi driver.
The TVDPLL_* mux and dividers are not direct inputs to the DPI module:
tvdpll ("pll") | ..|\ v ..| | mm_sel ----> mm_dpi_engine ("engine") tvdpll_594m(1/3) ..|/ | |`-> tvdpll_d2 -->|\ |`-> tvdpll_d4 -->| | dpi0_sel --> mm_dpi_pixel ("pixel") |`-> tvdpll_d8 -->| | `--> tvdpll_d16 ->|/
Currently the code first sets the "pll" to the desired multiple of the pixel clock manually (*3*4, *3*8) and than calls clk_set_rate on the "pixel" clock which gets propagated by the clock framework up to dpi0_sel. Since dpi0_sel doesn't have the CLK_SET_RATE_PARENT flag set, it should just choose the tvdpll_d* input divider. I'd like not to give the dpi driver direct access to all the intermediate clocks.
regards Philipp
Hi, Philipp,
Thanks for your comment.
On Wed, 2016-07-20 at 11:41 +0200, Philipp Zabel wrote:
Am Mittwoch, den 20.07.2016, 12:03 +0800 schrieb Bibby Hsieh:
From: Junzhi Zhao junzhi.zhao@mediatek.com
Pixel clock should be 297MHz when resolution is 4K.
Signed-off-by: Junzhi Zhao junzhi.zhao@mediatek.com Signed-off-by: Bibby Hsieh bibby.hsieh@mediatek.com
drivers/gpu/drm/mediatek/mtk_dpi.c | 184 +++++++++++++++++++++++++----------- 1 file changed, 131 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index d05ca79..c0f04d2 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -60,14 +60,35 @@ enum mtk_dpi_out_color_format { MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL };
+enum mtk_dpi_clk_id {
- MTK_DPI_CLK_DPI_ENGINE,
- MTK_DPI_CLK_DPI_PIXEL,
- MTK_DPI_CLK_TVD_PLL,
- MTK_DPI_CLK_TVDPLL_MUX,
- MTK_DPI_CLK_TVDPLL_D2,
- MTK_DPI_CLK_TVDPLL_D4,
- MTK_DPI_CLK_TVDPLL_D8,
- MTK_DPI_CLK_TVDPLL_D16,
- MTK_DPI_CLK_COUNT,
+};
I think this is going in the wrong direction. If the pixel clock output isn't correct after a clk_set_rate(dpi->pixel_clk, rate), the clock drivers should be fixed, not worked around in the dpi driver.
The TVDPLL_* mux and dividers are not direct inputs to the DPI module:
tvdpll ("pll") | ..|\ v ..| | mm_sel ----> mm_dpi_engine ("engine") tvdpll_594m(1/3) ..|/ | |`-> tvdpll_d2 -->|\ |`-> tvdpll_d4 -->| | dpi0_sel --> mm_dpi_pixel ("pixel") |`-> tvdpll_d8 -->| | `--> tvdpll_d16 ->|/
Currently the code first sets the "pll" to the desired multiple of the pixel clock manually (*3*4, *3*8) and than calls clk_set_rate on the "pixel" clock which gets propagated by the clock framework up to dpi0_sel. Since dpi0_sel doesn't have the CLK_SET_RATE_PARENT flag set, it should just choose the tvdpll_d* input divider. I'd like not to give the dpi driver direct access to all the intermediate clocks.
Ok, I will make some modifications according to your comment.
regards Philipp
if MT8173 display module can support 4K HDMI output, we have to adjust VENCPLL clock from default 660MHz to 800MHz.
Signed-off-by: Bibby Hsieh bibby.hsieh@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 9 +++++++++ drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + 2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index b1223d5..f159189 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -23,6 +23,7 @@ #include <linux/of_address.h> #include <linux/of_platform.h> #include <linux/pm_runtime.h> +#include <linux/clk.h>
#include "mtk_drm_crtc.h" #include "mtk_drm_ddp.h" @@ -363,6 +364,14 @@ static int mtk_drm_probe(struct platform_device *pdev) return ret; }
+ private->vencpll_clk = devm_clk_get(dev, "vencpll"); + if (IS_ERR(private->vencpll_clk)) { + ret = PTR_ERR(private->vencpll_clk); + dev_err(dev, "Failed to get vencpll clock: %d\n", ret); + return ret; + } + clk_set_rate(private->vencpll_clk, 800000000); + /* Iterate over sibling DISP function blocks */ for_each_child_of_node(dev->of_node->parent, node) { const struct of_device_id *of_id; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index aa93894..273ad02 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -40,6 +40,7 @@ struct mtk_drm_private { void __iomem *config_regs; struct device_node *comp_node[DDP_COMPONENT_ID_MAX]; struct mtk_ddp_comp *ddp_comp[DDP_COMPONENT_ID_MAX]; + struct clk *vencpll_clk;
struct { struct drm_atomic_state *state;
Hi Bibby,
Am Mittwoch, den 20.07.2016, 12:03 +0800 schrieb Bibby Hsieh:
if MT8173 display module can support 4K HDMI output, we have to adjust VENCPLL clock from default 660MHz to 800MHz.
Is vencpll(_d2) the active source for the mm_sel mux? If so, it seems to me that mm_sel or rather one of its children should be set to 800 MHz, and the clock framework should propagate it up to vencpll. I suppose the requirement is that the input clocks to all the display units (ovl, rdma, and so on) need to be sufficiently above the pixel clock.
Also, this reads as if we want to keep the clock at 660 MHz if 4K is not supported at all (for example because of a bridge connected at the outside). Actually, would it be desirable to switch vencpll to 660 MHz even on 4K capable devices as long as only lower pixel clocks are active?
regards Philipp
Signed-off-by: Bibby Hsieh bibby.hsieh@mediatek.com
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 9 +++++++++ drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + 2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index b1223d5..f159189 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -23,6 +23,7 @@ #include <linux/of_address.h> #include <linux/of_platform.h> #include <linux/pm_runtime.h> +#include <linux/clk.h>
#include "mtk_drm_crtc.h" #include "mtk_drm_ddp.h" @@ -363,6 +364,14 @@ static int mtk_drm_probe(struct platform_device *pdev) return ret; }
- private->vencpll_clk = devm_clk_get(dev, "vencpll");
- if (IS_ERR(private->vencpll_clk)) {
ret = PTR_ERR(private->vencpll_clk);dev_err(dev, "Failed to get vencpll clock: %d\n", ret);return ret;- }
- clk_set_rate(private->vencpll_clk, 800000000);
- /* Iterate over sibling DISP function blocks */ for_each_child_of_node(dev->of_node->parent, node) { const struct of_device_id *of_id;
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index aa93894..273ad02 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -40,6 +40,7 @@ struct mtk_drm_private { void __iomem *config_regs; struct device_node *comp_node[DDP_COMPONENT_ID_MAX]; struct mtk_ddp_comp *ddp_comp[DDP_COMPONENT_ID_MAX];
struct clk *vencpll_clk;
struct { struct drm_atomic_state *state;
dri-devel@lists.freedesktop.org
-
Bibby Hsieh -
CK Hu -
Philipp Zabel