The following patch-series adds support for emtrion's emCON-MX6 modules with all their dependencies. The focus is based on the emtion standard developer-kit configuration. It includes a new vendor-prefix, an new simple-panel type, a small modification of the imx6dl.dtsi, as well as modifications of the common imx_v6_v8_defconfig. And finally the board devicetrees themselves.
emtrion GmbH Kreativpark - Alter Schlachthof 45 76131 Karlsruhe GERMANY http://www.emtrion.de _______________________________________
Amtsgericht Mannheim HRB 110 300 Geschäftsführer: Dieter Baur, Ramona Maurer _______________________________________
The Emerging Display Technology ETM0700G0BDH6 is exactly the same display as the ETM0700G0DH6, exept the pixelclock polarity. Therefore re-use the ETM0700G0DH6 modes. It is used by default on emtrion Avari based development kits.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com --- .../bindings/display/panel/edt,etm0700g0bdh6.txt | 9 +++++++++ drivers/gpu/drm/panel/panel-simple.c | 15 +++++++++++++++ 2 files changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/edt,etm0700g0bdh6.txt
diff --git a/Documentation/devicetree/bindings/display/panel/edt,etm0700g0bdh6.txt b/Documentation/devicetree/bindings/display/panel/edt,etm0700g0bdh6.txt new file mode 100644 index 000000000000..099e30bfa17f --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/edt,etm0700g0bdh6.txt @@ -0,0 +1,9 @@ +Emerging Display Technology Corp. ETM0700G0BDH6 7.0" WVGA TFT LCD panel + +Required properties: + compatible: "edt,etm0700g0bdh6" + +This panel is exactly the same as ETM0700G0DH6 except the pixelclock polarity. + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index b7c4709f7b34..42442034b53e 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -886,6 +886,18 @@ static const struct panel_desc edt_etm0700g0dh6 = { .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, };
+static const struct panel_desc edt_etm0700g0bdh6 = { + .modes = &edt_etm0700g0dh6_mode, + .num_modes = 1, + .bpc = 6, + .size = { + .width = 152, + .height = 91, + }, + .bus_format = MEDIA_BUS_FMT_RGB666_1X18, + .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, +}; + static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { .clock = 32260, .hdisplay = 800, @@ -2029,6 +2041,9 @@ static const struct of_device_id platform_of_match[] = { .compatible = "edt,etm0700g0dh6", .data = &edt_etm0700g0dh6, }, { + .compatible = "edt,etm0700g0bdh6", + .data = &edt_etm0700g0bdh6, + }, { .compatible = "foxlink,fl500wvr00-a0t", .data = &foxlink_fl500wvr00_a0t, }, { -- 2.11.0
emtrion GmbH Kreativpark - Alter Schlachthof 45 76131 Karlsruhe GERMANY http://www.emtrion.de _______________________________________
Amtsgericht Mannheim HRB 110 300 Geschäftsführer: Dieter Baur, Ramona Maurer _______________________________________
Hi Jan,
On Thu, Nov 23, 2017 at 10:55 AM, Jan Tuerk jan.tuerk@emtrion.com wrote:
The Emerging Display Technology ETM0700G0BDH6 is exactly the same display as the ETM0700G0DH6, exept the pixelclock polarity. Therefore re-use the ETM0700G0DH6 modes. It is used by default on emtrion Avari based development kits.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com
Please run ./scripts/checkpatch.pl on your patch. Currently it gives: total: 18 errors, 13 warnings, 39 lines checked
Please fix and resend. Also, you could try git send-email in the next time.
Regards,
Fabio Estevam
Hi Fabio,
I've used git send-email and tested the patches by checkpatch.pl before without any problems. So it might have been touched by the mail server, so can you send me your checkpatch.pl log (directly)?
Regards, Jan Tuerk
emtrion GmbH Kreativpark - Alter Schlachthof 45 76131 Karlsruhe GERMANY http://www.emtrion.de _______________________________________
Amtsgericht Mannheim HRB 110 300 Geschäftsführer: Dieter Baur, Ramona Maurer _______________________________________
Hi Jan,
On Thu, Nov 23, 2017 at 1:18 PM, Türk, Jan Jan.Tuerk@emtrion.de wrote:
Hi Fabio,
I've used git send-email and tested the patches by checkpatch.pl before without any problems. So it might have been touched by the mail server, so can you send me your checkpatch.pl log (directly)?
Take a look at your patch here: https://patchwork.kernel.org/patch/10072765/
Click in the "patch" link and download it. You will notice that all tabs have been converted into spaces.
checkpatch will warn about it.
Hi Fabio, (and all others)
Von: Fabio Estevam [mailto:festevam@gmail.com] Gesendet: Freitag, 24. November 2017 15:22 Betreff: Re: [PATCH 1/5] drm/panel: Add support for the EDT ETM0700G0BDH6
Hi Jan,
On Thu, Nov 23, 2017 at 1:18 PM, Türk, Jan Jan.Tuerk@emtrion.de wrote:
Hi Fabio,
I've used git send-email and tested the patches by checkpatch.pl before
without any problems.
So it might have been touched by the mail server, so can you send me your
checkpatch.pl log (directly)?
Take a look at your patch here: https://patchwork.kernel.org/patch/10072765/
Click in the "patch" link and download it. You will notice that all tabs have been converted into spaces.
checkpatch will warn about it.
thanks for your feedback. Meanwhile I also did some investigation and found out that our SMTP modified the message in the redmond style. I'll resend the patches as soon as the issue has been solved.
emtrion GmbH Kreativpark - Alter Schlachthof 45 76131 Karlsruhe GERMANY http://www.emtrion.de _______________________________________
Amtsgericht Mannheim HRB 110 300 Geschäftsführer: Dieter Baur, Ramona Maurer _______________________________________
On Thu, Nov 23, 2017 at 01:55:51PM +0100, Jan Tuerk wrote:
The Emerging Display Technology ETM0700G0BDH6 is exactly the same display as the ETM0700G0DH6, exept the pixelclock polarity. Therefore re-use the ETM0700G0DH6 modes. It is used by default on emtrion Avari based development kits.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com
.../bindings/display/panel/edt,etm0700g0bdh6.txt | 9 +++++++++ drivers/gpu/drm/panel/panel-simple.c | 15 +++++++++++++++ 2 files changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/edt,etm0700g0bdh6.txt
diff --git a/Documentation/devicetree/bindings/display/panel/edt,etm0700g0bdh6.txt b/Documentation/devicetree/bindings/display/panel/edt,etm0700g0bdh6.txt new file mode 100644 index 000000000000..099e30bfa17f --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/edt,etm0700g0bdh6.txt @@ -0,0 +1,9 @@ +Emerging Display Technology Corp. ETM0700G0BDH6 7.0" WVGA TFT LCD panel
+Required properties:
compatible: "edt,etm0700g0bdh6"+This panel is exactly the same as ETM0700G0DH6 except the pixelclock polarity.
Perhaps document them together.
+This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory.
emtrion is a system integrator and manufacturer of embedded systems.
Website: https://www.emtrion.de
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 0994bdd82cd3..5215c5767260 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -102,6 +102,7 @@ eeti eGalax_eMPIA Technology Inc elan Elan Microelectronic Corp. embest Shenzhen Embest Technology Co., Ltd. emmicro EM Microelectronic +emtrion emtrion GmbH energymicro Silicon Laboratories (formerly Energy Micro AS) engicam Engicam S.r.l. epcos EPCOS AG -- 2.11.0
emtrion GmbH Kreativpark - Alter Schlachthof 45 76131 Karlsruhe GERMANY http://www.emtrion.de _______________________________________
Amtsgericht Mannheim HRB 110 300 Geschäftsführer: Dieter Baur, Ramona Maurer _______________________________________
Am 23.11.2017 um 13:55 schrieb Jan Tuerk:
emtrion is a system integrator and manufacturer of embedded systems.
Website: https://www.emtrion.de
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+)
Reviewed-by: Andreas Färber afaerber@suse.de
Regards, Andreas
On Thu, Nov 23, 2017 at 01:55:52PM +0100, Jan Tuerk wrote:
emtrion is a system integrator and manufacturer of embedded systems.
Website: https://www.emtrion.de
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+)
Acked-by: Rob Herring robh@kernel.org
Adding the label cpu0 allows the adjustment of cpu-parameters by reference in overlaying dtsi files in the same way as it is possible for imx6q devices.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com --- arch/arm/boot/dts/imx6dl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 4d693a75ce98..623c12519b81 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -21,7 +21,7 @@ #address-cells = <1>; #size-cells = <0>;
- cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; -- 2.11.0
emtrion GmbH Kreativpark - Alter Schlachthof 45 76131 Karlsruhe GERMANY http://www.emtrion.de _______________________________________
Amtsgericht Mannheim HRB 110 300 Geschäftsführer: Dieter Baur, Ramona Maurer _______________________________________
Am 23.11.2017 um 13:55 schrieb Jan Tuerk:
Adding the label cpu0 allows the adjustment of cpu-parameters by reference in overlaying dtsi files in the same way as it is possible for imx6q devices.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com
arch/arm/boot/dts/imx6dl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Andreas Färber afaerber@suse.de
Thanks, Andreas
This patch adds support for the emtrion GmbH emCON-MX6 modules. They are available with imx.6 Solo, Dual-Lite, Dual and Quad equipped with Memory from 512MB to 2GB (configured by U-Boot).
Our default developer-Kit ships with the Avari baseboard and the EDT ETM0700G0BDH6 Display (imx6[q|dl]-emcon-avari).
The devicetree is split into the common part providing all module components and the basic support for all SoC versions (imx6qdl-emcon.dtsi) and parts which are i.mx6 S|DL and D|Q relevant. Finally the support for the avari baseboard in the developer-kit configuration is provided by the emcon-avari dts files.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com --- Documentation/devicetree/bindings/arm/emtrion.txt | 13 + arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx6dl-emcon-avari.dts | 233 ++++++ arch/arm/boot/dts/imx6dl-emcon.dtsi | 37 + arch/arm/boot/dts/imx6q-emcon-avari.dts | 233 ++++++ arch/arm/boot/dts/imx6q-emcon.dtsi | 37 + arch/arm/boot/dts/imx6qdl-emcon.dtsi | 849 ++++++++++++++++++++++ 7 files changed, 1404 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/emtrion.txt create mode 100644 arch/arm/boot/dts/imx6dl-emcon-avari.dts create mode 100644 arch/arm/boot/dts/imx6dl-emcon.dtsi create mode 100644 arch/arm/boot/dts/imx6q-emcon-avari.dts create mode 100644 arch/arm/boot/dts/imx6q-emcon.dtsi create mode 100644 arch/arm/boot/dts/imx6qdl-emcon.dtsi
diff --git a/Documentation/devicetree/bindings/arm/emtrion.txt b/Documentation/devicetree/bindings/arm/emtrion.txt new file mode 100644 index 000000000000..3ff6c6c2034d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/emtrion.txt @@ -0,0 +1,13 @@ +Emtrion Devicetree Bindings +=========================== + +emCON Series: +------------- + +Required root node properties + - compatible: + - "emtrion,emcon-mx6", "fsl,imx6q", "fsl,imx6dl"; : emCON-MX6 Generic SoM + - "emtrion,emcon-mx6", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM + - "emtrion,emcon-mx6-avari", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM on Avari Base + - "emtrion,emcon-mx6", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM + - "emtrion,emcon-mx6-avari", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM on Avari Base diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d0381e9caf21..5ce643ece228 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -373,6 +373,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-colibri-eval-v3.dtb \ imx6dl-cubox-i.dtb \ imx6dl-dfi-fs700-m60.dtb \ + imx6dl-emcon-avari.dtb \ imx6dl-gw51xx.dtb \ imx6dl-gw52xx.dtb \ imx6dl-gw53xx.dtb \ @@ -424,6 +425,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-dfi-fs700-m60.dtb \ imx6q-display5-tianma-tm070-1280x768.dtb \ imx6q-dmo-edmqmx6.dtb \ + imx6q-emcon-avari.dtb \ imx6q-evi.dtb \ imx6q-gk802.dtb \ imx6q-gw51xx.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-emcon-avari.dts b/arch/arm/boot/dts/imx6dl-emcon-avari.dts new file mode 100644 index 000000000000..f8ca63258eda --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-emcon-avari.dts @@ -0,0 +1,233 @@ +/* + * Copyright (C) 2017 emtrion GmbH + * Author: Jan Tuerk jan.tuerk@emtrion.com + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-emcon.dtsi" +#include "imx6dl-emcon.dtsi" /*Include camera2 pinmux*/ + +/ { + model = "emtrion SoM emCON-MX6 Solo/Dual-Lite Avari"; + compatible = "emtrion,emcon-mx6-avari", "fsl,imx6dl"; + + aliases { + mmc0 = &usdhc3; + mmc2 = &usdhc1; + mmc1 = &usdhc2; + mmc3 = &usdhc4; + }; + + chosen { + stdout-path = <&uart1>; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + supplies { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + wallplug5p0: supply@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "WALL-PLUG"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + base3p3: supply@1 { + compatible = "regulator-fixed"; + reg = <1>; + vin-supply = <&wallplug5p0>; + regulator-name = "3V3-avari"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + base1p5: supply@2 { + compatible = "regulator-fixed"; + reg = <2>; + vin-supply = <&base3p3>; + regulator-name = "1V5-avari"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_usb_otg: otgvbus { + compatible = "regulator-fixed"; + reg = <3>; + vin-supply = <&wallplug5p0>; + regulator-name = "OTG_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + }; + + + sndosc: 12MHZosc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "emCON-avari-sgtl5000"; + ssi-controller = <&ssi2>; + audio-codec = <&sgtl5000>; + audio-routing = + "Headphone Jack", "HP_OUT"; + mux-int-port = <2>; + mux-ext-port = <3>; + }; + +}; + + +&iomuxc { + pinctrl-names = "default"; + /*Unused emCON-MX6 outputs on AVARI*/ + pinctrl-0 = < + &pinctrl_emcon_gpio1 &pinctrl_emcon_gpio2 + &pinctrl_emcon_gpio3 &pinctrl_emcon_gpio5 + &pinctrl_emcon_gpio6 &pinctrl_emcon_gpio7 + &pinctrl_emcon_gpio8 &pinctrl_emcon_irq_a + &pinctrl_emcon_irq_b &pinctrl_emcon_irq_c + &pinctrl_emcon_irq_pwr &pinctrl_nor_flash + &pinctrl_usdhc2 + &pinctrl_spdif_out &pinctrl_spdif_in + &pinctrl_cpi1 &pinctrl_cpi2 + >; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + + + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + sgtl5000: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&sndosc>; + VDDA-supply = <&base3p3>; + VDDIO-supply = <&base3p3>; + }; + + boardID: pca8754a@3A { + compatible = "nxp,pca8574"; + reg = <0x3A>; + gpio-controller; + #gpio-cells = <1>; + }; + + captouch: edt-ft5x06@38 { + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_irq_touch2 &pinctrl_emcon_gpio4>; + interrupt-parent = <&gpio6>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + compatible = "edt,edt-ft5406"; + wake-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + wakeup-source; + }; +}; + +&ssi2 { + status = "okay"; +}; + +&rgb_encoder { + status = "okay"; +}; + +&rgb_panel { + compatible = "edt,etm0700g0bdh6"; + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "okay"; +}; + +&uart2 { + status = "okay"; + uart-has-rtscts; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&ecspi2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-emcon.dtsi b/arch/arm/boot/dts/imx6dl-emcon.dtsi new file mode 100644 index 000000000000..47f43bae5ac5 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-emcon.dtsi @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2017 emtrion GmbH + * Author: Jan Tuerk jan.tuerk@emtrion.com + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +/ { + model = "emtrion SoM emCON-MX6 Solo/DualLite"; + compatible = "emtrion,emcon-mx6","fsl,imx6dl"; +}; + +&iomuxc { + pinctrl_cpi2: csi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0x0b0b1 + MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b1 + MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b1 + MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b1 + MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b1 + MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b1 + MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b1 + MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b1 + MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b1 + MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b1 + MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-emcon-avari.dts b/arch/arm/boot/dts/imx6q-emcon-avari.dts new file mode 100644 index 000000000000..bccfd6344c18 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-emcon-avari.dts @@ -0,0 +1,233 @@ +/* + * Copyright (C) 2017 emtrion GmbH + * Author: Jan Tuerk jan.tuerk@emtrion.com + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-emcon.dtsi" +#include "imx6q-emcon.dtsi" /*Include camera2 pinmux*/ + +/ { + model = "emtrion SoM emCON-MX6 Dual/Quad on Avari"; + compatible = "emtrion,emcon-mx6-avari", "fsl,imx6q"; + + aliases { + mmc0 = &usdhc3; + mmc2 = &usdhc1; + mmc1 = &usdhc2; + mmc3 = &usdhc4; + }; + + chosen { + stdout-path = <&uart1>; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + supplies { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + wallplug5p0: supply@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "WALL-PLUG"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + base3p3: supply@1 { + compatible = "regulator-fixed"; + reg = <1>; + vin-supply = <&wallplug5p0>; + regulator-name = "3V3-avari"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + base1p5: supply@2 { + compatible = "regulator-fixed"; + reg = <2>; + vin-supply = <&base3p3>; + regulator-name = "1V5-avari"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_usb_otg: otgvbus { + compatible = "regulator-fixed"; + reg = <3>; + vin-supply = <&wallplug5p0>; + regulator-name = "OTG_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + }; + + + sndosc: 12MHZosc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "emCON-avari-sgtl5000"; + ssi-controller = <&ssi2>; + audio-codec = <&sgtl5000>; + audio-routing = + "Headphone Jack", "HP_OUT"; + mux-int-port = <2>; + mux-ext-port = <3>; + }; + +}; + + +&iomuxc { + pinctrl-names = "default"; + /*Unused emCON-MX6 pingroups on AVARI baseboard, enable defaults*/ + pinctrl-0 = < + &pinctrl_emcon_gpio1 &pinctrl_emcon_gpio2 + &pinctrl_emcon_gpio3 &pinctrl_emcon_gpio5 + &pinctrl_emcon_gpio6 &pinctrl_emcon_gpio7 + &pinctrl_emcon_gpio8 &pinctrl_emcon_irq_a + &pinctrl_emcon_irq_b &pinctrl_emcon_irq_c + &pinctrl_emcon_irq_pwr &pinctrl_nor_flash + &pinctrl_usdhc2 + &pinctrl_spdif_out &pinctrl_spdif_in + &pinctrl_cpi1 &pinctrl_cpi2 + >; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + + + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + sgtl5000: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&sndosc>; + VDDA-supply = <&base3p3>; + VDDIO-supply = <&base3p3>; + }; + + boardID: pca8754a@3A { + compatible = "nxp,pca8574"; + reg = <0x3A>; + gpio-controller; + #gpio-cells = <1>; + }; + + captouch: edt-ft5x06@38 { + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_irq_touch2 &pinctrl_emcon_gpio4>; + interrupt-parent = <&gpio6>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + compatible = "edt,edt-ft5406"; + wake-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + wakeup-source; + }; +}; + +&ssi2 { + status = "okay"; +}; + +&rgb_encoder { + status = "okay"; +}; + +&rgb_panel { + compatible = "edt,etm0700g0bdh6"; + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "okay"; +}; + +&uart2 { + status = "okay"; + uart-has-rtscts; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&ecspi2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q-emcon.dtsi b/arch/arm/boot/dts/imx6q-emcon.dtsi new file mode 100644 index 000000000000..64fc0cd74c05 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-emcon.dtsi @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2017 emtrion GmbH + * Author: Jan Tuerk jan.tuerk@emtrion.com + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +/ { + model = "emtrion SoM emCON-MX6 Dual/Quad"; + compatible = "emtrion,emcon-mx6","fsl,imx6q"; +}; + +&iomuxc { + pinctrl_cpi2: csi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__IPU2_CSI1_PIXCLK 0x0b0b1 + MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b1 + MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b1 + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b1 + MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b1 + MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b1 + MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b1 + MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b1 + MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b1 + MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b1 + MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-emcon.dtsi b/arch/arm/boot/dts/imx6qdl-emcon.dtsi new file mode 100644 index 000000000000..22ad05880ea7 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-emcon.dtsi @@ -0,0 +1,849 @@ +/* + * Copyright (C) 2017 emtrion GmbH + * Author: Jan Tuerk jan.tuerk@emtrion.com + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/input/input.h> + +/ { + + model = "emtrion SoM emCON-MX6"; + compatible = "emtrion,emcon-mx6","fsl,imx6q", "fsl,imx6dl"; + + aliases { + mmc0 = &usdhc3; + mmc2 = &usdhc1; + mmc1 = &usdhc2; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_parallel_disp: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgb_bl_en>; + regulator-name = "LCD-Supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio7 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_lvds_disp: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "LVDS-Supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio7 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + som_leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_som_leds>; + + green { + label = "som:green"; + gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + + red { + label = "som:red"; + gpios = <&gpio3 1 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emcon_wake>; + + wake { + label = "Wake"; + linux,code = <KEY_WAKEUP>; + gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + pwm_fan: pwm-fan { + compatible = "pwm-fan"; + cooling-min-state = <0>; + cooling-max-state = <4>; + #cooling-cells = <2>; + pwms = <&pwm4 0 50000>; + cooling-levels = <0 64 127 191 255>; + status = "disabled"; + }; + + rgb_encoder: lcd@di0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgb24_display>; + status = "disabled"; + + port@0 { + reg = <0>; + rgb_encoder_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + rgb_encoder_out: endpoint { + remote-endpoint = <&rgb_panel_in>; + }; + }; + }; + + rgb_panel: panel { + backlight = <&rgb_backlight>; + power-supply = <®_prallel_disp>; + port { + rgb_panel_in: endpoint { + remote-endpoint = <&rgb_encoder_out>; + }; + }; + }; + + rgb_backlight: rgb_backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgb_bl>; + enable-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; + pwms = <&pwm3 0 5000000>; + brightness-levels = <250 176 160 144 128 112 + 96 80 64 48 32 16 8 1 + >; + default-brightness-level = <13>; + status = "okay"; + }; + + lvds_backlight: lvds_backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds_bl>; + enable-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; + pwms = <&pwm1 0 50000>; + brightness-levels = <0 4 8 16 32 64 80 96 112 + 128 144 160 176 250 + >; + default-brightness-level = <13>; + status = "okay"; + }; +}; + + +&iomuxc { + + pinctrl_secure: securegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_emcon_gpio1: emcongpio1 { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio2: emcongpio2 { + fsl,pins = < + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio3: emcongpio3 { + fsl,pins = < + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio4: emcongpio4 { + fsl,pins = < + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio5: emcongpio5 { + fsl,pins = < + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio6: emcongpio6 { + fsl,pins = < + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio7: emcongpio7 { + fsl,pins = < + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio8: emcongpio8 { + fsl,pins = < + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0b0b1 + >; + }; + + pinctrl_emcon_irq_a: emconirqa { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x0b0b1 + >; + }; + + pinctrl_emcon_irq_b: emconirqb { + fsl,pins = < + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x0b0b1 + >; + }; + + pinctrl_emcon_irq_c: emconirqc { + fsl,pins = < + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0b0b1 + >; + }; + + pinctrl_emcon_wake: emconwake { + fsl,pins = < + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1 + >; + }; + + pinctrl_emcon_irq_pwr: emconirqpwr { + fsl,pins = < + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0b0b1 + >; + }; + + pinctrl_som_leds: somledgrp { + fsl,pins = < + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x0b0b1 + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x0b0b1 + >; + }; + + pinctrl_nor_flash: norflashgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b1 + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 + >; + }; + + pinctrl_pwm_fan: pwmfan { + fsl,pins = < + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x0b0b1 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b1 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b1 + >; + }; + + pinctrl_spdif_out: spdifout { + fsl,pins = < + MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091 + >; + }; + + pinctrl_spdif_in: spdifin { + fsl,pins = < + MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_cpi1: csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b1 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b1 + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b1 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b1 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b1 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b1 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b1 + >; + }; + + /*camera2-pinctrl is in imx6q-emcon.dtsi or imx6dl-emcon.dtsi*/ + + pinctrl_pcie_ctrl: pciegrp { + fsl,pins = < + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 + >; + }; + + pinctrl_audmux: audmux { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b060 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130B0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b060 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4000b070 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b870 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0b0b1 + >; + }; + + pinctrl_usb_host1: usbhgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x1B058 + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1B058 + >; + }; + + pinctrl_usb_otg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x17059 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x17059 + >; + }; + + pinctrl_lvds_reg: lvdsreggrp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x0b0b1 + >; + }; + + pinctrl_lvds_bl: lvdsbacklightgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x0b0b1 + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b1 + >; + }; + + pinctrl_irq_touch1: irqtouch1 { + fsl,pins = < + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x0b0b1 + >; + }; + + pinctrl_rgb_bl_en: rgbenable { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x0b0b1 + >; + }; + + pinctrl_irq_touch2: irqtouch2 { + fsl,pins = < + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x0b0b1 + >; + }; + + pinctrl_rgb_bl: rgbbacklightgrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x0b0b1 + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b1 + >; + }; + + pinctrl_rgb24_display: rgbgrp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x4001a0b1 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b058 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 + >; + }; + + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + MX6QDL_PAD_GPIO_1__SD1_CD_B 0x1b0b1 + MX6QDL_PAD_DI0_PIN4__SD1_WP 0x1b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_GPIO_4__SD2_CD_B 0x1b0b1 + MX6QDL_PAD_GPIO_2__SD2_WP 0x1b0b1 + >; + }; + +}; + + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + rtc: rtc@68 { + compatible = "dallas,ds1307"; + reg = <0x68>; + }; + + da9063: da9063@58 { + compatible = "dlg,da9063"; + reg = <0x58>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio2>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + + onkey { + wakeup-source; + compatible = "dlg,da9063-onkey"; + }; + + wdt { + compatible = "dlg,da9063-watchdog"; + timeout-sec = <0>; + }; + + regulators { + vddcore_reg: bcore1 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <20000>; + regulator-name = "DA9063_CORE"; + regulator-always-on; + }; + + vddsoc_reg: bcore2 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <20000>; + regulator-name = "DA9063_SOC"; + regulator-always-on; + }; + + vdd_ddr3_reg: bpro { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <20000>; + regulator-always-on; + }; + + vdd_3v3_reg: bperi { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <20000>; + regulator-always-on; + }; + + vdd_sata_reg: ldo3 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + vdd_mipi_reg: ldo4 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vdd_mx6_snvs_reg: ldo5 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_hdmi_reg: ldo6 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_pcie_reg: ldo7 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vdd_1V8_reg: ldo8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_3V3_sdc_reg: ldo9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_1V2_reg: ldo10 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; + phy-reset-duration = <50>; + phy-supply = <&vdd_1V8_reg>; + phy-handle = <&ksz9031>; + status = "okay"; + + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ksz9031: phy { + reg = <0>; + compatible = "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio1>; + interrupts = <30 IRQ_TYPE_EDGE_FALLING>; + rxdv-skew-ps = <480>; + txen-skew-ps = <480>; + rxd0-skew-ps = <480>; + rxd1-skew-ps = <480>; + rxd2-skew-ps = <480>; + rxd3-skew-ps = <480>; + txd0-skew-ps = <420>; + txd1-skew-ps = <420>; + txd2-skew-ps = <360>; + txd3-skew-ps = <360>; + txc-skew-ps = <1020>; + rxc-skew-ps = <960>; + }; + }; +}; + + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + non-removable; + bus-width = <8>; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_ctrl>; + reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; + disable-gpio = <&gpio2 22 GPIO_ACTIVE_LOW>; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + fsl,wp-controller; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + fsl,wp-controller; +}; + + +&ipu1_di0_disp0 { + remote-endpoint = <&rgb_encoder_in>; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>, + <&gpio2 26 GPIO_ACTIVE_HIGH>; +}; + +&ecspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nor_flash>; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_host1>; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg>; + vbus-supply = <®_usb_otg>; + dr_mode = "peripheral"; +}; + +/******device power Management*********/ + +&cpu0 { + voltage-tolerance = <2>; +}; + +®_arm { + vin-supply = <&vddcore_reg>; +}; + +®_soc { + vin-supply = <&vddsoc_reg>; +}; + +®_pu { + vin-supply = <&vddsoc_reg>; +}; + + + +/*******Disabled HW following***********/ + + +&weim { + status = "disabled"; +}; + +&snvs_rtc { + status = "disabled"; +}; + -- 2.11.0
emtrion GmbH Kreativpark - Alter Schlachthof 45 76131 Karlsruhe GERMANY http://www.emtrion.de _______________________________________
Amtsgericht Mannheim HRB 110 300 Geschäftsführer: Dieter Baur, Ramona Maurer _______________________________________
On Thu, Nov 23, 2017 at 01:55:54PM +0100, Jan Tuerk wrote:
This patch adds support for the emtrion GmbH emCON-MX6 modules. They are available with imx.6 Solo, Dual-Lite, Dual and Quad equipped with Memory from 512MB to 2GB (configured by U-Boot).
Our default developer-Kit ships with the Avari baseboard and the EDT ETM0700G0BDH6 Display (imx6[q|dl]-emcon-avari).
The devicetree is split into the common part providing all module components and the basic support for all SoC versions (imx6qdl-emcon.dtsi) and parts which are i.mx6 S|DL and D|Q relevant. Finally the support for the avari baseboard in the developer-kit configuration is provided by the emcon-avari dts files.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com
Documentation/devicetree/bindings/arm/emtrion.txt | 13 + arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx6dl-emcon-avari.dts | 233 ++++++ arch/arm/boot/dts/imx6dl-emcon.dtsi | 37 + arch/arm/boot/dts/imx6q-emcon-avari.dts | 233 ++++++ arch/arm/boot/dts/imx6q-emcon.dtsi | 37 + arch/arm/boot/dts/imx6qdl-emcon.dtsi | 849 ++++++++++++++++++++++ 7 files changed, 1404 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/emtrion.txt create mode 100644 arch/arm/boot/dts/imx6dl-emcon-avari.dts create mode 100644 arch/arm/boot/dts/imx6dl-emcon.dtsi create mode 100644 arch/arm/boot/dts/imx6q-emcon-avari.dts create mode 100644 arch/arm/boot/dts/imx6q-emcon.dtsi create mode 100644 arch/arm/boot/dts/imx6qdl-emcon.dtsi
diff --git a/Documentation/devicetree/bindings/arm/emtrion.txt b/Documentation/devicetree/bindings/arm/emtrion.txt new file mode 100644 index 000000000000..3ff6c6c2034d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/emtrion.txt @@ -0,0 +1,13 @@ +Emtrion Devicetree Bindings +===========================
+emCON Series: +-------------
+Required root node properties
- compatible:- "emtrion,emcon-mx6", "fsl,imx6q", "fsl,imx6dl"; : emCON-MX6 Generic SoM- "emtrion,emcon-mx6", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM- "emtrion,emcon-mx6-avari", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM on Avari Base- "emtrion,emcon-mx6", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM- "emtrion,emcon-mx6-avari", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM on Avari Basediff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d0381e9caf21..5ce643ece228 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -373,6 +373,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-colibri-eval-v3.dtb \ imx6dl-cubox-i.dtb \ imx6dl-dfi-fs700-m60.dtb \
imx6dl-emcon-avari.dtb \ imx6dl-gw51xx.dtb \ imx6dl-gw52xx.dtb \ imx6dl-gw53xx.dtb \@@ -424,6 +425,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-dfi-fs700-m60.dtb \ imx6q-display5-tianma-tm070-1280x768.dtb \ imx6q-dmo-edmqmx6.dtb \
imx6q-emcon-avari.dtb \ imx6q-evi.dtb \ imx6q-gk802.dtb \ imx6q-gw51xx.dtb \diff --git a/arch/arm/boot/dts/imx6dl-emcon-avari.dts b/arch/arm/boot/dts/imx6dl-emcon-avari.dts new file mode 100644 index 000000000000..f8ca63258eda --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-emcon-avari.dts @@ -0,0 +1,233 @@ +/*
- Copyright (C) 2017 emtrion GmbH
- Author: Jan Tuerk jan.tuerk@emtrion.com
- The code contained herein is licensed under the GNU General Public
- License. You may obtain a copy of the GNU General Public License
- Version 2 or later at the following locations:
- SPDX-License-Identifier: GPL-2.0
- */
+/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-emcon.dtsi" +#include "imx6dl-emcon.dtsi" /*Include camera2 pinmux*/
+/ {
model = "emtrion SoM emCON-MX6 Solo/Dual-Lite Avari";compatible = "emtrion,emcon-mx6-avari", "fsl,imx6dl";aliases {mmc0 = &usdhc3;mmc2 = &usdhc1;mmc1 = &usdhc2;mmc3 = &usdhc4;};chosen {stdout-path = <&uart1>;};memory {reg = <0x10000000 0x40000000>;};supplies {compatible = "simple-bus";#address-cells = <1>;#size-cells = <0>;wallplug5p0: supply@0 {compatible = "regulator-fixed";reg = <0>;regulator-name = "WALL-PLUG";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;regulator-always-on;regulator-boot-on;};base3p3: supply@1 {compatible = "regulator-fixed";reg = <1>;vin-supply = <&wallplug5p0>;regulator-name = "3V3-avari";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-always-on;regulator-boot-on;};base1p5: supply@2 {compatible = "regulator-fixed";reg = <2>;vin-supply = <&base3p3>;regulator-name = "1V5-avari";regulator-min-microvolt = <1500000>;regulator-max-microvolt = <1500000>;regulator-always-on;regulator-boot-on;};reg_usb_otg: otgvbus {compatible = "regulator-fixed";reg = <3>;vin-supply = <&wallplug5p0>;regulator-name = "OTG_VBUS";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;regulator-always-on;};};sndosc: 12MHZosc {compatible = "fixed-clock";#clock-cells = <0>;clock-frequency = <12000000>;};sound {compatible = "fsl,imx-audio-sgtl5000";model = "emCON-avari-sgtl5000";ssi-controller = <&ssi2>;audio-codec = <&sgtl5000>;audio-routing ="Headphone Jack", "HP_OUT";mux-int-port = <2>;mux-ext-port = <3>;};+};
+&iomuxc {
pinctrl-names = "default";/*Unused emCON-MX6 outputs on AVARI*/pinctrl-0 = <&pinctrl_emcon_gpio1 &pinctrl_emcon_gpio2&pinctrl_emcon_gpio3 &pinctrl_emcon_gpio5&pinctrl_emcon_gpio6 &pinctrl_emcon_gpio7&pinctrl_emcon_gpio8 &pinctrl_emcon_irq_a&pinctrl_emcon_irq_b &pinctrl_emcon_irq_c&pinctrl_emcon_irq_pwr &pinctrl_nor_flash&pinctrl_usdhc2&pinctrl_spdif_out &pinctrl_spdif_in&pinctrl_cpi1 &pinctrl_cpi2>;+};
+&audmux {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_audmux>;status = "okay";+};
+&i2c3 {
clock-frequency = <100000>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_i2c3>;status = "okay";sgtl5000: sgtl5000@0a {
audio-codec@a
same errors repeat below.
compatible = "fsl,sgtl5000";reg = <0x0a>;clocks = <&sndosc>;VDDA-supply = <&base3p3>;VDDIO-supply = <&base3p3>;};boardID: pca8754a@3A {
...@3a
compatible = "nxp,pca8574";reg = <0x3A>;
0x3a
gpio-controller;#gpio-cells = <1>;};captouch: edt-ft5x06@38 {
touchscreen@38
reg = <0x38>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_irq_touch2 &pinctrl_emcon_gpio4>;interrupt-parent = <&gpio6>;interrupts = <31 IRQ_TYPE_EDGE_FALLING>;compatible = "edt,edt-ft5406";wake-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;wakeup-source;};+};
+&ssi2 {
status = "okay";+};
+&rgb_encoder {
status = "okay";+};
+&rgb_panel {
compatible = "edt,etm0700g0bdh6";status = "okay";+};
+&i2c2 {
status = "okay";+};
+&hdmi {
ddc-i2c-bus = <&i2c2>;status = "okay";+};
+&usbh1 {
status = "okay";+};
+&usbotg {
status = "okay";+};
+&pcie {
status = "okay";+};
+&usdhc1 {
status = "okay";+};
+&can1 {
status = "okay";+};
+&can2 {
status = "okay";+};
+&uart2 {
status = "okay";uart-has-rtscts;+};
+&uart3 {
status = "okay";+};
+&uart4 {
status = "okay";+};
+&uart5 {
status = "okay";+};
+&ecspi2 {
status = "okay";+}; diff --git a/arch/arm/boot/dts/imx6dl-emcon.dtsi b/arch/arm/boot/dts/imx6dl-emcon.dtsi new file mode 100644 index 000000000000..47f43bae5ac5 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-emcon.dtsi @@ -0,0 +1,37 @@ +/*
- Copyright (C) 2017 emtrion GmbH
- Author: Jan Tuerk jan.tuerk@emtrion.com
- The code contained herein is licensed under the GNU General Public
- License. You may obtain a copy of the GNU General Public License
- Version 2 or later at the following locations:
- SPDX-License-Identifier: GPL-2.0
- */
+/ {
model = "emtrion SoM emCON-MX6 Solo/DualLite";compatible = "emtrion,emcon-mx6","fsl,imx6dl";+};
+&iomuxc {
pinctrl_cpi2: csi1grp {fsl,pins = <MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0x0b0b1MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b1MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b1MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b1MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b1MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b1MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b1MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b1MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b1MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b1MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b1>;};+}; diff --git a/arch/arm/boot/dts/imx6q-emcon-avari.dts b/arch/arm/boot/dts/imx6q-emcon-avari.dts new file mode 100644 index 000000000000..bccfd6344c18 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-emcon-avari.dts @@ -0,0 +1,233 @@ +/*
- Copyright (C) 2017 emtrion GmbH
- Author: Jan Tuerk jan.tuerk@emtrion.com
- The code contained herein is licensed under the GNU General Public
- License. You may obtain a copy of the GNU General Public License
- Version 2 or later at the following locations:
- SPDX-License-Identifier: GPL-2.0
- */
+/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-emcon.dtsi" +#include "imx6q-emcon.dtsi" /*Include camera2 pinmux*/
+/ {
model = "emtrion SoM emCON-MX6 Dual/Quad on Avari";compatible = "emtrion,emcon-mx6-avari", "fsl,imx6q";aliases {mmc0 = &usdhc3;mmc2 = &usdhc1;mmc1 = &usdhc2;mmc3 = &usdhc4;};chosen {stdout-path = <&uart1>;};memory {reg = <0x10000000 0x40000000>;};supplies {compatible = "simple-bus";#address-cells = <1>;#size-cells = <0>;wallplug5p0: supply@0 {compatible = "regulator-fixed";reg = <0>;regulator-name = "WALL-PLUG";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;regulator-always-on;regulator-boot-on;};base3p3: supply@1 {compatible = "regulator-fixed";reg = <1>;vin-supply = <&wallplug5p0>;regulator-name = "3V3-avari";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-always-on;regulator-boot-on;};base1p5: supply@2 {compatible = "regulator-fixed";reg = <2>;vin-supply = <&base3p3>;regulator-name = "1V5-avari";regulator-min-microvolt = <1500000>;regulator-max-microvolt = <1500000>;regulator-always-on;regulator-boot-on;};reg_usb_otg: otgvbus {compatible = "regulator-fixed";reg = <3>;vin-supply = <&wallplug5p0>;regulator-name = "OTG_VBUS";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;regulator-always-on;};};sndosc: 12MHZosc {compatible = "fixed-clock";#clock-cells = <0>;clock-frequency = <12000000>;};sound {compatible = "fsl,imx-audio-sgtl5000";model = "emCON-avari-sgtl5000";ssi-controller = <&ssi2>;audio-codec = <&sgtl5000>;audio-routing ="Headphone Jack", "HP_OUT";mux-int-port = <2>;mux-ext-port = <3>;};+};
+&iomuxc {
pinctrl-names = "default";/*Unused emCON-MX6 pingroups on AVARI baseboard, enable defaults*/pinctrl-0 = <&pinctrl_emcon_gpio1 &pinctrl_emcon_gpio2&pinctrl_emcon_gpio3 &pinctrl_emcon_gpio5&pinctrl_emcon_gpio6 &pinctrl_emcon_gpio7&pinctrl_emcon_gpio8 &pinctrl_emcon_irq_a&pinctrl_emcon_irq_b &pinctrl_emcon_irq_c&pinctrl_emcon_irq_pwr &pinctrl_nor_flash&pinctrl_usdhc2&pinctrl_spdif_out &pinctrl_spdif_in&pinctrl_cpi1 &pinctrl_cpi2>;+};
+&audmux {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_audmux>;status = "okay";+};
+&i2c3 {
clock-frequency = <100000>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_i2c3>;status = "okay";sgtl5000: sgtl5000@0a {compatible = "fsl,sgtl5000";reg = <0x0a>;clocks = <&sndosc>;VDDA-supply = <&base3p3>;VDDIO-supply = <&base3p3>;};boardID: pca8754a@3A {compatible = "nxp,pca8574";reg = <0x3A>;gpio-controller;#gpio-cells = <1>;};captouch: edt-ft5x06@38 {reg = <0x38>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_irq_touch2 &pinctrl_emcon_gpio4>;interrupt-parent = <&gpio6>;interrupts = <31 IRQ_TYPE_EDGE_FALLING>;compatible = "edt,edt-ft5406";wake-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;wakeup-source;};+};
+&ssi2 {
status = "okay";+};
+&rgb_encoder {
status = "okay";+};
+&rgb_panel {
compatible = "edt,etm0700g0bdh6";status = "okay";+};
+&i2c2 {
status = "okay";+};
+&hdmi {
ddc-i2c-bus = <&i2c2>;status = "okay";+};
+&usbh1 {
status = "okay";+};
+&usbotg {
status = "okay";+};
+&pcie {
status = "okay";+};
+&usdhc1 {
status = "okay";+};
+&can1 {
status = "okay";+};
+&can2 {
status = "okay";+};
+&uart2 {
status = "okay";uart-has-rtscts;+};
+&uart3 {
status = "okay";+};
+&uart4 {
status = "okay";+};
+&uart5 {
status = "okay";+};
+&ecspi2 {
status = "okay";+}; diff --git a/arch/arm/boot/dts/imx6q-emcon.dtsi b/arch/arm/boot/dts/imx6q-emcon.dtsi new file mode 100644 index 000000000000..64fc0cd74c05 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-emcon.dtsi @@ -0,0 +1,37 @@ +/*
- Copyright (C) 2017 emtrion GmbH
- Author: Jan Tuerk jan.tuerk@emtrion.com
- The code contained herein is licensed under the GNU General Public
- License. You may obtain a copy of the GNU General Public License
- Version 2 or later at the following locations:
- SPDX-License-Identifier: GPL-2.0
- */
+/ {
model = "emtrion SoM emCON-MX6 Dual/Quad";compatible = "emtrion,emcon-mx6","fsl,imx6q";+};
+&iomuxc {
pinctrl_cpi2: csi1grp {fsl,pins = <MX6QDL_PAD_EIM_D17__IPU2_CSI1_PIXCLK 0x0b0b1MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b1MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b1MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b1MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b1MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b1MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b1MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b1MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b1MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b1MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b1>;};+}; diff --git a/arch/arm/boot/dts/imx6qdl-emcon.dtsi b/arch/arm/boot/dts/imx6qdl-emcon.dtsi new file mode 100644 index 000000000000..22ad05880ea7 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-emcon.dtsi @@ -0,0 +1,849 @@ +/*
- Copyright (C) 2017 emtrion GmbH
- Author: Jan Tuerk jan.tuerk@emtrion.com
- The code contained herein is licensed under the GNU General Public
- License. You may obtain a copy of the GNU General Public License
- Version 2 or later at the following locations:
- SPDX-License-Identifier: GPL-2.0
- */
+#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/input/input.h>
+/ {
model = "emtrion SoM emCON-MX6";compatible = "emtrion,emcon-mx6","fsl,imx6q", "fsl,imx6dl";aliases {mmc0 = &usdhc3;mmc2 = &usdhc1;mmc1 = &usdhc2;};regulators {compatible = "simple-bus";#address-cells = <1>;#size-cells = <0>;reg_parallel_disp: regulator@0 {compatible = "regulator-fixed";reg = <0>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_rgb_bl_en>;regulator-name = "LCD-Supply";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;gpio = <&gpio7 9 GPIO_ACTIVE_HIGH>;enable-active-high;};reg_lvds_disp: regulator@1 {compatible = "regulator-fixed";reg = <1>;regulator-name = "LVDS-Supply";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;gpio = <&gpio7 10 GPIO_ACTIVE_HIGH>;enable-active-high;};};som_leds: leds {compatible = "gpio-leds";pinctrl-names = "default";pinctrl-0 = <&pinctrl_som_leds>;green {label = "som:green";gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;linux,default-trigger = "heartbeat";default-state = "on";};red {label = "som:red";gpios = <&gpio3 1 GPIO_ACTIVE_LOW>;default-state = "keep";};};gpio-keys {compatible = "gpio-keys";pinctrl-names = "default";pinctrl-0 = <&pinctrl_emcon_wake>;wake {label = "Wake";linux,code = <KEY_WAKEUP>;gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;wakeup-source;};};pwm_fan: pwm-fan {compatible = "pwm-fan";cooling-min-state = <0>;cooling-max-state = <4>;#cooling-cells = <2>;pwms = <&pwm4 0 50000>;cooling-levels = <0 64 127 191 255>;status = "disabled";};rgb_encoder: lcd@di0 {compatible = "fsl,imx-parallel-display";#address-cells = <1>;#size-cells = <0>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_rgb24_display>;status = "disabled";port@0 {reg = <0>;rgb_encoder_in: endpoint {remote-endpoint = <&ipu1_di0_disp0>;};};port@1 {reg = <1>;rgb_encoder_out: endpoint {remote-endpoint = <&rgb_panel_in>;};};};rgb_panel: panel {backlight = <&rgb_backlight>;power-supply = <®_prallel_disp>;port {rgb_panel_in: endpoint {remote-endpoint = <&rgb_encoder_out>;};};};rgb_backlight: rgb_backlight {
rgb-backlight {
compatible = "pwm-backlight";pinctrl-names = "default";pinctrl-0 = <&pinctrl_rgb_bl>;enable-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;pwms = <&pwm3 0 5000000>;brightness-levels = <250 176 160 144 128 11296 80 64 48 32 16 8 1>;default-brightness-level = <13>;status = "okay";};lvds_backlight: lvds_backlight {
lvds-backlight {
compatible = "pwm-backlight";pinctrl-names = "default";pinctrl-0 = <&pinctrl_lvds_bl>;enable-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>;pwms = <&pwm1 0 50000>;brightness-levels = <0 4 8 16 32 64 80 96 112128 144 160 176 250>;default-brightness-level = <13>;status = "okay";};+};
+&iomuxc {
pinctrl_secure: securegrp {fsl,pins = <MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1>;};pinctrl_uart1: uart1grp {fsl,pins = <MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1>;};pinctrl_uart2: uart2grp {fsl,pins = <MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1>;};pinctrl_uart3: uart3grp {fsl,pins = <MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1>;};pinctrl_uart4: uart4grp {fsl,pins = <MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1>;};pinctrl_uart5: uart5grp {fsl,pins = <MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1>;};pinctrl_emcon_gpio1: emcongpio1 {fsl,pins = <MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x0b0b1>;};pinctrl_emcon_gpio2: emcongpio2 {fsl,pins = <MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0b0b1>;};pinctrl_emcon_gpio3: emcongpio3 {fsl,pins = <MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0b0b1>;};pinctrl_emcon_gpio4: emcongpio4 {fsl,pins = <MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0b0b1>;};pinctrl_emcon_gpio5: emcongpio5 {fsl,pins = <MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x0b0b1>;};pinctrl_emcon_gpio6: emcongpio6 {fsl,pins = <MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0b0b1>;};pinctrl_emcon_gpio7: emcongpio7 {fsl,pins = <MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0b0b1>;};pinctrl_emcon_gpio8: emcongpio8 {fsl,pins = <MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0b0b1>;};pinctrl_emcon_irq_a: emconirqa {fsl,pins = <MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x0b0b1>;};pinctrl_emcon_irq_b: emconirqb {fsl,pins = <MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x0b0b1>;};pinctrl_emcon_irq_c: emconirqc {fsl,pins = <MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0b0b1>;};pinctrl_emcon_wake: emconwake {fsl,pins = <MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1>;};pinctrl_emcon_irq_pwr: emconirqpwr {fsl,pins = <MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0b0b1>;};pinctrl_som_leds: somledgrp {fsl,pins = <MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x0b0b1MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x0b0b1>;};pinctrl_nor_flash: norflashgrp {fsl,pins = <MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b1MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1>;};pinctrl_ecspi2: ecspi2grp {fsl,pins = <MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1>;};pinctrl_pwm_fan: pwmfan {fsl,pins = <MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x0b0b1>;};pinctrl_can1: can1grp {fsl,pins = <MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1>;};pinctrl_can2: can2grp {fsl,pins = <MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b1MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b1>;};pinctrl_spdif_out: spdifout {fsl,pins = <MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091>;};pinctrl_spdif_in: spdifin {fsl,pins = <MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0>;};pinctrl_cpi1: csi0grp {fsl,pins = <MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b1MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b1MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b1MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b1MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b1MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b1MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b1MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b1MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b1MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b1>;};/*camera2-pinctrl is in imx6q-emcon.dtsi or imx6dl-emcon.dtsi*/pinctrl_pcie_ctrl: pciegrp {fsl,pins = <MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1>;};pinctrl_audmux: audmux {fsl,pins = <MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b060MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130B0MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b060>;};pinctrl_i2c1: i2c1grp {fsl,pins = <MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1>;};pinctrl_i2c2: i2c2grp {fsl,pins = <MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1>;};pinctrl_i2c3: i2c3grp {fsl,pins = <MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4000b070MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b870>;};pinctrl_pmic: pmicgrp {fsl,pins = <MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0b0b1>;};pinctrl_usb_host1: usbhgrp {fsl,pins = <MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x1B058MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1B058>;};pinctrl_usb_otg: usbotggrp {fsl,pins = <MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x17059MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x17059>;};pinctrl_lvds_reg: lvdsreggrp {fsl,pins = <MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x0b0b1>;};pinctrl_lvds_bl: lvdsbacklightgrp {fsl,pins = <MX6QDL_PAD_GPIO_9__PWM1_OUT 0x0b0b1MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b1>;};pinctrl_irq_touch1: irqtouch1 {fsl,pins = <MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x0b0b1>;};pinctrl_rgb_bl_en: rgbenable {fsl,pins = <MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x0b0b1>;};pinctrl_irq_touch2: irqtouch2 {fsl,pins = <MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x0b0b1>;};pinctrl_rgb_bl: rgbbacklightgrp {fsl,pins = <MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x0b0b1MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b1>;};pinctrl_rgb24_display: rgbgrp {fsl,pins = <MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10>;};pinctrl_enet: enetgrp {fsl,pins = <MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b030MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b030MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x4001a0b1MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b058MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0>;};pinctrl_usdhc3: usdhc3grp {fsl,pins = <MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1>;};pinctrl_usdhc1: usdhc1grp {fsl,pins = <MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059MX6QDL_PAD_GPIO_1__SD1_CD_B 0x1b0b1MX6QDL_PAD_DI0_PIN4__SD1_WP 0x1b0b1>;};pinctrl_usdhc2: usdhc2grp {fsl,pins = <MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059MX6QDL_PAD_GPIO_4__SD2_CD_B 0x1b0b1MX6QDL_PAD_GPIO_2__SD2_WP 0x1b0b1>;};+};
+&i2c1 {
clock-frequency = <100000>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_i2c1>;status = "okay";rtc: rtc@68 {compatible = "dallas,ds1307";reg = <0x68>;};da9063: da9063@58 {
pmic@38
compatible = "dlg,da9063";reg = <0x58>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_pmic>;interrupt-parent = <&gpio2>;interrupts = <8 IRQ_TYPE_LEVEL_LOW>;interrupt-controller;onkey {wakeup-source;compatible = "dlg,da9063-onkey";};wdt {compatible = "dlg,da9063-watchdog";timeout-sec = <0>;};regulators {vddcore_reg: bcore1 {regulator-min-microvolt = <1100000>;regulator-max-microvolt = <1450000>;regulator-ramp-delay = <20000>;regulator-name = "DA9063_CORE";regulator-always-on;};vddsoc_reg: bcore2 {regulator-min-microvolt = <1100000>;regulator-max-microvolt = <1450000>;regulator-ramp-delay = <20000>;regulator-name = "DA9063_SOC";regulator-always-on;};vdd_ddr3_reg: bpro {regulator-min-microvolt = <1500000>;regulator-max-microvolt = <1500000>;regulator-ramp-delay = <20000>;regulator-always-on;};vdd_3v3_reg: bperi {regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-ramp-delay = <20000>;regulator-always-on;};vdd_sata_reg: ldo3 {regulator-min-microvolt = <2500000>;regulator-max-microvolt = <2500000>;regulator-always-on;};vdd_mipi_reg: ldo4 {regulator-min-microvolt = <2500000>;regulator-max-microvolt = <2500000>;regulator-always-on;};vdd_mx6_snvs_reg: ldo5 {regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-always-on;};vdd_hdmi_reg: ldo6 {regulator-min-microvolt = <2500000>;regulator-max-microvolt = <2500000>;regulator-always-on;regulator-boot-on;};vdd_pcie_reg: ldo7 {regulator-min-microvolt = <2500000>;regulator-max-microvolt = <2500000>;regulator-always-on;};vdd_1V8_reg: ldo8 {regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-always-on;};vdd_3V3_sdc_reg: ldo9 {regulator-min-microvolt = <1800000>;regulator-max-microvolt = <3300000>;regulator-always-on;};vdd_1V2_reg: ldo10 {regulator-min-microvolt = <1200000>;regulator-max-microvolt = <1200000>;regulator-always-on;};};};+};
+&uart1 {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_uart1>;status = "okay";+};
+&uart2 {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_uart2>;+};
+&uart3 {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_uart3>;+};
+&uart4 {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_uart4>;+};
+&uart5 {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_uart5>;+};
+&fec {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_enet>;phy-mode = "rgmii";phy-reset-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;phy-reset-duration = <50>;phy-supply = <&vdd_1V8_reg>;phy-handle = <&ksz9031>;status = "okay";mdio {#address-cells = <1>;#size-cells = <0>;ksz9031: phy {
phy@0
Building with W=2 or W=1 will tell you this.
reg = <0>;compatible = "ethernet-phy-ieee802.3-c22";interrupt-parent = <&gpio1>;interrupts = <30 IRQ_TYPE_EDGE_FALLING>;rxdv-skew-ps = <480>;txen-skew-ps = <480>;rxd0-skew-ps = <480>;rxd1-skew-ps = <480>;rxd2-skew-ps = <480>;rxd3-skew-ps = <480>;txd0-skew-ps = <420>;txd1-skew-ps = <420>;txd2-skew-ps = <360>;txd3-skew-ps = <360>;txc-skew-ps = <1020>;rxc-skew-ps = <960>;};};+};
+&usdhc3 {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_usdhc3>;non-removable;bus-width = <8>;status = "okay";+};
+&pcie {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_pcie_ctrl>;reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;disable-gpio = <&gpio2 22 GPIO_ACTIVE_LOW>;+};
+&i2c2 {
clock-frequency = <100000>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_i2c2>;+};
+&usdhc1 {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_usdhc1>;fsl,wp-controller;+};
+&usdhc2 {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_usdhc2>;fsl,wp-controller;+};
+&ipu1_di0_disp0 {
remote-endpoint = <&rgb_encoder_in>;+};
+&pwm1 {
status = "okay";+};
+&pwm3 {
status = "okay";+};
+&pwm4 {
status = "okay";+};
+&ecspi2 {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_ecspi2>;cs-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>,<&gpio2 26 GPIO_ACTIVE_HIGH>;+};
+&ecspi4 {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_nor_flash>;+};
+&can1 {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_can1>;+};
+&can2 {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_can2>;+};
+&usbh1 {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_usb_host1>;+};
+&usbotg {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_usb_otg>;vbus-supply = <®_usb_otg>;dr_mode = "peripheral";+};
+/******device power Management*********/
+&cpu0 {
voltage-tolerance = <2>;+};
+®_arm {
vin-supply = <&vddcore_reg>;+};
+®_soc {
vin-supply = <&vddsoc_reg>;+};
+®_pu {
vin-supply = <&vddsoc_reg>;+};
+/*******Disabled HW following***********/
+&weim {
status = "disabled";+};
+&snvs_rtc {
status = "disabled";+};
-- 2.11.0
emtrion GmbH Kreativpark - Alter Schlachthof 45 76131 Karlsruhe GERMANY http://www.emtrion.de _______________________________________
Amtsgericht Mannheim HRB 110 300 Gesch?ftsf?hrer: Dieter Baur, Ramona Maurer _______________________________________
Hi Rob,
thanks for your feedback, the changes will be included in V2 of the patch-series.
Jan
Von: Rob Herring Gesendet: Sonntag, 26. November 2017 20:24 On Thu, Nov 23, 2017 at 01:55:54PM +0100, Jan Tuerk wrote:
This patch adds support for the emtrion GmbH emCON-MX6 modules. They are available with imx.6 Solo, Dual-Lite, Dual and Quad equipped with Memory from 512MB to 2GB (configured by U-Boot).
[...]
+&i2c3 {
clock-frequency = <100000>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_i2c3>;status = "okay";sgtl5000: sgtl5000@0a {audio-codec@a
same errors repeat below.
changed for v2
compatible = "fsl,sgtl5000";reg = <0x0a>;clocks = <&sndosc>;VDDA-supply = <&base3p3>;VDDIO-supply = <&base3p3>;};boardID: pca8754a@3A {...@3a
changed in V2
compatible = "nxp,pca8574";reg = <0x3A>;0x3a
gpio-controller;#gpio-cells = <1>;};captouch: edt-ft5x06@38 {touchscreen@38
reg = <0x38>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_irq_touch2 &pinctrl_emcon_gpio4>;interrupt-parent = <&gpio6>;interrupts = <31 IRQ_TYPE_EDGE_FALLING>;compatible = "edt,edt-ft5406";wake-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;wakeup-source;};+};
+&ssi2 {
status = "okay";+};
+&rgb_encoder {
status = "okay";+};
[...]
rgb_panel: panel {backlight = <&rgb_backlight>;power-supply = <®_prallel_disp>;port {rgb_panel_in: endpoint {remote-endpoint = <&rgb_encoder_out>;};};};rgb_backlight: rgb_backlight {rgb-backlight {
[...]
lvds_backlight: lvds_backlight {lvds-backlight {
Ok, I'll change that in V2
[...]
+&i2c1 {
clock-frequency = <100000>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_i2c1>;status = "okay";rtc: rtc@68 {compatible = "dallas,ds1307";reg = <0x68>;};da9063: da9063@58 {pmic@38
changed
compatible = "dlg,da9063";reg = <0x58>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_pmic>;interrupt-parent = <&gpio2>;
[....]
mdio {#address-cells = <1>;#size-cells = <0>;ksz9031: phy {phy@0
Building with W=2 or W=1 will tell you this.
thanks for the hint, it will be also included in v2
reg = <0>;compatible = "ethernet-phy-ieee802.3-c22";interrupt-parent = <&gpio1>;interrupts = <30 IRQ_TYPE_EDGE_FALLING>;rxdv-skew-ps = <480>;txen-skew-ps = <480>;
[...]
emtrion GmbH Kreativpark - Alter Schlachthof 45 76131 Karlsruhe GERMANY http://www.emtrion.de _______________________________________
Amtsgericht Mannheim HRB 110 300 Geschäftsführer: Dieter Baur, Ramona Maurer _______________________________________
All recent emtrion modules based on i.mx6 make use of the DA0963. Therefore enable it with the following defaults: - CONFIG_MFD_DA9063=y - CONFIG_REGULATOR_DA9063=y - CONFIG_DA9063_WATCHDOG=m - CONFIG_RTC_DRV_DA9063=m MFD and REGULATOR are built-in to have it at Kernel boot-time. The WATCHDOG and RTC are optional and could be loaded from userspace.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com --- arch/arm/configs/imx_v6_v7_defconfig | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 0d4494922561..09cd8048b0c1 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -215,8 +215,10 @@ CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_CPU_THERMAL=y CONFIG_IMX_THERMAL=y CONFIG_WATCHDOG=y +CONFIG_DA9063_WATCHDOG=m CONFIG_IMX2_WDT=y CONFIG_MFD_DA9052_I2C=y +CONFIG_MFD_DA9063=y CONFIG_MFD_MC13XXX_SPI=y CONFIG_MFD_MC13XXX_I2C=y CONFIG_MFD_STMPE=y @@ -224,6 +226,7 @@ CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_ANATOP=y CONFIG_REGULATOR_DA9052=y +CONFIG_REGULATOR_DA9063=y CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_MC13783=y CONFIG_REGULATOR_MC13892=y @@ -349,6 +352,7 @@ CONFIG_RTC_DRV_PCF8563=y CONFIG_RTC_DRV_M41T80=y CONFIG_RTC_DRV_MC13XXX=y CONFIG_RTC_DRV_MXC=y +CONFIG_RTC_DRV_DA9063=m CONFIG_RTC_DRV_SNVS=y CONFIG_DMADEVICES=y CONFIG_FSL_EDMA=y -- 2.11.0
emtrion GmbH Kreativpark - Alter Schlachthof 45 76131 Karlsruhe GERMANY http://www.emtrion.de _______________________________________
Amtsgericht Mannheim HRB 110 300 Geschäftsführer: Dieter Baur, Ramona Maurer _______________________________________
From: Jan Tuerk jan.tuerk@emtrion.com
The following patch-series adds support for emtrion's emCON-MX6 modules with all their dependencies. The focus is based on the emtrion standard developer-kit configuration. It includes a new vendor-prefix, an new simple-panel type, a small modification of the imx6dl.dtsi, as well as modifications of the common imx_v6_v7_defconfig. And finally the board devicetrees themselves.
For V2 there are some changes and small fixes following below. The smtp issue which was converting tabs into spaces should be fixed now, so checkpatch should only warn about the new Documentation files and the new devicetree bindings which are documented in the corresponding patch.
The documentation for the EDT display is kept as an extra file currently, as it is done by the most displays in the documentation. Also a new new Vartiant of the EDT already arrived. So merging their documentations should be discussed separately.
[PATCH v2 1/5] drm/panel: Add support for the EDT ETM0700G0BDH6 No changes, resend.
[PATCH v2 2/5] dt-bindings: Add vendor prefix for emtrion GmbH v2: - Reviewed-by: Andreas Färber afaerber@suse.de - Acked-by: Rob Herring robh@kernel.org
[PATCH v2 3/5] ARM: dts: imx: Add an cpu0 label for imx6dl devices. v2: - Reviewed-by: Andreas Färber afaerber@suse.de
[PATCH v2 4/5] ARM: dts: Add support for emtrion emCON-MX6 series Changes in v2: - Fixed typo (reg_prallel.. --> reg_parallel) - Removed trailing new-line - Fix uppercase addresses as Rob H. noted - Fix warning about lcd@di0 -> rename to disp0 - Renamed some nodes regarding Rob H.
[PATCH v2 5/5] ARM: imx_v6_v7_defconfig: Enable DA0963 PMIC support. No changes, resend.
Documentation/devicetree/bindings/arm/emtrion.txt | 13 + .../bindings/display/panel/edt,etm0700g0bdh6.txt | 9 + .../devicetree/bindings/vendor-prefixes.txt | 1 + arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx6dl-emcon-avari.dts | 233 ++++++ arch/arm/boot/dts/imx6dl-emcon.dtsi | 37 + arch/arm/boot/dts/imx6dl.dtsi | 2 +- arch/arm/boot/dts/imx6q-emcon-avari.dts | 233 ++++++ arch/arm/boot/dts/imx6q-emcon.dtsi | 37 + arch/arm/boot/dts/imx6qdl-emcon.dtsi | 848 ++++++++++++++++ arch/arm/configs/imx_v6_v7_defconfig | 4 + drivers/gpu/drm/panel/panel-simple.c | 15 + 12 files changed, 1433 insertions(+), 1 deletion(-)
From: Jan Tuerk jan.tuerk@emtrion.com
The Emerging Display Technology ETM0700G0BDH6 is exactly the same display as the ETM0700G0DH6, exept the pixelclock polarity. Therefore re-use the ETM0700G0DH6 modes. It is used by default on emtrion Avari based development kits.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com --- .../bindings/display/panel/edt,etm0700g0bdh6.txt | 9 +++++++++ drivers/gpu/drm/panel/panel-simple.c | 15 +++++++++++++++ 2 files changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/edt,etm0700g0bdh6.txt
diff --git a/Documentation/devicetree/bindings/display/panel/edt,etm0700g0bdh6.txt b/Documentation/devicetree/bindings/display/panel/edt,etm0700g0bdh6.txt new file mode 100644 index 000000000000..099e30bfa17f --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/edt,etm0700g0bdh6.txt @@ -0,0 +1,9 @@ +Emerging Display Technology Corp. ETM0700G0BDH6 7.0" WVGA TFT LCD panel + +Required properties: + compatible: "edt,etm0700g0bdh6" + +This panel is exactly the same as ETM0700G0DH6 except the pixelclock polarity. + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index b7c4709f7b34..42442034b53e 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -886,6 +886,18 @@ static const struct panel_desc edt_etm0700g0dh6 = { .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, };
+static const struct panel_desc edt_etm0700g0bdh6 = { + .modes = &edt_etm0700g0dh6_mode, + .num_modes = 1, + .bpc = 6, + .size = { + .width = 152, + .height = 91, + }, + .bus_format = MEDIA_BUS_FMT_RGB666_1X18, + .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, +}; + static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { .clock = 32260, .hdisplay = 800, @@ -2029,6 +2041,9 @@ static const struct of_device_id platform_of_match[] = { .compatible = "edt,etm0700g0dh6", .data = &edt_etm0700g0dh6, }, { + .compatible = "edt,etm0700g0bdh6", + .data = &edt_etm0700g0bdh6, + }, { .compatible = "foxlink,fl500wvr00-a0t", .data = &foxlink_fl500wvr00_a0t, }, {
On Wed, Dec 20, 2017 at 02:47:01PM +0100, jan.tuerk@emtrion.com wrote:
From: Jan Tuerk jan.tuerk@emtrion.com
The Emerging Display Technology ETM0700G0BDH6 is exactly the same display as the ETM0700G0DH6, exept the pixelclock polarity. Therefore re-use the ETM0700G0DH6 modes. It is used by default on emtrion Avari based development kits.
As I asked on v1, why not document the panels together in a single doc?
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com
.../bindings/display/panel/edt,etm0700g0bdh6.txt | 9 +++++++++ drivers/gpu/drm/panel/panel-simple.c | 15 +++++++++++++++ 2 files changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/edt,etm0700g0bdh6.txt
From: Jan Tuerk jan.tuerk@emtrion.com
Changes for v3: [PATCH v3 1/6] drm/panel: Add support for the EDT ETM0700G0BDH6 - moved Documentation into seperate commit ([PATCH v3/6])
[PATCH v3 2/6] drm/panel: Add support for the EDT ETM0700G0EDH6 - new Patch, adding additionally compatible for the new hardware type
[PATCH v3 3/6] dt-bindings: display: Document the EDT et* displays in one file. - new Patch, as requested by Rob Herring document the EDT Displays in a single file
[PATCH v3 4/6] ARM: dts: imx: Add an cpu0 label for imx6dl devices. - Unchanged [PATCH v3 5/6] ARM: dts: Add support for emtrion emCON-MX6 series - change License Header to SPDX + dual-license without licence text. - coding-style fixes [PATCH v3 6/6] ARM: imx_v6_v7_defconfig: Enable DA0963 PMIC support. - Rebased and merged
Documentation/devicetree/bindings/arm/emtrion.txt | 13 + .../bindings/display/panel/edt,et-series.txt | 39 + .../bindings/display/panel/edt,et057090dhu.txt | 7 - .../bindings/display/panel/edt,et070080dh6.txt | 10 - .../bindings/display/panel/edt,etm0700g0dh6.txt | 10 - arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx6dl-emcon-avari.dts | 224 ++++++ arch/arm/boot/dts/imx6dl-emcon.dtsi | 27 + arch/arm/boot/dts/imx6dl.dtsi | 2 +- arch/arm/boot/dts/imx6q-emcon-avari.dts | 224 ++++++ arch/arm/boot/dts/imx6q-emcon.dtsi | 27 + arch/arm/boot/dts/imx6qdl-emcon.dtsi | 838 +++++++++++++++++++++ arch/arm/configs/imx_v6_v7_defconfig | 3 + drivers/gpu/drm/panel/panel-simple.c | 18 + 14 files changed, 1416 insertions(+), 28 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/emtrion.txt create mode 100644 Documentation/devicetree/bindings/display/panel/edt,et-series.txt delete mode 100644 Documentation/devicetree/bindings/display/panel/edt,et057090dhu.txt delete mode 100644 Documentation/devicetree/bindings/display/panel/edt,et070080dh6.txt delete mode 100644 Documentation/devicetree/bindings/display/panel/edt,etm0700g0dh6.txt create mode 100644 arch/arm/boot/dts/imx6dl-emcon-avari.dts create mode 100644 arch/arm/boot/dts/imx6dl-emcon.dtsi create mode 100644 arch/arm/boot/dts/imx6q-emcon-avari.dts create mode 100644 arch/arm/boot/dts/imx6q-emcon.dtsi create mode 100644 arch/arm/boot/dts/imx6qdl-emcon.dtsi
From: Jan Tuerk jan.tuerk@emtrion.com
The Emerging Display Technology ETM0700G0BDH6 is exactly the same display as the ETM0700G0DH6, exept the pixelclock polarity. Therefore re-use the ETM0700G0DH6 modes. It is used by default on emtrion Avari based development kits.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com --- drivers/gpu/drm/panel/panel-simple.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index cbf1ab404ee7..8b7feb2888f2 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -909,6 +909,18 @@ static const struct panel_desc edt_etm0700g0dh6 = { .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, };
+static const struct panel_desc edt_etm0700g0bdh6 = { + .modes = &edt_etm0700g0dh6_mode, + .num_modes = 1, + .bpc = 6, + .size = { + .width = 152, + .height = 91, + }, + .bus_format = MEDIA_BUS_FMT_RGB666_1X18, + .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, +}; + static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { .clock = 32260, .hdisplay = 800, @@ -2134,6 +2146,9 @@ static const struct of_device_id platform_of_match[] = { .compatible = "edt,etm0700g0dh6", .data = &edt_etm0700g0dh6, }, { + .compatible = "edt,etm0700g0bdh6", + .data = &edt_etm0700g0bdh6, + }, { .compatible = "foxlink,fl500wvr00-a0t", .data = &foxlink_fl500wvr00_a0t, }, {
From: Jan Tuerk jan.tuerk@emtrion.com
The Emerging Display Technology ETM0700G0EDH6 is the uses the same panel as the ETM0700G0BDH6. It differs in the hardware design for the backlight and the touchscreen i2c interface. As the new display type has different requirements for drive-strengths on the i2c-bus, add an additional compatible to allow the handling of it or warn about incompatible cpu and display combinations.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com --- drivers/gpu/drm/panel/panel-simple.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 8b7feb2888f2..2eed60134fa3 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -2149,6 +2149,9 @@ static const struct of_device_id platform_of_match[] = { .compatible = "edt,etm0700g0bdh6", .data = &edt_etm0700g0bdh6, }, { + .compatible = "edt,etm0700g0edh6", + .data = &edt_etm0700g0bdh6, + }, { .compatible = "foxlink,fl500wvr00-a0t", .data = &foxlink_fl500wvr00_a0t, }, {
From: Jan Tuerk jan.tuerk@emtrion.com
Document the Emerging Display Technology Corp. (EDT) using the simple-panel binding in one single file.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com --- .../bindings/display/panel/edt,et-series.txt | 39 ++++++++++++++++++++++ .../bindings/display/panel/edt,et057090dhu.txt | 7 ---- .../bindings/display/panel/edt,et070080dh6.txt | 10 ------ .../bindings/display/panel/edt,etm0700g0dh6.txt | 10 ------ 4 files changed, 39 insertions(+), 27 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/panel/edt,et-series.txt delete mode 100644 Documentation/devicetree/bindings/display/panel/edt,et057090dhu.txt delete mode 100644 Documentation/devicetree/bindings/display/panel/edt,et070080dh6.txt delete mode 100644 Documentation/devicetree/bindings/display/panel/edt,etm0700g0dh6.txt
diff --git a/Documentation/devicetree/bindings/display/panel/edt,et-series.txt b/Documentation/devicetree/bindings/display/panel/edt,et-series.txt new file mode 100644 index 000000000000..f56b99ebd9be --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/edt,et-series.txt @@ -0,0 +1,39 @@ +Emerging Display Technology Corp. Displays +========================================== + + +Display bindings for EDT Display Technology Corp. Displays which are +compatible with the simple-panel binding, which is specified in +simple-panel.txt + + +5,7" WVGA TFT Panels +-------------------- + ++-----------------+---------------------+-------------------------------------+ +| Identifier | compatbile | description | ++=================+=====================+=====================================+ +| ET057090DHU | edt,et057090dhu | 5.7" VGA TFT LCD panel | ++-----------------+---------------------+-------------------------------------+ + + +7,0" WVGA TFT Panels +-------------------- + ++-----------------+---------------------+-------------------------------------+ +| Identifier | compatbile | description | ++=================+=====================+=====================================+ +| ETM0700G0DH6 | edt,etm070080dh6 | WVGA TFT Display with capacitive | +| | | Touchscreen | ++-----------------+---------------------+-------------------------------------+ +| ETM0700G0BDH6 | edt,etm070080bdh6 | Same as ETM0700G0DH6 but with | +| | | inverted pixel clock. | ++-----------------+---------------------+-------------------------------------+ +| ETM0700G0EDH6 | edt,etm070080edh6 | Same display as the ETM0700G0BDH6, | +| | | but with changed Hardware for the | +| | | backlight and the touch interface | ++-----------------+---------------------+-------------------------------------+ +| ET070080DH6 | edt,etm070080dh6 | Same timings as the ETM0700G0DH6, | +| | | but with resistive touch. | ++-----------------+---------------------+-------------------------------------+ + diff --git a/Documentation/devicetree/bindings/display/panel/edt,et057090dhu.txt b/Documentation/devicetree/bindings/display/panel/edt,et057090dhu.txt deleted file mode 100644 index 4903d7b1d947..000000000000 --- a/Documentation/devicetree/bindings/display/panel/edt,et057090dhu.txt +++ /dev/null @@ -1,7 +0,0 @@ -Emerging Display Technology Corp. 5.7" VGA TFT LCD panel - -Required properties: -- compatible: should be "edt,et057090dhu" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/edt,et070080dh6.txt b/Documentation/devicetree/bindings/display/panel/edt,et070080dh6.txt deleted file mode 100644 index 20cb38e836e4..000000000000 --- a/Documentation/devicetree/bindings/display/panel/edt,et070080dh6.txt +++ /dev/null @@ -1,10 +0,0 @@ -Emerging Display Technology Corp. ET070080DH6 7.0" WVGA TFT LCD panel - -Required properties: -- compatible: should be "edt,et070080dh6" - -This panel is the same as ETM0700G0DH6 except for the touchscreen. -ET070080DH6 is the model with resistive touch. - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/edt,etm0700g0dh6.txt b/Documentation/devicetree/bindings/display/panel/edt,etm0700g0dh6.txt deleted file mode 100644 index ee4b18053e40..000000000000 --- a/Documentation/devicetree/bindings/display/panel/edt,etm0700g0dh6.txt +++ /dev/null @@ -1,10 +0,0 @@ -Emerging Display Technology Corp. ETM0700G0DH6 7.0" WVGA TFT LCD panel - -Required properties: -- compatible: should be "edt,etm0700g0dh6" - -This panel is the same as ET070080DH6 except for the touchscreen. -ETM0700G0DH6 is the model with capacitive multitouch. - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory.
From: Jan Tuerk jan.tuerk@emtrion.com
Adding the label cpu0 allows the adjustment of cpu-parameters by reference in overlaying dtsi files in the same way as it is possible for imx6q devices.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com --- arch/arm/boot/dts/imx6dl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 558bce81209d..fc658bf3a693 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -21,7 +21,7 @@ #address-cells = <1>; #size-cells = <0>;
- cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>;
From: Jan Tuerk jan.tuerk@emtrion.com
This patch adds support for the emtrion GmbH emCON-MX6 modules. They are available with imx.6 Solo, Dual-Lite, Dual and Quad equipped with Memory from 512MB to 2GB (configured by U-Boot).
Our default developer-Kit ships with the Avari baseboard and the EDT ETM0700G0BDH6 Display (imx6[q|dl]-emcon-avari).
The devicetree is split into the common part providing all module components and the basic support for all SoC versions (imx6qdl-emcon.dtsi) and parts which are i.mx6 S|DL and D|Q relevant. Finally the support for the avari baseboard in the developer-kit configuration is provided by the emcon-avari dts files.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com --- Documentation/devicetree/bindings/arm/emtrion.txt | 13 + arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx6dl-emcon-avari.dts | 224 ++++++ arch/arm/boot/dts/imx6dl-emcon.dtsi | 27 + arch/arm/boot/dts/imx6q-emcon-avari.dts | 224 ++++++ arch/arm/boot/dts/imx6q-emcon.dtsi | 27 + arch/arm/boot/dts/imx6qdl-emcon.dtsi | 838 ++++++++++++++++++++++ 7 files changed, 1355 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/emtrion.txt create mode 100644 arch/arm/boot/dts/imx6dl-emcon-avari.dts create mode 100644 arch/arm/boot/dts/imx6dl-emcon.dtsi create mode 100644 arch/arm/boot/dts/imx6q-emcon-avari.dts create mode 100644 arch/arm/boot/dts/imx6q-emcon.dtsi create mode 100644 arch/arm/boot/dts/imx6qdl-emcon.dtsi
diff --git a/Documentation/devicetree/bindings/arm/emtrion.txt b/Documentation/devicetree/bindings/arm/emtrion.txt new file mode 100644 index 000000000000..3ff6c6c2034d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/emtrion.txt @@ -0,0 +1,13 @@ +Emtrion Devicetree Bindings +=========================== + +emCON Series: +------------- + +Required root node properties + - compatible: + - "emtrion,emcon-mx6", "fsl,imx6q", "fsl,imx6dl"; : emCON-MX6 Generic SoM + - "emtrion,emcon-mx6", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM + - "emtrion,emcon-mx6-avari", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM on Avari Base + - "emtrion,emcon-mx6", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM + - "emtrion,emcon-mx6-avari", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM on Avari Base diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7e2424957809..05b930da3fda 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -381,6 +381,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-cubox-i-emmc-som-v15.dtb \ imx6dl-cubox-i-som-v15.dtb \ imx6dl-dfi-fs700-m60.dtb \ + imx6dl-emcon-avari.dtb \ imx6dl-gw51xx.dtb \ imx6dl-gw52xx.dtb \ imx6dl-gw53xx.dtb \ @@ -442,6 +443,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-display5-tianma-tm070-1280x768.dtb \ imx6q-dmo-edmqmx6.dtb \ imx6q-dms-ba16.dtb \ + imx6q-emcon-avari.dtb \ imx6q-evi.dtb \ imx6q-gk802.dtb \ imx6q-gw51xx.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-emcon-avari.dts b/arch/arm/boot/dts/imx6dl-emcon-avari.dts new file mode 100644 index 000000000000..2344fb9498e3 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-emcon-avari.dts @@ -0,0 +1,224 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/* Copyright (C) 2018 emtrion GmbH + * Author: Jan Tuerk jan.tuerk@emtrion.com + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-emcon.dtsi" +#include "imx6dl-emcon.dtsi" /*Include camera2 pinmux*/ + +/ { + model = "emtrion SoM emCON-MX6 Solo/Dual-Lite Avari"; + compatible = "emtrion,emcon-mx6-avari", "fsl,imx6dl"; + + aliases { + mmc0 = &usdhc3; + mmc2 = &usdhc1; + mmc1 = &usdhc2; + mmc3 = &usdhc4; + }; + + chosen { + stdout-path = <&uart1>; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + supplies { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + wallplug5p0: supply@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "WALL-PLUG"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + base3p3: supply@1 { + compatible = "regulator-fixed"; + reg = <1>; + vin-supply = <&wallplug5p0>; + regulator-name = "3V3-avari"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + base1p5: supply@2 { + compatible = "regulator-fixed"; + reg = <2>; + vin-supply = <&base3p3>; + regulator-name = "1V5-avari"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_usb_otg: otgvbus@3 { + compatible = "regulator-fixed"; + reg = <3>; + vin-supply = <&wallplug5p0>; + regulator-name = "OTG_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + }; + + + sndosc: 12MHZosc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "emCON-avari-sgtl5000"; + ssi-controller = <&ssi2>; + audio-codec = <&sgtl5000>; + audio-routing = + "Headphone Jack", "HP_OUT"; + mux-int-port = <2>; + mux-ext-port = <3>; + }; + +}; + + +&iomuxc { + pinctrl-names = "default"; + /*Unused emCON-MX6 outputs on AVARI*/ + pinctrl-0 = < + &pinctrl_emcon_gpio1 &pinctrl_emcon_gpio2 + &pinctrl_emcon_gpio3 &pinctrl_emcon_gpio5 + &pinctrl_emcon_gpio6 &pinctrl_emcon_gpio7 + &pinctrl_emcon_gpio8 &pinctrl_emcon_irq_a + &pinctrl_emcon_irq_b &pinctrl_emcon_irq_c + &pinctrl_emcon_irq_pwr &pinctrl_nor_flash + &pinctrl_usdhc2 + &pinctrl_spdif_out &pinctrl_spdif_in + &pinctrl_cpi1 &pinctrl_cpi2 + >; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + + + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + sgtl5000: audio-codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&sndosc>; + VDDA-supply = <&base3p3>; + VDDIO-supply = <&base3p3>; + }; + + boardID: pca8754a@3a { + compatible = "nxp,pca8574"; + reg = <0x3a>; + gpio-controller; + #gpio-cells = <1>; + }; + + captouch: touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_irq_touch2 &pinctrl_emcon_gpio4>; + interrupt-parent = <&gpio6>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + wake-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + wakeup-source; + status = "okay"; + }; +}; + +&ssi2 { + status = "okay"; +}; + +&rgb_encoder { + status = "okay"; +}; + +&rgb_panel { + compatible = "edt,etm0700g0bdh6"; + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "okay"; +}; + +&uart2 { + status = "okay"; + uart-has-rtscts; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&ecspi2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-emcon.dtsi b/arch/arm/boot/dts/imx6dl-emcon.dtsi new file mode 100644 index 000000000000..1ed629c9747e --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-emcon.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/* Copyright (C) 2018 emtrion GmbH + * Author: Jan Tuerk jan.tuerk@emtrion.com + */ + +/ { + model = "emtrion SoM emCON-MX6 Solo/DualLite"; + compatible = "emtrion,emcon-mx6", "fsl,imx6dl"; +}; + +&iomuxc { + pinctrl_cpi2: csi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0x0b0b1 + MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b1 + MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b1 + MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b1 + MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b1 + MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b1 + MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b1 + MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b1 + MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b1 + MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b1 + MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-emcon-avari.dts b/arch/arm/boot/dts/imx6q-emcon-avari.dts new file mode 100644 index 000000000000..0c85b5ee011c --- /dev/null +++ b/arch/arm/boot/dts/imx6q-emcon-avari.dts @@ -0,0 +1,224 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/* Copyright (C) 2018 emtrion GmbH + * Author: Jan Tuerk jan.tuerk@emtrion.com + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-emcon.dtsi" +#include "imx6q-emcon.dtsi" /*Include camera2 pinmux*/ + +/ { + model = "emtrion SoM emCON-MX6 Dual/Quad on Avari"; + compatible = "emtrion,emcon-mx6-avari", "fsl,imx6q"; + + aliases { + mmc0 = &usdhc3; + mmc2 = &usdhc1; + mmc1 = &usdhc2; + mmc3 = &usdhc4; + }; + + chosen { + stdout-path = <&uart1>; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + supplies { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + wallplug5p0: supply@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "WALL-PLUG"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + base3p3: supply@1 { + compatible = "regulator-fixed"; + reg = <1>; + vin-supply = <&wallplug5p0>; + regulator-name = "3V3-avari"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + base1p5: supply@2 { + compatible = "regulator-fixed"; + reg = <2>; + vin-supply = <&base3p3>; + regulator-name = "1V5-avari"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_usb_otg: otgvbus@3 { + compatible = "regulator-fixed"; + reg = <3>; + vin-supply = <&wallplug5p0>; + regulator-name = "OTG_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + }; + + + sndosc: 12MHZosc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "emCON-avari-sgtl5000"; + ssi-controller = <&ssi2>; + audio-codec = <&sgtl5000>; + audio-routing = + "Headphone Jack", "HP_OUT"; + mux-int-port = <2>; + mux-ext-port = <3>; + }; + +}; + + +&iomuxc { + pinctrl-names = "default"; + /*Unused emCON-MX6 pingroups on AVARI baseboard, enable defaults*/ + pinctrl-0 = < + &pinctrl_emcon_gpio1 &pinctrl_emcon_gpio2 + &pinctrl_emcon_gpio3 &pinctrl_emcon_gpio5 + &pinctrl_emcon_gpio6 &pinctrl_emcon_gpio7 + &pinctrl_emcon_gpio8 &pinctrl_emcon_irq_a + &pinctrl_emcon_irq_b &pinctrl_emcon_irq_c + &pinctrl_emcon_irq_pwr &pinctrl_nor_flash + &pinctrl_usdhc2 + &pinctrl_spdif_out &pinctrl_spdif_in + &pinctrl_cpi1 &pinctrl_cpi2 + >; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + + + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + sgtl5000: audio-codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&sndosc>; + VDDA-supply = <&base3p3>; + VDDIO-supply = <&base3p3>; + }; + + boardID: pca8754a@3a { + compatible = "nxp,pca8574"; + reg = <0x3a>; + gpio-controller; + #gpio-cells = <1>; + }; + + captouch: touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_irq_touch2 &pinctrl_emcon_gpio4>; + interrupt-parent = <&gpio6>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + wake-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + wakeup-source; + status = "okay"; + }; +}; + +&ssi2 { + status = "okay"; +}; + +&rgb_encoder { + status = "okay"; +}; + +&rgb_panel { + compatible = "edt,etm0700g0bdh6"; + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "okay"; +}; + +&uart2 { + status = "okay"; + uart-has-rtscts; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&ecspi2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q-emcon.dtsi b/arch/arm/boot/dts/imx6q-emcon.dtsi new file mode 100644 index 000000000000..33b3fbf3fba0 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-emcon.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/* Copyright (C) 2018 emtrion GmbH + * Author: Jan Tuerk jan.tuerk@emtrion.com + */ + +/ { + model = "emtrion SoM emCON-MX6 Dual/Quad"; + compatible = "emtrion,emcon-mx6", "fsl,imx6q"; +}; + +&iomuxc { + pinctrl_cpi2: csi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__IPU2_CSI1_PIXCLK 0x0b0b1 + MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b1 + MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b1 + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b1 + MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b1 + MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b1 + MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b1 + MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b1 + MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b1 + MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b1 + MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-emcon.dtsi b/arch/arm/boot/dts/imx6qdl-emcon.dtsi new file mode 100644 index 000000000000..5f9296dce130 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-emcon.dtsi @@ -0,0 +1,838 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/* Copyright (C) 2018 emtrion GmbH + * Author: Jan Tuerk jan.tuerk@emtrion.com + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/input/input.h> + +/ { + + model = "emtrion SoM emCON-MX6"; + compatible = "emtrion,emcon-mx6", "fsl,imx6q", "fsl,imx6dl"; + + aliases { + mmc0 = &usdhc3; + mmc2 = &usdhc1; + mmc1 = &usdhc2; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_parallel_disp: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgb_bl_en>; + regulator-name = "LCD-Supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio7 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_lvds_disp: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "LVDS-Supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio7 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + som_leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_som_leds>; + + green { + label = "som:green"; + gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + + red { + label = "som:red"; + gpios = <&gpio3 1 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emcon_wake>; + + wake { + label = "Wake"; + linux,code = <KEY_WAKEUP>; + gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + pwm_fan: pwm-fan { + compatible = "pwm-fan"; + cooling-min-state = <0>; + cooling-max-state = <4>; + #cooling-cells = <2>; + pwms = <&pwm4 0 50000>; + cooling-levels = <0 64 127 191 255>; + status = "disabled"; + }; + + rgb_encoder: disp0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgb24_display>; + status = "disabled"; + + port@0 { + reg = <0>; + rgb_encoder_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + rgb_encoder_out: endpoint { + remote-endpoint = <&rgb_panel_in>; + }; + }; + }; + + rgb_panel: panel { + backlight = <&rgb_backlight>; + power-supply = <®_parallel_disp>; + port { + rgb_panel_in: endpoint { + remote-endpoint = <&rgb_encoder_out>; + }; + }; + }; + + rgb_backlight: rgb-backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgb_bl>; + enable-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; + pwms = <&pwm3 0 5000000>; + brightness-levels = <250 176 160 144 128 112 + 96 80 64 48 32 16 8 1 + >; + default-brightness-level = <13>; + status = "okay"; + }; + + lvds_backlight: lvds-backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds_bl>; + enable-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; + pwms = <&pwm1 0 50000>; + brightness-levels = <0 4 8 16 32 64 80 96 112 + 128 144 160 176 250 + >; + default-brightness-level = <13>; + status = "okay"; + }; +}; + + +&iomuxc { + + pinctrl_secure: securegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_emcon_gpio1: emcongpio1 { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio2: emcongpio2 { + fsl,pins = < + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio3: emcongpio3 { + fsl,pins = < + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio4: emcongpio4 { + fsl,pins = < + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio5: emcongpio5 { + fsl,pins = < + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio6: emcongpio6 { + fsl,pins = < + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio7: emcongpio7 { + fsl,pins = < + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio8: emcongpio8 { + fsl,pins = < + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0b0b1 + >; + }; + + pinctrl_emcon_irq_a: emconirqa { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x0b0b1 + >; + }; + + pinctrl_emcon_irq_b: emconirqb { + fsl,pins = < + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x0b0b1 + >; + }; + + pinctrl_emcon_irq_c: emconirqc { + fsl,pins = < + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0b0b1 + >; + }; + + pinctrl_emcon_wake: emconwake { + fsl,pins = < + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1 + >; + }; + + pinctrl_emcon_irq_pwr: emconirqpwr { + fsl,pins = < + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0b0b1 + >; + }; + + pinctrl_som_leds: somledgrp { + fsl,pins = < + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x0b0b1 + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x0b0b1 + >; + }; + + pinctrl_nor_flash: norflashgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b1 + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 + >; + }; + + pinctrl_pwm_fan: pwmfan { + fsl,pins = < + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x0b0b1 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b1 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b1 + >; + }; + + pinctrl_spdif_out: spdifout { + fsl,pins = < + MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091 + >; + }; + + pinctrl_spdif_in: spdifin { + fsl,pins = < + MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_cpi1: csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b1 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b1 + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b1 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b1 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b1 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b1 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b1 + >; + }; + + /*camera2-pinctrl is in imx6q-emcon.dtsi or imx6dl-emcon.dtsi*/ + + pinctrl_pcie_ctrl: pciegrp { + fsl,pins = < + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 + >; + }; + + pinctrl_audmux: audmux { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b060 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130B0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b060 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4000b070 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b870 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0b0b1 + >; + }; + + pinctrl_usb_host1: usbhgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x1B058 + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1B058 + >; + }; + + pinctrl_usb_otg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x17059 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x17059 + >; + }; + + pinctrl_lvds_reg: lvdsreggrp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x0b0b1 + >; + }; + + pinctrl_lvds_bl: lvdsbacklightgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x0b0b1 + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b1 + >; + }; + + pinctrl_irq_touch1: irqtouch1 { + fsl,pins = < + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x0b0b1 + >; + }; + + pinctrl_rgb_bl_en: rgbenable { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x0b0b1 + >; + }; + + pinctrl_irq_touch2: irqtouch2 { + fsl,pins = < + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x0b0b1 + >; + }; + + pinctrl_rgb_bl: rgbbacklightgrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x0b0b1 + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b1 + >; + }; + + pinctrl_rgb24_display: rgbgrp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x4001a0b1 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b058 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 + >; + }; + + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + MX6QDL_PAD_GPIO_1__SD1_CD_B 0x1b0b1 + MX6QDL_PAD_DI0_PIN4__SD1_WP 0x1b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_GPIO_4__SD2_CD_B 0x1b0b1 + MX6QDL_PAD_GPIO_2__SD2_WP 0x1b0b1 + >; + }; + +}; + + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + rtc: rtc@68 { + compatible = "dallas,ds1307"; + reg = <0x68>; + }; + + da9063: pmic@58 { + compatible = "dlg,da9063"; + reg = <0x58>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio2>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + + onkey { + compatible = "dlg,da9063-onkey"; + wakeup-source; + }; + + wdt { + compatible = "dlg,da9063-watchdog"; + timeout-sec = <0>; + }; + + regulators { + vddcore_reg: bcore1 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <20000>; + regulator-name = "DA9063_CORE"; + regulator-always-on; + }; + + vddsoc_reg: bcore2 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <20000>; + regulator-name = "DA9063_SOC"; + regulator-always-on; + }; + + vdd_ddr3_reg: bpro { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <20000>; + regulator-always-on; + }; + + vdd_3v3_reg: bperi { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <20000>; + regulator-always-on; + }; + + vdd_sata_reg: ldo3 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + vdd_mipi_reg: ldo4 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vdd_mx6_snvs_reg: ldo5 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_hdmi_reg: ldo6 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_pcie_reg: ldo7 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vdd_1V8_reg: ldo8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_3V3_sdc_reg: ldo9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_1V2_reg: ldo10 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; + phy-reset-duration = <50>; + phy-supply = <&vdd_1V8_reg>; + phy-handle = <&ksz9031>; + status = "okay"; + + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ksz9031: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <30 IRQ_TYPE_EDGE_FALLING>; + rxdv-skew-ps = <480>; + txen-skew-ps = <480>; + rxd0-skew-ps = <480>; + rxd1-skew-ps = <480>; + rxd2-skew-ps = <480>; + rxd3-skew-ps = <480>; + txd0-skew-ps = <420>; + txd1-skew-ps = <420>; + txd2-skew-ps = <360>; + txd3-skew-ps = <360>; + txc-skew-ps = <1020>; + rxc-skew-ps = <960>; + }; + }; +}; + + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + non-removable; + bus-width = <8>; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_ctrl>; + reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; + disable-gpio = <&gpio2 22 GPIO_ACTIVE_LOW>; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + fsl,wp-controller; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + fsl,wp-controller; +}; + + +&ipu1_di0_disp0 { + remote-endpoint = <&rgb_encoder_in>; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>, + <&gpio2 26 GPIO_ACTIVE_HIGH>; +}; + +&ecspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nor_flash>; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_host1>; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg>; + vbus-supply = <®_usb_otg>; + dr_mode = "peripheral"; +}; + +/******device power Management*********/ + +&cpu0 { + voltage-tolerance = <2>; +}; + +®_arm { + vin-supply = <&vddcore_reg>; +}; + +®_soc { + vin-supply = <&vddsoc_reg>; +}; + +®_pu { + vin-supply = <&vddsoc_reg>; +}; + + + +/*******Disabled HW following***********/ + + +&weim { + status = "disabled"; +}; + +&snvs_rtc { + status = "disabled"; +};
On Fri, Apr 20, 2018 at 02:50:52PM +0200, jan.tuerk@emtrion.com wrote:
From: Jan Tuerk jan.tuerk@emtrion.com
This patch adds support for the emtrion GmbH emCON-MX6 modules. They are available with imx.6 Solo, Dual-Lite, Dual and Quad equipped with Memory from 512MB to 2GB (configured by U-Boot).
Our default developer-Kit ships with the Avari baseboard and the EDT ETM0700G0BDH6 Display (imx6[q|dl]-emcon-avari).
The devicetree is split into the common part providing all module components and the basic support for all SoC versions (imx6qdl-emcon.dtsi) and parts which are i.mx6 S|DL and D|Q relevant. Finally the support for the avari baseboard in the developer-kit configuration is provided by the emcon-avari dts files.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com
Documentation/devicetree/bindings/arm/emtrion.txt | 13 +
It's better to have a separate patch for bindings doc, which needs to be acknowledged by DT maintainers.
arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx6dl-emcon-avari.dts | 224 ++++++ arch/arm/boot/dts/imx6dl-emcon.dtsi | 27 + arch/arm/boot/dts/imx6q-emcon-avari.dts | 224 ++++++ arch/arm/boot/dts/imx6q-emcon.dtsi | 27 + arch/arm/boot/dts/imx6qdl-emcon.dtsi | 838 ++++++++++++++++++++++ 7 files changed, 1355 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/emtrion.txt create mode 100644 arch/arm/boot/dts/imx6dl-emcon-avari.dts create mode 100644 arch/arm/boot/dts/imx6dl-emcon.dtsi create mode 100644 arch/arm/boot/dts/imx6q-emcon-avari.dts create mode 100644 arch/arm/boot/dts/imx6q-emcon.dtsi create mode 100644 arch/arm/boot/dts/imx6qdl-emcon.dtsi
diff --git a/Documentation/devicetree/bindings/arm/emtrion.txt b/Documentation/devicetree/bindings/arm/emtrion.txt new file mode 100644 index 000000000000..3ff6c6c2034d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/emtrion.txt @@ -0,0 +1,13 @@ +Emtrion Devicetree Bindings +===========================
+emCON Series: +-------------
+Required root node properties
- compatible:
- "emtrion,emcon-mx6", "fsl,imx6q", "fsl,imx6dl"; : emCON-MX6 Generic SoM
- "emtrion,emcon-mx6", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM
- "emtrion,emcon-mx6-avari", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM on Avari Base
- "emtrion,emcon-mx6", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM
- "emtrion,emcon-mx6-avari", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM on Avari Base
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7e2424957809..05b930da3fda 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -381,6 +381,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-cubox-i-emmc-som-v15.dtb \ imx6dl-cubox-i-som-v15.dtb \ imx6dl-dfi-fs700-m60.dtb \
- imx6dl-emcon-avari.dtb \ imx6dl-gw51xx.dtb \ imx6dl-gw52xx.dtb \ imx6dl-gw53xx.dtb \
@@ -442,6 +443,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-display5-tianma-tm070-1280x768.dtb \ imx6q-dmo-edmqmx6.dtb \ imx6q-dms-ba16.dtb \
- imx6q-emcon-avari.dtb \ imx6q-evi.dtb \ imx6q-gk802.dtb \ imx6q-gw51xx.dtb \
diff --git a/arch/arm/boot/dts/imx6dl-emcon-avari.dts b/arch/arm/boot/dts/imx6dl-emcon-avari.dts new file mode 100644 index 000000000000..2344fb9498e3 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-emcon-avari.dts @@ -0,0 +1,224 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/* Copyright (C) 2018 emtrion GmbH
- Author: Jan Tuerk jan.tuerk@emtrion.com
- */
/* * Copyright ... */
+/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-emcon.dtsi" +#include "imx6dl-emcon.dtsi" /*Include camera2 pinmux*/
/* bla bla */
+/ {
- model = "emtrion SoM emCON-MX6 Solo/Dual-Lite Avari";
- compatible = "emtrion,emcon-mx6-avari", "fsl,imx6dl";
- aliases {
mmc0 = &usdhc3;mmc2 = &usdhc1;mmc1 = &usdhc2;mmc3 = &usdhc4;- };
- chosen {
stdout-path = <&uart1>;- };
- memory {
The unit-address is missing.
reg = <0x10000000 0x40000000>;- };
- supplies {
compatible = "simple-bus";#address-cells = <1>;#size-cells = <0>;
DT maintainers do not like this fake container node. Please put the fixed regulator nodes directly under root with a unique name like below.
reg_xxx: regulator-xxx { ... };
wallplug5p0: supply@0 {compatible = "regulator-fixed";reg = <0>;regulator-name = "WALL-PLUG";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;regulator-always-on;regulator-boot-on;};base3p3: supply@1 {compatible = "regulator-fixed";reg = <1>;vin-supply = <&wallplug5p0>;regulator-name = "3V3-avari";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-always-on;regulator-boot-on;};base1p5: supply@2 {compatible = "regulator-fixed";reg = <2>;vin-supply = <&base3p3>;regulator-name = "1V5-avari";regulator-min-microvolt = <1500000>;regulator-max-microvolt = <1500000>;regulator-always-on;regulator-boot-on;};reg_usb_otg: otgvbus@3 {compatible = "regulator-fixed";reg = <3>;vin-supply = <&wallplug5p0>;regulator-name = "OTG_VBUS";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;regulator-always-on;};- };
- sndosc: 12MHZosc {
clock-xxx { ... };
compatible = "fixed-clock";#clock-cells = <0>;clock-frequency = <12000000>;- };
- sound {
compatible = "fsl,imx-audio-sgtl5000";model = "emCON-avari-sgtl5000";ssi-controller = <&ssi2>;audio-codec = <&sgtl5000>;audio-routing ="Headphone Jack", "HP_OUT";mux-int-port = <2>;mux-ext-port = <3>;- };
+};
One newline is good enough.
+&iomuxc {
- pinctrl-names = "default";
- /*Unused emCON-MX6 outputs on AVARI*/
- pinctrl-0 = <
&pinctrl_emcon_gpio1 &pinctrl_emcon_gpio2&pinctrl_emcon_gpio3 &pinctrl_emcon_gpio5&pinctrl_emcon_gpio6 &pinctrl_emcon_gpio7&pinctrl_emcon_gpio8 &pinctrl_emcon_irq_a&pinctrl_emcon_irq_b &pinctrl_emcon_irq_c&pinctrl_emcon_irq_pwr &pinctrl_nor_flash&pinctrl_usdhc2&pinctrl_spdif_out &pinctrl_spdif_in&pinctrl_cpi1 &pinctrl_cpi2>;
Only pins without clear consumer should be put into hog group. Also the indent seems broken.
+};
+&audmux {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_audmux>;
- status = "okay";
+};
One newline is good enough. Also, please try to sort these labelled nodes alphabetically.
+&i2c3 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- status = "okay";
- sgtl5000: audio-codec@a {
compatible = "fsl,sgtl5000";reg = <0x0a>;clocks = <&sndosc>;VDDA-supply = <&base3p3>;VDDIO-supply = <&base3p3>;
#sound-dai-cells is missing.
- };
- boardID: pca8754a@3a {
Please find a more generic node name for it.
compatible = "nxp,pca8574";reg = <0x3a>;gpio-controller;#gpio-cells = <1>;- };
- captouch: touchscreen@38 {
compatible = "edt,edt-ft5406";reg = <0x38>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_irq_touch2 &pinctrl_emcon_gpio4>;interrupt-parent = <&gpio6>;interrupts = <31 IRQ_TYPE_EDGE_FALLING>;wake-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;wakeup-source;status = "okay";
The "okay" status is only needed to flip the default "disabled" device.
- };
+};
+&ssi2 {
- status = "okay";
+};
+&rgb_encoder {
- status = "okay";
+};
+&rgb_panel {
- compatible = "edt,etm0700g0bdh6";
- status = "okay";
+};
+&i2c2 {
- status = "okay";
+};
+&hdmi {
- ddc-i2c-bus = <&i2c2>;
- status = "okay";
+};
+&usbh1 {
- status = "okay";
+};
+&usbotg {
- status = "okay";
+};
+&pcie {
- status = "okay";
+};
+&usdhc1 {
- status = "okay";
+};
+&can1 {
- status = "okay";
+};
+&can2 {
- status = "okay";
+};
+&uart2 {
- status = "okay";
- uart-has-rtscts;
+};
+&uart3 {
- status = "okay";
+};
+&uart4 {
- status = "okay";
+};
+&uart5 {
- status = "okay";
+};
+&ecspi2 {
- status = "okay";
+}; diff --git a/arch/arm/boot/dts/imx6dl-emcon.dtsi b/arch/arm/boot/dts/imx6dl-emcon.dtsi new file mode 100644 index 000000000000..1ed629c9747e --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-emcon.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/* Copyright (C) 2018 emtrion GmbH
- Author: Jan Tuerk jan.tuerk@emtrion.com
- */
+/ {
- model = "emtrion SoM emCON-MX6 Solo/DualLite";
- compatible = "emtrion,emcon-mx6", "fsl,imx6dl";
+};
+&iomuxc {
- pinctrl_cpi2: csi1grp {
fsl,pins = <MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0x0b0b1MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b1MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b1MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b1MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b1MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b1MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b1MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b1MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b1MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b1MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b1>;- };
+}; diff --git a/arch/arm/boot/dts/imx6q-emcon-avari.dts b/arch/arm/boot/dts/imx6q-emcon-avari.dts new file mode 100644 index 000000000000..0c85b5ee011c --- /dev/null +++ b/arch/arm/boot/dts/imx6q-emcon-avari.dts
There are so many things duplicated between imx6dl-emcon-avari.dts and imx6q-emcon-avari.dts. Can you do something to avoid that?
@@ -0,0 +1,224 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/* Copyright (C) 2018 emtrion GmbH
- Author: Jan Tuerk jan.tuerk@emtrion.com
- */
+/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-emcon.dtsi" +#include "imx6q-emcon.dtsi" /*Include camera2 pinmux*/
+/ {
- model = "emtrion SoM emCON-MX6 Dual/Quad on Avari";
- compatible = "emtrion,emcon-mx6-avari", "fsl,imx6q";
- aliases {
mmc0 = &usdhc3;mmc2 = &usdhc1;mmc1 = &usdhc2;mmc3 = &usdhc4;- };
- chosen {
stdout-path = <&uart1>;- };
- memory {
reg = <0x10000000 0x40000000>;- };
- supplies {
compatible = "simple-bus";#address-cells = <1>;#size-cells = <0>;wallplug5p0: supply@0 {compatible = "regulator-fixed";reg = <0>;regulator-name = "WALL-PLUG";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;regulator-always-on;regulator-boot-on;};base3p3: supply@1 {compatible = "regulator-fixed";reg = <1>;vin-supply = <&wallplug5p0>;regulator-name = "3V3-avari";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-always-on;regulator-boot-on;};base1p5: supply@2 {compatible = "regulator-fixed";reg = <2>;vin-supply = <&base3p3>;regulator-name = "1V5-avari";regulator-min-microvolt = <1500000>;regulator-max-microvolt = <1500000>;regulator-always-on;regulator-boot-on;};reg_usb_otg: otgvbus@3 {compatible = "regulator-fixed";reg = <3>;vin-supply = <&wallplug5p0>;regulator-name = "OTG_VBUS";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;regulator-always-on;};- };
- sndosc: 12MHZosc {
compatible = "fixed-clock";#clock-cells = <0>;clock-frequency = <12000000>;- };
- sound {
compatible = "fsl,imx-audio-sgtl5000";model = "emCON-avari-sgtl5000";ssi-controller = <&ssi2>;audio-codec = <&sgtl5000>;audio-routing ="Headphone Jack", "HP_OUT";mux-int-port = <2>;mux-ext-port = <3>;- };
+};
+&iomuxc {
- pinctrl-names = "default";
- /*Unused emCON-MX6 pingroups on AVARI baseboard, enable defaults*/
- pinctrl-0 = <
&pinctrl_emcon_gpio1 &pinctrl_emcon_gpio2&pinctrl_emcon_gpio3 &pinctrl_emcon_gpio5&pinctrl_emcon_gpio6 &pinctrl_emcon_gpio7&pinctrl_emcon_gpio8 &pinctrl_emcon_irq_a&pinctrl_emcon_irq_b &pinctrl_emcon_irq_c&pinctrl_emcon_irq_pwr &pinctrl_nor_flash&pinctrl_usdhc2&pinctrl_spdif_out &pinctrl_spdif_in&pinctrl_cpi1 &pinctrl_cpi2>;+};
+&audmux {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_audmux>;
- status = "okay";
+};
+&i2c3 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- status = "okay";
- sgtl5000: audio-codec@a {
compatible = "fsl,sgtl5000";reg = <0x0a>;clocks = <&sndosc>;VDDA-supply = <&base3p3>;VDDIO-supply = <&base3p3>;- };
- boardID: pca8754a@3a {
compatible = "nxp,pca8574";reg = <0x3a>;gpio-controller;#gpio-cells = <1>;- };
- captouch: touchscreen@38 {
compatible = "edt,edt-ft5406";reg = <0x38>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_irq_touch2 &pinctrl_emcon_gpio4>;interrupt-parent = <&gpio6>;interrupts = <31 IRQ_TYPE_EDGE_FALLING>;wake-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;wakeup-source;status = "okay";- };
+};
+&ssi2 {
- status = "okay";
+};
+&rgb_encoder {
- status = "okay";
+};
+&rgb_panel {
- compatible = "edt,etm0700g0bdh6";
- status = "okay";
+};
+&i2c2 {
- status = "okay";
+};
+&hdmi {
- ddc-i2c-bus = <&i2c2>;
- status = "okay";
+};
+&usbh1 {
- status = "okay";
+};
+&usbotg {
- status = "okay";
+};
+&pcie {
- status = "okay";
+};
+&usdhc1 {
- status = "okay";
+};
+&can1 {
- status = "okay";
+};
+&can2 {
- status = "okay";
+};
+&uart2 {
- status = "okay";
- uart-has-rtscts;
+};
+&uart3 {
- status = "okay";
+};
+&uart4 {
- status = "okay";
+};
+&uart5 {
- status = "okay";
+};
+&ecspi2 {
- status = "okay";
+}; diff --git a/arch/arm/boot/dts/imx6q-emcon.dtsi b/arch/arm/boot/dts/imx6q-emcon.dtsi new file mode 100644 index 000000000000..33b3fbf3fba0 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-emcon.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/* Copyright (C) 2018 emtrion GmbH
- Author: Jan Tuerk jan.tuerk@emtrion.com
- */
+/ {
- model = "emtrion SoM emCON-MX6 Dual/Quad";
- compatible = "emtrion,emcon-mx6", "fsl,imx6q";
+};
+&iomuxc {
- pinctrl_cpi2: csi1grp {
fsl,pins = <MX6QDL_PAD_EIM_D17__IPU2_CSI1_PIXCLK 0x0b0b1MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b1MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b1MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b1MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b1MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b1MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b1MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b1MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b1MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b1MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b1>;- };
+}; diff --git a/arch/arm/boot/dts/imx6qdl-emcon.dtsi b/arch/arm/boot/dts/imx6qdl-emcon.dtsi new file mode 100644 index 000000000000..5f9296dce130 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-emcon.dtsi @@ -0,0 +1,838 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/* Copyright (C) 2018 emtrion GmbH
- Author: Jan Tuerk jan.tuerk@emtrion.com
- */
+#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/input/input.h>
+/ {
- model = "emtrion SoM emCON-MX6";
- compatible = "emtrion,emcon-mx6", "fsl,imx6q", "fsl,imx6dl";
- aliases {
mmc0 = &usdhc3;mmc2 = &usdhc1;mmc1 = &usdhc2;- };
- regulators {
compatible = "simple-bus";#address-cells = <1>;#size-cells = <0>;reg_parallel_disp: regulator@0 {compatible = "regulator-fixed";reg = <0>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_rgb_bl_en>;regulator-name = "LCD-Supply";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;gpio = <&gpio7 9 GPIO_ACTIVE_HIGH>;enable-active-high;};reg_lvds_disp: regulator@1 {compatible = "regulator-fixed";reg = <1>;regulator-name = "LVDS-Supply";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;gpio = <&gpio7 10 GPIO_ACTIVE_HIGH>;enable-active-high;};- };
- som_leds: leds {
compatible = "gpio-leds";pinctrl-names = "default";pinctrl-0 = <&pinctrl_som_leds>;green {label = "som:green";gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;linux,default-trigger = "heartbeat";default-state = "on";};red {label = "som:red";gpios = <&gpio3 1 GPIO_ACTIVE_LOW>;default-state = "keep";};- };
- gpio-keys {
compatible = "gpio-keys";pinctrl-names = "default";pinctrl-0 = <&pinctrl_emcon_wake>;wake {label = "Wake";linux,code = <KEY_WAKEUP>;gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;wakeup-source;};- };
- pwm_fan: pwm-fan {
compatible = "pwm-fan";cooling-min-state = <0>;cooling-max-state = <4>;#cooling-cells = <2>;pwms = <&pwm4 0 50000>;cooling-levels = <0 64 127 191 255>;status = "disabled";- };
- rgb_encoder: disp0 {
s/disp0/display
compatible = "fsl,imx-parallel-display";#address-cells = <1>;#size-cells = <0>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_rgb24_display>;status = "disabled";port@0 {reg = <0>;
Have a newline between property list and child node.
rgb_encoder_in: endpoint {remote-endpoint = <&ipu1_di0_disp0>;};};port@1 {reg = <1>;rgb_encoder_out: endpoint {remote-endpoint = <&rgb_panel_in>;};};- };
- rgb_panel: panel {
backlight = <&rgb_backlight>;power-supply = <®_parallel_disp>;port {rgb_panel_in: endpoint {remote-endpoint = <&rgb_encoder_out>;};};- };
- rgb_backlight: rgb-backlight {
compatible = "pwm-backlight";pinctrl-names = "default";pinctrl-0 = <&pinctrl_rgb_bl>;enable-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;pwms = <&pwm3 0 5000000>;brightness-levels = <250 176 160 144 128 11296 80 64 48 32 16 8 1>;
Broken indent.
default-brightness-level = <13>;status = "okay";- };
- lvds_backlight: lvds-backlight {
compatible = "pwm-backlight";pinctrl-names = "default";pinctrl-0 = <&pinctrl_lvds_bl>;enable-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>;pwms = <&pwm1 0 50000>;brightness-levels = <0 4 8 16 32 64 80 96 112128 144 160 176 250>;default-brightness-level = <13>;status = "okay";- };
+};
+&iomuxc {
- pinctrl_secure: securegrp {
Unused?
fsl,pins = <MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1>;- };
- pinctrl_uart1: uart1grp {
fsl,pins = <MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1>;- };
- pinctrl_uart2: uart2grp {
fsl,pins = <MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1>;- };
- pinctrl_uart3: uart3grp {
fsl,pins = <MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1>;- };
- pinctrl_uart4: uart4grp {
fsl,pins = <MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1>;- };
- pinctrl_uart5: uart5grp {
fsl,pins = <MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1>;- };
- pinctrl_emcon_gpio1: emcongpio1 {
fsl,pins = <MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x0b0b1>;- };
Try to keep these pinctrl entries alphabetically sorted.
- pinctrl_emcon_gpio2: emcongpio2 {
fsl,pins = <MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0b0b1>;- };
- pinctrl_emcon_gpio3: emcongpio3 {
fsl,pins = <MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0b0b1>;- };
- pinctrl_emcon_gpio4: emcongpio4 {
fsl,pins = <MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0b0b1>;- };
- pinctrl_emcon_gpio5: emcongpio5 {
fsl,pins = <MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x0b0b1>;- };
- pinctrl_emcon_gpio6: emcongpio6 {
fsl,pins = <MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0b0b1>;- };
- pinctrl_emcon_gpio7: emcongpio7 {
fsl,pins = <MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0b0b1>;- };
- pinctrl_emcon_gpio8: emcongpio8 {
fsl,pins = <MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0b0b1>;- };
- pinctrl_emcon_irq_a: emconirqa {
fsl,pins = <MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x0b0b1>;- };
- pinctrl_emcon_irq_b: emconirqb {
fsl,pins = <MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x0b0b1>;- };
- pinctrl_emcon_irq_c: emconirqc {
fsl,pins = <MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0b0b1>;- };
- pinctrl_emcon_wake: emconwake {
fsl,pins = <MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1>;- };
- pinctrl_emcon_irq_pwr: emconirqpwr {
fsl,pins = <MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0b0b1>;- };
- pinctrl_som_leds: somledgrp {
fsl,pins = <MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x0b0b1MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x0b0b1>;- };
- pinctrl_nor_flash: norflashgrp {
fsl,pins = <MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b1MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1>;- };
- pinctrl_ecspi2: ecspi2grp {
fsl,pins = <MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1>;- };
- pinctrl_pwm_fan: pwmfan {
fsl,pins = <MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x0b0b1>;- };
- pinctrl_can1: can1grp {
fsl,pins = <MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1>;- };
- pinctrl_can2: can2grp {
fsl,pins = <MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b1MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b1>;- };
- pinctrl_spdif_out: spdifout {
fsl,pins = <MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091>;- };
- pinctrl_spdif_in: spdifin {
fsl,pins = <MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0>;- };
- pinctrl_cpi1: csi0grp {
fsl,pins = <MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b1MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b1MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b1MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b1MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b1MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b1MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b1MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b1MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b1MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b1>;- };
- /*camera2-pinctrl is in imx6q-emcon.dtsi or imx6dl-emcon.dtsi*/
- pinctrl_pcie_ctrl: pciegrp {
fsl,pins = <MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1>;- };
- pinctrl_audmux: audmux {
fsl,pins = <MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b060MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130B0MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b060>;- };
- pinctrl_i2c1: i2c1grp {
fsl,pins = <MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1>;- };
- pinctrl_i2c2: i2c2grp {
fsl,pins = <MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1>;- };
- pinctrl_i2c3: i2c3grp {
fsl,pins = <MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4000b070MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b870>;- };
- pinctrl_pmic: pmicgrp {
fsl,pins = <MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0b0b1>;- };
- pinctrl_usb_host1: usbhgrp {
fsl,pins = <MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x1B058MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1B058>;- };
- pinctrl_usb_otg: usbotggrp {
fsl,pins = <MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x17059MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x17059>;- };
- pinctrl_lvds_reg: lvdsreggrp {
fsl,pins = <MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x0b0b1>;- };
- pinctrl_lvds_bl: lvdsbacklightgrp {
fsl,pins = <MX6QDL_PAD_GPIO_9__PWM1_OUT 0x0b0b1MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b1>;- };
- pinctrl_irq_touch1: irqtouch1 {
fsl,pins = <MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x0b0b1>;- };
- pinctrl_rgb_bl_en: rgbenable {
fsl,pins = <MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x0b0b1>;- };
- pinctrl_irq_touch2: irqtouch2 {
fsl,pins = <MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x0b0b1>;- };
- pinctrl_rgb_bl: rgbbacklightgrp {
fsl,pins = <MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x0b0b1MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b1>;- };
- pinctrl_rgb24_display: rgbgrp {
fsl,pins = <MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10>;- };
- pinctrl_enet: enetgrp {
fsl,pins = <MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b030MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b030MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x4001a0b1MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b058MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0>;- };
- pinctrl_usdhc3: usdhc3grp {
fsl,pins = <MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1>;- };
- pinctrl_usdhc1: usdhc1grp {
fsl,pins = <MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059MX6QDL_PAD_GPIO_1__SD1_CD_B 0x1b0b1MX6QDL_PAD_DI0_PIN4__SD1_WP 0x1b0b1>;- };
- pinctrl_usdhc2: usdhc2grp {
fsl,pins = <MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059MX6QDL_PAD_GPIO_4__SD2_CD_B 0x1b0b1MX6QDL_PAD_GPIO_2__SD2_WP 0x1b0b1>;- };
+};
+&i2c1 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- status = "okay";
- rtc: rtc@68 {
compatible = "dallas,ds1307";reg = <0x68>;- };
- da9063: pmic@58 {
compatible = "dlg,da9063";reg = <0x58>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_pmic>;interrupt-parent = <&gpio2>;interrupts = <8 IRQ_TYPE_LEVEL_LOW>;interrupt-controller;onkey {compatible = "dlg,da9063-onkey";wakeup-source;};wdt {
s/wdt/watchdog
compatible = "dlg,da9063-watchdog";timeout-sec = <0>;};regulators {vddcore_reg: bcore1 {regulator-min-microvolt = <1100000>;regulator-max-microvolt = <1450000>;regulator-ramp-delay = <20000>;regulator-name = "DA9063_CORE";regulator-always-on;};vddsoc_reg: bcore2 {regulator-min-microvolt = <1100000>;regulator-max-microvolt = <1450000>;regulator-ramp-delay = <20000>;regulator-name = "DA9063_SOC";regulator-always-on;};vdd_ddr3_reg: bpro {regulator-min-microvolt = <1500000>;regulator-max-microvolt = <1500000>;regulator-ramp-delay = <20000>;regulator-always-on;};vdd_3v3_reg: bperi {regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-ramp-delay = <20000>;regulator-always-on;};vdd_sata_reg: ldo3 {regulator-min-microvolt = <2500000>;regulator-max-microvolt = <2500000>;regulator-always-on;};vdd_mipi_reg: ldo4 {regulator-min-microvolt = <2500000>;regulator-max-microvolt = <2500000>;regulator-always-on;};vdd_mx6_snvs_reg: ldo5 {regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-always-on;};vdd_hdmi_reg: ldo6 {regulator-min-microvolt = <2500000>;regulator-max-microvolt = <2500000>;regulator-always-on;regulator-boot-on;};vdd_pcie_reg: ldo7 {regulator-min-microvolt = <2500000>;regulator-max-microvolt = <2500000>;regulator-always-on;};vdd_1V8_reg: ldo8 {regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-always-on;};vdd_3V3_sdc_reg: ldo9 {regulator-min-microvolt = <1800000>;regulator-max-microvolt = <3300000>;regulator-always-on;};vdd_1V2_reg: ldo10 {regulator-min-microvolt = <1200000>;regulator-max-microvolt = <1200000>;regulator-always-on;};};- };
+};
+&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
+};
+&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
+};
+&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
+};
+&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart4>;
+};
+&uart5 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart5>;
+};
+&fec {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet>;
- phy-mode = "rgmii";
- phy-reset-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
- phy-reset-duration = <50>;
- phy-supply = <&vdd_1V8_reg>;
- phy-handle = <&ksz9031>;
- status = "okay";
- mdio {
#address-cells = <1>;#size-cells = <0>;ksz9031: phy@0 {compatible = "ethernet-phy-ieee802.3-c22";reg = <0>;interrupt-parent = <&gpio1>;interrupts = <30 IRQ_TYPE_EDGE_FALLING>;rxdv-skew-ps = <480>;txen-skew-ps = <480>;rxd0-skew-ps = <480>;rxd1-skew-ps = <480>;rxd2-skew-ps = <480>;rxd3-skew-ps = <480>;txd0-skew-ps = <420>;txd1-skew-ps = <420>;txd2-skew-ps = <360>;txd3-skew-ps = <360>;txc-skew-ps = <1020>;rxc-skew-ps = <960>;};- };
+};
+&usdhc3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc3>;
- non-removable;
- bus-width = <8>;
- status = "okay";
+};
+&pcie {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie_ctrl>;
- reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
- disable-gpio = <&gpio2 22 GPIO_ACTIVE_LOW>;
+};
+&i2c2 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
+};
+&usdhc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1>;
- fsl,wp-controller;
+};
+&usdhc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2>;
- fsl,wp-controller;
+};
+&ipu1_di0_disp0 {
- remote-endpoint = <&rgb_encoder_in>;
+};
+&pwm1 {
- status = "okay";
+};
+&pwm3 {
- status = "okay";
+};
+&pwm4 {
- status = "okay";
+};
+&ecspi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi2>;
- cs-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>,
<&gpio2 26 GPIO_ACTIVE_HIGH>;+};
+&ecspi4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nor_flash>;
+};
+&can1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_can1>;
+};
+&can2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_can2>;
+};
+&usbh1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb_host1>;
+};
+&usbotg {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb_otg>;
- vbus-supply = <®_usb_otg>;
- dr_mode = "peripheral";
+};
+/******device power Management*********/
+&cpu0 {
- voltage-tolerance = <2>;
+};
+®_arm {
- vin-supply = <&vddcore_reg>;
+};
+®_soc {
- vin-supply = <&vddsoc_reg>;
+};
+®_pu {
- vin-supply = <&vddsoc_reg>;
+};
+/*******Disabled HW following***********/
+&weim {
- status = "disabled";
+};
Isn't weim disabled by default?
Shawn
+&snvs_rtc {
- status = "disabled";
+};
2.11.0
-----Ursprüngliche Nachricht----- Von: Shawn Guo Gesendet: Montag, 23. April 2018 10:45 Re: [PATCH v3 5/6] ARM: dts: Add support for emtrion emCON-MX6 series
On Fri, Apr 20, 2018 at 02:50:52PM +0200, jan.tuerk@emtrion.com wrote:
From: Jan Tuerk jan.tuerk@emtrion.com
This patch adds support for the emtrion GmbH emCON-MX6 modules. They are available with imx.6 Solo, Dual-Lite, Dual and Quad equipped with Memory from 512MB to 2GB (configured by U-Boot).
Our default developer-Kit ships with the Avari baseboard and the EDT ETM0700G0BDH6 Display (imx6[q|dl]-emcon-avari).
The devicetree is split into the common part providing all module components and the basic support for all SoC versions (imx6qdl-emcon.dtsi) and parts which are i.mx6 S|DL and D|Q relevant. Finally the support for the avari baseboard in the developer-kit configuration is provided by the emcon-avari dts files.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com
Documentation/devicetree/bindings/arm/emtrion.txt | 13 +
It's better to have a separate patch for bindings doc, which needs to be acknowledged by DT maintainers.
I can change that, but nobody complained in the first 2 revisions of the patch. Also I though having the documentation is required for merging new bindings?
arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx6dl-emcon-avari.dts | 224 ++++++ arch/arm/boot/dts/imx6dl-emcon.dtsi | 27 + arch/arm/boot/dts/imx6q-emcon-avari.dts | 224 ++++++ arch/arm/boot/dts/imx6q-emcon.dtsi | 27 + arch/arm/boot/dts/imx6qdl-emcon.dtsi | 838
++++++++++++++++++++++
7 files changed, 1355 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/emtrion.txt create mode 100644 arch/arm/boot/dts/imx6dl-emcon-avari.dts create mode 100644 arch/arm/boot/dts/imx6dl-emcon.dtsi create mode 100644 arch/arm/boot/dts/imx6q-emcon-avari.dts create mode 100644 arch/arm/boot/dts/imx6q-emcon.dtsi create mode 100644 arch/arm/boot/dts/imx6qdl-emcon.dtsi
diff --git a/Documentation/devicetree/bindings/arm/emtrion.txt b/Documentation/devicetree/bindings/arm/emtrion.txt new file mode 100644 index 000000000000..3ff6c6c2034d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/emtrion.txt @@ -0,0 +1,13 @@ +Emtrion Devicetree Bindings +===========================
+emCON Series:
[..]
index 000000000000..2344fb9498e3 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-emcon-avari.dts @@ -0,0 +1,224 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/* Copyright (C) 2018 emtrion GmbH
- Author: Jan Tuerk jan.tuerk@emtrion.com */
/*
- Copyright ...
*/
Ack
+/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-emcon.dtsi" +#include "imx6dl-emcon.dtsi" /*Include camera2 pinmux*/
/* bla bla */
+/ {
- model = "emtrion SoM emCON-MX6 Solo/Dual-Lite Avari";
- compatible = "emtrion,emcon-mx6-avari", "fsl,imx6dl";
- aliases {
mmc0 = &usdhc3;mmc2 = &usdhc1;mmc1 = &usdhc2;mmc3 = &usdhc4;- };
- chosen {
stdout-path = <&uart1>;- };
- memory {
The unit-address is missing.
Ack
reg = <0x10000000 0x40000000>;- };
- supplies {
compatible = "simple-bus";#address-cells = <1>;#size-cells = <0>;DT maintainers do not like this fake container node. Please put the fixed regulator nodes directly under root with a unique name like below.
Ok I'll change this
reg_xxx: regulator-xxx { ... };
wallplug5p0: supply@0 {compatible = "regulator-fixed";reg = <0>;regulator-name = "WALL-PLUG";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;regulator-always-on;regulator-boot-on;};
[...]
reg_usb_otg: otgvbus@3 {compatible = "regulator-fixed";reg = <3>;vin-supply = <&wallplug5p0>;regulator-name = "OTG_VBUS";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;regulator-always-on;};- };
- sndosc: 12MHZosc {
clock-xxx { ... };
ok
compatible = "fixed-clock";#clock-cells = <0>;clock-frequency = <12000000>;- };
- sound {
compatible = "fsl,imx-audio-sgtl5000";model = "emCON-avari-sgtl5000";ssi-controller = <&ssi2>;audio-codec = <&sgtl5000>;audio-routing ="Headphone Jack", "HP_OUT";mux-int-port = <2>;mux-ext-port = <3>;- };
+};
One newline is good enough.
ack
+&iomuxc {
- pinctrl-names = "default";
- /*Unused emCON-MX6 outputs on AVARI*/
- pinctrl-0 = <
&pinctrl_emcon_gpio1&pinctrl_emcon_gpio2
&pinctrl_emcon_gpio3&pinctrl_emcon_gpio5
&pinctrl_emcon_gpio6&pinctrl_emcon_gpio7
&pinctrl_emcon_gpio8&pinctrl_emcon_irq_a
&pinctrl_emcon_irq_b &pinctrl_emcon_irq_c&pinctrl_emcon_irq_pwr &pinctrl_nor_flash&pinctrl_usdhc2&pinctrl_spdif_out &pinctrl_spdif_in&pinctrl_cpi1 &pinctrl_cpi2>;Only pins without clear consumer should be put into hog group. Also the indent seems broken.
Yes the consumer is currently "not-defined" on the Avari baseboard, as those pins are signals on the emCON Interface. I've added them there to force a basic initialization matching the Interfaces specified function blocks in the SoC. I'll rework the indent as well.
+};
+&audmux {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_audmux>;
- status = "okay";
+};
One newline is good enough. Also, please try to sort these labelled nodes alphabetically.
+&i2c3 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- status = "okay";
- sgtl5000: audio-codec@a {
compatible = "fsl,sgtl5000";reg = <0x0a>;clocks = <&sndosc>;VDDA-supply = <&base3p3>;VDDIO-supply = <&base3p3>;#sound-dai-cells is missing.
yes, I'll change that
- };
- boardID: pca8754a@3a {
Please find a more generic node name for it.
you mean boardID@3a? This chip identifies the baseboard type for the bootloader.
compatible = "nxp,pca8574";reg = <0x3a>;gpio-controller;#gpio-cells = <1>;- };
- captouch: touchscreen@38 {
compatible = "edt,edt-ft5406";reg = <0x38>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_irq_touch2 &pinctrl_emcon_gpio4>;interrupt-parent = <&gpio6>;interrupts = <31 IRQ_TYPE_EDGE_FALLING>;wake-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;wakeup-source;status = "okay";The "okay" status is only needed to flip the default "disabled" device.
- };
[...]
+}; diff --git a/arch/arm/boot/dts/imx6q-emcon-avari.dts b/arch/arm/boot/dts/imx6q-emcon-avari.dts new file mode 100644 index 000000000000..0c85b5ee011c --- /dev/null +++ b/arch/arm/boot/dts/imx6q-emcon-avari.dts
There are so many things duplicated between imx6dl-emcon-avari.dts and imx6q-emcon-avari.dts. Can you do something to avoid that?
I could try to merge them into a "common", but it will be an additional file.
@@ -0,0 +1,224 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/* Copyright (C) 2018 emtrion GmbH
- Author: Jan Tuerk jan.tuerk@emtrion.com
- */
+/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-emcon.dtsi" +#include "imx6q-emcon.dtsi" /*Include camera2 pinmux*/
+/ {
- model = "emtrion SoM emCON-MX6 Dual/Quad on Avari";
- compatible = "emtrion,emcon-mx6-avari", "fsl,imx6q";
- aliases {
mmc0 = &usdhc3;mmc2 = &usdhc1;mmc1 = &usdhc2;mmc3 = &usdhc4;- };
[...]
+};
+&ssi2 {
- pwm_fan: pwm-fan {
compatible = "pwm-fan";cooling-min-state = <0>;cooling-max-state = <4>;#cooling-cells = <2>;pwms = <&pwm4 0 50000>;cooling-levels = <0 64 127 191 255>;status = "disabled";- };
- rgb_encoder: disp0 {
s/disp0/display
Ack
compatible = "fsl,imx-parallel-display";#address-cells = <1>;#size-cells = <0>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_rgb24_display>;status = "disabled";port@0 {reg = <0>;Have a newline between property list and child node.
Ok
rgb_encoder_in: endpoint {remote-endpoint = <&ipu1_di0_disp0>;};};port@1 {reg = <1>;rgb_encoder_out: endpoint {remote-endpoint = <&rgb_panel_in>;};};- };
- rgb_panel: panel {
backlight = <&rgb_backlight>;power-supply = <®_parallel_disp>;port {rgb_panel_in: endpoint {remote-endpoint = <&rgb_encoder_out>;};};- };
- rgb_backlight: rgb-backlight {
compatible = "pwm-backlight";pinctrl-names = "default";pinctrl-0 = <&pinctrl_rgb_bl>;enable-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;pwms = <&pwm3 0 5000000>;brightness-levels = <250 176 160 144 128 11296 80 64 48 32 16 8 1>;Broken indent.
ack
default-brightness-level = <13>;status = "okay";- };
- lvds_backlight: lvds-backlight {
compatible = "pwm-backlight";pinctrl-names = "default";pinctrl-0 = <&pinctrl_lvds_bl>;enable-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>;pwms = <&pwm1 0 50000>;brightness-levels = <0 4 8 16 32 64 80 96 112128 144 160 176 250>;default-brightness-level = <13>;status = "okay";- };
+};
+&iomuxc {
- pinctrl_secure: securegrp {
Unused?
in this configuration, yes. The imx6qdl-emcon.dtsi defines all pinctrl values for the Interfaces defined in the emCON specification.
fsl,pins = <MX6QDL_PAD_GPIO_18__GPIO7_IO130x1b0b1
>;- };
- pinctrl_uart1: uart1grp {
fsl,pins = <MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA0x1b0b1
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA0x1b0b1
>;- };
[...]
- pinctrl_uart5: uart5grp {
fsl,pins = <MX6QDL_PAD_KEY_COL1__UART5_TX_DATA0x1b0b1
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA0x1b0b1
>;- };
- pinctrl_emcon_gpio1: emcongpio1 {
fsl,pins = <MX6QDL_PAD_NANDF_D0__GPIO2_IO000x0b0b1
>;- };
Try to keep these pinctrl entries alphabetically sorted.
If this helps to merge it, I'll change that
- pinctrl_emcon_gpio2: emcongpio2 {
fsl,pins = <MX6QDL_PAD_NANDF_D1__GPIO2_IO010x0b0b1
>;- };
[...]
wdt {s/wdt/watchdog
Ack.
compatible = "dlg,da9063-watchdog";timeout-sec = <0>;};regulators {vddcore_reg: bcore1 {regulator-min-microvolt = <1100000>;
[...]
+/*******Disabled HW following***********/
+&weim {
- status = "disabled";
+};
Isn't weim disabled by default?
Yes, the patch was originally done for our internal "vendor" kernel, which was based on 4.9 where it was enabled by default. I remove the node, as it became obsolete now.
Shawn
+&snvs_rtc {
- status = "disabled";
+};
2.11.0
On Tue, Apr 24, 2018 at 3:32 AM, Türk, Jan Jan.Tuerk@emtrion.de wrote:
-----Ursprüngliche Nachricht----- Von: Shawn Guo Gesendet: Montag, 23. April 2018 10:45 Re: [PATCH v3 5/6] ARM: dts: Add support for emtrion emCON-MX6 series
On Fri, Apr 20, 2018 at 02:50:52PM +0200, jan.tuerk@emtrion.com wrote:
From: Jan Tuerk jan.tuerk@emtrion.com
This patch adds support for the emtrion GmbH emCON-MX6 modules. They are available with imx.6 Solo, Dual-Lite, Dual and Quad equipped with Memory from 512MB to 2GB (configured by U-Boot).
Our default developer-Kit ships with the Avari baseboard and the EDT ETM0700G0BDH6 Display (imx6[q|dl]-emcon-avari).
The devicetree is split into the common part providing all module components and the basic support for all SoC versions (imx6qdl-emcon.dtsi) and parts which are i.mx6 S|DL and D|Q relevant. Finally the support for the avari baseboard in the developer-kit configuration is provided by the emcon-avari dts files.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com
Documentation/devicetree/bindings/arm/emtrion.txt | 13 +
It's better to have a separate patch for bindings doc, which needs to be acknowledged by DT maintainers.
I can change that, but nobody complained in the first 2 revisions of the patch.
Well, sometimes I forget to mention what is step 1 in Documentation/devicetree/bindings/submitting-patches.txt.
Also I though having the documentation is required for merging new bindings?
Yes, so binding patches come first (step 3).
arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx6dl-emcon-avari.dts | 224 ++++++ arch/arm/boot/dts/imx6dl-emcon.dtsi | 27 + arch/arm/boot/dts/imx6q-emcon-avari.dts | 224 ++++++ arch/arm/boot/dts/imx6q-emcon.dtsi | 27 + arch/arm/boot/dts/imx6qdl-emcon.dtsi | 838
++++++++++++++++++++++
7 files changed, 1355 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/emtrion.txt create mode 100644 arch/arm/boot/dts/imx6dl-emcon-avari.dts create mode 100644 arch/arm/boot/dts/imx6dl-emcon.dtsi create mode 100644 arch/arm/boot/dts/imx6q-emcon-avari.dts create mode 100644 arch/arm/boot/dts/imx6q-emcon.dtsi create mode 100644 arch/arm/boot/dts/imx6qdl-emcon.dtsi
[...]
- };
- boardID: pca8754a@3a {
Please find a more generic node name for it.
you mean boardID@3a?
No. "gpio@3a" as it is a gpio controller.
This chip identifies the baseboard type for the bootloader.
compatible = "nxp,pca8574";reg = <0x3a>;gpio-controller;#gpio-cells = <1>;- };
From: Jan Tuerk jan.tuerk@emtrion.com
All recent emtrion modules based on i.mx6 make use of the DA0963. Therefore enable it with the following defaults: - CONFIG_MFD_DA9063=y - CONFIG_REGULATOR_DA9063=y - CONFIG_DA9063_WATCHDOG=m MFD and REGULATOR are built-in to have it at Kernel boot-time. The WATCHDOG is optional and could be loaded from userspace.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com --- arch/arm/configs/imx_v6_v7_defconfig | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 3a308437b088..691d431250d4 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -214,9 +214,11 @@ CONFIG_CPU_THERMAL=y CONFIG_IMX_THERMAL=y CONFIG_WATCHDOG=y CONFIG_DA9062_WATCHDOG=y +CONFIG_DA9063_WATCHDOG=m CONFIG_IMX2_WDT=y CONFIG_MFD_DA9052_I2C=y CONFIG_MFD_DA9062=y +CONFIG_MFD_DA9063=y CONFIG_MFD_MC13XXX_SPI=y CONFIG_MFD_MC13XXX_I2C=y CONFIG_MFD_STMPE=y @@ -225,6 +227,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_ANATOP=y CONFIG_REGULATOR_DA9052=y CONFIG_REGULATOR_DA9062=y +CONFIG_REGULATOR_DA9063=y CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_MC13783=y CONFIG_REGULATOR_MC13892=y
From: Jan Tuerk jan.tuerk@emtrion.com
Changes for v4: - re-arrange the Patch-series to match the DT-submitting-patches - Additional patch for the Documentation of the new DT-bindings
[PATCH v4 1/7] dt-bindings: display: Document the EDT et* displays in one file. - no change (re-arranged 3/6 => 1/7)
[PATCH v4 2/7] drm/panel: Add support for the EDT ETM0700G0BDH6 - no change (re-arranged 1/6 => 2/7)
[PATCH v4 3/7] drm/panel: Add support for the EDT ETM0700G0EDH6 - no change (re-arranged 2/6 => 3/7)
[PATCH v4 4/7] ARM: dts: imx: Add an cpu0 label for imx6dl devices. - no change
[PATCH v4 5/7] dt-bindings: arm: Document emtrion emCON-MX6 bindings - separate patch for the emtrion emCON-MX6 DT-bindings
[PATCH v4 6/7] ARM: dts: Add support for emtrion emCON-MX6 series - alphabetically sort the DT - moved duplicated Avari baseboard code into separate file.
[PATCH v4 7/7] ARM: imx_v6_v7_defconfig: Enable DA0963 PMIC support. - unchaged
Documentation/devicetree/bindings/arm/emtrion.txt | 13 + .../bindings/display/panel/edt,et-series.txt | 39 + .../bindings/display/panel/edt,et057090dhu.txt | 7 - .../bindings/display/panel/edt,et070080dh6.txt | 10 - .../bindings/display/panel/edt,etm0700g0dh6.txt | 10 - arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx6dl-emcon-avari.dts | 17 + arch/arm/boot/dts/imx6dl-emcon.dtsi | 28 + arch/arm/boot/dts/imx6dl.dtsi | 2 +- arch/arm/boot/dts/imx6q-emcon-avari.dts | 17 + arch/arm/boot/dts/imx6q-emcon.dtsi | 28 + arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi | 208 ++++++ arch/arm/boot/dts/imx6qdl-emcon.dtsi | 826 +++++++++++++++++++++ arch/arm/configs/imx_v6_v7_defconfig | 3 + drivers/gpu/drm/panel/panel-simple.c | 18 + 15 files changed, 1200 insertions(+), 28 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/emtrion.txt create mode 100644 Documentation/devicetree/bindings/display/panel/edt,et-series.txt delete mode 100644 Documentation/devicetree/bindings/display/panel/edt,et057090dhu.txt delete mode 100644 Documentation/devicetree/bindings/display/panel/edt,et070080dh6.txt delete mode 100644 Documentation/devicetree/bindings/display/panel/edt,etm0700g0dh6.txt create mode 100644 arch/arm/boot/dts/imx6dl-emcon-avari.dts create mode 100644 arch/arm/boot/dts/imx6dl-emcon.dtsi create mode 100644 arch/arm/boot/dts/imx6q-emcon-avari.dts create mode 100644 arch/arm/boot/dts/imx6q-emcon.dtsi create mode 100644 arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi create mode 100644 arch/arm/boot/dts/imx6qdl-emcon.dtsi
From: Jan Tuerk jan.tuerk@emtrion.com
Document the Emerging Display Technology Corp. (EDT) using the simple-panel binding in one single file.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com --- Changes for v4: - re-arrange the Patch-series to match the DT-submitting-patches - Additional patch for the Documentation of the new DT-bindings - no change (re-arranged 3/6 => 1/7)
.../bindings/display/panel/edt,et-series.txt | 39 ++++++++++++++++++++++ .../bindings/display/panel/edt,et057090dhu.txt | 7 ---- .../bindings/display/panel/edt,et070080dh6.txt | 10 ------ .../bindings/display/panel/edt,etm0700g0dh6.txt | 10 ------ 4 files changed, 39 insertions(+), 27 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/panel/edt,et-series.txt delete mode 100644 Documentation/devicetree/bindings/display/panel/edt,et057090dhu.txt delete mode 100644 Documentation/devicetree/bindings/display/panel/edt,et070080dh6.txt delete mode 100644 Documentation/devicetree/bindings/display/panel/edt,etm0700g0dh6.txt
diff --git a/Documentation/devicetree/bindings/display/panel/edt,et-series.txt b/Documentation/devicetree/bindings/display/panel/edt,et-series.txt new file mode 100644 index 000000000000..f56b99ebd9be --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/edt,et-series.txt @@ -0,0 +1,39 @@ +Emerging Display Technology Corp. Displays +========================================== + + +Display bindings for EDT Display Technology Corp. Displays which are +compatible with the simple-panel binding, which is specified in +simple-panel.txt + + +5,7" WVGA TFT Panels +-------------------- + ++-----------------+---------------------+-------------------------------------+ +| Identifier | compatbile | description | ++=================+=====================+=====================================+ +| ET057090DHU | edt,et057090dhu | 5.7" VGA TFT LCD panel | ++-----------------+---------------------+-------------------------------------+ + + +7,0" WVGA TFT Panels +-------------------- + ++-----------------+---------------------+-------------------------------------+ +| Identifier | compatbile | description | ++=================+=====================+=====================================+ +| ETM0700G0DH6 | edt,etm070080dh6 | WVGA TFT Display with capacitive | +| | | Touchscreen | ++-----------------+---------------------+-------------------------------------+ +| ETM0700G0BDH6 | edt,etm070080bdh6 | Same as ETM0700G0DH6 but with | +| | | inverted pixel clock. | ++-----------------+---------------------+-------------------------------------+ +| ETM0700G0EDH6 | edt,etm070080edh6 | Same display as the ETM0700G0BDH6, | +| | | but with changed Hardware for the | +| | | backlight and the touch interface | ++-----------------+---------------------+-------------------------------------+ +| ET070080DH6 | edt,etm070080dh6 | Same timings as the ETM0700G0DH6, | +| | | but with resistive touch. | ++-----------------+---------------------+-------------------------------------+ + diff --git a/Documentation/devicetree/bindings/display/panel/edt,et057090dhu.txt b/Documentation/devicetree/bindings/display/panel/edt,et057090dhu.txt deleted file mode 100644 index 4903d7b1d947..000000000000 --- a/Documentation/devicetree/bindings/display/panel/edt,et057090dhu.txt +++ /dev/null @@ -1,7 +0,0 @@ -Emerging Display Technology Corp. 5.7" VGA TFT LCD panel - -Required properties: -- compatible: should be "edt,et057090dhu" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/edt,et070080dh6.txt b/Documentation/devicetree/bindings/display/panel/edt,et070080dh6.txt deleted file mode 100644 index 20cb38e836e4..000000000000 --- a/Documentation/devicetree/bindings/display/panel/edt,et070080dh6.txt +++ /dev/null @@ -1,10 +0,0 @@ -Emerging Display Technology Corp. ET070080DH6 7.0" WVGA TFT LCD panel - -Required properties: -- compatible: should be "edt,et070080dh6" - -This panel is the same as ETM0700G0DH6 except for the touchscreen. -ET070080DH6 is the model with resistive touch. - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/edt,etm0700g0dh6.txt b/Documentation/devicetree/bindings/display/panel/edt,etm0700g0dh6.txt deleted file mode 100644 index ee4b18053e40..000000000000 --- a/Documentation/devicetree/bindings/display/panel/edt,etm0700g0dh6.txt +++ /dev/null @@ -1,10 +0,0 @@ -Emerging Display Technology Corp. ETM0700G0DH6 7.0" WVGA TFT LCD panel - -Required properties: -- compatible: should be "edt,etm0700g0dh6" - -This panel is the same as ET070080DH6 except for the touchscreen. -ETM0700G0DH6 is the model with capacitive multitouch. - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory.
On Fri, Apr 27, 2018 at 03:24:36PM +0200, jan.tuerk@emtrion.com wrote:
From: Jan Tuerk jan.tuerk@emtrion.com
Document the Emerging Display Technology Corp. (EDT) using the simple-panel binding in one single file.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com
Changes for v4:
- re-arrange the Patch-series to match the DT-submitting-patches
- Additional patch for the Documentation of the new DT-bindings
- no change (re-arranged 3/6 => 1/7)
.../bindings/display/panel/edt,et-series.txt | 39 ++++++++++++++++++++++ .../bindings/display/panel/edt,et057090dhu.txt | 7 ---- .../bindings/display/panel/edt,et070080dh6.txt | 10 ------ .../bindings/display/panel/edt,etm0700g0dh6.txt | 10 ------ 4 files changed, 39 insertions(+), 27 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/panel/edt,et-series.txt delete mode 100644 Documentation/devicetree/bindings/display/panel/edt,et057090dhu.txt delete mode 100644 Documentation/devicetree/bindings/display/panel/edt,et070080dh6.txt delete mode 100644 Documentation/devicetree/bindings/display/panel/edt,etm0700g0dh6.txt
Reviewed-by: Rob Herring robh@kernel.org
From: Jan Tuerk jan.tuerk@emtrion.com
Document the Emerging Display Technology Corp. (EDT) using the simple-panel binding in one single file.
Reviewed-by: Rob Herring robh@kernel.org Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com --- .../bindings/display/panel/edt,et-series.txt | 39 +++++++++++++++++++ .../display/panel/edt,et057090dhu.txt | 7 ---- .../display/panel/edt,et070080dh6.txt | 10 ----- .../display/panel/edt,etm0700g0dh6.txt | 10 ----- 4 files changed, 39 insertions(+), 27 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/panel/edt,et-series.txt delete mode 100644 Documentation/devicetree/bindings/display/panel/edt,et057090dhu.txt delete mode 100644 Documentation/devicetree/bindings/display/panel/edt,et070080dh6.txt delete mode 100644 Documentation/devicetree/bindings/display/panel/edt,etm0700g0dh6.txt
[Changes from v4 of emCON patch-series] - rebased to mainline/master - split as requested by Shawn Guo
As requested by Sha
diff --git a/Documentation/devicetree/bindings/display/panel/edt,et-series.txt b/Documentation/devicetree/bindings/display/panel/edt,et-series.txt new file mode 100644 index 000000000000..f56b99ebd9be --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/edt,et-series.txt @@ -0,0 +1,39 @@ +Emerging Display Technology Corp. Displays +========================================== + + +Display bindings for EDT Display Technology Corp. Displays which are +compatible with the simple-panel binding, which is specified in +simple-panel.txt + + +5,7" WVGA TFT Panels +-------------------- + ++-----------------+---------------------+-------------------------------------+ +| Identifier | compatbile | description | ++=================+=====================+=====================================+ +| ET057090DHU | edt,et057090dhu | 5.7" VGA TFT LCD panel | ++-----------------+---------------------+-------------------------------------+ + + +7,0" WVGA TFT Panels +-------------------- + ++-----------------+---------------------+-------------------------------------+ +| Identifier | compatbile | description | ++=================+=====================+=====================================+ +| ETM0700G0DH6 | edt,etm070080dh6 | WVGA TFT Display with capacitive | +| | | Touchscreen | ++-----------------+---------------------+-------------------------------------+ +| ETM0700G0BDH6 | edt,etm070080bdh6 | Same as ETM0700G0DH6 but with | +| | | inverted pixel clock. | ++-----------------+---------------------+-------------------------------------+ +| ETM0700G0EDH6 | edt,etm070080edh6 | Same display as the ETM0700G0BDH6, | +| | | but with changed Hardware for the | +| | | backlight and the touch interface | ++-----------------+---------------------+-------------------------------------+ +| ET070080DH6 | edt,etm070080dh6 | Same timings as the ETM0700G0DH6, | +| | | but with resistive touch. | ++-----------------+---------------------+-------------------------------------+ + diff --git a/Documentation/devicetree/bindings/display/panel/edt,et057090dhu.txt b/Documentation/devicetree/bindings/display/panel/edt,et057090dhu.txt deleted file mode 100644 index 4903d7b1d947..000000000000 --- a/Documentation/devicetree/bindings/display/panel/edt,et057090dhu.txt +++ /dev/null @@ -1,7 +0,0 @@ -Emerging Display Technology Corp. 5.7" VGA TFT LCD panel - -Required properties: -- compatible: should be "edt,et057090dhu" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/edt,et070080dh6.txt b/Documentation/devicetree/bindings/display/panel/edt,et070080dh6.txt deleted file mode 100644 index 20cb38e836e4..000000000000 --- a/Documentation/devicetree/bindings/display/panel/edt,et070080dh6.txt +++ /dev/null @@ -1,10 +0,0 @@ -Emerging Display Technology Corp. ET070080DH6 7.0" WVGA TFT LCD panel - -Required properties: -- compatible: should be "edt,et070080dh6" - -This panel is the same as ETM0700G0DH6 except for the touchscreen. -ET070080DH6 is the model with resistive touch. - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/edt,etm0700g0dh6.txt b/Documentation/devicetree/bindings/display/panel/edt,etm0700g0dh6.txt deleted file mode 100644 index ee4b18053e40..000000000000 --- a/Documentation/devicetree/bindings/display/panel/edt,etm0700g0dh6.txt +++ /dev/null @@ -1,10 +0,0 @@ -Emerging Display Technology Corp. ETM0700G0DH6 7.0" WVGA TFT LCD panel - -Required properties: -- compatible: should be "edt,etm0700g0dh6" - -This panel is the same as ET070080DH6 except for the touchscreen. -ETM0700G0DH6 is the model with capacitive multitouch. - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory.
From: Jan Tuerk jan.tuerk@emtrion.com
The Emerging Display Technology ETM0700G0BDH6 is exactly the same display as the ETM0700G0DH6, exept the pixelclock polarity. Therefore re-use the ETM0700G0DH6 modes. It is used by default on emtrion Avari based development kits.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com --- drivers/gpu/drm/panel/panel-simple.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index cbf1ab404ee7..8b7feb2888f2 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -909,6 +909,18 @@ static const struct panel_desc edt_etm0700g0dh6 = { .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, };
+static const struct panel_desc edt_etm0700g0bdh6 = { + .modes = &edt_etm0700g0dh6_mode, + .num_modes = 1, + .bpc = 6, + .size = { + .width = 152, + .height = 91, + }, + .bus_format = MEDIA_BUS_FMT_RGB666_1X18, + .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, +}; + static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { .clock = 32260, .hdisplay = 800, @@ -2133,6 +2145,9 @@ static const struct of_device_id platform_of_match[] = { }, { .compatible = "edt,etm0700g0dh6", .data = &edt_etm0700g0dh6, + }, { + .compatible = "edt,etm0700g0bdh6", + .data = &edt_etm0700g0bdh6, }, { .compatible = "foxlink,fl500wvr00-a0t", .data = &foxlink_fl500wvr00_a0t,
From: Jan Tuerk jan.tuerk@emtrion.com
The Emerging Display Technology ETM0700G0EDH6 is the uses the same panel as the ETM0700G0BDH6. It differs in the hardware design for the backlight and the touchscreen i2c interface. As the new display type has different requirements for drive-strengths on the i2c-bus, add an additional compatible to allow the handling of it or warn about incompatible cpu and display combinations.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com --- drivers/gpu/drm/panel/panel-simple.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 8b7feb2888f2..2eed60134fa3 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -2148,6 +2148,9 @@ static const struct of_device_id platform_of_match[] = { }, { .compatible = "edt,etm0700g0bdh6", .data = &edt_etm0700g0bdh6, + }, { + .compatible = "edt,etm0700g0edh6", + .data = &edt_etm0700g0bdh6, }, { .compatible = "foxlink,fl500wvr00-a0t", .data = &foxlink_fl500wvr00_a0t,
On Tue, Jun 19, 2018 at 11:55:43AM +0200, jan.tuerk@emtrion.com wrote:
From: Jan Tuerk jan.tuerk@emtrion.com
Document the Emerging Display Technology Corp. (EDT) using the simple-panel binding in one single file.
Reviewed-by: Rob Herring robh@kernel.org Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com
.../bindings/display/panel/edt,et-series.txt | 39 +++++++++++++++++++ .../display/panel/edt,et057090dhu.txt | 7 ---- .../display/panel/edt,et070080dh6.txt | 10 ----- .../display/panel/edt,etm0700g0dh6.txt | 10 ----- 4 files changed, 39 insertions(+), 27 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/panel/edt,et-series.txt delete mode 100644 Documentation/devicetree/bindings/display/panel/edt,et057090dhu.txt delete mode 100644 Documentation/devicetree/bindings/display/panel/edt,et070080dh6.txt delete mode 100644 Documentation/devicetree/bindings/display/panel/edt,etm0700g0dh6.txt
[Changes from v4 of emCON patch-series]
- rebased to mainline/master
- split as requested by Shawn Guo
As requested by Sha
All three patches applied, thanks.
Thierry
From: Jan Tuerk jan.tuerk@emtrion.com
The Emerging Display Technology ETM0700G0BDH6 is exactly the same display as the ETM0700G0DH6, exept the pixelclock polarity. Therefore re-use the ETM0700G0DH6 modes. It is used by default on emtrion Avari based development kits.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com --- Changes for v4: - re-arrange the Patch-series to match the DT-submitting-patches - Additional patch for the Documentation of the new DT-bindings - no change (re-arranged 1/6 => 2/7)
drivers/gpu/drm/panel/panel-simple.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index cbf1ab404ee7..8b7feb2888f2 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -909,6 +909,18 @@ static const struct panel_desc edt_etm0700g0dh6 = { .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, };
+static const struct panel_desc edt_etm0700g0bdh6 = { + .modes = &edt_etm0700g0dh6_mode, + .num_modes = 1, + .bpc = 6, + .size = { + .width = 152, + .height = 91, + }, + .bus_format = MEDIA_BUS_FMT_RGB666_1X18, + .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, +}; + static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { .clock = 32260, .hdisplay = 800, @@ -2134,6 +2146,9 @@ static const struct of_device_id platform_of_match[] = { .compatible = "edt,etm0700g0dh6", .data = &edt_etm0700g0dh6, }, { + .compatible = "edt,etm0700g0bdh6", + .data = &edt_etm0700g0bdh6, + }, { .compatible = "foxlink,fl500wvr00-a0t", .data = &foxlink_fl500wvr00_a0t, }, {
From: Jan Tuerk jan.tuerk@emtrion.com
The Emerging Display Technology ETM0700G0EDH6 is the uses the same panel as the ETM0700G0BDH6. It differs in the hardware design for the backlight and the touchscreen i2c interface. As the new display type has different requirements for drive-strengths on the i2c-bus, add an additional compatible to allow the handling of it or warn about incompatible cpu and display combinations.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com --- Changes for v4: - re-arrange the Patch-series to match the DT-submitting-patches - Additional patch for the Documentation of the new DT-bindings - no change (re-arranged 2/6 => 3/7)
drivers/gpu/drm/panel/panel-simple.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 8b7feb2888f2..2eed60134fa3 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -2149,6 +2149,9 @@ static const struct of_device_id platform_of_match[] = { .compatible = "edt,etm0700g0bdh6", .data = &edt_etm0700g0bdh6, }, { + .compatible = "edt,etm0700g0edh6", + .data = &edt_etm0700g0bdh6, + }, { .compatible = "foxlink,fl500wvr00-a0t", .data = &foxlink_fl500wvr00_a0t, }, {
From: Jan Tuerk jan.tuerk@emtrion.com
Adding the label cpu0 allows the adjustment of cpu-parameters by reference in overlaying dtsi files in the same way as it is possible for imx6q devices.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com --- Changes for v4: - re-arrange the Patch-series to match the DT-submitting-patches - Additional patch for the Documentation of the new DT-bindings
arch/arm/boot/dts/imx6dl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 558bce81209d..fc658bf3a693 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -21,7 +21,7 @@ #address-cells = <1>; #size-cells = <0>;
- cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>;
From: Jan Tuerk jan.tuerk@emtrion.com
Document the compatible strings for emtrion emCON-MX6 SoM's.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com --- For v4: - separate patch for the emtrion emCON-MX6 DT-bindings
Documentation/devicetree/bindings/arm/emtrion.txt | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/emtrion.txt
diff --git a/Documentation/devicetree/bindings/arm/emtrion.txt b/Documentation/devicetree/bindings/arm/emtrion.txt new file mode 100644 index 000000000000..3ff6c6c2034d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/emtrion.txt @@ -0,0 +1,13 @@ +Emtrion Devicetree Bindings +=========================== + +emCON Series: +------------- + +Required root node properties + - compatible: + - "emtrion,emcon-mx6", "fsl,imx6q", "fsl,imx6dl"; : emCON-MX6 Generic SoM + - "emtrion,emcon-mx6", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM + - "emtrion,emcon-mx6-avari", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM on Avari Base + - "emtrion,emcon-mx6", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM + - "emtrion,emcon-mx6-avari", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM on Avari Base
On Fri, Apr 27, 2018 at 03:24:40PM +0200, jan.tuerk@emtrion.com wrote:
From: Jan Tuerk jan.tuerk@emtrion.com
Document the compatible strings for emtrion emCON-MX6 SoM's.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com
For v4:
- separate patch for the emtrion emCON-MX6 DT-bindings
Documentation/devicetree/bindings/arm/emtrion.txt | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/emtrion.txt
diff --git a/Documentation/devicetree/bindings/arm/emtrion.txt b/Documentation/devicetree/bindings/arm/emtrion.txt new file mode 100644 index 000000000000..3ff6c6c2034d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/emtrion.txt @@ -0,0 +1,13 @@ +Emtrion Devicetree Bindings +===========================
+emCON Series: +-------------
+Required root node properties
- compatible:
- "emtrion,emcon-mx6", "fsl,imx6q", "fsl,imx6dl"; : emCON-MX6 Generic SoM
You can't have both a 6Q and 6DL present and I don't think 6Q is a perfect superset of 6DL.
- "emtrion,emcon-mx6", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM
- "emtrion,emcon-mx6-avari", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM on Avari Base
- "emtrion,emcon-mx6", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM
- "emtrion,emcon-mx6-avari", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM on Avari Base
-- 2.11.0
From: Jan Tuerk jan.tuerk@emtrion.com
This patch adds support for the emtrion GmbH emCON-MX6 modules. They are available with imx.6 Solo, Dual-Lite, Dual and Quad equipped with Memory from 512MB to 2GB (configured by U-Boot).
Our default developer-Kit ships with the Avari baseboard and the EDT ETM0700G0BDH6 Display (imx6[q|dl]-emcon-avari).
The devicetree is split into the common part providing all module components and the basic support for all SoC versions (imx6qdl-emcon.dtsi) and parts which are i.mx6 S|DL and D|Q relevant. Finally the support for the avari baseboard in the developer-kit configuration is provided by the emcon-avari dts files.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com --- Changes for v4: - re-arrange the Patch-series to match the DT-submitting-patches - Additional patch for the Documentation of the new DT-bindings - alphabetically sort the DT - moved duplicated Avari baseboard code into separate common file.
arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx6dl-emcon-avari.dts | 17 + arch/arm/boot/dts/imx6dl-emcon.dtsi | 28 + arch/arm/boot/dts/imx6q-emcon-avari.dts | 17 + arch/arm/boot/dts/imx6q-emcon.dtsi | 28 + arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi | 208 ++++++++ arch/arm/boot/dts/imx6qdl-emcon.dtsi | 826 +++++++++++++++++++++++++++++ 7 files changed, 1126 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-emcon-avari.dts create mode 100644 arch/arm/boot/dts/imx6dl-emcon.dtsi create mode 100644 arch/arm/boot/dts/imx6q-emcon-avari.dts create mode 100644 arch/arm/boot/dts/imx6q-emcon.dtsi create mode 100644 arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi create mode 100644 arch/arm/boot/dts/imx6qdl-emcon.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7e2424957809..05b930da3fda 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -381,6 +381,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-cubox-i-emmc-som-v15.dtb \ imx6dl-cubox-i-som-v15.dtb \ imx6dl-dfi-fs700-m60.dtb \ + imx6dl-emcon-avari.dtb \ imx6dl-gw51xx.dtb \ imx6dl-gw52xx.dtb \ imx6dl-gw53xx.dtb \ @@ -442,6 +443,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-display5-tianma-tm070-1280x768.dtb \ imx6q-dmo-edmqmx6.dtb \ imx6q-dms-ba16.dtb \ + imx6q-emcon-avari.dtb \ imx6q-evi.dtb \ imx6q-gk802.dtb \ imx6q-gw51xx.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-emcon-avari.dts b/arch/arm/boot/dts/imx6dl-emcon-avari.dts new file mode 100644 index 000000000000..464c82a53da3 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-emcon-avari.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/* + * Copyright (C) 2018 emtrion GmbH + * Author: Jan Tuerk jan.tuerk@emtrion.com + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-emcon.dtsi" +/*Include camera2 pinmux*/ +#include "imx6dl-emcon.dtsi" +#include "imx6qdl-emcon-avari.dtsi" + +/ { + model = "emtrion SoM emCON-MX6 Solo/Dual-Lite Avari"; + compatible = "emtrion,emcon-mx6-avari", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6dl-emcon.dtsi b/arch/arm/boot/dts/imx6dl-emcon.dtsi new file mode 100644 index 000000000000..0d86e0ecdb4d --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-emcon.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/* + * Copyright (C) 2018 emtrion GmbH + * Author: Jan Tuerk jan.tuerk@emtrion.com + */ + +/ { + model = "emtrion SoM emCON-MX6 Solo/DualLite"; + compatible = "emtrion,emcon-mx6", "fsl,imx6dl"; +}; + +&iomuxc { + pinctrl_cpi2: csi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0x0b0b1 + MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b1 + MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b1 + MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b1 + MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b1 + MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b1 + MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b1 + MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b1 + MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b1 + MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b1 + MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-emcon-avari.dts b/arch/arm/boot/dts/imx6q-emcon-avari.dts new file mode 100644 index 000000000000..093afe2f9069 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-emcon-avari.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/* + * Copyright (C) 2018 emtrion GmbH + * Author: Jan Tuerk jan.tuerk@emtrion.com + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-emcon.dtsi" +/*Include camera2 pinmux*/ +#include "imx6q-emcon.dtsi" +#include "imx6qdl-emcon-avari.dtsi" + +/ { + model = "emtrion SoM emCON-MX6 Dual/Quad on Avari"; + compatible = "emtrion,emcon-mx6-avari", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6q-emcon.dtsi b/arch/arm/boot/dts/imx6q-emcon.dtsi new file mode 100644 index 000000000000..bd7d2aa4248e --- /dev/null +++ b/arch/arm/boot/dts/imx6q-emcon.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/* + * Copyright (C) 2018 emtrion GmbH + * Author: Jan Tuerk jan.tuerk@emtrion.com + */ + +/ { + model = "emtrion SoM emCON-MX6 Dual/Quad"; + compatible = "emtrion,emcon-mx6", "fsl,imx6q"; +}; + +&iomuxc { + pinctrl_cpi2: csi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__IPU2_CSI1_PIXCLK 0x0b0b1 + MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b1 + MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b1 + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b1 + MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b1 + MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b1 + MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b1 + MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b1 + MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b1 + MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b1 + MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi b/arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi new file mode 100644 index 000000000000..7fb870907ff8 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/* + * Copyright (C) 2018 emtrion GmbH + * Author: Jan Tuerk jan.tuerk@emtrion.com + */ + +/ { + aliases { + mmc0 = &usdhc3; + mmc2 = &usdhc1; + mmc1 = &usdhc2; + mmc3 = &usdhc4; + boardID = &boardID; + }; + + chosen { + stdout-path = <&uart1>; + }; + + memory@10000000 { + reg = <0x10000000 0x40000000>; + }; + + + reg_wall_5p0: reg_wall5p0 { + compatible = "regulator-fixed"; + regulator-name = "Main-Supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_base3p3: reg_base3p3 { + compatible = "regulator-fixed"; + vin-supply = <®_wall_5p0>; + regulator-name = "3V3-avari"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_base1p5: reg_base1p5 { + compatible = "regulator-fixed"; + vin-supply = <®_base3p3>; + regulator-name = "1V5-avari"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_usb_otg: reg_otg_vbus { + compatible = "regulator-fixed"; + vin-supply = <®_wall_5p0>; + regulator-name = "OTG_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + + clk_codec: clock-codec { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "emCON-avari-sgtl5000"; + ssi-controller = <&ssi2>; + audio-codec = <&sgtl5000>; + audio-routing = + "Headphone Jack", "HP_OUT"; + mux-int-port = <2>; + mux-ext-port = <3>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + /*Unused emCON-MX6 pingroups on AVARI baseboard, enable defaults*/ + pinctrl-0 = < + &pinctrl_emcon_gpio1 &pinctrl_emcon_gpio2 + &pinctrl_emcon_gpio3 &pinctrl_emcon_gpio5 + &pinctrl_emcon_gpio6 &pinctrl_emcon_gpio7 + &pinctrl_emcon_gpio8 &pinctrl_emcon_irq_a + &pinctrl_emcon_irq_b &pinctrl_emcon_irq_c + &pinctrl_emcon_irq_pwr &pinctrl_nor_flash + &pinctrl_usdhc2 + &pinctrl_spdif_out &pinctrl_spdif_in + &pinctrl_cpi1 &pinctrl_cpi2 + >; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "okay"; +}; + +&ecspi2 { + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + sgtl5000: audio-codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + clocks = <&clk_codec>; + VDDA-supply = <®_base3p3>; + VDDIO-supply = <®_base3p3>; + }; + + boardID: gpio@3a { + compatible = "nxp,pca8574"; + reg = <0x3a>; + gpio-controller; + #gpio-cells = <1>; + }; + + captouch: touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_irq_touch2 &pinctrl_emcon_gpio4>; + interrupt-parent = <&gpio6>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + wake-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + wakeup-source; + }; +}; + +&pcie { + status = "okay"; +}; + +&rgb_encoder { + status = "okay"; +}; + +&rgb_panel { + compatible = "edt,etm0700g0bdh6"; + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; + +&uart2 { + status = "okay"; + uart-has-rtscts; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; + + + + diff --git a/arch/arm/boot/dts/imx6qdl-emcon.dtsi b/arch/arm/boot/dts/imx6qdl-emcon.dtsi new file mode 100644 index 000000000000..32b9bfdc3c41 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-emcon.dtsi @@ -0,0 +1,826 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/* + * Copyright (C) 2018 emtrion GmbH + * Author: Jan Tuerk jan.tuerk@emtrion.com + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/input/input.h> + +/ { + + model = "emtrion SoM emCON-MX6"; + compatible = "emtrion,emcon-mx6", "fsl,imx6q", "fsl,imx6dl"; + + aliases { + mmc0 = &usdhc3; + mmc2 = &usdhc1; + mmc1 = &usdhc2; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emcon_wake>; + + wake { + label = "Wake"; + linux,code = <KEY_WAKEUP>; + gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + som_leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_som_leds>; + + green { + label = "som:green"; + gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + + red { + label = "som:red"; + gpios = <&gpio3 1 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + + }; + + lvds_backlight: lvds-backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds_bl>; + enable-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; + pwms = <&pwm1 0 50000>; + brightness-levels = < + 0 4 8 16 32 64 80 96 112 + 128 144 160 176 250 + >; + default-brightness-level = <13>; + status = "okay"; + }; + pwm_fan: pwm-fan { + compatible = "pwm-fan"; + cooling-min-state = <0>; + cooling-max-state = <4>; + #cooling-cells = <2>; + pwms = <&pwm4 0 50000>; + cooling-levels = <0 64 127 191 255>; + status = "disabled"; + }; + + + rgb_encoder: parallel-display { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgb24_display>; + status = "disabled"; + + port@0 { + reg = <0>; + + rgb_encoder_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + rgb_encoder_out: endpoint { + remote-endpoint = <&rgb_panel_in>; + }; + }; + }; + + rgb_panel: panel { + backlight = <&rgb_backlight>; + power-supply = <®_parallel_disp>; + + port { + rgb_panel_in: endpoint { + remote-endpoint = <&rgb_encoder_out>; + }; + }; + }; + + reg_parallel_disp: reg_parallel-display { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgb_bl_en>; + regulator-name = "LCD-Supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio7 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_lvds_disp: reg_lvds-display { + compatible = "regulator-fixed"; + regulator-name = "LVDS-Supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio7 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + rgb_backlight: rgb-backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgb_bl>; + enable-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; + pwms = <&pwm3 0 5000000>; + brightness-levels = < + 250 176 160 144 128 112 + 96 80 64 48 32 16 8 1 + >; + default-brightness-level = <13>; + status = "okay"; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>, + <&gpio2 26 GPIO_ACTIVE_HIGH>; +}; + +&ecspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nor_flash>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; + phy-reset-duration = <50>; + phy-supply = <&vdd_1V8_reg>; + phy-handle = <&ksz9031>; + status = "okay"; + + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ksz9031: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <30 IRQ_TYPE_EDGE_FALLING>; + rxdv-skew-ps = <480>; + txen-skew-ps = <480>; + rxd0-skew-ps = <480>; + rxd1-skew-ps = <480>; + rxd2-skew-ps = <480>; + rxd3-skew-ps = <480>; + txd0-skew-ps = <420>; + txd1-skew-ps = <420>; + txd2-skew-ps = <360>; + txd3-skew-ps = <360>; + txc-skew-ps = <1020>; + rxc-skew-ps = <960>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + rtc: rtc@68 { + compatible = "dallas,ds1307"; + reg = <0x68>; + }; + + da9063: pmic@58 { + compatible = "dlg,da9063"; + reg = <0x58>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio2>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + + onkey { + compatible = "dlg,da9063-onkey"; + wakeup-source; + }; + + wdt { + compatible = "dlg,da9063-watchdog"; + timeout-sec = <0>; + }; + + regulators { + vddcore_reg: bcore1 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <20000>; + regulator-name = "DA9063_CORE"; + regulator-always-on; + }; + + vddsoc_reg: bcore2 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <20000>; + regulator-name = "DA9063_SOC"; + regulator-always-on; + }; + + vdd_ddr3_reg: bpro { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <20000>; + regulator-always-on; + }; + + vdd_3v3_reg: bperi { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <20000>; + regulator-always-on; + }; + + vdd_sata_reg: ldo3 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + vdd_mipi_reg: ldo4 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vdd_mx6_snvs_reg: ldo5 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_hdmi_reg: ldo6 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_pcie_reg: ldo7 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vdd_1V8_reg: ldo8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_3V3_sdc_reg: ldo9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_1V2_reg: ldo10 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; +}; + +&iomuxc { + + pinctrl_audmux: audmux { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b060 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130B0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b060 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b1 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b1 + >; + }; + + pinctrl_cpi1: csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b1 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b1 + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b1 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b1 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b1 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b1 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b1 + >; + }; + + /*camera2-pinctrl is in imx6q-emcon.dtsi or imx6dl-emcon.dtsi*/ + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 + >; + }; + + pinctrl_emcon_gpio1: emcongpio1 { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio2: emcongpio2 { + fsl,pins = < + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio3: emcongpio3 { + fsl,pins = < + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio4: emcongpio4 { + fsl,pins = < + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio5: emcongpio5 { + fsl,pins = < + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio6: emcongpio6 { + fsl,pins = < + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio7: emcongpio7 { + fsl,pins = < + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio8: emcongpio8 { + fsl,pins = < + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0b0b1 + >; + }; + + pinctrl_emcon_irq_a: emconirqa { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x0b0b1 + >; + }; + + pinctrl_emcon_irq_b: emconirqb { + fsl,pins = < + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x0b0b1 + >; + }; + + pinctrl_emcon_irq_c: emconirqc { + fsl,pins = < + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0b0b1 + >; + }; + + pinctrl_emcon_irq_pwr: emconirqpwr { + fsl,pins = < + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0b0b1 + >; + }; + + pinctrl_emcon_wake: emconwake { + fsl,pins = < + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x4001a0b1 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b058 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4000b070 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b870 + >; + }; + + pinctrl_irq_touch1: irqtouch1 { + fsl,pins = < + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x0b0b1 + >; + }; + + pinctrl_irq_touch2: irqtouch2 { + fsl,pins = < + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x0b0b1 + >; + }; + + pinctrl_lvds_bl: lvdsbacklightgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x0b0b1 + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b1 + >; + }; + + pinctrl_lvds_reg: lvdsreggrp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x0b0b1 + >; + }; + + + pinctrl_nor_flash: norflashgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b1 + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 + >; + }; + + pinctrl_pcie_ctrl: pciegrp { + fsl,pins = < + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0b0b1 + >; + }; + + pinctrl_pwm_fan: pwmfan { + fsl,pins = < + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x0b0b1 + >; + }; + + pinctrl_rgb_bl: rgbbacklightgrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x0b0b1 + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b1 + >; + }; + + pinctrl_rgb_bl_en: rgbenable { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x0b0b1 + >; + }; + + pinctrl_rgb24_display: rgbgrp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_secure: securegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1 + >; + }; + + pinctrl_som_leds: somledgrp { + fsl,pins = < + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x0b0b1 + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x0b0b1 + >; + }; + + pinctrl_spdif_in: spdifin { + fsl,pins = < + MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_spdif_out: spdifout { + fsl,pins = < + MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usb_host1: usbhgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x1B058 + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1B058 + >; + }; + + pinctrl_usb_otg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x17059 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + MX6QDL_PAD_GPIO_1__SD1_CD_B 0x1b0b1 + MX6QDL_PAD_DI0_PIN4__SD1_WP 0x1b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_GPIO_4__SD2_CD_B 0x1b0b1 + MX6QDL_PAD_GPIO_2__SD2_WP 0x1b0b1 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 + >; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&rgb_encoder_in>; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_ctrl>; + reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; + disable-gpio = <&gpio2 22 GPIO_ACTIVE_LOW>; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_host1>; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg>; + vbus-supply = <®_usb_otg>; + dr_mode = "peripheral"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + fsl,wp-controller; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + fsl,wp-controller; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + non-removable; + bus-width = <8>; + status = "okay"; +}; + +/******device power Management*********/ + +&cpu0 { + voltage-tolerance = <2>; +}; + +®_arm { + vin-supply = <&vddcore_reg>; +}; + +®_soc { + vin-supply = <&vddsoc_reg>; +}; + +®_pu { + vin-supply = <&vddsoc_reg>; +}; + + + +/*******Disabled HW following***********/ + +&snvs_rtc { + status = "disabled"; +};
On Fri, Apr 27, 2018 at 03:24:41PM +0200, jan.tuerk@emtrion.com wrote:
From: Jan Tuerk jan.tuerk@emtrion.com
This patch adds support for the emtrion GmbH emCON-MX6 modules. They are available with imx.6 Solo, Dual-Lite, Dual and Quad equipped with Memory from 512MB to 2GB (configured by U-Boot).
Our default developer-Kit ships with the Avari baseboard and the EDT ETM0700G0BDH6 Display (imx6[q|dl]-emcon-avari).
The devicetree is split into the common part providing all module components and the basic support for all SoC versions (imx6qdl-emcon.dtsi) and parts which are i.mx6 S|DL and D|Q relevant. Finally the support for the avari baseboard in the developer-kit configuration is provided by the emcon-avari dts files.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com
Changes for v4:
- re-arrange the Patch-series to match the DT-submitting-patches
- Additional patch for the Documentation of the new DT-bindings
- alphabetically sort the DT
- moved duplicated Avari baseboard code into separate common file.
arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx6dl-emcon-avari.dts | 17 + arch/arm/boot/dts/imx6dl-emcon.dtsi | 28 + arch/arm/boot/dts/imx6q-emcon-avari.dts | 17 + arch/arm/boot/dts/imx6q-emcon.dtsi | 28 + arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi | 208 ++++++++ arch/arm/boot/dts/imx6qdl-emcon.dtsi | 826 +++++++++++++++++++++++++++++ 7 files changed, 1126 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-emcon-avari.dts create mode 100644 arch/arm/boot/dts/imx6dl-emcon.dtsi create mode 100644 arch/arm/boot/dts/imx6q-emcon-avari.dts create mode 100644 arch/arm/boot/dts/imx6q-emcon.dtsi create mode 100644 arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi create mode 100644 arch/arm/boot/dts/imx6qdl-emcon.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7e2424957809..05b930da3fda 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -381,6 +381,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-cubox-i-emmc-som-v15.dtb \ imx6dl-cubox-i-som-v15.dtb \ imx6dl-dfi-fs700-m60.dtb \
- imx6dl-emcon-avari.dtb \ imx6dl-gw51xx.dtb \ imx6dl-gw52xx.dtb \ imx6dl-gw53xx.dtb \
@@ -442,6 +443,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-display5-tianma-tm070-1280x768.dtb \ imx6q-dmo-edmqmx6.dtb \ imx6q-dms-ba16.dtb \
- imx6q-emcon-avari.dtb \ imx6q-evi.dtb \ imx6q-gk802.dtb \ imx6q-gw51xx.dtb \
diff --git a/arch/arm/boot/dts/imx6dl-emcon-avari.dts b/arch/arm/boot/dts/imx6dl-emcon-avari.dts new file mode 100644 index 000000000000..464c82a53da3 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-emcon-avari.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/*
- Copyright (C) 2018 emtrion GmbH
- Author: Jan Tuerk jan.tuerk@emtrion.com
- */
+/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-emcon.dtsi" +/*Include camera2 pinmux*/ +#include "imx6dl-emcon.dtsi" +#include "imx6qdl-emcon-avari.dtsi"
+/ {
- model = "emtrion SoM emCON-MX6 Solo/Dual-Lite Avari";
- compatible = "emtrion,emcon-mx6-avari", "fsl,imx6dl";
+}; diff --git a/arch/arm/boot/dts/imx6dl-emcon.dtsi b/arch/arm/boot/dts/imx6dl-emcon.dtsi new file mode 100644 index 000000000000..0d86e0ecdb4d --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-emcon.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/*
- Copyright (C) 2018 emtrion GmbH
- Author: Jan Tuerk jan.tuerk@emtrion.com
- */
+/ {
- model = "emtrion SoM emCON-MX6 Solo/DualLite";
- compatible = "emtrion,emcon-mx6", "fsl,imx6dl";
+};
+&iomuxc {
- pinctrl_cpi2: csi1grp {
fsl,pins = <MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0x0b0b1MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b1MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b1MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b1MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b1MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b1MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b1MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b1MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b1MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b1MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b1>;- };
+};
I'm uncomfortable with maintain two more dtsi files only for a single pinctrl entry. Instead, I would suggest you put CSI node and its pinctrl entry into imx6q/dl-emcon-avari.dts, and have CSI node refer to its pinctrl entry rather than having the pinctrl in hog group.
diff --git a/arch/arm/boot/dts/imx6q-emcon-avari.dts b/arch/arm/boot/dts/imx6q-emcon-avari.dts new file mode 100644 index 000000000000..093afe2f9069 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-emcon-avari.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/*
- Copyright (C) 2018 emtrion GmbH
- Author: Jan Tuerk jan.tuerk@emtrion.com
- */
+/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-emcon.dtsi" +/*Include camera2 pinmux*/ +#include "imx6q-emcon.dtsi" +#include "imx6qdl-emcon-avari.dtsi"
+/ {
- model = "emtrion SoM emCON-MX6 Dual/Quad on Avari";
- compatible = "emtrion,emcon-mx6-avari", "fsl,imx6q";
+}; diff --git a/arch/arm/boot/dts/imx6q-emcon.dtsi b/arch/arm/boot/dts/imx6q-emcon.dtsi new file mode 100644 index 000000000000..bd7d2aa4248e --- /dev/null +++ b/arch/arm/boot/dts/imx6q-emcon.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/*
- Copyright (C) 2018 emtrion GmbH
- Author: Jan Tuerk jan.tuerk@emtrion.com
- */
+/ {
- model = "emtrion SoM emCON-MX6 Dual/Quad";
- compatible = "emtrion,emcon-mx6", "fsl,imx6q";
+};
+&iomuxc {
- pinctrl_cpi2: csi1grp {
fsl,pins = <MX6QDL_PAD_EIM_D17__IPU2_CSI1_PIXCLK 0x0b0b1MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b1MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b1MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b1MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b1MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b1MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b1MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b1MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b1MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b1MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b1>;- };
+}; diff --git a/arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi b/arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi new file mode 100644 index 000000000000..7fb870907ff8 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/*
- Copyright (C) 2018 emtrion GmbH
- Author: Jan Tuerk jan.tuerk@emtrion.com
- */
+/ {
- aliases {
mmc0 = &usdhc3;mmc2 = &usdhc1;mmc1 = &usdhc2;mmc3 = &usdhc4;boardID = &boardID;
Why do you need this boardID alias?
- };
- chosen {
stdout-path = <&uart1>;- };
- memory@10000000 {
reg = <0x10000000 0x40000000>;- };
- reg_wall_5p0: reg_wall5p0 {
For fixed regulators, please use regulator-xxx as node name.
compatible = "regulator-fixed";regulator-name = "Main-Supply";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;regulator-always-on;regulator-boot-on;- };
- reg_base3p3: reg_base3p3 {
compatible = "regulator-fixed";vin-supply = <®_wall_5p0>;regulator-name = "3V3-avari";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-always-on;regulator-boot-on;- };
- reg_base1p5: reg_base1p5 {
compatible = "regulator-fixed";vin-supply = <®_base3p3>;regulator-name = "1V5-avari";regulator-min-microvolt = <1500000>;regulator-max-microvolt = <1500000>;regulator-always-on;regulator-boot-on;- };
- reg_usb_otg: reg_otg_vbus {
compatible = "regulator-fixed";vin-supply = <®_wall_5p0>;regulator-name = "OTG_VBUS";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;regulator-always-on;- };
- clk_codec: clock-codec {
compatible = "fixed-clock";#clock-cells = <0>;clock-frequency = <12000000>;- };
- sound {
compatible = "fsl,imx-audio-sgtl5000";model = "emCON-avari-sgtl5000";ssi-controller = <&ssi2>;audio-codec = <&sgtl5000>;audio-routing ="Headphone Jack", "HP_OUT";mux-int-port = <2>;mux-ext-port = <3>;- };
+};
+&iomuxc {
- pinctrl-names = "default";
- /*Unused emCON-MX6 pingroups on AVARI baseboard, enable defaults*/
- pinctrl-0 = <
&pinctrl_emcon_gpio1 &pinctrl_emcon_gpio2&pinctrl_emcon_gpio3 &pinctrl_emcon_gpio5&pinctrl_emcon_gpio6 &pinctrl_emcon_gpio7&pinctrl_emcon_gpio8 &pinctrl_emcon_irq_a&pinctrl_emcon_irq_b &pinctrl_emcon_irq_c&pinctrl_emcon_irq_pwr
Can these GPIO pins be put into one single pinctrl_emcon_gpio entry?
&pinctrl_nor_flash
&pinctrl_usdhc2&pinctrl_spdif_out &pinctrl_spdif_in&pinctrl_cpi1 &pinctrl_cpi2>;
Again, please do not put consumer device specific pins in hog group. Also, it's confusing to have the same pinctrl in both hog and consumer device node, like pinctrl_nor_flash and pinctrl_usdhc2 here.
+};
+&audmux {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_audmux>;
- status = "okay";
+};
+&can1 {
- status = "okay";
+};
+&can2 {
- status = "okay";
+};
+&ecspi2 {
- status = "okay";
+};
+&hdmi {
- ddc-i2c-bus = <&i2c2>;
- status = "okay";
+};
+&i2c2 {
- status = "okay";
+};
+&i2c3 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- status = "okay";
- sgtl5000: audio-codec@a {
compatible = "fsl,sgtl5000";reg = <0x0a>;#sound-dai-cells = <0>;clocks = <&clk_codec>;VDDA-supply = <®_base3p3>;VDDIO-supply = <®_base3p3>;- };
- boardID: gpio@3a {
compatible = "nxp,pca8574";reg = <0x3a>;gpio-controller;#gpio-cells = <1>;- };
- captouch: touchscreen@38 {
compatible = "edt,edt-ft5406";reg = <0x38>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_irq_touch2 &pinctrl_emcon_gpio4>;interrupt-parent = <&gpio6>;interrupts = <31 IRQ_TYPE_EDGE_FALLING>;wake-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;wakeup-source;- };
+};
+&pcie {
- status = "okay";
+};
+&rgb_encoder {
- status = "okay";
+};
+&rgb_panel {
- compatible = "edt,etm0700g0bdh6";
- status = "okay";
+};
+&ssi2 {
- status = "okay";
+};
+&uart2 {
- status = "okay";
- uart-has-rtscts;
+};
+&uart3 {
- status = "okay";
+};
+&uart4 {
- status = "okay";
+};
+&uart5 {
- status = "okay";
+};
+&usbh1 {
- status = "okay";
+};
+&usbotg {
- status = "okay";
+};
+&usdhc1 {
- status = "okay";
+};
Remove these end of file newlines.
diff --git a/arch/arm/boot/dts/imx6qdl-emcon.dtsi b/arch/arm/boot/dts/imx6qdl-emcon.dtsi new file mode 100644 index 000000000000..32b9bfdc3c41 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-emcon.dtsi @@ -0,0 +1,826 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/*
- Copyright (C) 2018 emtrion GmbH
- Author: Jan Tuerk jan.tuerk@emtrion.com
- */
+#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/input/input.h>
+/ {
- model = "emtrion SoM emCON-MX6";
- compatible = "emtrion,emcon-mx6", "fsl,imx6q", "fsl,imx6dl";
- aliases {
mmc0 = &usdhc3;mmc2 = &usdhc1;mmc1 = &usdhc2;- };
- gpio-keys {
compatible = "gpio-keys";pinctrl-names = "default";pinctrl-0 = <&pinctrl_emcon_wake>;wake {label = "Wake";linux,code = <KEY_WAKEUP>;gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;wakeup-source;};- };
- som_leds: leds {
compatible = "gpio-leds";pinctrl-names = "default";pinctrl-0 = <&pinctrl_som_leds>;green {label = "som:green";gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;linux,default-trigger = "heartbeat";default-state = "on";};red {label = "som:red";gpios = <&gpio3 1 GPIO_ACTIVE_LOW>;default-state = "keep";};- };
- lvds_backlight: lvds-backlight {
compatible = "pwm-backlight";pinctrl-names = "default";pinctrl-0 = <&pinctrl_lvds_bl>;enable-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>;pwms = <&pwm1 0 50000>;brightness-levels = <0 4 8 16 32 64 80 96 112
One tab indent is good enough.
128 144 160 176 250>;
Please align the close '>' with the beginning character of open '<' line, i.e. 'b'.
default-brightness-level = <13>;status = "okay";- };
Have a newline between nodes.
- pwm_fan: pwm-fan {
compatible = "pwm-fan";cooling-min-state = <0>;cooling-max-state = <4>;#cooling-cells = <2>;pwms = <&pwm4 0 50000>;cooling-levels = <0 64 127 191 255>;status = "disabled";- };
- rgb_encoder: parallel-display {
display for node name.
compatible = "fsl,imx-parallel-display";#address-cells = <1>;#size-cells = <0>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_rgb24_display>;status = "disabled";port@0 {reg = <0>;rgb_encoder_in: endpoint {remote-endpoint = <&ipu1_di0_disp0>;};};port@1 {reg = <1>;rgb_encoder_out: endpoint {remote-endpoint = <&rgb_panel_in>;};};- };
- rgb_panel: panel {
lcd for node name as suggested by Devicetree Specification?
backlight = <&rgb_backlight>;power-supply = <®_parallel_disp>;port {rgb_panel_in: endpoint {remote-endpoint = <&rgb_encoder_out>;};};- };
- reg_parallel_disp: reg_parallel-display {
compatible = "regulator-fixed";pinctrl-names = "default";pinctrl-0 = <&pinctrl_rgb_bl_en>;regulator-name = "LCD-Supply";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;gpio = <&gpio7 9 GPIO_ACTIVE_HIGH>;enable-active-high;- };
- reg_lvds_disp: reg_lvds-display {
compatible = "regulator-fixed";regulator-name = "LVDS-Supply";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;gpio = <&gpio7 10 GPIO_ACTIVE_HIGH>;enable-active-high;- };
- rgb_backlight: rgb-backlight {
compatible = "pwm-backlight";pinctrl-names = "default";pinctrl-0 = <&pinctrl_rgb_bl>;enable-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;pwms = <&pwm3 0 5000000>;brightness-levels = <250 176 160 144 128 11296 80 64 48 32 16 8 1>;default-brightness-level = <13>;status = "okay";- };
+};
+&can1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_can1>;
+};
+&can2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_can2>;
+};
+&ecspi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi2>;
- cs-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>,
One space after =.
<&gpio2 26 GPIO_ACTIVE_HIGH>;
Align the line with above one.
+};
+&ecspi4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nor_flash>;
+};
+&fec {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet>;
- phy-mode = "rgmii";
- phy-reset-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
- phy-reset-duration = <50>;
- phy-supply = <&vdd_1V8_reg>;
- phy-handle = <&ksz9031>;
- status = "okay";
One newline.
- mdio {
#address-cells = <1>;#size-cells = <0>;ksz9031: phy@0 {compatible = "ethernet-phy-ieee802.3-c22";reg = <0>;interrupt-parent = <&gpio1>;interrupts = <30 IRQ_TYPE_EDGE_FALLING>;rxdv-skew-ps = <480>;txen-skew-ps = <480>;rxd0-skew-ps = <480>;rxd1-skew-ps = <480>;rxd2-skew-ps = <480>;rxd3-skew-ps = <480>;txd0-skew-ps = <420>;txd1-skew-ps = <420>;txd2-skew-ps = <360>;txd3-skew-ps = <360>;txc-skew-ps = <1020>;rxc-skew-ps = <960>;};- };
+};
+&i2c1 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- status = "okay";
- rtc: rtc@68 {
Is the label actually used? If yes, I would suggest a more specific name like ds1307.
compatible = "dallas,ds1307";reg = <0x68>;- };
- da9063: pmic@58 {
compatible = "dlg,da9063";reg = <0x58>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_pmic>;interrupt-parent = <&gpio2>;interrupts = <8 IRQ_TYPE_LEVEL_LOW>;interrupt-controller;onkey {compatible = "dlg,da9063-onkey";wakeup-source;};wdt {
s/wdt/watchdog. I remember I have already put this comment on previous version.
compatible = "dlg,da9063-watchdog";timeout-sec = <0>;};regulators {vddcore_reg: bcore1 {regulator-min-microvolt = <1100000>;regulator-max-microvolt = <1450000>;regulator-ramp-delay = <20000>;regulator-name = "DA9063_CORE";regulator-always-on;};vddsoc_reg: bcore2 {regulator-min-microvolt = <1100000>;regulator-max-microvolt = <1450000>;regulator-ramp-delay = <20000>;regulator-name = "DA9063_SOC";regulator-always-on;};vdd_ddr3_reg: bpro {regulator-min-microvolt = <1500000>;regulator-max-microvolt = <1500000>;regulator-ramp-delay = <20000>;regulator-always-on;};vdd_3v3_reg: bperi {regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-ramp-delay = <20000>;regulator-always-on;};vdd_sata_reg: ldo3 {regulator-min-microvolt = <2500000>;regulator-max-microvolt = <2500000>;regulator-always-on;};vdd_mipi_reg: ldo4 {regulator-min-microvolt = <2500000>;regulator-max-microvolt = <2500000>;regulator-always-on;};vdd_mx6_snvs_reg: ldo5 {regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-always-on;};vdd_hdmi_reg: ldo6 {regulator-min-microvolt = <2500000>;regulator-max-microvolt = <2500000>;regulator-always-on;regulator-boot-on;};vdd_pcie_reg: ldo7 {regulator-min-microvolt = <2500000>;regulator-max-microvolt = <2500000>;regulator-always-on;};vdd_1V8_reg: ldo8 {regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-always-on;};vdd_3V3_sdc_reg: ldo9 {regulator-min-microvolt = <1800000>;regulator-max-microvolt = <3300000>;regulator-always-on;};vdd_1V2_reg: ldo10 {regulator-min-microvolt = <1200000>;regulator-max-microvolt = <1200000>;regulator-always-on;};};- };
+};
+&i2c2 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
+};
+&iomuxc {
- pinctrl_audmux: audmux {
Please name the pinctrl node more consistently, maybe audmuxgrp to align with others?
fsl,pins = <MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b060MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130B0MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b060>;- };
- pinctrl_can1: can1grp {
fsl,pins = <MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1>;- };
- pinctrl_can2: can2grp {
fsl,pins = <MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b1MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b1>;- };
- pinctrl_cpi1: csi0grp {
fsl,pins = <MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b1MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b1MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b1MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b1MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b1MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b1MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b1MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b1MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b1MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b1>;- };
- /*camera2-pinctrl is in imx6q-emcon.dtsi or imx6dl-emcon.dtsi*/
- pinctrl_ecspi2: ecspi2grp {
fsl,pins = <MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1>;- };
- pinctrl_emcon_gpio1: emcongpio1 {
fsl,pins = <MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x0b0b1>;- };
- pinctrl_emcon_gpio2: emcongpio2 {
fsl,pins = <MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0b0b1>;- };
- pinctrl_emcon_gpio3: emcongpio3 {
fsl,pins = <MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0b0b1>;- };
- pinctrl_emcon_gpio4: emcongpio4 {
fsl,pins = <MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0b0b1>;- };
- pinctrl_emcon_gpio5: emcongpio5 {
fsl,pins = <MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x0b0b1>;- };
- pinctrl_emcon_gpio6: emcongpio6 {
fsl,pins = <MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0b0b1>;- };
- pinctrl_emcon_gpio7: emcongpio7 {
fsl,pins = <MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0b0b1>;- };
- pinctrl_emcon_gpio8: emcongpio8 {
fsl,pins = <MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0b0b1>;- };
- pinctrl_emcon_irq_a: emconirqa {
fsl,pins = <MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x0b0b1>;- };
- pinctrl_emcon_irq_b: emconirqb {
fsl,pins = <MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x0b0b1>;- };
- pinctrl_emcon_irq_c: emconirqc {
fsl,pins = <MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0b0b1>;- };
- pinctrl_emcon_irq_pwr: emconirqpwr {
fsl,pins = <MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0b0b1>;- };
- pinctrl_emcon_wake: emconwake {
fsl,pins = <MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1>;- };
- pinctrl_enet: enetgrp {
fsl,pins = <MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b030MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b030MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x4001a0b1MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b058MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0>;- };
- pinctrl_i2c1: i2c1grp {
fsl,pins = <MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1>;- };
- pinctrl_i2c2: i2c2grp {
fsl,pins = <MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1>;- };
- pinctrl_i2c3: i2c3grp {
fsl,pins = <MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4000b070MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b870>;- };
- pinctrl_irq_touch1: irqtouch1 {
fsl,pins = <MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x0b0b1>;- };
Unused?
- pinctrl_irq_touch2: irqtouch2 {
fsl,pins = <MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x0b0b1>;- };
- pinctrl_lvds_bl: lvdsbacklightgrp {
fsl,pins = <MX6QDL_PAD_GPIO_9__PWM1_OUT 0x0b0b1MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b1>;- };
- pinctrl_lvds_reg: lvdsreggrp {
fsl,pins = <MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x0b0b1>;- };
- pinctrl_nor_flash: norflashgrp {
fsl,pins = <MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b1MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1>;- };
- pinctrl_pcie_ctrl: pciegrp {
fsl,pins = <MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1>;- };
- pinctrl_pmic: pmicgrp {
fsl,pins = <MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0b0b1>;- };
- pinctrl_pwm_fan: pwmfan {
fsl,pins = <MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x0b0b1>;- };
- pinctrl_rgb_bl: rgbbacklightgrp {
fsl,pins = <MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x0b0b1MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b1>;- };
- pinctrl_rgb_bl_en: rgbenable {
fsl,pins = <MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x0b0b1>;- };
- pinctrl_rgb24_display: rgbgrp {
fsl,pins = <MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10>;- };
- pinctrl_secure: securegrp {
fsl,pins = <MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1>;- };
Unused?
- pinctrl_som_leds: somledgrp {
fsl,pins = <MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x0b0b1MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x0b0b1>;- };
- pinctrl_spdif_in: spdifin {
fsl,pins = <MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0>;- };
- pinctrl_spdif_out: spdifout {
fsl,pins = <MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091>;- };
- pinctrl_uart1: uart1grp {
fsl,pins = <MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1>;- };
- pinctrl_uart2: uart2grp {
fsl,pins = <MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1>;- };
- pinctrl_uart3: uart3grp {
fsl,pins = <MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1>;- };
- pinctrl_uart4: uart4grp {
fsl,pins = <MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1>;- };
- pinctrl_uart5: uart5grp {
fsl,pins = <MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1>;- };
- pinctrl_usb_host1: usbhgrp {
fsl,pins = <MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x1B058MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1B058>;- };
- pinctrl_usb_otg: usbotggrp {
fsl,pins = <MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x17059MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x17059>;- };
- pinctrl_usdhc1: usdhc1grp {
fsl,pins = <MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059MX6QDL_PAD_GPIO_1__SD1_CD_B 0x1b0b1MX6QDL_PAD_DI0_PIN4__SD1_WP 0x1b0b1>;- };
- pinctrl_usdhc2: usdhc2grp {
fsl,pins = <MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059MX6QDL_PAD_GPIO_4__SD2_CD_B 0x1b0b1MX6QDL_PAD_GPIO_2__SD2_WP 0x1b0b1>;- };
- pinctrl_usdhc3: usdhc3grp {
fsl,pins = <MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1>;- };
+};
+&ipu1_di0_disp0 {
- remote-endpoint = <&rgb_encoder_in>;
+};
+&pcie {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie_ctrl>;
- reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
- disable-gpio = <&gpio2 22 GPIO_ACTIVE_LOW>;
+};
+&pwm1 {
- status = "okay";
+};
+&pwm3 {
- status = "okay";
+};
+&pwm4 {
- status = "okay";
+};
+&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
+};
+&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
+};
+&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
+};
+&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart4>;
+};
+&uart5 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart5>;
+};
+&usbh1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb_host1>;
+};
+&usbotg {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb_otg>;
- vbus-supply = <®_usb_otg>;
- dr_mode = "peripheral";
+};
+&usdhc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1>;
- fsl,wp-controller;
+};
+&usdhc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2>;
- fsl,wp-controller;
+};
+&usdhc3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc3>;
- non-removable;
- bus-width = <8>;
- status = "okay";
+};
+/******device power Management*********/
+&cpu0 {
- voltage-tolerance = <2>;
+};
+®_arm {
- vin-supply = <&vddcore_reg>;
+};
+®_soc {
- vin-supply = <&vddsoc_reg>;
+};
+®_pu {
- vin-supply = <&vddsoc_reg>;
+};
One newline.
Shawn
+/*******Disabled HW following***********/
+&snvs_rtc {
- status = "disabled";
+};
2.11.0
-----Ursprüngliche Nachricht----- Von: Shawn Guo Gesendet: Samstag, 28. April 2018 05:13 An: Türk, Jan Cc: Rob Herring; Mark Rutland; Thierry Reding; David Airlie; Sascha Hauer; Pengutronix Kernel Team; Fabio Estevam; Russell King; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; dri- devel@lists.freedesktop.org; LinuxArmKernelMailingListe Betreff: Re: [PATCH v4 6/7] ARM: dts: Add support for emtrion emCON-MX6 series
On Fri, Apr 27, 2018 at 03:24:41PM +0200, jan.tuerk@emtrion.com wrote:
From: Jan Tuerk jan.tuerk@emtrion.com
This patch adds support for the emtrion GmbH emCON-MX6 modules. They are available with imx.6 Solo, Dual-Lite, Dual and Quad equipped with Memory from 512MB to 2GB (configured by U-Boot).
Our default developer-Kit ships with the Avari baseboard and the EDT ETM0700G0BDH6 Display (imx6[q|dl]-emcon-avari).
The devicetree is split into the common part providing all module components and the basic support for all SoC versions (imx6qdl-emcon.dtsi) and parts which are i.mx6 S|DL and D|Q relevant. Finally the support for the avari baseboard in the developer-kit configuration is provided by the emcon-avari dts files.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com
Changes for v4:
- re-arrange the Patch-series to match the DT-submitting-patches
- Additional patch for the Documentation of the new DT-bindings
- alphabetically sort the DT
- moved duplicated Avari baseboard code into separate common file.
arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx6dl-emcon-avari.dts | 17 + arch/arm/boot/dts/imx6dl-emcon.dtsi | 28 + arch/arm/boot/dts/imx6q-emcon-avari.dts | 17 + arch/arm/boot/dts/imx6q-emcon.dtsi | 28 + arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi | 208 ++++++++ arch/arm/boot/dts/imx6qdl-emcon.dtsi | 826
+++++++++++++++++++++++++++++
7 files changed, 1126 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-emcon-avari.dts create mode 100644 arch/arm/boot/dts/imx6dl-emcon.dtsi create mode 100644 arch/arm/boot/dts/imx6q-emcon-avari.dts create mode 100644 arch/arm/boot/dts/imx6q-emcon.dtsi create mode 100644 arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi create mode 100644 arch/arm/boot/dts/imx6qdl-emcon.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7e2424957809..05b930da3fda 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -381,6 +381,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-cubox-i-emmc-som-v15.dtb \ imx6dl-cubox-i-som-v15.dtb \ imx6dl-dfi-fs700-m60.dtb \
- imx6dl-emcon-avari.dtb \ imx6dl-gw51xx.dtb \ imx6dl-gw52xx.dtb \ imx6dl-gw53xx.dtb \
@@ -442,6 +443,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-display5-tianma-tm070-1280x768.dtb \ imx6q-dmo-edmqmx6.dtb \ imx6q-dms-ba16.dtb \
- imx6q-emcon-avari.dtb \ imx6q-evi.dtb \ imx6q-gk802.dtb \ imx6q-gw51xx.dtb \
diff --git a/arch/arm/boot/dts/imx6dl-emcon-avari.dts b/arch/arm/boot/dts/imx6dl-emcon-avari.dts new file mode 100644 index 000000000000..464c82a53da3 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-emcon-avari.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/*
- Copyright (C) 2018 emtrion GmbH
- Author: Jan Tuerk jan.tuerk@emtrion.com */
+/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-emcon.dtsi" +/*Include camera2 pinmux*/ +#include "imx6dl-emcon.dtsi" +#include "imx6qdl-emcon-avari.dtsi"
+/ {
- model = "emtrion SoM emCON-MX6 Solo/Dual-Lite Avari";
- compatible = "emtrion,emcon-mx6-avari", "fsl,imx6dl"; };
diff --git a/arch/arm/boot/dts/imx6dl-emcon.dtsi b/arch/arm/boot/dts/imx6dl-emcon.dtsi new file mode 100644 index 000000000000..0d86e0ecdb4d --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-emcon.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/*
- Copyright (C) 2018 emtrion GmbH
- Author: Jan Tuerk jan.tuerk@emtrion.com */
+/ {
- model = "emtrion SoM emCON-MX6 Solo/DualLite";
- compatible = "emtrion,emcon-mx6", "fsl,imx6dl"; };
+&iomuxc {
- pinctrl_cpi2: csi1grp {
fsl,pins = <MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK0x0b0b1
MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC0x1b0b1
MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC0x1b0b1
MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA120x1b0b1
MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA130x1b0b1
MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA140x1b0b1
MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA150x1b0b1
MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA160x1b0b1
MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA170x1b0b1
MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA180x1b0b1
MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA190x1b0b1
>;- };
+};
I'm uncomfortable with maintain two more dtsi files only for a single pinctrl entry. Instead, I would suggest you put CSI node and its pinctrl entry into imx6q/dl-emcon-avari.dts, and have CSI node refer to its pinctrl entry rather than having the pinctrl in hog group.
The origin Idea behind it is to prevent code duplication. For now there is only the avari baseboard which is upstreamed. But for example, the Bvari [1] baseboard is upcoming and then we'll have code duplication for the csi node and their pincontrols. Also I wanted a clean split between the processor module description (which is the emCON-MX6) and the baseboard (Avari), to make it cleaner to integrate the module code with custom products (for example from our customers) without changing the File-layout over and over.
[1] https://www.emtrion.de/en/details_products-accessoires/bvari.html
diff --git a/arch/arm/boot/dts/imx6q-emcon-avari.dts b/arch/arm/boot/dts/imx6q-emcon-avari.dts new file mode 100644 index 000000000000..093afe2f9069 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-emcon-avari.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/*
- Copyright (C) 2018 emtrion GmbH
- Author: Jan Tuerk jan.tuerk@emtrion.com */
+/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-emcon.dtsi" +/*Include camera2 pinmux*/ +#include "imx6q-emcon.dtsi" +#include "imx6qdl-emcon-avari.dtsi"
+/ {
- model = "emtrion SoM emCON-MX6 Dual/Quad on Avari";
- compatible = "emtrion,emcon-mx6-avari", "fsl,imx6q"; };
diff --git a/arch/arm/boot/dts/imx6q-emcon.dtsi b/arch/arm/boot/dts/imx6q-emcon.dtsi new file mode 100644 index 000000000000..bd7d2aa4248e --- /dev/null +++ b/arch/arm/boot/dts/imx6q-emcon.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/*
- Copyright (C) 2018 emtrion GmbH
- Author: Jan Tuerk jan.tuerk@emtrion.com */
+/ {
- model = "emtrion SoM emCON-MX6 Dual/Quad";
- compatible = "emtrion,emcon-mx6", "fsl,imx6q"; };
+&iomuxc {
- pinctrl_cpi2: csi1grp {
fsl,pins = <MX6QDL_PAD_EIM_D17__IPU2_CSI1_PIXCLK0x0b0b1
MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC0x1b0b1
MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC0x1b0b1
MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA120x1b0b1
MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA130x1b0b1
MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA140x1b0b1
MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA150x1b0b1
MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA160x1b0b1
MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA170x1b0b1
MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA180x1b0b1
MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA190x1b0b1
>;- };
+}; diff --git a/arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi b/arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi new file mode 100644 index 000000000000..7fb870907ff8 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/*
- Copyright (C) 2018 emtrion GmbH
- Author: Jan Tuerk jan.tuerk@emtrion.com */
+/ {
- aliases {
mmc0 = &usdhc3;mmc2 = &usdhc1;mmc1 = &usdhc2;mmc3 = &usdhc4;boardID = &boardID;Why do you need this boardID alias?
I wanted to have a generic entry point to address the board-id on all CPU-modules with their different SoC's resulting in different devicetree paths. Also as it now has the generic "gpio@3a" name, there would be no other way in differencing the board Identifying GPIO-expander from an additionally attached one (except platform code etc.) With the alias every code could look up the information required over the alias path with the same piece of code.
- };
- chosen {
stdout-path = <&uart1>;- };
- memory@10000000 {
reg = <0x10000000 0x40000000>;- };
- reg_wall_5p0: reg_wall5p0 {
For fixed regulators, please use regulator-xxx as node name.
OK
compatible = "regulator-fixed";regulator-name = "Main-Supply";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;regulator-always-on;regulator-boot-on;- };
- reg_base3p3: reg_base3p3 {
compatible = "regulator-fixed";vin-supply = <®_wall_5p0>;regulator-name = "3V3-avari";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-always-on;regulator-boot-on;- };
- reg_base1p5: reg_base1p5 {
compatible = "regulator-fixed";vin-supply = <®_base3p3>;regulator-name = "1V5-avari";regulator-min-microvolt = <1500000>;regulator-max-microvolt = <1500000>;regulator-always-on;regulator-boot-on;- };
- reg_usb_otg: reg_otg_vbus {
compatible = "regulator-fixed";vin-supply = <®_wall_5p0>;regulator-name = "OTG_VBUS";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;regulator-always-on;- };
- clk_codec: clock-codec {
compatible = "fixed-clock";#clock-cells = <0>;clock-frequency = <12000000>;- };
- sound {
compatible = "fsl,imx-audio-sgtl5000";model = "emCON-avari-sgtl5000";ssi-controller = <&ssi2>;audio-codec = <&sgtl5000>;audio-routing ="Headphone Jack", "HP_OUT";mux-int-port = <2>;mux-ext-port = <3>;- };
+};
+&iomuxc {
- pinctrl-names = "default";
- /*Unused emCON-MX6 pingroups on AVARI baseboard, enable
defaults*/
- pinctrl-0 = <
&pinctrl_emcon_gpio1 &pinctrl_emcon_gpio2&pinctrl_emcon_gpio3 &pinctrl_emcon_gpio5&pinctrl_emcon_gpio6 &pinctrl_emcon_gpio7&pinctrl_emcon_gpio8 &pinctrl_emcon_irq_a&pinctrl_emcon_irq_b &pinctrl_emcon_irq_c&pinctrl_emcon_irq_pwrCan these GPIO pins be put into one single pinctrl_emcon_gpio entry? From your point of view I agree, but our customers using the emCON module do not have
the schematics as I do, so they would have to create custom groups for every application the emCON-MX6[2] module is used for. With those pinctrls defined, the modules dtsi much more generic to use for different baseboards and applications, IF they're used as specified on the connector. Also the pinctrl_names are deferred from the Names on the Hardware Interface. For example &pinctrl_emcon_gpio5 is for the signal "GPIO_5" on the emCON connector. Some of them are not even connected on the baseboard so they are in the Hog group, to force default settings for them.
[2] https://www.emtrion.de/en/details_products-accessoires/emcon-mx6-57.html
&pinctrl_nor_flash
&pinctrl_usdhc2&pinctrl_spdif_out &pinctrl_spdif_in&pinctrl_cpi1 &pinctrl_cpi2>;Again, please do not put consumer device specific pins in hog group. Also, it's confusing to have the same pinctrl in both hog and consumer device node, like pinctrl_nor_flash and pinctrl_usdhc2 here.
About pinctrl_nor_flash I fully agree, that's a mistake. pinctrl_usdhc2 is not connected on the avari, and therefore not enabled. As told before it is added to the Hog group to force the default pinmuxing without enabling the hardware itself.
+};
+&audmux {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_audmux>;
- status = "okay";
+};
+&can1 {
- status = "okay";
+};
+&can2 {
- status = "okay";
+};
+&ecspi2 {
- status = "okay";
+};
+&hdmi {
- ddc-i2c-bus = <&i2c2>;
- status = "okay";
+};
+&i2c2 {
- status = "okay";
+};
+&i2c3 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- status = "okay";
- sgtl5000: audio-codec@a {
compatible = "fsl,sgtl5000";reg = <0x0a>;#sound-dai-cells = <0>;clocks = <&clk_codec>;VDDA-supply = <®_base3p3>;VDDIO-supply = <®_base3p3>;- };
- boardID: gpio@3a {
compatible = "nxp,pca8574";reg = <0x3a>;gpio-controller;#gpio-cells = <1>;- };
- captouch: touchscreen@38 {
compatible = "edt,edt-ft5406";reg = <0x38>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_irq_touch2 &pinctrl_emcon_gpio4>;interrupt-parent = <&gpio6>;interrupts = <31 IRQ_TYPE_EDGE_FALLING>;wake-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;wakeup-source;- };
+};
+&pcie {
- status = "okay";
+};
+&rgb_encoder {
- status = "okay";
+};
+&rgb_panel {
- compatible = "edt,etm0700g0bdh6";
- status = "okay";
+};
+&ssi2 {
- status = "okay";
+};
+&uart2 {
- status = "okay";
- uart-has-rtscts;
+};
+&uart3 {
- status = "okay";
+};
+&uart4 {
- status = "okay";
+};
+&uart5 {
- status = "okay";
+};
+&usbh1 {
- status = "okay";
+};
+&usbotg {
- status = "okay";
+};
+&usdhc1 {
- status = "okay";
+};
Remove these end of file newlines.
ack
diff --git a/arch/arm/boot/dts/imx6qdl-emcon.dtsi b/arch/arm/boot/dts/imx6qdl-emcon.dtsi new file mode 100644 index 000000000000..32b9bfdc3c41 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-emcon.dtsi @@ -0,0 +1,826 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/*
- Copyright (C) 2018 emtrion GmbH
- Author: Jan Tuerk jan.tuerk@emtrion.com */
+#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/input/input.h>
+/ {
- model = "emtrion SoM emCON-MX6";
- compatible = "emtrion,emcon-mx6", "fsl,imx6q", "fsl,imx6dl";
- aliases {
mmc0 = &usdhc3;mmc2 = &usdhc1;mmc1 = &usdhc2;- };
- gpio-keys {
compatible = "gpio-keys";pinctrl-names = "default";pinctrl-0 = <&pinctrl_emcon_wake>;wake {label = "Wake";linux,code = <KEY_WAKEUP>;gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;wakeup-source;};- };
- som_leds: leds {
compatible = "gpio-leds";pinctrl-names = "default";pinctrl-0 = <&pinctrl_som_leds>;green {label = "som:green";gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;linux,default-trigger = "heartbeat";default-state = "on";};red {label = "som:red";gpios = <&gpio3 1 GPIO_ACTIVE_LOW>;default-state = "keep";};- };
- lvds_backlight: lvds-backlight {
compatible = "pwm-backlight";pinctrl-names = "default";pinctrl-0 = <&pinctrl_lvds_bl>;enable-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>;pwms = <&pwm1 0 50000>;brightness-levels = <0 4 8 16 32 64 80 96 112One tab indent is good enough.
128 144 160 176 250>;Please align the close '>' with the beginning character of open '<' line, i.e. 'b'.
default-brightness-level = <13>;status = "okay";- };
Have a newline between nodes.
Sorry.
- pwm_fan: pwm-fan {
compatible = "pwm-fan";cooling-min-state = <0>;cooling-max-state = <4>;#cooling-cells = <2>;pwms = <&pwm4 0 50000>;cooling-levels = <0 64 127 191 255>;status = "disabled";- };
- rgb_encoder: parallel-display {
display for node name.
compatible = "fsl,imx-parallel-display";#address-cells = <1>;#size-cells = <0>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_rgb24_display>;status = "disabled";port@0 {reg = <0>;rgb_encoder_in: endpoint {remote-endpoint = <&ipu1_di0_disp0>;};};port@1 {reg = <1>;rgb_encoder_out: endpoint {remote-endpoint = <&rgb_panel_in>;};};- };
- rgb_panel: panel {
lcd for node name as suggested by Devicetree Specification?
I used the Kernel documentation as reference: Documentation/devicetree/bindings/display/panel/simple-panel.txt-Example: Documentation/devicetree/bindings/display/panel/simple-panel.txt- Documentation/devicetree/bindings/display/panel/simple-panel.txt: panel: panel { Documentation/devicetree/bindings/display/panel/simple-panel.txt- compatible = "cptt,claa101wb01"; Documentation/devicetree/bindings/display/panel/simple-panel.txt- ddc-i2c-bus = <&panelddc>; Documentation/devicetree/bindings/display/panel/simple-panel.txt-
Same for a lot entries there...
sharp,ls037v7dw01.txt-lcd0: display { samsung,s6e3ha2.txt- panel@0 { sharp,lq101r1sx01.txt- panel: panel@0 {
etc. etc.
backlight = <&rgb_backlight>;power-supply = <®_parallel_disp>;port {rgb_panel_in: endpoint {remote-endpoint = <&rgb_encoder_out>;};};- };
- reg_parallel_disp: reg_parallel-display {
compatible = "regulator-fixed";pinctrl-names = "default";pinctrl-0 = <&pinctrl_rgb_bl_en>;regulator-name = "LCD-Supply";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;gpio = <&gpio7 9 GPIO_ACTIVE_HIGH>;enable-active-high;- };
- reg_lvds_disp: reg_lvds-display {
compatible = "regulator-fixed";regulator-name = "LVDS-Supply";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;gpio = <&gpio7 10 GPIO_ACTIVE_HIGH>;enable-active-high;- };
- rgb_backlight: rgb-backlight {
compatible = "pwm-backlight";pinctrl-names = "default";pinctrl-0 = <&pinctrl_rgb_bl>;enable-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;pwms = <&pwm3 0 5000000>;brightness-levels = <250 176 160 144 128 11296 80 64 48 32 16 8 1>;default-brightness-level = <13>;status = "okay";- };
+};
+&can1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_can1>;
+};
+&can2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_can2>;
+};
+&ecspi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi2>;
- cs-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>,
One space after =.
<&gpio2 26 GPIO_ACTIVE_HIGH>;Align the line with above one.
+};
+&ecspi4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nor_flash>;
+};
+&fec {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet>;
- phy-mode = "rgmii";
- phy-reset-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
- phy-reset-duration = <50>;
- phy-supply = <&vdd_1V8_reg>;
- phy-handle = <&ksz9031>;
- status = "okay";
One newline.
- mdio {
#address-cells = <1>;#size-cells = <0>;ksz9031: phy@0 {compatible = "ethernet-phy-ieee802.3-c22";reg = <0>;interrupt-parent = <&gpio1>;interrupts = <30 IRQ_TYPE_EDGE_FALLING>;rxdv-skew-ps = <480>;txen-skew-ps = <480>;rxd0-skew-ps = <480>;rxd1-skew-ps = <480>;rxd2-skew-ps = <480>;rxd3-skew-ps = <480>;txd0-skew-ps = <420>;txd1-skew-ps = <420>;txd2-skew-ps = <360>;txd3-skew-ps = <360>;txc-skew-ps = <1020>;rxc-skew-ps = <960>;};- };
+};
+&i2c1 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- status = "okay";
- rtc: rtc@68 {
Is the label actually used? If yes, I would suggest a more specific name like ds1307.
Really? Why should it be a generic name for "gpio" and "pmic" but not a generic name for an "rtc" chip?
compatible = "dallas,ds1307";reg = <0x68>;- };
- da9063: pmic@58 {
compatible = "dlg,da9063";reg = <0x58>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_pmic>;interrupt-parent = <&gpio2>;interrupts = <8 IRQ_TYPE_LEVEL_LOW>;interrupt-controller;onkey {compatible = "dlg,da9063-onkey";wakeup-source;};wdt {s/wdt/watchdog. I remember I have already put this comment on previous version.
Yes , I do also remember, my fault sorry.
compatible = "dlg,da9063-watchdog";timeout-sec = <0>;};regulators {vddcore_reg: bcore1 {regulator-min-microvolt = <1100000>;regulator-max-microvolt = <1450000>;regulator-ramp-delay = <20000>;regulator-name = "DA9063_CORE";regulator-always-on;};vddsoc_reg: bcore2 {regulator-min-microvolt = <1100000>;regulator-max-microvolt = <1450000>;regulator-ramp-delay = <20000>;regulator-name = "DA9063_SOC";regulator-always-on;};vdd_ddr3_reg: bpro {regulator-min-microvolt = <1500000>;regulator-max-microvolt = <1500000>;regulator-ramp-delay = <20000>;regulator-always-on;};vdd_3v3_reg: bperi {regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-ramp-delay = <20000>;regulator-always-on;};vdd_sata_reg: ldo3 {regulator-min-microvolt = <2500000>;regulator-max-microvolt = <2500000>;regulator-always-on;};vdd_mipi_reg: ldo4 {regulator-min-microvolt = <2500000>;regulator-max-microvolt = <2500000>;regulator-always-on;};vdd_mx6_snvs_reg: ldo5 {regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-always-on;};vdd_hdmi_reg: ldo6 {regulator-min-microvolt = <2500000>;regulator-max-microvolt = <2500000>;regulator-always-on;regulator-boot-on;};vdd_pcie_reg: ldo7 {regulator-min-microvolt = <2500000>;regulator-max-microvolt = <2500000>;regulator-always-on;};vdd_1V8_reg: ldo8 {regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-always-on;};vdd_3V3_sdc_reg: ldo9 {regulator-min-microvolt = <1800000>;regulator-max-microvolt = <3300000>;regulator-always-on;};vdd_1V2_reg: ldo10 {regulator-min-microvolt = <1200000>;regulator-max-microvolt = <1200000>;regulator-always-on;};};- };
+};
+&i2c2 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
+};
+&iomuxc {
- pinctrl_audmux: audmux {
Please name the pinctrl node more consistently, maybe audmuxgrp to align with others?
I agree
fsl,pins = <MX6QDL_PAD_CSI0_DAT7__AUD3_RXD0x130b0
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC0x1b060
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD0x130B0
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS0x1b060
>;- };
- pinctrl_can1: can1grp {
fsl,pins = <MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX0x1b0b1
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX0x1b0b1
>;- };
- pinctrl_can2: can2grp {
fsl,pins = <MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX0x1b0b1
MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX0x1b0b1
>;- };
- pinctrl_cpi1: csi0grp {
fsl,pins = <MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK0xb0b1
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC0x1b0b1
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC0x1b0b1
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA120x1b0b1
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA130x1b0b1
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA140x1b0b1
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA150x1b0b1
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA160x1b0b1
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA170x1b0b1
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA180x1b0b1
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA190x1b0b1
>;- };
- /*camera2-pinctrl is in imx6q-emcon.dtsi or imx6dl-emcon.dtsi*/
- pinctrl_ecspi2: ecspi2grp {
fsl,pins = <MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK0x100b1
MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI0x100b1
MX6QDL_PAD_EIM_OE__ECSPI2_MISO0x100b1
MX6QDL_PAD_EIM_LBA__GPIO2_IO270x100b1
MX6QDL_PAD_EIM_RW__GPIO2_IO260x100b1
>;- };
- pinctrl_emcon_gpio1: emcongpio1 {
fsl,pins = <MX6QDL_PAD_NANDF_D0__GPIO2_IO000x0b0b1
>;- };
- pinctrl_emcon_gpio2: emcongpio2 {
fsl,pins = <MX6QDL_PAD_NANDF_D1__GPIO2_IO010x0b0b1
>;- };
- pinctrl_emcon_gpio3: emcongpio3 {
fsl,pins = <MX6QDL_PAD_NANDF_D2__GPIO2_IO020x0b0b1
>;- };
- pinctrl_emcon_gpio4: emcongpio4 {
fsl,pins = <MX6QDL_PAD_NANDF_D3__GPIO2_IO030x0b0b1
>;- };
- pinctrl_emcon_gpio5: emcongpio5 {
fsl,pins = <MX6QDL_PAD_NANDF_D4__GPIO2_IO040x0b0b1
>;- };
- pinctrl_emcon_gpio6: emcongpio6 {
fsl,pins = <MX6QDL_PAD_NANDF_D5__GPIO2_IO050x0b0b1
>;- };
- pinctrl_emcon_gpio7: emcongpio7 {
fsl,pins = <MX6QDL_PAD_NANDF_D6__GPIO2_IO060x0b0b1
>;- };
- pinctrl_emcon_gpio8: emcongpio8 {
fsl,pins = <MX6QDL_PAD_NANDF_D7__GPIO2_IO070x0b0b1
>;- };
- pinctrl_emcon_irq_a: emconirqa {
fsl,pins = <MX6QDL_PAD_NANDF_CLE__GPIO6_IO070x0b0b1
>;- };
- pinctrl_emcon_irq_b: emconirqb {
fsl,pins = <MX6QDL_PAD_NANDF_CS2__GPIO6_IO150x0b0b1
>;- };
- pinctrl_emcon_irq_c: emconirqc {
fsl,pins = <MX6QDL_PAD_NANDF_CS3__GPIO6_IO160x0b0b1
>;- };
- pinctrl_emcon_irq_pwr: emconirqpwr {
fsl,pins = <MX6QDL_PAD_EIM_D23__GPIO3_IO230x0b0b1
>;- };
- pinctrl_emcon_wake: emconwake {
fsl,pins = <MX6QDL_PAD_EIM_DA2__GPIO3_IO020x1b0b1
>;- };
- pinctrl_enet: enetgrp {
fsl,pins = <MX6QDL_PAD_ENET_MDIO__ENET_MDIO0x1b030
MX6QDL_PAD_ENET_MDC__ENET_MDC0x1b030
MX6QDL_PAD_RGMII_TXC__RGMII_TXC0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD00x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD10x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD20x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD30x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK0x4001a0b1
MX6QDL_PAD_RGMII_RXC__RGMII_RXC0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD00x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD10x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD20x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD30x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL0x1b0b0
MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO200x1b058
MX6QDL_PAD_ENET_TXD0__GPIO1_IO300x1b0b0
>;- };
- pinctrl_i2c1: i2c1grp {
fsl,pins = <MX6QDL_PAD_CSI0_DAT8__I2C1_SDA0x4001b8b1
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL0x4001b8b1
>;- };
- pinctrl_i2c2: i2c2grp {
fsl,pins = <MX6QDL_PAD_KEY_COL3__I2C2_SCL0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA0x4001b8b1
>;- };
- pinctrl_i2c3: i2c3grp {
fsl,pins = <MX6QDL_PAD_GPIO_3__I2C3_SCL0x4000b070
MX6QDL_PAD_GPIO_6__I2C3_SDA0x4001b870
>;- };
- pinctrl_irq_touch1: irqtouch1 {
fsl,pins = <MX6QDL_PAD_GPIO_5__GPIO1_IO050x0b0b1
>;- };
Unused?
Yes on the avari baseboard in the developer-kit configuration. But used when a LVDS Display is connected.
- pinctrl_irq_touch2: irqtouch2 {
fsl,pins = <MX6QDL_PAD_EIM_BCLK__GPIO6_IO310x0b0b1
>;- };
- pinctrl_lvds_bl: lvdsbacklightgrp {
fsl,pins = <MX6QDL_PAD_GPIO_9__PWM1_OUT0x0b0b1
MX6QDL_PAD_NANDF_WP_B__GPIO6_IO090x0b0b1
>;- };
- pinctrl_lvds_reg: lvdsreggrp {
fsl,pins = <MX6QDL_PAD_SD4_CLK__GPIO7_IO100x0b0b1
>;- };
- pinctrl_nor_flash: norflashgrp {
fsl,pins = <MX6QDL_PAD_NANDF_CS0__GPIO6_IO110x1b0b1
MX6QDL_PAD_EIM_D21__ECSPI4_SCLK0x100b1
MX6QDL_PAD_EIM_D28__ECSPI4_MOSI0x100b1
MX6QDL_PAD_EIM_D22__ECSPI4_MISO0x100b1
MX6QDL_PAD_EIM_A25__GPIO5_IO020x100b1
>;- };
- pinctrl_pcie_ctrl: pciegrp {
fsl,pins = <MX6QDL_PAD_EIM_A16__GPIO2_IO220x1b0b1
MX6QDL_PAD_GPIO_17__GPIO7_IO120x1b0b1
>;- };
- pinctrl_pmic: pmicgrp {
fsl,pins = <MX6QDL_PAD_SD4_DAT0__GPIO2_IO080x0b0b1
>;- };
- pinctrl_pwm_fan: pwmfan {
fsl,pins = <MX6QDL_PAD_SD4_DAT2__PWM4_OUT0x0b0b1
>;- };
- pinctrl_rgb_bl: rgbbacklightgrp {
fsl,pins = <MX6QDL_PAD_SD4_DAT1__PWM3_OUT0x0b0b1
MX6QDL_PAD_NANDF_ALE__GPIO6_IO080x0b0b1
>;- };
- pinctrl_rgb_bl_en: rgbenable {
fsl,pins = <MX6QDL_PAD_SD4_CMD__GPIO7_IO090x0b0b1
>;- };
- pinctrl_rgb24_display: rgbgrp {
fsl,pins = <MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK0x10
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN150x10
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA000x10
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA010x10
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA020x10
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA030x10
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA040x10
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA050x10
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA060x10
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA070x10
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA080x10
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA090x10
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA100x10
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA110x10
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA120x10
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA130x10
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA140x10
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA150x10
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA160x10
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA170x10
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA180x10
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA190x10
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA200x10
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA210x10
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA220x10
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA230x10
>;- };
- pinctrl_secure: securegrp {
fsl,pins = <MX6QDL_PAD_GPIO_18__GPIO7_IO130x1b0b1
>;- };
Unused?
For now yes, but it describes the HW of the module.
- pinctrl_som_leds: somledgrp {
fsl,pins = <MX6QDL_PAD_EIM_DA0__GPIO3_IO000x0b0b1
MX6QDL_PAD_EIM_DA1__GPIO3_IO010x0b0b1
>;- };
- pinctrl_spdif_in: spdifin {
fsl,pins = <MX6QDL_PAD_GPIO_16__SPDIF_IN0x1b0b0
>;- };
- pinctrl_spdif_out: spdifout {
fsl,pins = <MX6QDL_PAD_GPIO_19__SPDIF_OUT0x13091
>;- };
- pinctrl_uart1: uart1grp {
fsl,pins = <MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA0x1b0b1
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA0x1b0b1
>;- };
- pinctrl_uart2: uart2grp {
fsl,pins = <MX6QDL_PAD_SD4_DAT5__UART2_RTS_B0x1b0b1
MX6QDL_PAD_SD4_DAT6__UART2_CTS_B0x1b0b1
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA0x1b0b1
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA0x1b0b1
>;- };
- pinctrl_uart3: uart3grp {
fsl,pins = <MX6QDL_PAD_EIM_D24__UART3_TX_DATA0x1b0b1
MX6QDL_PAD_EIM_D25__UART3_RX_DATA0x1b0b1
>;- };
- pinctrl_uart4: uart4grp {
fsl,pins = <MX6QDL_PAD_KEY_COL0__UART4_TX_DATA0x1b0b1
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA0x1b0b1
>;- };
- pinctrl_uart5: uart5grp {
fsl,pins = <MX6QDL_PAD_KEY_COL1__UART5_TX_DATA0x1b0b1
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA0x1b0b1
>;- };
- pinctrl_usb_host1: usbhgrp {
fsl,pins = <MX6QDL_PAD_EIM_D31__USB_H1_PWR0x1B058
MX6QDL_PAD_EIM_D30__USB_H1_OC0x1B058
>;- };
- pinctrl_usb_otg: usbotggrp {
fsl,pins = <MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID0x17059
MX6QDL_PAD_GPIO_7__GPIO1_IO070x17059
MX6QDL_PAD_GPIO_8__GPIO1_IO080x17059
>;- };
- pinctrl_usdhc1: usdhc1grp {
fsl,pins = <MX6QDL_PAD_SD1_CMD__SD1_CMD0x17059
MX6QDL_PAD_SD1_CLK__SD1_CLK0x10059
MX6QDL_PAD_SD1_DAT0__SD1_DATA00x17059
MX6QDL_PAD_SD1_DAT1__SD1_DATA10x17059
MX6QDL_PAD_SD1_DAT2__SD1_DATA20x17059
MX6QDL_PAD_SD1_DAT3__SD1_DATA30x17059
MX6QDL_PAD_GPIO_1__SD1_CD_B0x1b0b1
MX6QDL_PAD_DI0_PIN4__SD1_WP0x1b0b1
>;- };
- pinctrl_usdhc2: usdhc2grp {
fsl,pins = <MX6QDL_PAD_SD2_CMD__SD2_CMD0x17059
MX6QDL_PAD_SD2_CLK__SD2_CLK0x10059
MX6QDL_PAD_SD2_DAT0__SD2_DATA00x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA10x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA20x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA30x17059
MX6QDL_PAD_GPIO_4__SD2_CD_B0x1b0b1
MX6QDL_PAD_GPIO_2__SD2_WP0x1b0b1
>;- };
- pinctrl_usdhc3: usdhc3grp {
fsl,pins = <MX6QDL_PAD_SD3_CMD__SD3_CMD0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA00x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA10x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA20x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA30x17059
MX6QDL_PAD_SD3_DAT4__SD3_DATA40x17059
MX6QDL_PAD_SD3_DAT5__SD3_DATA50x17059
MX6QDL_PAD_SD3_DAT6__SD3_DATA60x17059
MX6QDL_PAD_SD3_DAT7__SD3_DATA70x17059
MX6QDL_PAD_SD3_RST__SD3_RESET0x1b0b1
>;- };
+};
+&ipu1_di0_disp0 {
- remote-endpoint = <&rgb_encoder_in>; };
+&pcie {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie_ctrl>;
- reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
- disable-gpio = <&gpio2 22 GPIO_ACTIVE_LOW>; };
+&pwm1 {
- status = "okay";
+};
+&pwm3 {
- status = "okay";
+};
+&pwm4 {
- status = "okay";
+};
+&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
+};
+&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
+};
+&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
+};
+&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart4>;
+};
+&uart5 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart5>;
+};
+&usbh1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb_host1>;
+};
+&usbotg {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb_otg>;
- vbus-supply = <®_usb_otg>;
- dr_mode = "peripheral";
+};
+&usdhc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1>;
- fsl,wp-controller;
+};
+&usdhc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2>;
- fsl,wp-controller;
+};
+&usdhc3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc3>;
- non-removable;
- bus-width = <8>;
- status = "okay";
+};
+/******device power Management*********/
+&cpu0 {
- voltage-tolerance = <2>;
+};
+®_arm {
- vin-supply = <&vddcore_reg>;
+};
+®_soc {
- vin-supply = <&vddsoc_reg>;
+};
+®_pu {
- vin-supply = <&vddsoc_reg>;
+};
One newline.
Ack
Shawn
+/*******Disabled HW following***********/
+&snvs_rtc {
- status = "disabled";
+};
2.11.0
Jan
On Thu, May 03, 2018 at 12:00:06PM +0200, Türk, Jan wrote:
+/ {
- aliases {
mmc0 = &usdhc3;mmc2 = &usdhc1;mmc1 = &usdhc2;mmc3 = &usdhc4;boardID = &boardID;Why do you need this boardID alias?
I wanted to have a generic entry point to address the board-id on all CPU-modules with their different SoC's resulting in different devicetree paths. Also as it now has the generic "gpio@3a" name, there would be no other way in differencing the board Identifying GPIO-expander from an additionally attached one (except platform code etc.) With the alias every code could look up the information required over the alias path with the same piece of code.
Okay. But no uppercase please. Otherwise, you introduce the following DTC warnings (with W=1 switch) we are trying to clean up.
Warning (alias_paths): /aliases: aliases property name must include only lowercase and '-'
- };
<snip>
&pinctrl_nor_flash
&pinctrl_usdhc2&pinctrl_spdif_out &pinctrl_spdif_in&pinctrl_cpi1 &pinctrl_cpi2>;Again, please do not put consumer device specific pins in hog group. Also, it's confusing to have the same pinctrl in both hog and consumer device node, like pinctrl_nor_flash and pinctrl_usdhc2 here.
About pinctrl_nor_flash I fully agree, that's a mistake. pinctrl_usdhc2 is not connected on the avari, and therefore not enabled. As told before it is added to the Hog group to force the default pinmuxing without enabling the hardware itself.
If you want to do such default pinmuxing, please do it in your firmware. We generally do not want to use hog group too much, because that makes it difficult to find out which client devices consume which pins.
+};
<snip>
+&i2c1 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- status = "okay";
- rtc: rtc@68 {
Is the label actually used? If yes, I would suggest a more specific name like ds1307.
Really? Why should it be a generic name for "gpio" and "pmic" but not a generic name for an "rtc" chip?
I'm talking about label not node name. That said I was suggesting something like:
ds1307: rtc@68
compatible = "dallas,ds1307";reg = <0x68>;- };
Shawn
From: Jan Tuerk jan.tuerk@emtrion.com
All recent emtrion modules based on i.mx6 make use of the DA0963. Therefore enable it with the following defaults: - CONFIG_MFD_DA9063=y - CONFIG_REGULATOR_DA9063=y - CONFIG_DA9063_WATCHDOG=m MFD and REGULATOR are built-in to have it at Kernel boot-time. The WATCHDOG is optional and could be loaded from userspace.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com --- arch/arm/configs/imx_v6_v7_defconfig | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 3a308437b088..691d431250d4 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -214,9 +214,11 @@ CONFIG_CPU_THERMAL=y CONFIG_IMX_THERMAL=y CONFIG_WATCHDOG=y CONFIG_DA9062_WATCHDOG=y +CONFIG_DA9063_WATCHDOG=m CONFIG_IMX2_WDT=y CONFIG_MFD_DA9052_I2C=y CONFIG_MFD_DA9062=y +CONFIG_MFD_DA9063=y CONFIG_MFD_MC13XXX_SPI=y CONFIG_MFD_MC13XXX_I2C=y CONFIG_MFD_STMPE=y @@ -225,6 +227,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_ANATOP=y CONFIG_REGULATOR_DA9052=y CONFIG_REGULATOR_DA9062=y +CONFIG_REGULATOR_DA9063=y CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_MC13783=y CONFIG_REGULATOR_MC13892=y
On Fri, Apr 27, 2018 at 03:24:35PM +0200, jan.tuerk@emtrion.com wrote:
From: Jan Tuerk jan.tuerk@emtrion.com
Changes for v4:
- re-arrange the Patch-series to match the DT-submitting-patches
- Additional patch for the Documentation of the new DT-bindings
[PATCH v4 1/7] dt-bindings: display: Document the EDT et* displays in one file.
- no change (re-arranged 3/6 => 1/7)
[PATCH v4 2/7] drm/panel: Add support for the EDT ETM0700G0BDH6
- no change (re-arranged 1/6 => 2/7)
[PATCH v4 3/7] drm/panel: Add support for the EDT ETM0700G0EDH6
- no change (re-arranged 2/6 => 3/7)
Please split the series into two, DRM driver (above) and platform part (below), to avoid posting one part over and over again with zero changes, but only because the other part needs update.
Shawn
[PATCH v4 4/7] ARM: dts: imx: Add an cpu0 label for imx6dl devices.
- no change
[PATCH v4 5/7] dt-bindings: arm: Document emtrion emCON-MX6 bindings
- separate patch for the emtrion emCON-MX6 DT-bindings
[PATCH v4 6/7] ARM: dts: Add support for emtrion emCON-MX6 series
- alphabetically sort the DT
- moved duplicated Avari baseboard code into separate file.
[PATCH v4 7/7] ARM: imx_v6_v7_defconfig: Enable DA0963 PMIC support.
- unchaged
-----Ursprüngliche Nachricht----- Von: Shawn Guo [mailto:shawnguo@kernel.org] Gesendet: Samstag, 28. April 2018 04:35 An: Türk, Jan Cc: Rob Herring; Mark Rutland; Thierry Reding; David Airlie; Sascha Hauer; Pengutronix Kernel Team; Fabio Estevam; Russell King; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; dri- devel@lists.freedesktop.org; LinuxArmKernelMailingListe Betreff: Re: [PATCH v4 0/7] Add basic support for emtrion emCON-MX6 modules
On Fri, Apr 27, 2018 at 03:24:35PM +0200, jan.tuerk@emtrion.com wrote:
From: Jan Tuerk jan.tuerk@emtrion.com
Changes for v4:
- re-arrange the Patch-series to match the DT-submitting-patches
- Additional patch for the Documentation of the new DT-bindings
[PATCH v4 1/7] dt-bindings: display: Document the EDT et* displays in one
file.
- no change (re-arranged 3/6 => 1/7)
[PATCH v4 2/7] drm/panel: Add support for the EDT ETM0700G0BDH6
- no change (re-arranged 1/6 => 2/7)
[PATCH v4 3/7] drm/panel: Add support for the EDT ETM0700G0EDH6
- no change (re-arranged 2/6 => 3/7)
Please split the series into two, DRM driver (above) and platform part (below), to avoid posting one part over and over again with zero changes, but only because the other part needs update.
Shawn
Ok I'll split them.
[PATCH v4 4/7] ARM: dts: imx: Add an cpu0 label for imx6dl devices.
- no change
[PATCH v4 5/7] dt-bindings: arm: Document emtrion emCON-MX6 bindings
- separate patch for the emtrion emCON-MX6 DT-bindings
[PATCH v4 6/7] ARM: dts: Add support for emtrion emCON-MX6 series
- alphabetically sort the DT
- moved duplicated Avari baseboard code into separate file.
[PATCH v4 7/7] ARM: imx_v6_v7_defconfig: Enable DA0963 PMIC support.
- unchaged
From: Jan Tuerk jan.tuerk@emtrion.com
emtrion is a system integrator and manufacturer of embedded systems.
Website: https://www.emtrion.de
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com Reviewed-by: Andreas Färber afaerber@suse.de Acked-by: Rob Herring robh@kernel.org --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 0994bdd82cd3..5215c5767260 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -102,6 +102,7 @@ eeti eGalax_eMPIA Technology Inc elan Elan Microelectronic Corp. embest Shenzhen Embest Technology Co., Ltd. emmicro EM Microelectronic +emtrion emtrion GmbH energymicro Silicon Laboratories (formerly Energy Micro AS) engicam Engicam S.r.l. epcos EPCOS AG
From: Jan Tuerk jan.tuerk@emtrion.com
Adding the label cpu0 allows the adjustment of cpu-parameters by reference in overlaying dtsi files in the same way as it is possible for imx6q devices.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com Reviewed-by: Andreas Färber afaerber@suse.de --- arch/arm/boot/dts/imx6dl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 4d693a75ce98..623c12519b81 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -21,7 +21,7 @@ #address-cells = <1>; #size-cells = <0>;
- cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>;
From: Jan Tuerk jan.tuerk@emtrion.com
This patch adds support for the emtrion GmbH emCON-MX6 modules. They are available with imx.6 Solo, Dual-Lite, Dual and Quad equipped with Memory from 512MB to 2GB (configured by U-Boot).
Our default developer-Kit ships with the Avari baseboard and the EDT ETM0700G0BDH6 Display (imx6[q|dl]-emcon-avari).
The devicetree is split into the common part providing all module components and the basic support for all SoC versions (imx6qdl-emcon.dtsi) and parts which are i.mx6 S|DL and D|Q relevant. Finally the support for the avari baseboard in the developer-kit configuration is provided by the emcon-avari dts files.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com --- Changes in v2: - Fixed typo (reg_prallel.. --> reg_parallel) - Removed trailing new-line - Fix uppercase addresses as Rob H. noted - Fix warning about lcd@di0 -> rename to disp0 - Renamed some nodes regarding Rob H.
Documentation/devicetree/bindings/arm/emtrion.txt | 13 + arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx6dl-emcon-avari.dts | 233 ++++++ arch/arm/boot/dts/imx6dl-emcon.dtsi | 37 + arch/arm/boot/dts/imx6q-emcon-avari.dts | 233 ++++++ arch/arm/boot/dts/imx6q-emcon.dtsi | 37 + arch/arm/boot/dts/imx6qdl-emcon.dtsi | 848 ++++++++++++++++++++++ 7 files changed, 1403 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/emtrion.txt create mode 100644 arch/arm/boot/dts/imx6dl-emcon-avari.dts create mode 100644 arch/arm/boot/dts/imx6dl-emcon.dtsi create mode 100644 arch/arm/boot/dts/imx6q-emcon-avari.dts create mode 100644 arch/arm/boot/dts/imx6q-emcon.dtsi create mode 100644 arch/arm/boot/dts/imx6qdl-emcon.dtsi
diff --git a/Documentation/devicetree/bindings/arm/emtrion.txt b/Documentation/devicetree/bindings/arm/emtrion.txt new file mode 100644 index 000000000000..3ff6c6c2034d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/emtrion.txt @@ -0,0 +1,13 @@ +Emtrion Devicetree Bindings +=========================== + +emCON Series: +------------- + +Required root node properties + - compatible: + - "emtrion,emcon-mx6", "fsl,imx6q", "fsl,imx6dl"; : emCON-MX6 Generic SoM + - "emtrion,emcon-mx6", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM + - "emtrion,emcon-mx6-avari", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM on Avari Base + - "emtrion,emcon-mx6", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM + - "emtrion,emcon-mx6-avari", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM on Avari Base diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d0381e9caf21..5ce643ece228 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -373,6 +373,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-colibri-eval-v3.dtb \ imx6dl-cubox-i.dtb \ imx6dl-dfi-fs700-m60.dtb \ + imx6dl-emcon-avari.dtb \ imx6dl-gw51xx.dtb \ imx6dl-gw52xx.dtb \ imx6dl-gw53xx.dtb \ @@ -424,6 +425,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-dfi-fs700-m60.dtb \ imx6q-display5-tianma-tm070-1280x768.dtb \ imx6q-dmo-edmqmx6.dtb \ + imx6q-emcon-avari.dtb \ imx6q-evi.dtb \ imx6q-gk802.dtb \ imx6q-gw51xx.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-emcon-avari.dts b/arch/arm/boot/dts/imx6dl-emcon-avari.dts new file mode 100644 index 000000000000..f1333a48d8c5 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-emcon-avari.dts @@ -0,0 +1,233 @@ +/* + * Copyright (C) 2017 emtrion GmbH + * Author: Jan Tuerk jan.tuerk@emtrion.com + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-emcon.dtsi" +#include "imx6dl-emcon.dtsi" /*Include camera2 pinmux*/ + +/ { + model = "emtrion SoM emCON-MX6 Solo/Dual-Lite Avari"; + compatible = "emtrion,emcon-mx6-avari", "fsl,imx6dl"; + + aliases { + mmc0 = &usdhc3; + mmc2 = &usdhc1; + mmc1 = &usdhc2; + mmc3 = &usdhc4; + }; + + chosen { + stdout-path = <&uart1>; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + supplies { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + wallplug5p0: supply@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "WALL-PLUG"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + base3p3: supply@1 { + compatible = "regulator-fixed"; + reg = <1>; + vin-supply = <&wallplug5p0>; + regulator-name = "3V3-avari"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + base1p5: supply@2 { + compatible = "regulator-fixed"; + reg = <2>; + vin-supply = <&base3p3>; + regulator-name = "1V5-avari"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_usb_otg: otgvbus@3 { + compatible = "regulator-fixed"; + reg = <3>; + vin-supply = <&wallplug5p0>; + regulator-name = "OTG_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + }; + + + sndosc: 12MHZosc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "emCON-avari-sgtl5000"; + ssi-controller = <&ssi2>; + audio-codec = <&sgtl5000>; + audio-routing = + "Headphone Jack", "HP_OUT"; + mux-int-port = <2>; + mux-ext-port = <3>; + }; + +}; + + +&iomuxc { + pinctrl-names = "default"; + /*Unused emCON-MX6 outputs on AVARI*/ + pinctrl-0 = < + &pinctrl_emcon_gpio1 &pinctrl_emcon_gpio2 + &pinctrl_emcon_gpio3 &pinctrl_emcon_gpio5 + &pinctrl_emcon_gpio6 &pinctrl_emcon_gpio7 + &pinctrl_emcon_gpio8 &pinctrl_emcon_irq_a + &pinctrl_emcon_irq_b &pinctrl_emcon_irq_c + &pinctrl_emcon_irq_pwr &pinctrl_nor_flash + &pinctrl_usdhc2 + &pinctrl_spdif_out &pinctrl_spdif_in + &pinctrl_cpi1 &pinctrl_cpi2 + >; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + + + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + sgtl5000: audio-codec@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&sndosc>; + VDDA-supply = <&base3p3>; + VDDIO-supply = <&base3p3>; + }; + + boardID: pca8754a@3a { + compatible = "nxp,pca8574"; + reg = <0x3a>; + gpio-controller; + #gpio-cells = <1>; + }; + + captouch: touchscreen@38 { + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_irq_touch2 &pinctrl_emcon_gpio4>; + interrupt-parent = <&gpio6>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + compatible = "edt,edt-ft5406"; + wake-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + wakeup-source; + }; +}; + +&ssi2 { + status = "okay"; +}; + +&rgb_encoder { + status = "okay"; +}; + +&rgb_panel { + compatible = "edt,etm0700g0bdh6"; + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "okay"; +}; + +&uart2 { + status = "okay"; + uart-has-rtscts; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&ecspi2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-emcon.dtsi b/arch/arm/boot/dts/imx6dl-emcon.dtsi new file mode 100644 index 000000000000..47f43bae5ac5 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-emcon.dtsi @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2017 emtrion GmbH + * Author: Jan Tuerk jan.tuerk@emtrion.com + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +/ { + model = "emtrion SoM emCON-MX6 Solo/DualLite"; + compatible = "emtrion,emcon-mx6","fsl,imx6dl"; +}; + +&iomuxc { + pinctrl_cpi2: csi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0x0b0b1 + MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b1 + MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b1 + MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b1 + MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b1 + MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b1 + MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b1 + MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b1 + MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b1 + MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b1 + MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-emcon-avari.dts b/arch/arm/boot/dts/imx6q-emcon-avari.dts new file mode 100644 index 000000000000..c0b20c040790 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-emcon-avari.dts @@ -0,0 +1,233 @@ +/* + * Copyright (C) 2017 emtrion GmbH + * Author: Jan Tuerk jan.tuerk@emtrion.com + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-emcon.dtsi" +#include "imx6q-emcon.dtsi" /*Include camera2 pinmux*/ + +/ { + model = "emtrion SoM emCON-MX6 Dual/Quad on Avari"; + compatible = "emtrion,emcon-mx6-avari", "fsl,imx6q"; + + aliases { + mmc0 = &usdhc3; + mmc2 = &usdhc1; + mmc1 = &usdhc2; + mmc3 = &usdhc4; + }; + + chosen { + stdout-path = <&uart1>; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + supplies { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + wallplug5p0: supply@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "WALL-PLUG"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + base3p3: supply@1 { + compatible = "regulator-fixed"; + reg = <1>; + vin-supply = <&wallplug5p0>; + regulator-name = "3V3-avari"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + base1p5: supply@2 { + compatible = "regulator-fixed"; + reg = <2>; + vin-supply = <&base3p3>; + regulator-name = "1V5-avari"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_usb_otg: otgvbus@3 { + compatible = "regulator-fixed"; + reg = <3>; + vin-supply = <&wallplug5p0>; + regulator-name = "OTG_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + }; + + + sndosc: 12MHZosc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "emCON-avari-sgtl5000"; + ssi-controller = <&ssi2>; + audio-codec = <&sgtl5000>; + audio-routing = + "Headphone Jack", "HP_OUT"; + mux-int-port = <2>; + mux-ext-port = <3>; + }; + +}; + + +&iomuxc { + pinctrl-names = "default"; + /*Unused emCON-MX6 pingroups on AVARI baseboard, enable defaults*/ + pinctrl-0 = < + &pinctrl_emcon_gpio1 &pinctrl_emcon_gpio2 + &pinctrl_emcon_gpio3 &pinctrl_emcon_gpio5 + &pinctrl_emcon_gpio6 &pinctrl_emcon_gpio7 + &pinctrl_emcon_gpio8 &pinctrl_emcon_irq_a + &pinctrl_emcon_irq_b &pinctrl_emcon_irq_c + &pinctrl_emcon_irq_pwr &pinctrl_nor_flash + &pinctrl_usdhc2 + &pinctrl_spdif_out &pinctrl_spdif_in + &pinctrl_cpi1 &pinctrl_cpi2 + >; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + + + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + sgtl5000: audo-codec@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&sndosc>; + VDDA-supply = <&base3p3>; + VDDIO-supply = <&base3p3>; + }; + + boardID: pca8754a@3a { + compatible = "nxp,pca8574"; + reg = <0x3a>; + gpio-controller; + #gpio-cells = <1>; + }; + + captouch: touchscreen@38 { + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_irq_touch2 &pinctrl_emcon_gpio4>; + interrupt-parent = <&gpio6>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + compatible = "edt,edt-ft5406"; + wake-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + wakeup-source; + }; +}; + +&ssi2 { + status = "okay"; +}; + +&rgb_encoder { + status = "okay"; +}; + +&rgb_panel { + compatible = "edt,etm0700g0bdh6"; + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "okay"; +}; + +&uart2 { + status = "okay"; + uart-has-rtscts; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&ecspi2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q-emcon.dtsi b/arch/arm/boot/dts/imx6q-emcon.dtsi new file mode 100644 index 000000000000..64fc0cd74c05 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-emcon.dtsi @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2017 emtrion GmbH + * Author: Jan Tuerk jan.tuerk@emtrion.com + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +/ { + model = "emtrion SoM emCON-MX6 Dual/Quad"; + compatible = "emtrion,emcon-mx6","fsl,imx6q"; +}; + +&iomuxc { + pinctrl_cpi2: csi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__IPU2_CSI1_PIXCLK 0x0b0b1 + MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b1 + MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b1 + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b1 + MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b1 + MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b1 + MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b1 + MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b1 + MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b1 + MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b1 + MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-emcon.dtsi b/arch/arm/boot/dts/imx6qdl-emcon.dtsi new file mode 100644 index 000000000000..f87d8ed6a1b1 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-emcon.dtsi @@ -0,0 +1,848 @@ +/* + * Copyright (C) 2017 emtrion GmbH + * Author: Jan Tuerk jan.tuerk@emtrion.com + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/input/input.h> + +/ { + + model = "emtrion SoM emCON-MX6"; + compatible = "emtrion,emcon-mx6","fsl,imx6q", "fsl,imx6dl"; + + aliases { + mmc0 = &usdhc3; + mmc2 = &usdhc1; + mmc1 = &usdhc2; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_parallel_disp: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgb_bl_en>; + regulator-name = "LCD-Supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio7 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_lvds_disp: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "LVDS-Supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio7 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + som_leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_som_leds>; + + green { + label = "som:green"; + gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + + red { + label = "som:red"; + gpios = <&gpio3 1 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emcon_wake>; + + wake { + label = "Wake"; + linux,code = <KEY_WAKEUP>; + gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + pwm_fan: pwm-fan { + compatible = "pwm-fan"; + cooling-min-state = <0>; + cooling-max-state = <4>; + #cooling-cells = <2>; + pwms = <&pwm4 0 50000>; + cooling-levels = <0 64 127 191 255>; + status = "disabled"; + }; + + rgb_encoder: disp0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgb24_display>; + status = "disabled"; + + port@0 { + reg = <0>; + rgb_encoder_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + rgb_encoder_out: endpoint { + remote-endpoint = <&rgb_panel_in>; + }; + }; + }; + + rgb_panel: panel { + backlight = <&rgb_backlight>; + power-supply = <®_parallel_disp>; + port { + rgb_panel_in: endpoint { + remote-endpoint = <&rgb_encoder_out>; + }; + }; + }; + + rgb_backlight: rgb-backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgb_bl>; + enable-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; + pwms = <&pwm3 0 5000000>; + brightness-levels = <250 176 160 144 128 112 + 96 80 64 48 32 16 8 1 + >; + default-brightness-level = <13>; + status = "okay"; + }; + + lvds_backlight: lvds-backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds_bl>; + enable-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; + pwms = <&pwm1 0 50000>; + brightness-levels = <0 4 8 16 32 64 80 96 112 + 128 144 160 176 250 + >; + default-brightness-level = <13>; + status = "okay"; + }; +}; + + +&iomuxc { + + pinctrl_secure: securegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_emcon_gpio1: emcongpio1 { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio2: emcongpio2 { + fsl,pins = < + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio3: emcongpio3 { + fsl,pins = < + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio4: emcongpio4 { + fsl,pins = < + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio5: emcongpio5 { + fsl,pins = < + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio6: emcongpio6 { + fsl,pins = < + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio7: emcongpio7 { + fsl,pins = < + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio8: emcongpio8 { + fsl,pins = < + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0b0b1 + >; + }; + + pinctrl_emcon_irq_a: emconirqa { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x0b0b1 + >; + }; + + pinctrl_emcon_irq_b: emconirqb { + fsl,pins = < + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x0b0b1 + >; + }; + + pinctrl_emcon_irq_c: emconirqc { + fsl,pins = < + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0b0b1 + >; + }; + + pinctrl_emcon_wake: emconwake { + fsl,pins = < + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1 + >; + }; + + pinctrl_emcon_irq_pwr: emconirqpwr { + fsl,pins = < + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0b0b1 + >; + }; + + pinctrl_som_leds: somledgrp { + fsl,pins = < + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x0b0b1 + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x0b0b1 + >; + }; + + pinctrl_nor_flash: norflashgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b1 + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 + >; + }; + + pinctrl_pwm_fan: pwmfan { + fsl,pins = < + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x0b0b1 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b1 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b1 + >; + }; + + pinctrl_spdif_out: spdifout { + fsl,pins = < + MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091 + >; + }; + + pinctrl_spdif_in: spdifin { + fsl,pins = < + MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_cpi1: csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b1 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b1 + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b1 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b1 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b1 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b1 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b1 + >; + }; + + /*camera2-pinctrl is in imx6q-emcon.dtsi or imx6dl-emcon.dtsi*/ + + pinctrl_pcie_ctrl: pciegrp { + fsl,pins = < + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 + >; + }; + + pinctrl_audmux: audmux { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b060 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130B0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b060 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4000b070 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b870 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0b0b1 + >; + }; + + pinctrl_usb_host1: usbhgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x1B058 + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1B058 + >; + }; + + pinctrl_usb_otg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x17059 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x17059 + >; + }; + + pinctrl_lvds_reg: lvdsreggrp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x0b0b1 + >; + }; + + pinctrl_lvds_bl: lvdsbacklightgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x0b0b1 + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b1 + >; + }; + + pinctrl_irq_touch1: irqtouch1 { + fsl,pins = < + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x0b0b1 + >; + }; + + pinctrl_rgb_bl_en: rgbenable { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x0b0b1 + >; + }; + + pinctrl_irq_touch2: irqtouch2 { + fsl,pins = < + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x0b0b1 + >; + }; + + pinctrl_rgb_bl: rgbbacklightgrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x0b0b1 + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b1 + >; + }; + + pinctrl_rgb24_display: rgbgrp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x4001a0b1 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b058 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 + >; + }; + + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + MX6QDL_PAD_GPIO_1__SD1_CD_B 0x1b0b1 + MX6QDL_PAD_DI0_PIN4__SD1_WP 0x1b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_GPIO_4__SD2_CD_B 0x1b0b1 + MX6QDL_PAD_GPIO_2__SD2_WP 0x1b0b1 + >; + }; + +}; + + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + rtc: rtc@68 { + compatible = "dallas,ds1307"; + reg = <0x68>; + }; + + da9063: pmic@58 { + compatible = "dlg,da9063"; + reg = <0x58>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio2>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + + onkey { + wakeup-source; + compatible = "dlg,da9063-onkey"; + }; + + wdt { + compatible = "dlg,da9063-watchdog"; + timeout-sec = <0>; + }; + + regulators { + vddcore_reg: bcore1 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <20000>; + regulator-name = "DA9063_CORE"; + regulator-always-on; + }; + + vddsoc_reg: bcore2 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <20000>; + regulator-name = "DA9063_SOC"; + regulator-always-on; + }; + + vdd_ddr3_reg: bpro { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <20000>; + regulator-always-on; + }; + + vdd_3v3_reg: bperi { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <20000>; + regulator-always-on; + }; + + vdd_sata_reg: ldo3 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + vdd_mipi_reg: ldo4 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vdd_mx6_snvs_reg: ldo5 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_hdmi_reg: ldo6 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_pcie_reg: ldo7 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vdd_1V8_reg: ldo8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_3V3_sdc_reg: ldo9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_1V2_reg: ldo10 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; + phy-reset-duration = <50>; + phy-supply = <&vdd_1V8_reg>; + phy-handle = <&ksz9031>; + status = "okay"; + + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ksz9031: phy@0 { + reg = <0>; + compatible = "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio1>; + interrupts = <30 IRQ_TYPE_EDGE_FALLING>; + rxdv-skew-ps = <480>; + txen-skew-ps = <480>; + rxd0-skew-ps = <480>; + rxd1-skew-ps = <480>; + rxd2-skew-ps = <480>; + rxd3-skew-ps = <480>; + txd0-skew-ps = <420>; + txd1-skew-ps = <420>; + txd2-skew-ps = <360>; + txd3-skew-ps = <360>; + txc-skew-ps = <1020>; + rxc-skew-ps = <960>; + }; + }; +}; + + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + non-removable; + bus-width = <8>; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_ctrl>; + reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; + disable-gpio = <&gpio2 22 GPIO_ACTIVE_LOW>; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + fsl,wp-controller; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + fsl,wp-controller; +}; + + +&ipu1_di0_disp0 { + remote-endpoint = <&rgb_encoder_in>; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>, + <&gpio2 26 GPIO_ACTIVE_HIGH>; +}; + +&ecspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nor_flash>; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_host1>; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg>; + vbus-supply = <®_usb_otg>; + dr_mode = "peripheral"; +}; + +/******device power Management*********/ + +&cpu0 { + voltage-tolerance = <2>; +}; + +®_arm { + vin-supply = <&vddcore_reg>; +}; + +®_soc { + vin-supply = <&vddsoc_reg>; +}; + +®_pu { + vin-supply = <&vddsoc_reg>; +}; + + + +/*******Disabled HW following***********/ + + +&weim { + status = "disabled"; +}; + +&snvs_rtc { + status = "disabled"; +};
On Wed, Dec 20, 2017 at 02:47:04PM +0100, jan.tuerk@emtrion.com wrote:
From: Jan Tuerk jan.tuerk@emtrion.com
This patch adds support for the emtrion GmbH emCON-MX6 modules. They are available with imx.6 Solo, Dual-Lite, Dual and Quad equipped with Memory from 512MB to 2GB (configured by U-Boot).
Our default developer-Kit ships with the Avari baseboard and the EDT ETM0700G0BDH6 Display (imx6[q|dl]-emcon-avari).
The devicetree is split into the common part providing all module components and the basic support for all SoC versions (imx6qdl-emcon.dtsi) and parts which are i.mx6 S|DL and D|Q relevant. Finally the support for the avari baseboard in the developer-kit configuration is provided by the emcon-avari dts files.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com
Changes in v2:
- Fixed typo (reg_prallel.. --> reg_parallel)
- Removed trailing new-line
- Fix uppercase addresses as Rob H. noted
- Fix warning about lcd@di0 -> rename to disp0
- Renamed some nodes regarding Rob H.
Documentation/devicetree/bindings/arm/emtrion.txt | 13 + arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx6dl-emcon-avari.dts | 233 ++++++ arch/arm/boot/dts/imx6dl-emcon.dtsi | 37 + arch/arm/boot/dts/imx6q-emcon-avari.dts | 233 ++++++ arch/arm/boot/dts/imx6q-emcon.dtsi | 37 + arch/arm/boot/dts/imx6qdl-emcon.dtsi | 848 ++++++++++++++++++++++ 7 files changed, 1403 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/emtrion.txt create mode 100644 arch/arm/boot/dts/imx6dl-emcon-avari.dts create mode 100644 arch/arm/boot/dts/imx6dl-emcon.dtsi create mode 100644 arch/arm/boot/dts/imx6q-emcon-avari.dts create mode 100644 arch/arm/boot/dts/imx6q-emcon.dtsi create mode 100644 arch/arm/boot/dts/imx6qdl-emcon.dtsi
[...]
- captouch: touchscreen@38 {
reg = <0x38>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_irq_touch2 &pinctrl_emcon_gpio4>;interrupt-parent = <&gpio6>;interrupts = <31 IRQ_TYPE_EDGE_FALLING>;compatible = "edt,edt-ft5406";
Put compatible as the first property.
wake-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;wakeup-source;- };
+};
[...]
+&rgb_panel {
- compatible = "edt,etm0700g0bdh6";
- status = "okay";
Having compatible here is a bit strange and fragile. It's assuming 2 different panels have the same common properties.
diff --git a/arch/arm/boot/dts/imx6q-emcon.dtsi b/arch/arm/boot/dts/imx6q-emcon.dtsi new file mode 100644 index 000000000000..64fc0cd74c05 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-emcon.dtsi @@ -0,0 +1,37 @@ +/*
- Copyright (C) 2017 emtrion GmbH
- Author: Jan Tuerk jan.tuerk@emtrion.com
- The code contained herein is licensed under the GNU General Public
- License. You may obtain a copy of the GNU General Public License
- Version 2 or later at the following locations:
You don't need this if...
- SPDX-License-Identifier: GPL-2.0
You have this.
Also, the rules around this are getting a bit stricter saying the SPDX tag should be the first line of the file using a C++ style comment.
- */
+/ {
- model = "emtrion SoM emCON-MX6 Dual/Quad";
- compatible = "emtrion,emcon-mx6","fsl,imx6q";
Need a space ^
diff --git a/arch/arm/boot/dts/imx6qdl-emcon.dtsi b/arch/arm/boot/dts/imx6qdl-emcon.dtsi new file mode 100644 index 000000000000..f87d8ed6a1b1 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-emcon.dtsi @@ -0,0 +1,848 @@ +/*
- Copyright (C) 2017 emtrion GmbH
- Author: Jan Tuerk jan.tuerk@emtrion.com
- The code contained herein is licensed under the GNU General Public
- License. You may obtain a copy of the GNU General Public License
- Version 2 or later at the following locations:
- SPDX-License-Identifier: GPL-2.0
- */
+#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/input/input.h>
+/ {
- model = "emtrion SoM emCON-MX6";
- compatible = "emtrion,emcon-mx6","fsl,imx6q", "fsl,imx6dl";
Need a space ^
From: Jan Tuerk jan.tuerk@emtrion.com
All recent emtrion modules based on i.mx6 make use of the DA0963. Therefore enable it with the following defaults: - CONFIG_MFD_DA9063=y - CONFIG_REGULATOR_DA9063=y - CONFIG_DA9063_WATCHDOG=m - CONFIG_RTC_DRV_DA9063=m MFD and REGULATOR are built-in to have it at Kernel boot-time. The WATCHDOG and RTC are optional and could be loaded from userspace.
Signed-off-by: Jan Tuerk jan.tuerk@emtrion.com --- arch/arm/configs/imx_v6_v7_defconfig | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 0d4494922561..09cd8048b0c1 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -215,8 +215,10 @@ CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_CPU_THERMAL=y CONFIG_IMX_THERMAL=y CONFIG_WATCHDOG=y +CONFIG_DA9063_WATCHDOG=m CONFIG_IMX2_WDT=y CONFIG_MFD_DA9052_I2C=y +CONFIG_MFD_DA9063=y CONFIG_MFD_MC13XXX_SPI=y CONFIG_MFD_MC13XXX_I2C=y CONFIG_MFD_STMPE=y @@ -224,6 +226,7 @@ CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_ANATOP=y CONFIG_REGULATOR_DA9052=y +CONFIG_REGULATOR_DA9063=y CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_MC13783=y CONFIG_REGULATOR_MC13892=y @@ -349,6 +352,7 @@ CONFIG_RTC_DRV_PCF8563=y CONFIG_RTC_DRV_M41T80=y CONFIG_RTC_DRV_MC13XXX=y CONFIG_RTC_DRV_MXC=y +CONFIG_RTC_DRV_DA9063=m CONFIG_RTC_DRV_SNVS=y CONFIG_DMADEVICES=y CONFIG_FSL_EDMA=y
dri-devel@lists.freedesktop.org
-
Andreas Färber -
Fabio Estevam -
Jan Tuerk -
jan.tuerk＠emtrion.com
-
Rob Herring -
Rob Herring -
Shawn Guo -
Thierry Reding -
Türk, Jan