Hi, Hsin-Yi:

On Tue, 2021-02-02 at 16:12 +0800, Hsin-Yi Wang wrote:

From: Yongqiang Niu yongqiang.niu@mediatek.com

This patch add component POSTMASK.

Reviewed-by: CK Hu ck.hu@mediatek.com

Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org

---

drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 102 ++++++++++++++------ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + 2 files changed, 73 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index b6c4e73031ca6..0a84ae53eb72a 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -64,6 +64,12 @@

#define AAL_EN BIT(0)

+#define DISP_POSTMASK_EN 0x0000 +#define POSTMASK_EN BIT(0) +#define DISP_POSTMASK_CFG 0x0020 +#define POSTMASK_RELAY_MODE BIT(0) +#define DISP_POSTMASK_SIZE 0x0030

#define DISP_DITHERING BIT(2) #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28) #define DITHER_OVFLW_BIT_R(x) (((x) & 0x7) << 24) @@ -204,6 +210,32 @@ static void mtk_ufoe_start(struct device *dev) writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START); }

+void mtk_postmask_config(struct device *dev, unsigned int w,

• 	unsigned int h, unsigned int vrefresh,
  

• 	unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
  

+{

• struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
• mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs,

•       DISP_POSTMASK_SIZE);
  

• mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg,

•       priv->regs, DISP_POSTMASK_CFG);
  

+}

+void mtk_postmask_start(struct device *dev) +{

• struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
• writel(POSTMASK_EN, priv->regs + DISP_POSTMASK_EN);

+}

+void mtk_postmask_stop(struct device *dev) +{

• struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
• writel_relaxed(0x0, priv->regs + DISP_POSTMASK_EN);

+}

static void mtk_aal_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) @@ -413,6 +445,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = { .bgclr_in_off = mtk_ovl_bgclr_in_off, };

+static const struct mtk_ddp_comp_funcs ddp_postmask = {

• .clk_enable = mtk_ddp_clk_enable,
• .clk_disable = mtk_ddp_clk_disable,
• .config = mtk_postmask_config,
• .start = mtk_postmask_start,
• .stop = mtk_postmask_stop,

+};

static const struct mtk_ddp_comp_funcs ddp_rdma = { .clk_enable = mtk_rdma_clk_enable, .clk_disable = mtk_rdma_clk_disable, @@ -448,6 +488,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { [MTK_DISP_MUTEX] = "mutex", [MTK_DISP_OD] = "od", [MTK_DISP_BLS] = "bls",

• [MTK_DISP_POSTMASK] = "postmask",

};

struct mtk_ddp_comp_match { @@ -457,36 +498,37 @@ struct mtk_ddp_comp_match { };

static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {

• [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal },
• [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal },
• [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
• [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr },
• [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
• [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
• [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither },
• [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
• [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
• [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
• [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
• [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
• [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
• [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
• [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
• [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
• [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl },
• [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
• [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
• [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
• [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl },
• [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
• [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
• [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
• [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma },
• [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma },
• [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma },
• [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe },
• [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL },
• [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },

• [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal },
• [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal },
• [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
• [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr },
• [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
• [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
• [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither },
• [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
• [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
• [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
• [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
• [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
• [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
• [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
• [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
• [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
• [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl },
• [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
• [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
• [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
• [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl },
• [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask },
• [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
• [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
• [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
• [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma },
• [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma },
• [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma },
• [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe },
• [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL },
• [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },

};

static bool mtk_drm_find_comp_in_ddp(struct device *dev, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index bb914d976cf5d..cd1dec6b4cdf2 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -30,6 +30,7 @@ enum mtk_ddp_comp_type { MTK_DISP_UFOE, MTK_DSI, MTK_DPI,

• MTK_DISP_POSTMASK, MTK_DISP_PWM, MTK_DISP_MUTEX, MTK_DISP_OD,

Hi, Hsin-Yi:

Hsin-Yi Wang hsinyi@chromium.org 於 2021年2月2日 週二 下午4:13寫道：

From: Yongqiang Niu yongqiang.niu@mediatek.com

ccorr ctm matrix bits will be different in mt8192

Applied to mediatek-drm-next [1], thanks.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?...

Regards, Chun-Kuang.

Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org Reviewed-by: CK Hu ck.hu@mediatek.com

---

drivers/gpu/drm/mediatek/Makefile | 3 +- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 216 ++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_disp_drv.h | 9 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 95 +-------- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 +- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + 6 files changed, 236 insertions(+), 96 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c

diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index b64674b944860..dc54a7a690054 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0

-mediatek-drm-y := mtk_disp_color.o \ +mediatek-drm-y := mtk_disp_ccorr.o \

•             mtk_disp_color.o \
              mtk_disp_gamma.o \
              mtk_disp_ovl.o \
              mtk_disp_rdma.o \
  

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c new file mode 100644 index 0000000000000..6ee2431e6b843 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0-only +/*

• • Copyright (c) 2021 MediaTek Inc.
• */

+#include <linux/clk.h> +#include <linux/component.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-cmdq.h>

+#include "mtk_disp_drv.h" +#include "mtk_drm_crtc.h" +#include "mtk_drm_ddp_comp.h"

+#define DISP_CCORR_EN 0x0000 +#define CCORR_EN BIT(0) +#define DISP_CCORR_CFG 0x0020 +#define CCORR_RELAY_MODE BIT(0) +#define CCORR_ENGINE_EN BIT(1) +#define CCORR_GAMMA_OFF BIT(2) +#define CCORR_WGAMUT_SRC_CLIP BIT(3) +#define DISP_CCORR_SIZE 0x0030 +#define DISP_CCORR_COEF_0 0x0080 +#define DISP_CCORR_COEF_1 0x0084 +#define DISP_CCORR_COEF_2 0x0088 +#define DISP_CCORR_COEF_3 0x008C +#define DISP_CCORR_COEF_4 0x0090

+struct mtk_disp_ccorr_data {

•   u32 reserved;
  

+};

+/**

• • struct mtk_disp_ccorr - DISP_CCORR driver structure
• • @ddp_comp - structure containing type enum and hardware resources
• • @crtc - associated crtc to report irq events to
• */

+struct mtk_disp_ccorr {

•   struct clk *clk;
  

•   void __iomem *regs;
  

•   struct cmdq_client_reg cmdq_reg;
  

•   const struct mtk_disp_ccorr_data        *data;
  

+};

+int mtk_ccorr_clk_enable(struct device *dev) +{

•   struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
  

•   return clk_prepare_enable(ccorr->clk);
  

+}

+void mtk_ccorr_clk_disable(struct device *dev) +{

•   struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
  

•   clk_disable_unprepare(ccorr->clk);
  

+}

+void mtk_ccorr_config(struct device *dev, unsigned int w,

•                        unsigned int h, unsigned int vrefresh,
  

•                        unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
  

+{

•   struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
  

•   mtk_ddp_write(cmdq_pkt, h << 16 | w, &ccorr->cmdq_reg, ccorr->regs,
  

•                 DISP_CCORR_SIZE);
  

•   mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs,
  

•                 DISP_CCORR_CFG);
  

+}

+void mtk_ccorr_start(struct device *dev) +{

•   struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
  

•   writel(CCORR_EN, ccorr->regs + DISP_CCORR_EN);
  

+}

+void mtk_ccorr_stop(struct device *dev) +{

•   struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
  

•   writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN);
  

+}

+/* Converts a DRM S31.32 value to the HW S1.10 format. */ +static u16 mtk_ctm_s31_32_to_s1_10(u64 in) +{

•   u16 r;
  

•   /* Sign bit. */
  

•   r = in & BIT_ULL(63) ? BIT(11) : 0;
  

•   if ((in & GENMASK_ULL(62, 33)) > 0) {
  

•           /* identity value 0x100000000 -> 0x400, */
  

•           /* if bigger this, set it to max 0x7ff. */
  

•           r |= GENMASK(10, 0);
  

•   } else {
  

•           /* take the 11 most important bits. */
  

•           r |= (in >> 22) & GENMASK(10, 0);
  

•   }
  

•   return r;
  

+}

+void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) +{

•   struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
  

•   struct drm_property_blob *blob = state->ctm;
  

•   struct drm_color_ctm *ctm;
  

•   const u64 *input;
  

•   uint16_t coeffs[9] = { 0 };
  

•   int i;
  

•   struct cmdq_pkt *cmdq_pkt = NULL;
  

•   if (!blob)
  

•           return;
  

•   ctm = (struct drm_color_ctm *)blob->data;
  

•   input = ctm->matrix;
  

•   for (i = 0; i < ARRAY_SIZE(coeffs); i++)
  

•           coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
  

•   mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
  

•                 &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0);
  

•   mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3],
  

•                 &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_1);
  

•   mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5],
  

•                 &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_2);
  

•   mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7],
  

•                 &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_3);
  

•   mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
  

•                 &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_4);
  

+}

+static int mtk_disp_ccorr_bind(struct device *dev, struct device *master,

•                          void *data)
  

+{

•   return 0;
  

+}

+static void mtk_disp_ccorr_unbind(struct device *dev, struct device *master,

•                             void *data)
  

+{ +}

+static const struct component_ops mtk_disp_ccorr_component_ops = {

•   .bind   = mtk_disp_ccorr_bind,
  

•   .unbind = mtk_disp_ccorr_unbind,
  

+};

+static int mtk_disp_ccorr_probe(struct platform_device *pdev) +{

•   struct device *dev = &pdev->dev;
  

•   struct mtk_disp_ccorr *priv;
  

•   struct resource *res;
  

•   int ret;
  

•   priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  

•   if (!priv)
  

•           return -ENOMEM;
  

•   priv->clk = devm_clk_get(dev, NULL);
  

•   if (IS_ERR(priv->clk)) {
  

•           dev_err(dev, "failed to get ccorr clk\n");
  

•           return PTR_ERR(priv->clk);
  

•   }
  

•   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  

•   priv->regs = devm_ioremap_resource(dev, res);
  

•   if (IS_ERR(priv->regs)) {
  

•           dev_err(dev, "failed to ioremap ccorr\n");
  

•           return PTR_ERR(priv->regs);
  

•   }
  

+#if IS_REACHABLE(CONFIG_MTK_CMDQ)

•   ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
  

•   if (ret)
  

•           dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
  

+#endif

•   priv->data = of_device_get_match_data(dev);
  

•   platform_set_drvdata(pdev, priv);
  

•   ret = component_add(dev, &mtk_disp_ccorr_component_ops);
  

•   if (ret)
  

•           dev_err(dev, "Failed to add component: %d\n", ret);
  

•   return ret;
  

+}

+static int mtk_disp_ccorr_remove(struct platform_device *pdev) +{

•   component_del(&pdev->dev, &mtk_disp_ccorr_component_ops);
  

•   return 0;
  

+}

+static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = {

•   { .compatible = "mediatek,mt8183-disp-ccorr"},
  

•   {},
  

+}; +MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match);

+struct platform_driver mtk_disp_ccorr_driver = {

•   .probe          = mtk_disp_ccorr_probe,
  

•   .remove         = mtk_disp_ccorr_remove,
  

•   .driver         = {
  

•           .name   = "mediatek-disp-ccorr",
  

•           .owner  = THIS_MODULE,
  

•           .of_match_table = mtk_disp_ccorr_driver_dt_match,
  

•   },
  

+}; diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index cdb0383f99061..cafd9df2d63bb 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -9,6 +9,15 @@ #include <linux/soc/mediatek/mtk-cmdq.h> #include "mtk_drm_plane.h"

+void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state); +int mtk_ccorr_clk_enable(struct device *dev); +void mtk_ccorr_clk_disable(struct device *dev); +void mtk_ccorr_config(struct device *dev, unsigned int w,

•                 unsigned int h, unsigned int vrefresh,
  

•                 unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
  

+void mtk_ccorr_start(struct device *dev); +void mtk_ccorr_stop(struct device *dev);

void mtk_color_bypass_shadow(struct device *dev); int mtk_color_clk_enable(struct device *dev); void mtk_color_clk_disable(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 7f5614a6faab8..445ea805d43f3 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -35,20 +35,6 @@ #define DISP_AAL_EN 0x0000 #define DISP_AAL_SIZE 0x0030

-#define DISP_CCORR_EN 0x0000 -#define CCORR_EN BIT(0) -#define DISP_CCORR_CFG 0x0020 -#define CCORR_RELAY_MODE BIT(0) -#define CCORR_ENGINE_EN BIT(1) -#define CCORR_GAMMA_OFF BIT(2) -#define CCORR_WGAMUT_SRC_CLIP BIT(3) -#define DISP_CCORR_SIZE 0x0030 -#define DISP_CCORR_COEF_0 0x0080 -#define DISP_CCORR_COEF_1 0x0084 -#define DISP_CCORR_COEF_2 0x0088 -#define DISP_CCORR_COEF_3 0x008C -#define DISP_CCORR_COEF_4 0x0090

#define DISP_DITHER_EN 0x0000 #define DITHER_EN BIT(0) #define DISP_DITHER_CFG 0x0020 @@ -266,82 +252,6 @@ static void mtk_aal_stop(struct device *dev) writel_relaxed(0x0, priv->regs + DISP_AAL_EN); }

-static void mtk_ccorr_config(struct device *dev, unsigned int w,

•                        unsigned int h, unsigned int vrefresh,
  

•                        unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
  

-{

•   struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
  

•   mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_CCORR_SIZE);
  

•   mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &priv->cmdq_reg, priv->regs, DISP_CCORR_CFG);
  

-}

-static void mtk_ccorr_start(struct device *dev) -{

•   struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
  

•   writel(CCORR_EN, priv->regs + DISP_CCORR_EN);
  

-}

-static void mtk_ccorr_stop(struct device *dev) -{

•   struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
  

•   writel_relaxed(0x0, priv->regs + DISP_CCORR_EN);
  

-}

-/* Converts a DRM S31.32 value to the HW S1.10 format. */ -static u16 mtk_ctm_s31_32_to_s1_10(u64 in) -{

•   u16 r;
  

•   /* Sign bit. */
  

•   r = in & BIT_ULL(63) ? BIT(11) : 0;
  

•   if ((in & GENMASK_ULL(62, 33)) > 0) {
  

•           /* identity value 0x100000000 -> 0x400, */
  

•           /* if bigger this, set it to max 0x7ff. */
  

•           r |= GENMASK(10, 0);
  

•   } else {
  

•           /* take the 11 most important bits. */
  

•           r |= (in >> 22) & GENMASK(10, 0);
  

•   }
  

•   return r;
  

-}

-static void mtk_ccorr_ctm_set(struct device *dev,

•                         struct drm_crtc_state *state)
  

-{

•   struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
  

•   struct drm_property_blob *blob = state->ctm;
  

•   struct drm_color_ctm *ctm;
  

•   const u64 *input;
  

•   uint16_t coeffs[9] = { 0 };
  

•   int i;
  

•   struct cmdq_pkt *cmdq_pkt = NULL;
  

•   if (!blob)
  

•           return;
  

•   ctm = (struct drm_color_ctm *)blob->data;
  

•   input = ctm->matrix;
  

•   for (i = 0; i < ARRAY_SIZE(coeffs); i++)
  

•           coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
  

•   mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
  

•                 &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_0);
  

•   mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3],
  

•                 &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_1);
  

•   mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5],
  

•                 &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_2);
  

•   mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7],
  

•                 &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_3);
  

•   mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
  

•                 &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_4);
  

-}

static void mtk_dither_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) @@ -380,8 +290,8 @@ static const struct mtk_ddp_comp_funcs ddp_aal = { };

static const struct mtk_ddp_comp_funcs ddp_ccorr = {

•   .clk_enable = mtk_ddp_clk_enable,
  

•   .clk_disable = mtk_ddp_clk_disable,
  

•   .clk_enable = mtk_ccorr_clk_enable,
  

•   .clk_disable = mtk_ccorr_clk_disable,
    .config = mtk_ccorr_config,
    .start = mtk_ccorr_start,
    .stop = mtk_ccorr_stop,
  

@@ -642,6 +552,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, }

    if (type == MTK_DISP_BLS ||

•       type == MTK_DISP_CCORR ||
        type == MTK_DISP_COLOR ||
        type == MTK_DISP_GAMMA ||
        type == MTK_DPI ||
  

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 486e73e675ad5..b013d56d27773 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -531,11 +531,12 @@ static int mtk_drm_probe(struct platform_device *pdev) private->comp_node[comp_id] = of_node_get(node);

            /*

•            * Currently only the COLOR, GAMMA, OVL, RDMA, DSI, and DPI blocks have
  

•            * separate component platform drivers and initialize their own
  

•            * Currently only the CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI
  

•            * blocks have separate component platform drivers and initialize their own
             * DDP component structure. The others are initialized here.
             */
  

•           if (comp_type == MTK_DISP_COLOR ||
  

•           if (comp_type == MTK_DISP_CCORR ||
  

•               comp_type == MTK_DISP_COLOR ||
                comp_type == MTK_DISP_GAMMA ||
                comp_type == MTK_DISP_OVL ||
                comp_type == MTK_DISP_OVL_2L ||
  

@@ -634,6 +635,7 @@ static struct platform_driver mtk_drm_platform_driver = { };

static struct platform_driver * const mtk_drm_drivers[] = {

•   &mtk_disp_ccorr_driver,
    &mtk_disp_color_driver,
    &mtk_disp_gamma_driver,
    &mtk_disp_ovl_driver,
  

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index 0e54e3d51014a..637f5669e8954 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -46,6 +46,7 @@ struct mtk_drm_private { struct drm_atomic_state *suspend_state; };

+extern struct platform_driver mtk_disp_ccorr_driver; extern struct platform_driver mtk_disp_color_driver; extern struct platform_driver mtk_disp_gamma_driver; extern struct platform_driver mtk_disp_ovl_driver; -- 2.30.0.365.g02bc693789-goog

---

Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek

Hi, Hsin-Yi:

Hsin-Yi Wang hsinyi@chromium.org 於 2021年2月2日 週二 下午4:13寫道：

From: Yongqiang Niu yongqiang.niu@mediatek.com

Fix setting to follow hardware datasheet. The original error setting affects mt8192 display.

Applied to mediatek-drm-next [1], thanks.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?...

Regards, Chun-Kuang.

Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org Reviewed-by: CK Hu ck.hu@mediatek.com

---

drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c index 6ee2431e6b843..6c86673a835c3 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -65,7 +65,7 @@ void mtk_ccorr_config(struct device *dev, unsigned int w, { struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);

•   mtk_ddp_write(cmdq_pkt, h << 16 | w, &ccorr->cmdq_reg, ccorr->regs,
  

•   mtk_ddp_write(cmdq_pkt, w << 16 | h, &ccorr->cmdq_reg, ccorr->regs,
                  DISP_CCORR_SIZE);
    mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs,
                  DISP_CCORR_CFG);
  

-- 2.30.0.365.g02bc693789-goog

---

Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek

Hi, Hsin-Yi:

On Tue, 2021-02-02 at 16:12 +0800, Hsin-Yi Wang wrote:

From: Yongqiang Niu yongqiang.niu@mediatek.com

Add matrix_bits and coeffs_precision to ccorr private data:

• matrix bits of mt8183 is 10
• matrix bits of mt8192 is 11

Reviewed-by: CK Hu ck.hu@mediatek.com

Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org

---

drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 27 ++++++++++++++--------- 1 file changed, 17 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c index 6c86673a835c3..141cb36b9c07b 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -30,7 +30,7 @@ #define DISP_CCORR_COEF_4 0x0090

struct mtk_disp_ccorr_data {

• u32 reserved;

• u32 matrix_bits;

};

/** @@ -85,21 +85,22 @@ void mtk_ccorr_stop(struct device *dev) writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN); }

-/* Converts a DRM S31.32 value to the HW S1.10 format. */ -static u16 mtk_ctm_s31_32_to_s1_10(u64 in) +/* Converts a DRM S31.32 value to the HW S1.n format. */ +static u16 mtk_ctm_s31_32_to_s1_n(u64 in, u32 n) { u16 r;

/* Sign bit. */

• r = in & BIT_ULL(63) ? BIT(11) : 0;

• r = in & BIT_ULL(63) ? BIT(n + 1) : 0;

  if ((in & GENMASK_ULL(62, 33)) > 0) {

• /* identity value 0x100000000 -> 0x400, */
  

• /* identity value 0x100000000 -> 0x400(mt8183), */
  

• /* identity value 0x100000000 -> 0x800(mt8192), */
  

  /* if bigger this, set it to max 0x7ff. */

• r |= GENMASK(10, 0);
  

• r |= GENMASK(n, 0);
  

  } else {

• /* take the 11 most important bits. */
  

• r |= (in >> 22) & GENMASK(10, 0);
  

• /* take the n+1 most important bits. */
  

• r |= (in >> (32 - n)) & GENMASK(n, 0);
  

  }

  return r;

@@ -114,6 +115,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) uint16_t coeffs[9] = { 0 }; int i; struct cmdq_pkt *cmdq_pkt = NULL;

• u32 matrix_bits = ccorr->data->matrix_bits;

  if (!blob) return;

@@ -122,7 +124,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) input = ctm->matrix;

for (i = 0; i < ARRAY_SIZE(coeffs); i++)

• coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
  

• coeffs[i] = mtk_ctm_s31_32_to_s1_n(input[i], matrix_bits);
  
  

  mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0);

@@ -199,8 +201,13 @@ static int mtk_disp_ccorr_remove(struct platform_device *pdev) return 0; }

+static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = {

• .matrix_bits = 10,

+};

static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = {

• { .compatible = "mediatek,mt8183-disp-ccorr"},

• { .compatible = "mediatek,mt8183-disp-ccorr",

•  .data = &mt8183_ccorr_driver_data},
  

  {},

}; MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match);

Hi, Hsin-Yi:

On Tue, 2021-02-02 at 16:12 +0800, Hsin-Yi Wang wrote:

From: Yongqiang Niu yongqiang.niu@mediatek.com

add support for mediatek SOC MT8192

Reviewed-by: CK Hu ck.hu@mediatek.com

Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org

---

drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 6 ++++ drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 20 +++++++++++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 42 +++++++++++++++++++++++ 4 files changed, 74 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c index 141cb36b9c07b..3a53ebc4e1724 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -205,9 +205,15 @@ static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = { .matrix_bits = 10, };

+static const struct mtk_disp_ccorr_data mt8192_ccorr_driver_data = {

• .matrix_bits = 11,

+};

static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { { .compatible = "mediatek,mt8183-disp-ccorr", .data = &mt8183_ccorr_driver_data},

• { .compatible = "mediatek,mt8192-disp-ccorr",

•  .data = &mt8192_ccorr_driver_data},
  

  {},

}; MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 961f87f8d4d15..e266baae586c4 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -455,6 +455,22 @@ static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { .fmt_rgb565_is_0 = true, };

+static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = {

• .addr = DISP_REG_OVL_ADDR_MT8173,
• .gmc_bits = 10,
• .layer_nr = 4,
• .fmt_rgb565_is_0 = true,
• .smi_id_en = true,

+};

+static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = {

• .addr = DISP_REG_OVL_ADDR_MT8173,
• .gmc_bits = 10,
• .layer_nr = 2,
• .fmt_rgb565_is_0 = true,
• .smi_id_en = true,

+};

static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-ovl", .data = &mt2701_ovl_driver_data}, @@ -464,6 +480,10 @@ static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { .data = &mt8183_ovl_driver_data}, { .compatible = "mediatek,mt8183-disp-ovl-2l", .data = &mt8183_ovl_2l_driver_data},

• { .compatible = "mediatek,mt8192-disp-ovl",

•  .data = &mt8192_ovl_driver_data},
  

• { .compatible = "mediatek,mt8192-disp-ovl-2l",

•  .data = &mt8192_ovl_2l_driver_data},
  

  {},

}; MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 728aaadfea8cf..f123fc00a3935 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -355,6 +355,10 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { .fifo_size = 5 * SZ_1K, };

+static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = {

• .fifo_size = 5 * SZ_1K,

+};

static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-rdma", .data = &mt2701_rdma_driver_data}, @@ -362,6 +366,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { .data = &mt8173_rdma_driver_data}, { .compatible = "mediatek,mt8183-disp-rdma", .data = &mt8183_rdma_driver_data},

• { .compatible = "mediatek,mt8192-disp-rdma",

•  .data = &mt8192_rdma_driver_data},
  

  {},

}; MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index b013d56d27773..6df551055630c 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -147,6 +147,25 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { DDP_COMPONENT_DPI0, };

+static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = {

• DDP_COMPONENT_OVL0,
• DDP_COMPONENT_OVL_2L0,
• DDP_COMPONENT_RDMA0,
• DDP_COMPONENT_COLOR0,
• DDP_COMPONENT_CCORR,
• DDP_COMPONENT_AAL0,
• DDP_COMPONENT_GAMMA,
• DDP_COMPONENT_POSTMASK0,
• DDP_COMPONENT_DITHER,
• DDP_COMPONENT_DSI0,

+};

+static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = {

• DDP_COMPONENT_OVL_2L2,
• DDP_COMPONENT_RDMA4,
• DDP_COMPONENT_DPI0,

+};

static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .main_path = mt2701_mtk_ddp_main, .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), @@ -186,6 +205,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), };

+static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {

• .main_path = mt8192_mtk_ddp_main,
• .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
• .ext_path = mt8192_mtk_ddp_ext,
• .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),

+};

static int mtk_drm_kms_init(struct drm_device *drm) { struct mtk_drm_private *private = drm->dev_private; @@ -404,22 +430,32 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_OVL }, { .compatible = "mediatek,mt8183-disp-ovl-2l", .data = (void *)MTK_DISP_OVL_2L },

• { .compatible = "mediatek,mt8192-disp-ovl",

•  .data = (void *)MTK_DISP_OVL },
  

• { .compatible = "mediatek,mt8192-disp-ovl-2l",

•  .data = (void *)MTK_DISP_OVL_2L },
  

  { .compatible = "mediatek,mt2701-disp-rdma", .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-rdma", .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8183-disp-rdma", .data = (void *)MTK_DISP_RDMA },
• { .compatible = "mediatek,mt8192-disp-rdma",

•  .data = (void *)MTK_DISP_RDMA },
  

  { .compatible = "mediatek,mt8173-disp-wdma", .data = (void *)MTK_DISP_WDMA }, { .compatible = "mediatek,mt8183-disp-ccorr", .data = (void *)MTK_DISP_CCORR },
• { .compatible = "mediatek,mt8192-disp-ccorr",

•  .data = (void *)MTK_DISP_CCORR },
  

  { .compatible = "mediatek,mt2701-disp-color", .data = (void *)MTK_DISP_COLOR }, { .compatible = "mediatek,mt8173-disp-color", .data = (void *)MTK_DISP_COLOR }, { .compatible = "mediatek,mt8173-disp-aal", .data = (void *)MTK_DISP_AAL},
• { .compatible = "mediatek,mt8192-disp-aal",

•  .data = (void *)MTK_DISP_AAL},
  

  { .compatible = "mediatek,mt8173-disp-gamma", .data = (void *)MTK_DISP_GAMMA, }, { .compatible = "mediatek,mt8183-disp-gamma",

@@ -448,12 +484,16 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8183-disp-mutex", .data = (void *)MTK_DISP_MUTEX },

• { .compatible = "mediatek,mt8192-disp-mutex",

•  .data = (void *)MTK_DISP_MUTEX },
  

  { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_BLS }, { .compatible = "mediatek,mt8173-disp-pwm", .data = (void *)MTK_DISP_PWM }, { .compatible = "mediatek,mt8173-disp-od", .data = (void *)MTK_DISP_OD },
• { .compatible = "mediatek,mt8192-disp-postmask",

•  .data = (void *)MTK_DISP_POSTMASK },
  

  { }

};

@@ -468,6 +508,8 @@ static const struct of_device_id mtk_drm_of_ids[] = { .data = &mt8173_mmsys_driver_data}, { .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data},

• { .compatible = "mediatek,mt8192-mmsys",

• .data = &mt8192_mmsys_driver_data},
  

  { }

};