This reverts commit 5f2fd347eeff7d4ce271920efd47baaa18fe968c.

Re-enable enc2_dp_set_dsc_config. This function caused warnings due to missing register definitions. With the registers added, this now works

Signed-off-by: David Francis David.Francis@amd.com Reviewed-by: Roman Li Roman.Li@amd.com Reviewed-by: Harry Wentland harry.wentland@amd.com Reviewed-by: Nicholas Kazlauskas nicholas.kazlauskas@amd.com --- .../gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c | 8 -------- 1 file changed, 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c index 6d54942ab98b..a4e67286cdad 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c @@ -277,14 +277,6 @@ static void enc2_dp_set_dsc_config(struct stream_encoder *enc, uint32_t dsc_slice_width) { struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - uint32_t dsc_value = 0; - - dsc_value = REG_READ(DP_DSC_CNTL); - - /* dsc disable skip */ - if ((dsc_value & 0x3) == 0x0) - return; -

REG_UPDATE_2(DP_DSC_CNTL, DP_DSC_MODE, dsc_mode,

This reverts commit 80e80ec817f161560b4159608fb41bd289abede3.

This commit fixed an issue with underscan commits not updating all needed timing values, but through various refactors it is no longer necessary. It causes corruption on odm combine by overwriting the halved h_active in the stream timing

Signed-off-by: David Francis David.Francis@amd.com Reviewed-by: Roman Li Roman.Li@amd.com Reviewed-by: Harry Wentland harry.wentland@amd.com Reviewed-by: Nicholas Kazlauskas nicholas.kazlauskas@amd.com --- drivers/gpu/drm/amd/display/dc/core/dc.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 77ac7f707ec5..1189e320062b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2127,7 +2127,7 @@ void dc_commit_updates_for_stream(struct dc *dc, enum surface_update_type update_type; struct dc_state *context; struct dc_context *dc_ctx = dc->ctx; - int i, j; + int i;

stream_status = dc_stream_get_status(stream); context = dc->current_state; @@ -2165,16 +2165,6 @@ void dc_commit_updates_for_stream(struct dc *dc,

copy_surface_update_to_plane(surface, &srf_updates[i]);

- if (update_type >= UPDATE_TYPE_MED) { - for (j = 0; j < dc->res_pool->pipe_count; j++) { - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - - if (pipe_ctx->plane_state != surface) - continue; - - resource_build_scaling_params(pipe_ctx); - } - } }

copy_stream_update_to_stream(dc, context, stream, stream_update);

We were using drm helpers to convert a timing into its bandwidth, its bandwidth into pbn, and its pbn into timeslots

These helpers -Did not take DSC timings into account -Used the link rate and lane count of the link's aux device, which are not the same as the link's current cap -Did not take FEC into account (FEC reduces the PBN per timeslot)

For converting timing into PBN, add a new function drm_dp_calc_pbn_mode_dsc that handles the DSC case

For converting PBN into time slots, amdgpu doesn't use the 'correct' atomic method (drm_dp_atomic_find_vcpi_slots), so don't add a new helper to cover our approach. Use the same means of calculating pbn per time slot as the DSC code.

v2: Add drm helper for clock to pbn conversion

Cc: Jerry Zuo Jerry.Zuo@amd.com Cc: Nicholas Kazlauskas nicholas.kazlauskas@amd.com Signed-off-by: David Francis David.Francis@amd.com --- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 18 +++++--- drivers/gpu/drm/drm_dp_mst_topology.c | 41 +++++++++++++++++++ include/drm/drm_dp_mst_helper.h | 2 +- 3 files changed, 54 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 5f2c315b18ba..dfa99e0d6e64 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -189,8 +189,8 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( int slots = 0; bool ret; int clock; - int bpp = 0; int pbn = 0; + int pbn_per_timeslot, bpp = 0;

aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;

@@ -208,7 +208,6 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( clock = stream->timing.pix_clk_100hz / 10;

switch (stream->timing.display_color_depth) { - case COLOR_DEPTH_666: bpp = 6; break; @@ -234,11 +233,18 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(

bpp = bpp * 3;

- /* TODO need to know link rate */ - - pbn = drm_dp_calc_pbn_mode(clock, bpp); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + if (stream->timing.flags.DSC) + pbn = drm_dp_calc_pbn_mode_dsc(clock, + stream->timing.dsc_cfg.bits_per_pixel); + else +#endif + pbn = drm_dp_calc_pbn_mode(clock, bpp);

- slots = drm_dp_find_vcpi_slots(mst_mgr, pbn); + /* Convert kilobits per second / 64 (for 64 timeslots) to pbn (54/64 megabytes per second) */ + pbn_per_timeslot = dc_link_bandwidth_kbps( + stream->link, dc_link_get_link_cap(stream->link)) / (8 * 1000 * 54); + slots = DIV_ROUND_UP(pbn, pbn_per_timeslot); ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, slots);

if (!ret) diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index 398e7314ea8b..d789b7af7dbf 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -3588,6 +3588,47 @@ static int test_calc_pbn_mode(void) return 0; }

+/** + * drm_dp_calc_pbn_mode_dsc() - Calculate the PBN for a mode with DSC enabled. + * @clock: dot clock for the mode + * @dsc_bpp: dsc bits per pixel x16 (e.g. dsc_bpp = 136 is 8.5 bpp) + * + * This uses the formula in the spec to calculate the PBN value for a mode, + * given that the mode is using DSC + */ +int drm_dp_calc_pbn_mode_dsc(int clock, int dsc_bpp) +{ + u64 kbps; + s64 peak_kbps; + u32 numerator; + u32 denominator; + + kbps = clock * dsc_bpp; + + /* + * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006 + * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on + * common multiplier to render an integer PBN for all link rate/lane + * counts combinations + * calculate + * peak_kbps *= (1/16) bppx16 to bpp + * peak_kbps *= (1006/1000) + * peak_kbps *= (64/54) + * peak_kbps *= 8 convert to bytes + * + * Divide numerator and denominator by 16 to avoid overflow + */ + + numerator = 64 * 1006 / 16; + denominator = 54 * 8 * 1000 * 1000; + + kbps *= numerator; + peak_kbps = drm_fixp_from_fraction(kbps, denominator); + + return drm_fixp2int_ceil(peak_kbps); +} +EXPORT_SYMBOL(drm_dp_calc_pbn_mode_dsc); + /* we want to kick the TX after we've ack the up/down IRQs. */ static void drm_dp_mst_kick_tx(struct drm_dp_mst_topology_mgr *mgr) { diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h index 2ba6253ea6d3..ddb518f2157a 100644 --- a/include/drm/drm_dp_mst_helper.h +++ b/include/drm/drm_dp_mst_helper.h @@ -611,7 +611,7 @@ struct edid *drm_dp_mst_get_edid(struct drm_connector *connector, struct drm_dp_

int drm_dp_calc_pbn_mode(int clock, int bpp); - +int drm_dp_calc_pbn_mode_dsc(int clock, int dsc_bpp);

bool drm_dp_mst_allocate_vcpi(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, int pbn, int slots);

For DSC MST, sometimes monitors would break out in full-screen static. The issue traced back to the PPS generation code, where these variables were being used uninitialized and were picking up garbage.

memset to 0 to avoid this

Signed-off-by: David Francis David.Francis@amd.com Reviewed-by: Nicholas Kazlauskas nicholas.kazlauskas@amd.com --- drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 3 +++ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 3 +++ 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c index 35c5467e60e8..619ac48edd05 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c @@ -491,6 +491,9 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable) struct dsc_config dsc_cfg; uint8_t dsc_packed_pps[128];

+ memset(&dsc_cfg, 0, sizeof(dsc_cfg)); + memset(dsc_packed_pps, 0, 128); + /* Enable DSC hw block */ dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c index 379c9e4ac63b..16debe6d89f2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c @@ -207,6 +207,9 @@ static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const str struct dsc_reg_values dsc_reg_vals; struct dsc_optc_config dsc_optc_cfg;

+ memset(&dsc_reg_vals, 0, sizeof(dsc_reg_vals)); + memset(&dsc_optc_cfg, 0, sizeof(dsc_optc_cfg)); + DC_LOG_DSC("Getting packed DSC PPS for DSC Config:"); dsc_config_log(dsc, dsc_cfg); DC_LOG_DSC("DSC Picture Parameter Set (PPS):");

This field on drm_dp_mst_branch was never filled

Initialize it to zero when the list of ports is created. When a port is added to the list, increment num_ports

Signed-off-by: David Francis David.Francis@amd.com --- drivers/gpu/drm/drm_dp_mst_topology.c | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index 5d5bd42da17c..0c580d5279c1 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -918,6 +918,7 @@ static struct drm_dp_mst_branch *drm_dp_add_mst_branch_device(u8 lct, u8 *rad) INIT_LIST_HEAD(&mstb->ports); kref_init(&mstb->topology_kref); kref_init(&mstb->malloc_kref); + mstb->num_ports = 0; return mstb; }

@@ -1672,6 +1673,7 @@ static void drm_dp_add_port(struct drm_dp_mst_branch *mstb, mutex_lock(&mstb->mgr->lock); drm_dp_mst_topology_get_port(port); list_add(&port->next, &mstb->ports); + mstb->num_ports++; mutex_unlock(&mstb->mgr->lock); }

The first step in MST DSC is checking MST endpoints to see how DSC can be enabled

Case 1: DP-to-DP peer device if the branch immediately upstream has - PDT = DP_PEER_DEVICE_DP_MST_BRANCHING (2) - DPCD rev. >= DP 1.4 - Exactly one input and one output - The output has PDT = DP_PEER_DEVICE_SST_SINK (3)

In this case, DSC could be possible either on the endpoint or the peer device. Prefer the endpoint, which is possible if - The endpoint has DP_DSC_DECOMPRESSION_IS_SUPPORTED bit set - The endpoint has DP_FEC_CAPABLE bit set - The peer device has DSC_PASSTHROUGH_CAPABILITY bit set (from DP v2.0)

Otherwise, use the peer device

Case 2: DP-to-HDMI peer device If the output port has - PDT = DP_PEER_DEVICE_DP_LEGACY_CONV (4) - DPCD rev. >= DP 1.4 - LDPS = true - MCS = false

In this case, DSC can only be attempted on the peer device (the output port)

Case 3: Virtual DP Sink (Internal Display Panel) If the output port has - DPCD rev. >= DP 1.4 - port_num >= 8

In this case, DSC can only be attempted on the peer device (the output port)

Case 4: Synaptix Workaround If the output has - link DPCD rev. >= DP 1.4 - link branch_dev_id = 0x90CC24 (Synaptix) - There is exactly one branch device between the link and output

In this case, DSC can be attempted, but only using the *link* aux device's caps. This is a quirk.

Test for these cases as modes are enumerated for an MST endpoint. We cannot do this during link attach because the dc_sink object will not have been created yet

If no DSC is attempted, zero the DSC caps

Cc: Wenjing Liu Wenjing.Liu@amd.com Cc: Nikola Cornij Nikola.Cornij@amd.com Signed-off-by: David Francis David.Francis@amd.com --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 123 +++++++++++++++++- .../display/amdgpu_dm/amdgpu_dm_mst_types.h | 3 + 2 files changed, 125 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 16218a202b59..58571844f6d5 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -25,6 +25,7 @@

#include <linux/version.h> #include <drm/drm_atomic_helper.h> +#include <drm/drm_dp_mst_helper.h> #include "dm_services.h" #include "amdgpu.h" #include "amdgpu_dm.h" @@ -189,6 +190,120 @@ static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { .early_unregister = amdgpu_dm_mst_connector_early_unregister, };

+bool is_virtual_dpcd(struct drm_dp_mst_port *port) +{ + struct drm_dp_mst_port *downstream_port; + + if (!port) + return false; + + if (port->port_num >= 8 && + port->dpcd_rev >= DP_DPCD_REV_14) { + /* Virtual DP Sink (Internal Display Panel) */ + return true; + } else if (port->pdt == DP_PEER_DEVICE_DP_LEGACY_CONV && + !port->mcs && + port->ldps && + port->dpcd_rev >= DP_DPCD_REV_14) { + /* DP-to-HDMI Protocol Converter */ + return true; + } else if (port->pdt == DP_PEER_DEVICE_MST_BRANCHING && + port->mstb && + port->dpcd_rev >= DP_DPCD_REV_14) { + /* DP-to-DP */ + if (port->mstb->num_ports == 2) { + list_for_each_entry(downstream_port, &port->mstb->ports, next) { + if (!downstream_port->input && + downstream_port->pdt == DP_PEER_DEVICE_SST_SINK) + return true; + } + } + } + return false; +} + +bool synaptix_workaround(struct amdgpu_dm_connector *aconnector) +{ + struct drm_dp_mst_port *port = aconnector->port; + struct dc_link *link = aconnector->dc_sink->link; + u8 down_stream_port_data; + + if (port->mgr->mst_primary == port->parent && + link->dpcd_caps.branch_dev_id == 0x90CC24 && + link->dpcd_caps.dpcd_rev.raw >= DP_DPCD_REV_14) { + drm_dp_mst_dpcd_read(&port->aux, DP_DOWNSTREAMPORT_PRESENT, &down_stream_port_data, 1); + if ((down_stream_port_data & 7) != 3) + return true; + } + return false; +} + +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector) +{ + u8 upstream_dsc_caps[16] = { 0 }; + u8 endpoint_dsc_caps[16] = { 0 }; + u8 endpoint_fec_caps = 0; + struct dc_sink *dc_sink = aconnector->dc_sink; + struct drm_dp_mst_port *output_port = aconnector->port; + struct drm_dp_mst_port *immediate_upstream_port; + struct drm_dp_mst_port *fec_port; + + if (aconnector->port && aconnector->port->parent) + immediate_upstream_port = aconnector->port->parent->port_parent; + else + immediate_upstream_port = NULL; + + fec_port = immediate_upstream_port; + while (fec_port) { + if (!fec_port->fec_capable) + return false; + + fec_port = fec_port->parent->port_parent; + } + + if (immediate_upstream_port) + drm_dp_mst_dpcd_read(&immediate_upstream_port->aux, DP_DSC_SUPPORT, upstream_dsc_caps, 16); + drm_dp_mst_dpcd_read(&output_port->aux, DP_DSC_SUPPORT, endpoint_dsc_caps, 16); + drm_dp_mst_dpcd_read(&output_port->aux, DP_FEC_CAPABILITY, &endpoint_fec_caps, 1); + + if (is_virtual_dpcd(immediate_upstream_port) + && (upstream_dsc_caps[0] & 0x2) /* DSC passthrough capability */ + && (endpoint_fec_caps & DP_FEC_CAPABLE) + && (endpoint_dsc_caps[0] & DP_DSC_DECOMPRESSION_IS_SUPPORTED)) { + /* Enpoint decompression with DP-to-DP peer device */ + if (!dc_dsc_parse_dsc_dpcd(endpoint_dsc_caps, NULL, &dc_sink->sink_dsc_caps.dsc_dec_caps)) + return false; + + dc_sink->sink_dsc_caps.is_virtual_dpcd_dsc = false; + } else if (is_virtual_dpcd(immediate_upstream_port)) { + /* Virtual DPCD decompression with DP-to-DP peer device */ + if (!dc_dsc_parse_dsc_dpcd(upstream_dsc_caps, NULL, &dc_sink->sink_dsc_caps.dsc_dec_caps)) + return false; + + dc_sink->sink_dsc_caps.is_virtual_dpcd_dsc = true; + } else if (is_virtual_dpcd(output_port)) { + /* Virtual DPCD decompression with DP-to-HDMI or Virtual DP Sink */ + if (!dc_dsc_parse_dsc_dpcd(endpoint_dsc_caps, NULL, &dc_sink->sink_dsc_caps.dsc_dec_caps)) + return false; + + dc_sink->sink_dsc_caps.is_virtual_dpcd_dsc = true; + } else if (synaptix_workaround(aconnector)) { + /* Synaptix workaround */ + aconnector = dc_sink->link->priv; + drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, DP_DSC_SUPPORT, upstream_dsc_caps, 16); + if (!dc_dsc_parse_dsc_dpcd(upstream_dsc_caps, NULL, &dc_sink->sink_dsc_caps.dsc_dec_caps)) + return false; + + dc_sink->sink_dsc_caps.is_virtual_dpcd_dsc = true; + } else { + return false; + } + + return true; +} +#endif + static int dm_dp_mst_get_modes(struct drm_connector *connector) { struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); @@ -231,10 +346,16 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) /* dc_link_add_remote_sink returns a new reference */ aconnector->dc_sink = dc_sink;

- if (aconnector->dc_sink) + if (aconnector->dc_sink) { amdgpu_dm_update_freesync_caps( connector, aconnector->edid);

+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + if (!validate_dsc_caps_on_connector(aconnector)) + memset(&aconnector->dc_sink->sink_dsc_caps, + 0, sizeof(aconnector->dc_sink->sink_dsc_caps)); +#endif + } }

drm_connector_update_edid_property( diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h index 2da851b40042..8de3d8c30f8d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h @@ -32,4 +32,7 @@ struct amdgpu_dm_connector; void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, struct amdgpu_dm_connector *aconnector);

+bool is_virtual_dpcd(struct drm_dp_mst_port *port); +bool synaptix_workaround(struct amdgpu_dm_connector *aconnector); + #endif

If there is limited link bandwidth on a MST network, it must be divided fairly between the streams on that network

Implement an algorithm to determine the correct DSC config for each stream

The algorithm: This [ ] ( ) represents the range of bandwidths possible for a given stream. The [] area represents the range of DSC configs, and the () represents no DSC. The bandwidth used increases from left to right.

First, try disabling DSC on all streams [ ] (|) [ ] (|) Check this against the bandwidth limits of the link and each branch (including each endpoint). If it passes, the job is done

Second, try maximum DSC compression on all streams that support DSC [| ] ( ) [| ] ( ) If this does not pass, then enabling this combination of streams is impossible

Otherwise, divide the remaining bandwidth evenly amongst the streams [ | ] ( ) [ | ] ( )

If one or more of the streams reach minimum compression, evenly divide the reamining bandwidth amongst the remaining streams [ |] ( ) [ |] ( ) [ | ] ( ) [ | ] ( )

If all streams can reach minimum compression, disable compression greedily [ |] ( ) [ |] ( ) [ ] (|)

Perform this algorithm on each full update, on each MST link with at least one DSC stream on it

After the configs are computed, call dcn20_add_dsc_to_stream_resource on each stream with DSC enabled. It is only after all streams are created that we can know which of them will need DSC.

Do all of this at the end of amdgpu atomic check. If it fails, fail check; This combination of timings cannot be supported.

Cc: Wenjing Liu Wenjing.Liu@amd.com Cc: Nikola Cornij Nikola.Cornij@amd.com Signed-off-by: David Francis David.Francis@amd.com --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 + .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 375 ++++++++++++++++++ .../display/amdgpu_dm/amdgpu_dm_mst_types.h | 4 +- .../drm/amd/display/dc/dcn20/dcn20_resource.c | 7 +- .../drm/amd/display/dc/dcn20/dcn20_resource.h | 1 + 5 files changed, 388 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 84249057e181..145fd73025dc 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7331,6 +7331,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, if (ret) goto fail;

+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + if (!compute_mst_dsc_configs_for_state(dm_state->context)) + goto fail; +#endif if (dc_validate_global_state(dc, dm_state->context, false) != DC_OK) { ret = -EINVAL; goto fail; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 58571844f6d5..0b6bfa093e83 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -38,6 +38,8 @@

#include "i2caux_interface.h"

+#include "dc/dcn20/dcn20_resource.h" + /* #define TRACE_DPCD */

#ifdef TRACE_DPCD @@ -548,3 +550,376 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, aconnector->connector_id); }

+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +struct dsc_mst_fairness_params { + struct dc_crtc_timing *timing; + struct dc_sink *sink; + struct dc_dsc_bw_range bw_range; + bool compression_possible; + struct drm_dp_mst_port *port; +}; + +struct dsc_mst_fairness_vars { + int pbn; + bool dsc_enabled; + int bpp_x16; +}; + +static bool port_downstream_of_branch(struct drm_dp_mst_port *port, + struct drm_dp_mst_branch *branch) +{ + while (port->parent) { + if (port->parent == branch) + return true; + + if (port->parent->port_parent) + port = port->parent->port_parent; + else + break; + } + return false; +} + +static bool check_pbn_limit_on_branch(struct drm_dp_mst_branch *branch, + struct dsc_mst_fairness_params *params, + struct dsc_mst_fairness_vars *vars, int count) +{ + struct drm_dp_mst_port *port; + int i; + int pbn_limit = 0; + int pbn_used = 0; + + list_for_each_entry(port, &branch->ports, next) { + if (port->mstb) + if (!check_pbn_limit_on_branch(port->mstb, params, vars, count)) + return false; + + if (port->available_pbn > 0) + pbn_limit = port->available_pbn; + } + + for (i = 0; i < count; i++) { + if (port_downstream_of_branch(params[i].port, branch)) + pbn_used += vars[i].pbn; + } + + if (pbn_used > pbn_limit) + return false; + + return true; +} + +static bool check_bandwidth_limits(struct dc_link *dc_link, + struct dsc_mst_fairness_params *params, + struct dsc_mst_fairness_vars *vars, + int count) +{ + int link_timeslot_limit = 63; + int link_timeslots_used = 0; + int pbn_per_timeslot; + int i; + struct drm_dp_mst_topology_mgr *mst_mgr; + + /* kbits to pbn, dividing by 64 */ + pbn_per_timeslot = dc_link_bandwidth_kbps(dc_link, + dc_link_get_link_cap(dc_link)) / (8 * 1000 * 54); + + /* Check link bandwidth limit */ + for (i = 0; i < count; i++) + link_timeslots_used += DIV_ROUND_UP(vars[i].pbn, pbn_per_timeslot); + + if (link_timeslots_used > link_timeslot_limit) + return false; + + /* Check branch bandwidth limit for each port on each branch */ + mst_mgr = params[0].port->mgr; + if (!check_pbn_limit_on_branch(mst_mgr->mst_primary, params, vars, count)) + return false; + + return true; +} + +static int kbps_to_peak_pbn(int kbps) +{ + u64 peak_kbps = kbps; + + peak_kbps *= 1006; + peak_kbps /= 1000; + return (int) DIV_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000)); +} + +static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params, + struct dsc_mst_fairness_vars *vars, + int count) +{ + int i; + + for (i = 0; i < count; i++) { + memset(&params[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg)); + if (vars[i].dsc_enabled && dc_dsc_compute_config(params[i].sink->ctx->dc, + &params[i].sink->sink_dsc_caps.dsc_dec_caps, + 0, + params[i].timing, + &params[i].timing->dsc_cfg)) { + params[i].timing->flags.DSC = 1; + params[i].timing->dsc_cfg.bits_per_pixel = vars[i].bpp_x16; + } else { + params[i].timing->flags.DSC = 0; + } + + } + +} + +static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn) +{ + struct dc_dsc_config dsc_config; + u64 kbps; + + kbps = (u64)pbn * 994 * 8 * 54 / 64; + dc_dsc_compute_config(param.sink->ctx->dc, + &param.sink->sink_dsc_caps.dsc_dec_caps, + (int) kbps, param.timing, &dsc_config); + + return dsc_config.bits_per_pixel; +} + +static void increase_dsc_bpp(struct dc_link *dc_link, + struct dsc_mst_fairness_params *params, + struct dsc_mst_fairness_vars *vars, + int count) +{ + int i; + bool bpp_increased[MAX_PIPES]; + int initial_slack[MAX_PIPES]; + int min_initial_slack; + int next_index; + int remaining_to_increase = 0; + int pbn_per_timeslot; + int link_timeslots_used; + int fair_pbn_alloc; + + for (i = 0; i < count; i++) { + if (vars[i].dsc_enabled) { + initial_slack[i] = kbps_to_peak_pbn(params[i].bw_range.max_kbps) - vars[i].pbn; + bpp_increased[i] = false; + remaining_to_increase += 1; + } else { + initial_slack[i] = 0; + bpp_increased[i] = true; + } + } + + pbn_per_timeslot = dc_link_bandwidth_kbps(dc_link, + dc_link_get_link_cap(dc_link)) / (8 * 1000 * 54); + + while (remaining_to_increase) { + next_index = -1; + min_initial_slack = -1; + for (i = 0; i < count; i++) { + if (!bpp_increased[i]) { + if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) { + min_initial_slack = initial_slack[i]; + next_index = i; + } + } + } + + if (next_index == -1) + break; + + link_timeslots_used = 0; + + for (i = 0; i < count; i++) + link_timeslots_used += DIV_ROUND_UP(vars[i].pbn, pbn_per_timeslot); + + fair_pbn_alloc = (63 - link_timeslots_used) / remaining_to_increase * pbn_per_timeslot; + + if (initial_slack[next_index] > fair_pbn_alloc) { + vars[next_index].pbn += fair_pbn_alloc; + if (check_bandwidth_limits(dc_link, params, vars, count)) + vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn); + else + vars[next_index].pbn -= fair_pbn_alloc; + } else { + vars[next_index].pbn += initial_slack[next_index]; + if (check_bandwidth_limits(dc_link, params, vars, count)) + vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16; + else + vars[next_index].pbn -= initial_slack[next_index]; + } + + bpp_increased[next_index] = true; + remaining_to_increase--; + } +} + +static void try_disable_dsc(struct dc_link *dc_link, + struct dsc_mst_fairness_params *params, + struct dsc_mst_fairness_vars *vars, + int count) +{ + int i; + bool tried[MAX_PIPES]; + int kbps_increase[MAX_PIPES]; + int max_kbps_increase; + int next_index; + int remaining_to_try = 0; + + for (i = 0; i < count; i++) { + if (vars[i].dsc_enabled && vars[i].bpp_x16 == params[i].bw_range.max_target_bpp_x16) { + kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps; + tried[i] = false; + remaining_to_try += 1; + } else { + kbps_increase[i] = 0; + tried[i] = true; + } + } + + while (remaining_to_try) { + next_index = -1; + max_kbps_increase = -1; + for (i = 0; i < count; i++) { + if (!tried[i]) { + if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) { + max_kbps_increase = kbps_increase[i]; + next_index = i; + } + } + } + + if (next_index == -1) + break; + + vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps); + + if (check_bandwidth_limits(dc_link, params, vars, count)) { + vars[next_index].dsc_enabled = false; + vars[next_index].bpp_x16 = 0; + } else { + vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps); + } + + tried[next_index] = true; + remaining_to_try--; + } +} + +static bool compute_mst_dsc_configs_for_link(struct dc_state *dc_state, struct dc_link *dc_link) +{ + int i; + struct dc_stream_state *stream; + struct dsc_mst_fairness_params params[MAX_PIPES]; + struct dsc_mst_fairness_vars vars[MAX_PIPES]; + struct amdgpu_dm_connector *aconnector; + int count = 0; + + memset(params, 0, sizeof(params)); + + /* Set up params */ + for (i = 0; i < dc_state->stream_count; i++) { + stream = dc_state->streams[i]; + + if (stream->link != dc_link) + continue; + + stream->timing.flags.DSC = 0; + + params[count].timing = &stream->timing; + params[count].sink = stream->sink; + aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; + params[count].port = aconnector->port; + params[count].compression_possible = stream->sink->sink_dsc_caps.dsc_dec_caps.is_dsc_supported; + if (!dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc, 8, 16, + &stream->sink->sink_dsc_caps.dsc_dec_caps, + &stream->timing, &params[count].bw_range)) + params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing); + + count++; + } + + /* Try no compression */ + for (i = 0; i < count; i++) { + vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps); + vars[i].dsc_enabled = false; + vars[i].bpp_x16 = 0; + } + + if (check_bandwidth_limits(dc_link, params, vars, count)) { + set_dsc_configs_from_fairness_vars(params, vars, count); + return true; + } + + /* Try max compression */ + for (i = 0; i < count; i++) { + if (params[i].compression_possible) { + vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps); + vars[i].dsc_enabled = true; + vars[i].bpp_x16 = params[i].bw_range.min_target_bpp_x16; + } else { + vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps); + vars[i].dsc_enabled = false; + vars[i].bpp_x16 = 0; + } + } + + if (!check_bandwidth_limits(dc_link, params, vars, count)) + return false; + + /* Optimize degree of compression */ + increase_dsc_bpp(dc_link, params, vars, count); + + try_disable_dsc(dc_link, params, vars, count); + + set_dsc_configs_from_fairness_vars(params, vars, count); + + return true; +} + +bool compute_mst_dsc_configs_for_state(struct dc_state *dc_state) +{ + int i, j; + struct dc_stream_state *stream; + bool computed_streams[MAX_PIPES]; + struct amdgpu_dm_connector *aconnector; + + for (i = 0; i < dc_state->stream_count; i++) + computed_streams[i] = false; + + for (i = 0; i < dc_state->stream_count; i++) { + stream = dc_state->streams[i]; + + if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) + continue; + + aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; + + if (!aconnector || !aconnector->dc_sink) + continue; + + if (!aconnector->dc_sink->sink_dsc_caps.dsc_dec_caps.is_dsc_supported) + continue; + + if (computed_streams[i]) + continue; + + if (!compute_mst_dsc_configs_for_link(dc_state, stream->link)) + return false; + + for (j = 0; j < dc_state->stream_count; j++) { + if (dc_state->streams[j]->link == stream->link) + computed_streams[j] = true; + } + } + + for (i = 0; i < dc_state->stream_count; i++) { + stream = dc_state->streams[i]; + + if (stream->timing.flags.DSC == 1) + dcn20_add_dsc_to_stream_resource(stream->ctx->dc, dc_state, stream); + } + + return true; +} +#endif diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h index 8de3d8c30f8d..b7d2e4e70185 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h @@ -34,5 +34,7 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,

bool is_virtual_dpcd(struct drm_dp_mst_port *port); bool synaptix_workaround(struct amdgpu_dm_connector *aconnector); - +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +bool compute_mst_dsc_configs_for_state(struct dc_state *dc_state); +#endif #endif diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c index c59f31dcdc0d..22511b047837 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c @@ -1439,7 +1439,7 @@ static void release_dsc(struct resource_context *res_ctx,

#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT -static enum dc_status add_dsc_to_stream_resource(struct dc *dc, +enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, struct dc_state *dc_ctx, struct dc_stream_state *dc_stream) { @@ -1454,6 +1454,9 @@ static enum dc_status add_dsc_to_stream_resource(struct dc *dc, if (pipe_ctx->stream != dc_stream) continue;

+ if (pipe_ctx->stream_res.dsc) + continue; + acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc);

/* The number of DSCs can be less than the number of pipes */ @@ -1511,7 +1514,7 @@ enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Get a DSC if required and available */ if (result == DC_OK && dc_stream->timing.flags.DSC) - result = add_dsc_to_stream_resource(dc, new_ctx, dc_stream); + result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream); #endif

if (result == DC_OK) diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h index 44f95aa0d61e..2209ebda6ef6 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h @@ -131,6 +131,7 @@ void dcn20_calculate_dlg_params(

enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream); enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream); +enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, struct dc_state *dc_ctx, struct dc_stream_state *dc_stream); enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream); enum dc_status dcn20_get_default_swizzle_mode(struct dc_plane_state *plane_state);