Panel Replay is a power saving feature for DP 2.0 monitor and similar to PSR on EDP.
These patches are basic enablement patches and reused psr framework to add panel replay related new changes which may need further fine tuning to fill the gap if there is any.
Note: The patches are not tested due to unavailability of monitor
Animesh Manna (5): drm/i915/panelreplay: dpcd register definition for panelreplay drm/i915/panelreplay: HAS_PR() macro added for panel replay drm/i915/panelreplay: Initializaton and compute config for panel replay drm/i915/panelreplay: enable/disable panel replay drm/i915/panelreplay: Added state checker for panel replay state
drivers/gpu/drm/i915/display/intel_display.c | 1 + .../drm/i915/display/intel_display_types.h | 2 + drivers/gpu/drm/i915/display/intel_dp.c | 43 ++++++++-- drivers/gpu/drm/i915/display/intel_psr.c | 84 ++++++++++++++++++- drivers/gpu/drm/i915/display/intel_psr.h | 3 + drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 1 + include/drm/drm_dp_helper.h | 6 ++ 8 files changed, 128 insertions(+), 13 deletions(-)
DPCD register definition added to check and enable panel replay capability of the sink.
Signed-off-by: Animesh Manna animesh.manna@intel.com --- include/drm/drm_dp_helper.h | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index b52df4db3e8f..8a2b929c3f88 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -541,6 +541,9 @@ struct drm_panel; /* DFP Capability Extension */ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+#define DP_PANEL_REPLAY_CAP 0x0b0 +# define PANEL_REPLAY_SUPPORT (1 << 0) + /* Link Configuration */ #define DP_LINK_BW_SET 0x100 # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ @@ -709,6 +712,9 @@ struct drm_panel; #define DP_BRANCH_DEVICE_CTRL 0x1a1 # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
+#define PANEL_REPLAY_CONFIG 0x1b0 +# define PANEL_REPLAY_ENABLE (1 << 0) + #define DP_PAYLOAD_ALLOCATE_SET 0x1c0 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
On Sun, 2021-10-10 at 17:40 +0530, Animesh Manna wrote:
Missing bit 1, that is very important when panel do not support selective update panel replay needs to act like PSR1 when it is sets it needs to act like PSR2.
All other bits are also important, for the errors ones we have PSR counter parts and your are missing the error status register.
Platforms having Display 13 and above will support panel replay feature of DP 2.0 monitor. Added a HAS_PR() macro to check for panel replay capability.
v1: Initial version. v2: DISPLAY_VER macro used instead of has_pr flag. [Jose] v3: HAS_PR renamed to HAS_PANEL_REPLAY. [Jani]
Signed-off-by: Animesh Manna animesh.manna@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 12256218634f..37313bf51a90 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1693,6 +1693,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi) #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg) #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) +#define HAS_PANEL_REPLAY(dev_priv) (DISPLAY_VER(dev_priv) >= 13) #define HAS_PSR_HW_TRACKING(dev_priv) \ (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking) #define HAS_PSR2_SEL_FETCH(dev_priv) (GRAPHICS_VER(dev_priv) >= 12)
As panel replay feature similar to PSR feature of EDP panel, so currently utilized existing psr framework for panel replay.
v1: RFC version. v2: optimized code, pr_enabled and pr_dpcd variable removed. [Jose] v3: - code comments improved. [Jani] - dpcd_readb used instead of dpcd_read. [Jani] - panel-repaplay init/compute functions moved inside respective psr function. [Jani]
Signed-off-by: Animesh Manna animesh.manna@intel.com --- .../drm/i915/display/intel_display_types.h | 2 + drivers/gpu/drm/i915/display/intel_dp.c | 43 +++++++++++++---- drivers/gpu/drm/i915/display/intel_psr.c | 48 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_psr.h | 3 ++ 4 files changed, 87 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 39e11eaec1a3..48f7d676ed2c 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1070,6 +1070,7 @@ struct intel_crtc_state { bool req_psr2_sdp_prior_scanline; u32 dc3co_exitline; u16 su_y_granularity; + bool has_panel_replay; struct drm_dp_vsc_sdp psr_vsc;
/* @@ -1531,6 +1532,7 @@ struct intel_psr { bool irq_aux_error; u16 su_w_granularity; u16 su_y_granularity; + bool sink_panel_replay_support; u32 dc3co_exitline; u32 dc3co_exit_delay; struct delayed_work dc3co_work; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 10fda20a5bd8..f58a7b72be14 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1587,12 +1587,22 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- /* - * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 - * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/ - * Colorimetry Format indication. - */ - vsc->revision = 0x5; + if (crtc_state->has_panel_replay) { + /* + * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223 + * VSC SDP supporting 3D stereo, Panel Replay, and Pixel + * Encoding/Colorimetry Format indication. + */ + vsc->revision = 0x7; + } else { + /* + * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 + * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/ + * Colorimetry Format indication. + */ + vsc->revision = 0x5; + } + vsc->length = 0x13;
/* DP 1.4a spec, Table 2-120 */ @@ -1701,6 +1711,21 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp, vsc->revision = 0x4; vsc->length = 0xe; } + } else if (intel_dp->psr.enabled && !intel_dp_is_edp(intel_dp)) { + if (intel_dp->psr.colorimetry_support && + intel_dp_needs_vsc_sdp(crtc_state, conn_state)) { + /* [Panel Replay with colorimetry info] */ + intel_dp_compute_vsc_colorimetry(crtc_state, conn_state, + vsc); + } else { + /* + * [Panel Replay without colorimetry info] + * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223 + * VSC SDP supporting 3D stereo + Panel Replay. + */ + vsc->revision = 0x6; + vsc->length = 0x10; + } } else { /* * [PSR1] @@ -2749,10 +2774,10 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
/* - * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as - * per DP 1.4a spec. + * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format as + * per DP 1.4a spec and DP 2.0 spec respectively. */ - if (vsc->revision != 0x5) + if (vsc->revision != 0x5 || vsc->revision != 0x7) goto out;
/* VSC SDP Payload for DB16 through DB18 */ diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 7a205fd5023b..91c2efe2f3ad 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -933,6 +933,21 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return true; }
+void intel_panel_replay_compute_config(struct intel_dp *intel_dp, + struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + + if (!intel_dp->psr.sink_panel_replay_support) + return; + + crtc_state->has_panel_replay = true; + crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); + + if (HAS_PSR2_SEL_FETCH(i915)) + intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state); +} + void intel_psr_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state) @@ -942,6 +957,8 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, &crtc_state->hw.adjusted_mode; int psr_setup_time;
+ intel_panel_replay_compute_config(intel_dp, crtc_state); + /* * Current PSR panels dont work reliably with VRR enabled * So if VRR is enabled, do not enable PSR. @@ -2170,6 +2187,35 @@ void intel_psr_flush(struct drm_i915_private *dev_priv, } }
+/** + * intel_panel_replay_init - Check for sink and source capability. + * @intel_dp: Intel DP + * + * This function is called after the initializing connector. + * (the initializing of connector treats the handling of connector capabilities) + * And it initializes basic panel replay stuff for each DP Encoder. + */ +void intel_panel_replay_init(struct intel_dp *intel_dp) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + u8 pr_dpcd = 0; + + if (!(HAS_DP20(dev_priv) && HAS_PANEL_REPLAY(dev_priv))) + return; + + drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP, &pr_dpcd); + + if (!(pr_dpcd & PANEL_REPLAY_SUPPORT)) { + drm_dbg_kms(&dev_priv->drm, + "Panel replay is not supported by panel\n"); + return; + } + + drm_dbg_kms(&dev_priv->drm, + "Panel replay is supported by panel\n"); + intel_dp->psr.sink_panel_replay_support = true; +} + /** * intel_psr_init - Init basic PSR work and mutex. * @intel_dp: Intel DP @@ -2183,6 +2229,8 @@ void intel_psr_init(struct intel_dp *intel_dp) struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ intel_panel_replay_init(intel_dp); + if (!HAS_PSR(dev_priv)) return;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h index facffbacd357..c9d1c1f0b470 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.h +++ b/drivers/gpu/drm/i915/display/intel_psr.h @@ -32,6 +32,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv, unsigned frontbuffer_bits, enum fb_op_origin origin); void intel_psr_init(struct intel_dp *intel_dp); +void intel_panel_replay_init(struct intel_dp *intel_dp); void intel_psr_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state); @@ -52,5 +53,7 @@ void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane, const struct intel_crtc_state *crtc_state); void intel_psr_pause(struct intel_dp *intel_dp); void intel_psr_resume(struct intel_dp *intel_dp); +void intel_panel_replay_compute_config(struct intel_dp *intel_dp, + struct intel_crtc_state *crtc_state);
#endif /* __INTEL_PSR_H__ */
Hi Animesh,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip] [also build test WARNING on next-20211008] [cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next tegra-drm/drm/tegra/for-next linus/master airlied/drm-next v5.15-rc4] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Animesh-Manna/Panel-replay-phase1-i... base: git://anongit.freedesktop.org/drm/drm-tip drm-tip config: i386-randconfig-a014-20211010 (attached as .config) compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 903b30fea21f99d8f48fde4defcc838970e30ee1) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/0day-ci/linux/commit/474a8190321f2836a1fe989326736d19dc9a... git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Animesh-Manna/Panel-replay-phase1-implementation/20211010-203447 git checkout 474a8190321f2836a1fe989326736d19dc9a732b # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=i386
If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot lkp@intel.com
All warnings (new ones prefixed by >>):
drivers/gpu/drm/i915/display/intel_dp.c:2780:27: warning: overlapping comparisons always evaluate to true [-Wtautological-overlap-compare]
if (vsc->revision != 0x5 || vsc->revision != 0x7) ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~ 1 warning generated.
vim +2780 drivers/gpu/drm/i915/display/intel_dp.c
2756 2757 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, 2758 struct dp_sdp *sdp, size_t size) 2759 { 2760 size_t length = sizeof(struct dp_sdp); 2761 2762 if (size < length) 2763 return -ENOSPC; 2764 2765 memset(sdp, 0, size); 2766 2767 /* 2768 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 2769 * VSC SDP Header Bytes 2770 */ 2771 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */ 2772 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */ 2773 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */ 2774 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */ 2775 2776 /* 2777 * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format as 2778 * per DP 1.4a spec and DP 2.0 spec respectively. 2779 */
2780 if (vsc->revision != 0x5 || vsc->revision != 0x7)
2781 goto out; 2782 2783 /* VSC SDP Payload for DB16 through DB18 */ 2784 /* Pixel Encoding and Colorimetry Formats */ 2785 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */ 2786 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */ 2787 2788 switch (vsc->bpc) { 2789 case 6: 2790 /* 6bpc: 0x0 */ 2791 break; 2792 case 8: 2793 sdp->db[17] = 0x1; /* DB17[3:0] */ 2794 break; 2795 case 10: 2796 sdp->db[17] = 0x2; 2797 break; 2798 case 12: 2799 sdp->db[17] = 0x3; 2800 break; 2801 case 16: 2802 sdp->db[17] = 0x4; 2803 break; 2804 default: 2805 MISSING_CASE(vsc->bpc); 2806 break; 2807 } 2808 /* Dynamic Range and Component Bit Depth */ 2809 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA) 2810 sdp->db[17] |= 0x80; /* DB17[7] */ 2811 2812 /* Content Type */ 2813 sdp->db[18] = vsc->content_type & 0x7; 2814 2815 out: 2816 return length; 2817 } 2818
--- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
Hi Animesh,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-tip/drm-tip] [also build test ERROR on next-20211008] [cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next tegra-drm/drm/tegra/for-next linus/master airlied/drm-next v5.15-rc4] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Animesh-Manna/Panel-replay-phase1-i... base: git://anongit.freedesktop.org/drm/drm-tip drm-tip config: i386-randconfig-r014-20211010 (attached as .config) compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 903b30fea21f99d8f48fde4defcc838970e30ee1) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/0day-ci/linux/commit/474a8190321f2836a1fe989326736d19dc9a... git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Animesh-Manna/Panel-replay-phase1-implementation/20211010-203447 git checkout 474a8190321f2836a1fe989326736d19dc9a732b # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=i386
If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot lkp@intel.com
All errors (new ones prefixed by >>):
drivers/gpu/drm/i915/display/intel_dp.c:2780:27: error: overlapping comparisons always evaluate to true [-Werror,-Wtautological-overlap-compare]
if (vsc->revision != 0x5 || vsc->revision != 0x7) ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~ 1 error generated.
vim +2780 drivers/gpu/drm/i915/display/intel_dp.c
2756 2757 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, 2758 struct dp_sdp *sdp, size_t size) 2759 { 2760 size_t length = sizeof(struct dp_sdp); 2761 2762 if (size < length) 2763 return -ENOSPC; 2764 2765 memset(sdp, 0, size); 2766 2767 /* 2768 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 2769 * VSC SDP Header Bytes 2770 */ 2771 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */ 2772 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */ 2773 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */ 2774 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */ 2775 2776 /* 2777 * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format as 2778 * per DP 1.4a spec and DP 2.0 spec respectively. 2779 */
2780 if (vsc->revision != 0x5 || vsc->revision != 0x7)
2781 goto out; 2782 2783 /* VSC SDP Payload for DB16 through DB18 */ 2784 /* Pixel Encoding and Colorimetry Formats */ 2785 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */ 2786 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */ 2787 2788 switch (vsc->bpc) { 2789 case 6: 2790 /* 6bpc: 0x0 */ 2791 break; 2792 case 8: 2793 sdp->db[17] = 0x1; /* DB17[3:0] */ 2794 break; 2795 case 10: 2796 sdp->db[17] = 0x2; 2797 break; 2798 case 12: 2799 sdp->db[17] = 0x3; 2800 break; 2801 case 16: 2802 sdp->db[17] = 0x4; 2803 break; 2804 default: 2805 MISSING_CASE(vsc->bpc); 2806 break; 2807 } 2808 /* Dynamic Range and Component Bit Depth */ 2809 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA) 2810 sdp->db[17] |= 0x80; /* DB17[7] */ 2811 2812 /* Content Type */ 2813 sdp->db[18] = vsc->content_type & 0x7; 2814 2815 out: 2816 return length; 2817 } 2818
--- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
On Sun, 2021-10-10 at 17:40 +0530, Animesh Manna wrote:
We can drop this and reuse current ones ones, see bellow.
move this closer to has_psr and set both when it is panel replay. otherwise psr functions will not be executed for panel replay, see CAN_PSR().
have you checked if the other PSR are needed for panel replay? what about the psr2 checks? when using panel replay selective update some additional tests will be needed regarding granularity...
mutex initialization is not executed, workers not initialized... please go more carefully trough every PSR function and check what are the panel replay implications
Hi,
AFIU Panel replay do not have any dependency with PSR. So that’s why I have created separate function for panel replay which is doing similar thing whatever needed for panel replay. For example intel_panel_replay_compute_config() can be independent of intel_psr_compute_config(). Do you see any dependency with PSR for panel replay?
As mentioned above I understood panel replay do not have any dependency with PSR. Will not target panel replay selective update for dg2.
Tried to double check once more. Currently as per bspec and dp 2.0 spec did not see any dependency with PSR. Not sure if we really need worker thread to enter in panel replay mode unlike psr where we need to wait for few idle frames. Any suggestion/input will be helpful here.
Regards, Animesh
On Tue, 2022-01-04 at 21:21 +0530, Manna, Animesh wrote:
There is no dependency but panel replay is PSR for DP so we should re-use PSR code as much as possible.
eDP + sink_support = PSR DP + sink_support = panel replay
So we can reuse has_psr and all other stuff.
TRANS_DP2_CTL register is programmed to enable panel replay from source and sink is enabled through panel replay dpcd configuration address.
Signed-off-by: Animesh Manna animesh.manna@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 30 ++++++++++++++++++++---- drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 27 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 91c2efe2f3ad..49f6242c2fde 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -370,8 +370,14 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp) struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); u8 dpcd_val = DP_PSR_ENABLE;
- /* Enable ALPM at sink for psr2 */ + if (intel_dp->psr.enabled && !intel_dp_is_edp(intel_dp)) { + drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, + PANEL_REPLAY_ENABLE); + return; + } + if (intel_dp->psr.psr2_enabled) { + /* Enable ALPM at sink for psr2 */ drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, DP_ALPM_ENABLE | DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE); @@ -498,6 +504,17 @@ static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp) return val; }
+static void dg2_activate_panel_replay(struct intel_dp *intel_dp) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + + intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), + ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE); + + intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0, + TRANS_DP2_PANEL_REPLAY_ENABLE); +} + static void hsw_activate_psr2(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@ -1069,8 +1086,10 @@ static void intel_psr_activate(struct intel_dp *intel_dp) drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active); lockdep_assert_held(&intel_dp->psr.lock);
- /* psr1 and psr2 are mutually exclusive.*/ - if (intel_dp->psr.psr2_enabled) + /* psr1, psr2 and panel-replay are mutually exclusive.*/ + if (intel_dp->psr.enabled && !intel_dp_is_edp(intel_dp)) + dg2_activate_panel_replay(intel_dp); + else if (intel_dp->psr.psr2_enabled) hsw_activate_psr2(intel_dp); else hsw_activate_psr1(intel_dp); @@ -1243,7 +1262,10 @@ static void intel_psr_exit(struct intel_dp *intel_dp) return; }
- if (intel_dp->psr.psr2_enabled) { + if (intel_dp->psr.enabled && !intel_dp_is_edp(intel_dp)) { + intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), + TRANS_DP2_PANEL_REPLAY_ENABLE, 0); + } else if (intel_dp->psr.psr2_enabled) { tgl_disallow_dc3co_on_psr2_exit(intel_dp); val = intel_de_read(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder)); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a897f4abea0c..6cc6ebcd3bdb 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4725,6 +4725,7 @@ enum { #define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3) #define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2) #define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1) +#define ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(31) #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(28, 16) #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val) #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(12, 0)
has_panel_replay flag is used to check panel replay state which is part of crtc_state structure.
v1: RFC version. v2: has_panel_replay flag updated as per hw readout. [Jani]
Signed-off-by: Animesh Manna animesh.manna@intel.com --- drivers/gpu/drm/i915/display/intel_display.c | 1 + drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++++ 2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 4f0badb11bbb..a30b6fe87dfc 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -8136,6 +8136,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_BOOL(has_psr); PIPE_CONF_CHECK_BOOL(has_psr2); PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); + PIPE_CONF_CHECK_BOOL(has_panel_replay); PIPE_CONF_CHECK_I(dc3co_exitline); } } diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 49f6242c2fde..d1a30b82ce6f 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1054,6 +1054,12 @@ void intel_psr_get_config(struct intel_encoder *encoder, pipe_config->has_psr2 = intel_dp->psr.psr2_enabled; pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
+ if (HAS_PANEL_REPLAY(dev_priv) && HAS_DP20(dev_priv)) { + val = intel_de_read(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder)); + if (val & TRANS_DP2_PANEL_REPLAY_ENABLE) + pipe_config->has_panel_replay = true; + } + if (!intel_dp->psr.psr2_enabled) goto unlock;
dri-devel@lists.freedesktop.org
-
Animesh Manna -
kernel test robot -
Manna, Animesh
-
Souza, Jose