On MT8167, the two registers SYS_CFG1C and SYS_CFG20 don't have the same address as on MT8173. Add OF data in order to store the address of these two registers.
Signed-off-by: Fabien Parent fparent@baylibre.com --- drivers/gpu/drm/mediatek/mtk_hdmi.c | 45 ++++++++++++++++++++++------- 1 file changed, 34 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c index a97725680d4e..c70f195c21be 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -36,6 +36,11 @@
#define NCTS_BYTES 7
+struct mtk_hdmi_data { + uint32_t sys_cfg1c; + uint32_t sys_cfg20; +}; + enum mtk_hdmi_clk_id { MTK_HDMI_CLK_HDMI_PIXEL, MTK_HDMI_CLK_HDMI_PLL, @@ -146,6 +151,7 @@ struct hdmi_audio_param { };
struct mtk_hdmi { + const struct mtk_hdmi_data *data; struct drm_bridge bridge; struct drm_bridge *next_bridge; struct drm_connector conn; @@ -244,21 +250,24 @@ static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable) */ if (hdmi_phy->conf && hdmi_phy->conf->tz_disabled) regmap_update_bits(hdmi->sys_regmap, - hdmi->sys_offset + HDMI_SYS_CFG20, + hdmi->sys_offset + hdmi->data->sys_cfg20, 0x80008005, enable ? 0x80000005 : 0x8000); else arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904, 0x80000000, 0, 0, 0, 0, 0, &res);
- regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, + regmap_update_bits(hdmi->sys_regmap, + hdmi->sys_offset + hdmi->data->sys_cfg20, HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0); - regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, + regmap_update_bits(hdmi->sys_regmap, + hdmi->sys_offset + hdmi->data->sys_cfg1c, HDMI_ON | ANLG_ON, enable ? (HDMI_ON | ANLG_ON) : 0); }
static void mtk_hdmi_hw_1p4_version_enable(struct mtk_hdmi *hdmi, bool enable) { - regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, + regmap_update_bits(hdmi->sys_regmap, + hdmi->sys_offset + hdmi->data->sys_cfg20, HDMI2P0_EN, enable ? 0 : HDMI2P0_EN); }
@@ -274,12 +283,15 @@ static void mtk_hdmi_hw_aud_unmute(struct mtk_hdmi *hdmi)
static void mtk_hdmi_hw_reset(struct mtk_hdmi *hdmi) { - regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, + regmap_update_bits(hdmi->sys_regmap, + hdmi->sys_offset + hdmi->data->sys_cfg1c, HDMI_RST, HDMI_RST); - regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, + regmap_update_bits(hdmi->sys_regmap, + hdmi->sys_offset + hdmi->data->sys_cfg1c, HDMI_RST, 0); mtk_hdmi_clear_bits(hdmi, GRL_CFG3, CFG3_CONTROL_PACKET_DELAY); - regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, + regmap_update_bits(hdmi->sys_regmap, + hdmi->sys_offset + hdmi->data->sys_cfg1c, ANLG_ON, ANLG_ON); }
@@ -362,16 +374,19 @@ static void mtk_hdmi_hw_send_aud_packet(struct mtk_hdmi *hdmi, bool enable)
static void mtk_hdmi_hw_config_sys(struct mtk_hdmi *hdmi) { - regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, + regmap_update_bits(hdmi->sys_regmap, + hdmi->sys_offset + hdmi->data->sys_cfg20, HDMI_OUT_FIFO_EN | MHL_MODE_ON, 0); usleep_range(2000, 4000); - regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, + regmap_update_bits(hdmi->sys_regmap, + hdmi->sys_offset + hdmi->data->sys_cfg20, HDMI_OUT_FIFO_EN | MHL_MODE_ON, HDMI_OUT_FIFO_EN); }
static void mtk_hdmi_hw_set_deep_color_mode(struct mtk_hdmi *hdmi) { - regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, + regmap_update_bits(hdmi->sys_regmap, + hdmi->sys_offset + hdmi->data->sys_cfg20, DEEP_COLOR_MODE_MASK | DEEP_COLOR_EN, COLOR_8BIT_MODE); } @@ -1733,6 +1748,7 @@ static int mtk_drm_hdmi_probe(struct platform_device *pdev) return -ENOMEM;
hdmi->dev = dev; + hdmi->conf = of_device_get_match_data(dev);
ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev); if (ret) @@ -1813,8 +1829,15 @@ static int mtk_hdmi_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops, mtk_hdmi_suspend, mtk_hdmi_resume);
+ +static struct mtk_hdmi_data mt8173_hdmi_driver_data = { + .sys_cfg1c = HDMI_SYS_CFG1C, + .sys_cfg20 = HDMI_SYS_CFG20, +}; + static const struct of_device_id mtk_drm_hdmi_of_ids[] = { - { .compatible = "mediatek,mt8173-hdmi", }, + { .compatible = "mediatek,mt8173-hdmi", + .data = &mt8173_hdmi_driver_data }, {} };
Add support for HDMI on MT8167. HDMI on MT8167 is similar to MT8173/MT2701 execpt for the two registers: SYS_CFG1C and SYS_CFG20
Signed-off-by: Fabien Parent fparent@baylibre.com --- drivers/gpu/drm/mediatek/mtk_hdmi.c | 7 +++++++ drivers/gpu/drm/mediatek/mtk_hdmi_regs.h | 2 ++ 2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c index c70f195c21be..7762be5cb446 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -1835,9 +1835,16 @@ static struct mtk_hdmi_data mt8173_hdmi_driver_data = { .sys_cfg20 = HDMI_SYS_CFG20, };
+static struct mtk_hdmi_conf mt8167_hdmi_driver_data = { + .sys_cfg1c = MT8167_HDMI_SYS_CFG1C, + .sys_cfg20 = MT8167_HDMI_SYS_CFG20, +}; + static const struct of_device_id mtk_drm_hdmi_of_ids[] = { { .compatible = "mediatek,mt8173-hdmi", .data = &mt8173_hdmi_driver_data }, + { .compatible = "mediatek,mt8167-hdmi", + .data = &mt8167_hdmi_driver_data }, {} };
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h b/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h index 2050ba45b23a..a0f9c367d7aa 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h @@ -195,6 +195,7 @@ #define GEN_RGB (0 << 7)
#define HDMI_SYS_CFG1C 0x000 +#define MT8167_HDMI_SYS_CFG1C 0x800 #define HDMI_ON BIT(0) #define HDMI_RST BIT(1) #define ANLG_ON BIT(2) @@ -211,6 +212,7 @@ #define HTPLG_PIN_SEL_OFF BIT(30) #define AES_EFUSE_ENABLE BIT(31) #define HDMI_SYS_CFG20 0x004 +#define MT8167_HDMI_SYS_CFG20 0x804 #define DEEP_COLOR_MODE_MASK (3 << 1) #define COLOR_8BIT_MODE (0 << 1) #define COLOR_10BIT_MODE (1 << 1)
On Tue, Oct 13, 2020 at 7:28 PM Fabien Parent fparent@baylibre.com wrote:
Add support for HDMI on MT8167. HDMI on MT8167 is similar to MT8173/MT2701 execpt for the two registers: SYS_CFG1C and SYS_CFG20
Signed-off-by: Fabien Parent fparent@baylibre.com
drivers/gpu/drm/mediatek/mtk_hdmi.c | 7 +++++++ drivers/gpu/drm/mediatek/mtk_hdmi_regs.h | 2 ++ 2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c index c70f195c21be..7762be5cb446 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -1835,9 +1835,16 @@ static struct mtk_hdmi_data mt8173_hdmi_driver_data = { .sys_cfg20 = HDMI_SYS_CFG20, };
+static struct mtk_hdmi_conf mt8167_hdmi_driver_data = {
Sent the wrong patch. Sending v2 soon.
.sys_cfg1c = MT8167_HDMI_SYS_CFG1C,.sys_cfg20 = MT8167_HDMI_SYS_CFG20,+};
static const struct of_device_id mtk_drm_hdmi_of_ids[] = { { .compatible = "mediatek,mt8173-hdmi", .data = &mt8173_hdmi_driver_data },
{ .compatible = "mediatek,mt8167-hdmi",.data = &mt8167_hdmi_driver_data }, {}};
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h b/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h index 2050ba45b23a..a0f9c367d7aa 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h @@ -195,6 +195,7 @@ #define GEN_RGB (0 << 7)
#define HDMI_SYS_CFG1C 0x000 +#define MT8167_HDMI_SYS_CFG1C 0x800 #define HDMI_ON BIT(0) #define HDMI_RST BIT(1) #define ANLG_ON BIT(2) @@ -211,6 +212,7 @@ #define HTPLG_PIN_SEL_OFF BIT(30) #define AES_EFUSE_ENABLE BIT(31) #define HDMI_SYS_CFG20 0x004 +#define MT8167_HDMI_SYS_CFG20 0x804 #define DEEP_COLOR_MODE_MASK (3 << 1) #define COLOR_8BIT_MODE (0 << 1)
#define COLOR_10BIT_MODE (1 << 1)
2.28.0
dri-devel@lists.freedesktop.org
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Fabien Parent