Query hardware IP information to find out if there are uvd encode rings ready for use in kernel driver.
Signed-off-by: James Zhu James.Zhu@amd.com --- tests/amdgpu/uvd_enc_tests.c | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-)
diff --git a/tests/amdgpu/uvd_enc_tests.c b/tests/amdgpu/uvd_enc_tests.c index 6c19f7b..7518103 100644 --- a/tests/amdgpu/uvd_enc_tests.c +++ b/tests/amdgpu/uvd_enc_tests.c @@ -79,6 +79,8 @@ static void amdgpu_cs_uvd_enc_session_init(void); static void amdgpu_cs_uvd_enc_encode(void); static void amdgpu_cs_uvd_enc_destroy(void);
+static bool uvd_enc_support(void); + CU_TestInfo uvd_enc_tests[] = { { "UVD ENC create", amdgpu_cs_uvd_enc_create }, { "UVD ENC session init", amdgpu_cs_uvd_enc_session_init }, @@ -98,7 +100,7 @@ int suite_uvd_enc_tests_init(void)
family_id = device_handle->info.family_id;
- if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) { + if (!uvd_enc_support()) { printf("\n\nThe ASIC NOT support UVD ENC, all sub-tests will pass\n"); return CUE_SUCCESS; } @@ -121,7 +123,7 @@ int suite_uvd_enc_tests_clean(void) { int r;
- if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) { + if (!uvd_enc_support()) {
r = amdgpu_device_deinitialize(device_handle); if (r) @@ -238,11 +240,24 @@ static void free_resource(struct amdgpu_uvd_enc_bo *uvd_enc_bo) memset(uvd_enc_bo, 0, sizeof(*uvd_enc_bo)); }
+static bool uvd_enc_support(void) +{ + int r; + struct drm_amdgpu_info_hw_ip info; + + r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_UVD_ENC, 0, &info); + + if (r) + return false; + else + return (info.available_rings?true:false); +} + static void amdgpu_cs_uvd_enc_create(void) { int len, r;
- if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) + if (!uvd_enc_support()) return;
enc.width = 160; @@ -281,7 +296,7 @@ static void amdgpu_cs_uvd_enc_session_init(void) { int len, r;
- if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) + if (!uvd_enc_support()) return;
len = 0; @@ -339,7 +354,7 @@ static void amdgpu_cs_uvd_enc_encode(void) vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5; cpb_size = vbuf_size * 10;
- if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) + if (!uvd_enc_support()) return;
num_resources = 0; @@ -472,7 +487,7 @@ static void amdgpu_cs_uvd_enc_destroy(void) struct amdgpu_uvd_enc_bo sw_ctx; int len, r;
- if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) + if (!uvd_enc_support()) return;
num_resources = 0;
In uvd encode parameter package, parameters input_pic_luma_pitch and input_pic_chroma_pitch should be picture width align with hardware alignment. The hardware alignment is 16 for amdgpu family earlier than AMDGPU_FAMILY_AI, and 256 for later than and including AMDGPU_FAMILY_AI.
Signed-off-by: James Zhu James.Zhu@amd.com --- tests/amdgpu/uvd_enc_tests.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/tests/amdgpu/uvd_enc_tests.c b/tests/amdgpu/uvd_enc_tests.c index 7518103..bbda131 100644 --- a/tests/amdgpu/uvd_enc_tests.c +++ b/tests/amdgpu/uvd_enc_tests.c @@ -272,7 +272,7 @@ static void amdgpu_cs_uvd_enc_create(void) static void check_result(struct amdgpu_uvd_enc *enc) { uint64_t sum; - uint32_t s = 26382; + uint32_t s = 175602; uint32_t *ptr, size; int i, j, r;
@@ -463,6 +463,8 @@ static void amdgpu_cs_uvd_enc_encode(void) ib_cpu[len++] = chroma_offset >> 32; ib_cpu[len++] = chroma_offset; memcpy((ib_cpu + len), uve_encode_param, sizeof(uve_encode_param)); + ib_cpu[len] = ALIGN(enc.width, align); + ib_cpu[len + 1] = ALIGN(enc.width, align); len += sizeof(uve_encode_param) / 4;
memcpy((ib_cpu + len), uve_op_speed_enc_mode, sizeof(uve_op_speed_enc_mode));
On 10/05/2017 11:24 AM, James Zhu wrote:
In uvd encode parameter package, parameters input_pic_luma_pitch and input_pic_chroma_pitch should be picture width align with hardware alignment. The hardware alignment is 16 for amdgpu family earlier than AMDGPU_FAMILY_AI, and 256 for later than and including AMDGPU_FAMILY_AI.
Signed-off-by: James Zhu James.Zhu@amd.com
tests/amdgpu/uvd_enc_tests.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/tests/amdgpu/uvd_enc_tests.c b/tests/amdgpu/uvd_enc_tests.c index 7518103..bbda131 100644 --- a/tests/amdgpu/uvd_enc_tests.c +++ b/tests/amdgpu/uvd_enc_tests.c @@ -272,7 +272,7 @@ static void amdgpu_cs_uvd_enc_create(void) static void check_result(struct amdgpu_uvd_enc *enc) { uint64_t sum;
- uint32_t s = 26382;
- uint32_t s = 175602; uint32_t *ptr, size; int i, j, r;
@@ -463,6 +463,8 @@ static void amdgpu_cs_uvd_enc_encode(void) ib_cpu[len++] = chroma_offset >> 32; ib_cpu[len++] = chroma_offset; memcpy((ib_cpu + len), uve_encode_param, sizeof(uve_encode_param));
- ib_cpu[len] = ALIGN(enc.width, align);
- ib_cpu[len + 1] = ALIGN(enc.width, align);
Since here we override the pitch value based on below from uve_ib.h.
static const uint32_t uve_encode_param[] = { 0x000000a0, 0x00000080,
We'd better to reset them to 0 from the header file, since we don't want to leave the incorrect value there.
With that fixed, the series is
Reviewed-by: Leo Liu leo.liu@amd.com
len += sizeof(uve_encode_param) / 4;
memcpy((ib_cpu + len), uve_op_speed_enc_mode, sizeof(uve_op_speed_enc_mode));
Hi Leo,
Sure, I will reset 0 in header file
Thanks! James Zhu On 2017-10-05 11:39 AM, Leo Liu wrote:
On 10/05/2017 11:24 AM, James Zhu wrote:
In uvd encode parameter package, parameters input_pic_luma_pitch and input_pic_chroma_pitch should be picture width align with hardware alignment. The hardware alignment is 16 for amdgpu family earlier than AMDGPU_FAMILY_AI, and 256 for later than and including AMDGPU_FAMILY_AI.
Signed-off-by: James Zhu James.Zhu@amd.com
tests/amdgpu/uvd_enc_tests.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/tests/amdgpu/uvd_enc_tests.c b/tests/amdgpu/uvd_enc_tests.c index 7518103..bbda131 100644 --- a/tests/amdgpu/uvd_enc_tests.c +++ b/tests/amdgpu/uvd_enc_tests.c @@ -272,7 +272,7 @@ static void amdgpu_cs_uvd_enc_create(void) static void check_result(struct amdgpu_uvd_enc *enc) { uint64_t sum; - uint32_t s = 26382; + uint32_t s = 175602; uint32_t *ptr, size; int i, j, r; @@ -463,6 +463,8 @@ static void amdgpu_cs_uvd_enc_encode(void) ib_cpu[len++] = chroma_offset >> 32; ib_cpu[len++] = chroma_offset; memcpy((ib_cpu + len), uve_encode_param, sizeof(uve_encode_param)); + ib_cpu[len] = ALIGN(enc.width, align); + ib_cpu[len + 1] = ALIGN(enc.width, align);
Since here we override the pitch value based on below from uve_ib.h.
static const uint32_t uve_encode_param[] = { 0x000000a0, 0x00000080,
We'd better to reset them to 0 from the header file, since we don't want to leave the incorrect value there.
With that fixed, the series is
Reviewed-by: Leo Liu leo.liu@amd.com
len += sizeof(uve_encode_param) / 4; memcpy((ib_cpu + len), uve_op_speed_enc_mode, sizeof(uve_op_speed_enc_mode));
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Leo Liu