This series is based on kernel/git/chunkuang.hu/linux.git mediatek-drm-next The series is tested on a mt8183 krane device.
Change since v10 - fix review comments in v9
Change since v9 - change several function to rebase to mediatek-drm-next
Change since v8 - fix some review comment in v8 - separate gamma module for mt8183 has no dither function in gamma - enable dither function for 5 or 6 bpc panel display - separate ddp mutex patch from the whole Soc patch
Change since v7 - add dt-binding for mt8183 display - base mmsys patch https://patchwork.kernel.org/project/linux-mediatek/cover/1607506379-10998-1... - base dts patch https://patchwork.kernel.org/project/linux-mediatek/cover/20201127104930.198... - add mt8183 function call for setting the routing registers - add RDMA fifo size error handle
Change since v6 - move ddp component define into mtk_mmsys.h - add mmsys private data to support different ic path connection - add mt8183-mmsys.c to support 8183 path connection - fix reviewed issue in v6
Change since v5 - fix reviewed issue in v5 base https://patchwork.kernel.org/project/linux-mediatek/list/?series=213219
Change since v4 - fix reviewed issue in v4
Change since v3 - fix reviewed issue in v3 - fix type error in v3 - fix conflict with iommu patch
Change since v2 - fix reviewed issue in v2 - add mutex node into dts file
Changes since v1: - fix reviewed issue in v1 - add dts for mt8183 display nodes - adjust display clock control flow in patch 22 - add vmap support for mediatek drm in patch 23 - fix page offset issue for mmap function in patch 24 - enable allow_fb_modifiers for mediatek drm in patch 25
Hsin-Yi Wang (1): drm/mediatek: add mtk_dither_set_common() function
Yongqiang Niu (8): arm64: dts: mt8183: rename rdma fifo size arm64: dts: mt8183: refine gamma compatible name drm/mediatek: add RDMA fifo size error handle drm/mediatek: separate gamma module drm/mediatek: add has_dither private data for gamma drm/mediatek: enable dither function soc: mediatek: add mtk mutex support for MT8183 drm/mediatek: add support for mediatek SOC MT8183
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 7 +- drivers/gpu/drm/mediatek/Makefile | 1 + drivers/gpu/drm/mediatek/mtk_disp_drv.h | 14 ++ drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 196 ++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 10 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 138 +++++++------- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 49 ++++- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + drivers/soc/mediatek/mtk-mutex.c | 50 +++++ 10 files changed, 410 insertions(+), 74 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_gamma.c
From: Yongqiang Niu yongqiang.niu@mediatek.com
property name must include only lowercase and '-'
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org Reviewed-by: Chun-Kuang Hu chunkuang.hu@kernel.org --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 5b782a4769e7e..6c84ccb709af6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1011,7 +1011,7 @@ rdma0: rdma@1400b000 { clocks = <&mmsys CLK_MM_DISP_RDMA0>; iommus = <&iommu M4U_PORT_DISP_RDMA0>; mediatek,larb = <&larb0>; - mediatek,rdma_fifo_size = <5120>; + mediatek,rdma-fifo-size = <5120>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; };
@@ -1023,7 +1023,7 @@ rdma1: rdma@1400c000 { clocks = <&mmsys CLK_MM_DISP_RDMA1>; iommus = <&iommu M4U_PORT_DISP_RDMA1>; mediatek,larb = <&larb0>; - mediatek,rdma_fifo_size = <2048>; + mediatek,rdma-fifo-size = <2048>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; };
Hi Hsin-Yi,
Thank you for the patch.
Missatge de Hsin-Yi Wang hsinyi@chromium.org del dia dj., 28 de gen. 2021 a les 8:28:
From: Yongqiang Niu yongqiang.niu@mediatek.com
property name must include only lowercase and '-'
This is a leftover while I forward ported the patch, the rdma_fifo_size only existed on the downstream kernels, in mainline it is with '-', so we should probably add the fixes tag here.
Fixes: 91f9c963ce79 ("arm64: dts: mt8183: Add display nodes for MT8183")
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org Reviewed-by: Chun-Kuang Hu chunkuang.hu@kernel.org
Reviewed-by: Enric Balletbo i Serra enric.balletbo@collabora.com
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 5b782a4769e7e..6c84ccb709af6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1011,7 +1011,7 @@ rdma0: rdma@1400b000 { clocks = <&mmsys CLK_MM_DISP_RDMA0>; iommus = <&iommu M4U_PORT_DISP_RDMA0>; mediatek,larb = <&larb0>;
mediatek,rdma_fifo_size = <5120>;
mediatek,rdma-fifo-size = <5120>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; };@@ -1023,7 +1023,7 @@ rdma1: rdma@1400c000 { clocks = <&mmsys CLK_MM_DISP_RDMA1>; iommus = <&iommu M4U_PORT_DISP_RDMA1>; mediatek,larb = <&larb0>;
mediatek,rdma_fifo_size = <2048>;
mediatek,rdma-fifo-size = <2048>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; };-- 2.30.0.280.ga3ce27912f-goog
Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek
From: Yongqiang Niu yongqiang.niu@mediatek.com
mt8183 gamma is different with mt8173 remove mt8173 compatible name for mt8183 gamma
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 6c84ccb709af6..9c0073cfad452 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1055,8 +1055,7 @@ aal0: aal@14010000 { };
gamma0: gamma@14011000 { - compatible = "mediatek,mt8183-disp-gamma", - "mediatek,mt8173-disp-gamma"; + compatible = "mediatek,mt8183-disp-gamma"; reg = <0 0x14011000 0 0x1000>; interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>; power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
Hi Hsin-Yi,
Thank you for your patch.
Missatge de Hsin-Yi Wang hsinyi@chromium.org del dia dj., 28 de gen. 2021 a les 8:28:
From: Yongqiang Niu yongqiang.niu@mediatek.com
mt8183 gamma is different with mt8173 remove mt8173 compatible name for mt8183 gamma
Should this patch contain?
Fixes: 91f9c963ce79 ("arm64: dts: mt8183: Add display nodes for MT8183")
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org
Reviewed-by: Enric Balletbo i Serra enric.balletbo@collabora.com
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 6c84ccb709af6..9c0073cfad452 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1055,8 +1055,7 @@ aal0: aal@14010000 { };
gamma0: gamma@14011000 {
compatible = "mediatek,mt8183-disp-gamma","mediatek,mt8173-disp-gamma";
compatible = "mediatek,mt8183-disp-gamma"; reg = <0 0x14011000 0 0x1000>; interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>; power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;-- 2.30.0.280.ga3ce27912f-goog
Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek
From: Yongqiang Niu yongqiang.niu@mediatek.com
This patch add RDMA fifo size error handle rdma fifo size will not always bigger than the calculated threshold if that case happened, we need set fifo size as the threshold
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org --- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index b84004394970f..04b9542010b00 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -168,6 +168,10 @@ void mtk_rdma_config(struct device *dev, unsigned int width, * account for blanking, and with a pixel depth of 4 bytes: */ threshold = width * height * vrefresh * 4 * 7 / 1000000; + + if (threshold > rdma_fifo_size) + threshold = rdma_fifo_size; + reg = RDMA_FIFO_UNDERFLOW_EN | RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) | RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
Hi, Hsin-Yi:
On Thu, 2021-01-28 at 15:27 +0800, Hsin-Yi Wang wrote:
From: Yongqiang Niu yongqiang.niu@mediatek.com
This patch add RDMA fifo size error handle rdma fifo size will not always bigger than the calculated threshold if that case happened, we need set fifo size as the threshold
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index b84004394970f..04b9542010b00 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -168,6 +168,10 @@ void mtk_rdma_config(struct device *dev, unsigned int width, * account for blanking, and with a pixel depth of 4 bytes: */ threshold = width * height * vrefresh * 4 * 7 / 1000000;
- if (threshold > rdma_fifo_size)
threshold = rdma_fifo_size;
Please see the discussion in [1].
[1] https://patchwork.kernel.org/project/linux-mediatek/patch/1607591262-21736-6...
Regards, CK
reg = RDMA_FIFO_UNDERFLOW_EN | RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) | RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
On Thu, Jan 28, 2021 at 3:52 PM CK Hu ck.hu@mediatek.com wrote:
Hi, Hsin-Yi:
On Thu, 2021-01-28 at 15:27 +0800, Hsin-Yi Wang wrote:
From: Yongqiang Niu yongqiang.niu@mediatek.com
This patch add RDMA fifo size error handle rdma fifo size will not always bigger than the calculated threshold if that case happened, we need set fifo size as the threshold
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index b84004394970f..04b9542010b00 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -168,6 +168,10 @@ void mtk_rdma_config(struct device *dev, unsigned int width, * account for blanking, and with a pixel depth of 4 bytes: */ threshold = width * height * vrefresh * 4 * 7 / 1000000;
if (threshold > rdma_fifo_size)threshold = rdma_fifo_size;Please see the discussion in [1].
[1] https://patchwork.kernel.org/project/linux-mediatek/patch/1607591262-21736-6...
Regards, CK
Hi CK,
Even if we set threshold to threshold = RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) * width * height * vrefresh / 2 / MAX_WIDTH / MAX_HEIGHT / MAX_VREFRESH;
I'm not sure what value MAX_WIDTH, MAX_HEIGHT, and MAX_VREFRESH should set to for each SoC. Since there's no conclusion yet, I'll drop this patch in the series, as this seems not an mt8183 specific fix.
reg = RDMA_FIFO_UNDERFLOW_EN | RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) | RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
Current implementation of mtk_dither_set() cast dev data to struct mtk_ddp_comp_dev. But other devices with different dev data would also call this function.
Separate necessary parameters out so other device components (dither, gamma) can call this function.
Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org --- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 4 ++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 25 +++++++++++++-------- 2 files changed, 20 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index 46d199b7b4a29..c50d5fc9fd349 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -17,6 +17,10 @@ void mtk_color_config(struct device *dev, unsigned int w, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); void mtk_color_start(struct device *dev);
+void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg, + unsigned int bpc, unsigned int CFG, + struct cmdq_pkt *cmdq_pkt); + void mtk_dpi_start(struct device *dev); void mtk_dpi_stop(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 7b5293429426d..53d25823a37cc 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -151,33 +151,40 @@ static void mtk_ddp_clk_disable(struct device *dev) clk_disable_unprepare(priv->clk); }
-static void mtk_dither_set(struct device *dev, unsigned int bpc, - unsigned int CFG, struct cmdq_pkt *cmdq_pkt) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg, + unsigned int bpc, unsigned int CFG, struct cmdq_pkt *cmdq_pkt) +{ /* If bpc equal to 0, the dithering function didn't be enabled */ if (bpc == 0) return;
if (bpc >= MTK_MIN_BPC) { - mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, DISP_DITHER_5); - mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, DISP_DITHER_7); + mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_5); + mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_7); mtk_ddp_write(cmdq_pkt, DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | DITHER_NEW_BIT_MODE, - &priv->cmdq_reg, priv->regs, DISP_DITHER_15); + cmdq_reg, regs, DISP_DITHER_15); mtk_ddp_write(cmdq_pkt, DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc), - &priv->cmdq_reg, priv->regs, DISP_DITHER_16); - mtk_ddp_write(cmdq_pkt, DISP_DITHERING, &priv->cmdq_reg, priv->regs, CFG); + cmdq_reg, regs, DISP_DITHER_16); + mtk_ddp_write(cmdq_pkt, DISP_DITHERING, cmdq_reg, regs, CFG); } }
+static void mtk_dither_set(struct device *dev, unsigned int bpc, + unsigned int CFG, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); + + mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, CFG, cmdq_pkt); +} + static void mtk_od_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
On Thu, 2021-01-28 at 15:27 +0800, Hsin-Yi Wang wrote:
Current implementation of mtk_dither_set() cast dev data to struct mtk_ddp_comp_dev. But other devices with different dev data would also call this function.
Separate necessary parameters out so other device components (dither, gamma) can call this function.
Reviewed-by: CK Hu ck.hu@mediatek.com
Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 4 ++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 25 +++++++++++++-------- 2 files changed, 20 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index 46d199b7b4a29..c50d5fc9fd349 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -17,6 +17,10 @@ void mtk_color_config(struct device *dev, unsigned int w, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); void mtk_color_start(struct device *dev);
+void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
unsigned int bpc, unsigned int CFG,struct cmdq_pkt *cmdq_pkt);void mtk_dpi_start(struct device *dev); void mtk_dpi_stop(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 7b5293429426d..53d25823a37cc 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -151,33 +151,40 @@ static void mtk_ddp_clk_disable(struct device *dev) clk_disable_unprepare(priv->clk); }
-static void mtk_dither_set(struct device *dev, unsigned int bpc,
unsigned int CFG, struct cmdq_pkt *cmdq_pkt)-{
- struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
unsigned int bpc, unsigned int CFG, struct cmdq_pkt *cmdq_pkt)+{ /* If bpc equal to 0, the dithering function didn't be enabled */ if (bpc == 0) return;
if (bpc >= MTK_MIN_BPC) {
mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, DISP_DITHER_5);mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, DISP_DITHER_7);
mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_5);mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_7);
&priv->cmdq_reg, priv->regs, DISP_DITHER_15);
cmdq_reg, regs, DISP_DITHER_15);
&priv->cmdq_reg, priv->regs, DISP_DITHER_16);mtk_ddp_write(cmdq_pkt, DISP_DITHERING, &priv->cmdq_reg, priv->regs, CFG);
cmdq_reg, regs, DISP_DITHER_16);mtk_ddp_write(cmdq_pkt, DISP_DITHERING, cmdq_reg, regs, CFG);}
+static void mtk_dither_set(struct device *dev, unsigned int bpc,
unsigned int CFG, struct cmdq_pkt *cmdq_pkt)+{
- struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
- mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, CFG, cmdq_pkt);
+}
static void mtk_od_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
From: Yongqiang Niu yongqiang.niu@mediatek.com
mt8183 gamma module will different with mt8173 separate gamma for add private data
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/Makefile | 1 + drivers/gpu/drm/mediatek/mtk_disp_drv.h | 10 ++ drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 189 ++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 71 ++------ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + 6 files changed, 215 insertions(+), 61 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_gamma.c
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index 01d06332f7679..b64674b944860 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0
mediatek-drm-y := mtk_disp_color.o \ + mtk_disp_gamma.o \ mtk_disp_ovl.o \ mtk_disp_rdma.o \ mtk_drm_crtc.o \ diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index c50d5fc9fd349..c1e658b490b6c 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -27,6 +27,16 @@ void mtk_dpi_stop(struct device *dev); void mtk_dsi_ddp_start(struct device *dev); void mtk_dsi_ddp_stop(struct device *dev);
+int mtk_gamma_clk_enable(struct device *dev); +void mtk_gamma_clk_disable(struct device *dev); +void mtk_gamma_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt); +void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state); +void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state); +void mtk_gamma_start(struct device *dev); +void mtk_gamma_stop(struct device *dev); + void mtk_ovl_bgclr_in_on(struct device *dev); void mtk_ovl_bgclr_in_off(struct device *dev); void mtk_ovl_bypass_shadow(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c new file mode 100644 index 0000000000000..a7e2e326b2183 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -0,0 +1,189 @@ +/* + * SPDX-License-Identifier: + * + * Copyright (c) 2020 MediaTek Inc. + */ + +#include <linux/clk.h> +#include <linux/component.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-cmdq.h> + +#include "mtk_disp_drv.h" +#include "mtk_drm_crtc.h" +#include "mtk_drm_ddp_comp.h" + +#define DISP_GAMMA_EN 0x0000 +#define GAMMA_EN BIT(0) +#define DISP_GAMMA_CFG 0x0020 +#define GAMMA_LUT_EN BIT(1) +#define DISP_GAMMA_SIZE 0x0030 +#define DISP_GAMMA_LUT 0x0700 + +#define LUT_10BIT_MASK 0x03ff + +struct mtk_disp_gamma_data { + u32 reserved; +}; + +/** + * struct mtk_disp_gamma - DISP_GAMMA driver structure + * @ddp_comp - structure containing type enum and hardware resources + * @crtc - associated crtc to report irq events to + */ +struct mtk_disp_gamma { + struct clk *clk; + void __iomem *regs; + struct cmdq_client_reg cmdq_reg; + const struct mtk_disp_gamma_data *data; +}; + +int mtk_gamma_clk_enable(struct device *dev) +{ + struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); + + return clk_prepare_enable(gamma->clk); +} + +void mtk_gamma_clk_disable(struct device *dev) +{ + struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); + + clk_disable_unprepare(gamma->clk); +} + +void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state) +{ + unsigned int i, reg; + struct drm_color_lut *lut; + void __iomem *lut_base; + u32 word; + + if (state->gamma_lut) { + reg = readl(regs + DISP_GAMMA_CFG); + reg = reg | GAMMA_LUT_EN; + writel(reg, regs + DISP_GAMMA_CFG); + lut_base = regs + DISP_GAMMA_LUT; + lut = (struct drm_color_lut *)state->gamma_lut->data; + for (i = 0; i < MTK_LUT_SIZE; i++) { + word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + + (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) + + ((lut[i].blue >> 6) & LUT_10BIT_MASK); + writel(word, (lut_base + i * 4)); + } + } +} + +void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) +{ + struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); + + mtk_gamma_set_common(gamma->regs, state); +} + +void mtk_gamma_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); + + mtk_ddp_write(cmdq_pkt, h << 16 | w, &gamma->cmdq_reg, gamma->regs, + DISP_GAMMA_SIZE); + mtk_dither_set_common(gamma->regs, &gamma->cmdq_reg, bpc, DISP_GAMMA_CFG, cmdq_pkt); +} + +void mtk_gamma_start(struct device *dev) +{ + struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); + + writel(GAMMA_EN, gamma->regs + DISP_GAMMA_EN); +} + +void mtk_gamma_stop(struct device *dev) +{ + struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); + + writel_relaxed(0x0, gamma->regs + DISP_GAMMA_EN); +} + +static int mtk_disp_gamma_bind(struct device *dev, struct device *master, + void *data) +{ + return 0; +} + +static void mtk_disp_gamma_unbind(struct device *dev, struct device *master, + void *data) +{ +} + +static const struct component_ops mtk_disp_gamma_component_ops = { + .bind = mtk_disp_gamma_bind, + .unbind = mtk_disp_gamma_unbind, +}; + +static int mtk_disp_gamma_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mtk_disp_gamma *priv; + struct resource *res; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->clk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->clk)) { + dev_err(dev, "failed to get gamma clk\n"); + return PTR_ERR(priv->clk); + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->regs = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->regs)) { + dev_err(dev, "failed to ioremap gamma\n"); + return PTR_ERR(priv->regs); + } + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); + if (ret) + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); +#endif + + priv->data = of_device_get_match_data(dev); + platform_set_drvdata(pdev, priv); + + ret = component_add(dev, &mtk_disp_gamma_component_ops); + if (ret) + dev_err(dev, "Failed to add component: %d\n", ret); + + return ret; +} + +static int mtk_disp_gamma_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &mtk_disp_gamma_component_ops); + + return 0; +} + +static const struct of_device_id mtk_disp_gamma_driver_dt_match[] = { + { .compatible = "mediatek,mt8173-disp-gamma"}, + {}, +}; +MODULE_DEVICE_TABLE(of, mtk_disp_gamma_driver_dt_match); + +struct platform_driver mtk_disp_gamma_driver = { + .probe = mtk_disp_gamma_probe, + .remove = mtk_disp_gamma_remove, + .driver = { + .name = "mediatek-disp-gamma", + .owner = THIS_MODULE, + .of_match_table = mtk_disp_gamma_driver_dt_match, + }, +}; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 53d25823a37cc..8173f709272be 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -55,11 +55,6 @@ #define DITHER_RELAY_MODE BIT(0) #define DISP_DITHER_SIZE 0x0030
-#define DISP_GAMMA_EN 0x0000 -#define DISP_GAMMA_CFG 0x0020 -#define DISP_GAMMA_SIZE 0x0030 -#define DISP_GAMMA_LUT 0x0700 - #define LUT_10BIT_MASK 0x03ff
#define OD_RELAYMODE BIT(0) @@ -68,9 +63,6 @@
#define AAL_EN BIT(0)
-#define GAMMA_EN BIT(0) -#define GAMMA_LUT_EN BIT(1) - #define DISP_DITHERING BIT(2) #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28) #define DITHER_OVFLW_BIT_R(x) (((x) & 0x7) << 24) @@ -151,7 +143,6 @@ static void mtk_ddp_clk_disable(struct device *dev) clk_disable_unprepare(priv->clk); }
- void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg, unsigned int bpc, unsigned int CFG, struct cmdq_pkt *cmdq_pkt) { @@ -219,6 +210,13 @@ static void mtk_aal_config(struct device *dev, unsigned int w, mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_AAL_SIZE); }
+static void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state) +{ + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); + + mtk_gamma_set_common(priv->regs, state); +} + static void mtk_aal_start(struct device *dev) { struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); @@ -333,58 +331,10 @@ static void mtk_dither_stop(struct device *dev) writel_relaxed(0x0, priv->regs + DISP_DITHER_EN); }
-static void mtk_gamma_config(struct device *dev, unsigned int w, - unsigned int h, unsigned int vrefresh, - unsigned int bpc, struct cmdq_pkt *cmdq_pkt) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_GAMMA_SIZE); - mtk_dither_set(dev, bpc, DISP_GAMMA_CFG, cmdq_pkt); -} - -static void mtk_gamma_start(struct device *dev) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - - writel(GAMMA_EN, priv->regs + DISP_GAMMA_EN); -} - -static void mtk_gamma_stop(struct device *dev) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - - writel_relaxed(0x0, priv->regs + DISP_GAMMA_EN); -} - -static void mtk_gamma_set(struct device *dev, - struct drm_crtc_state *state) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - unsigned int i, reg; - struct drm_color_lut *lut; - void __iomem *lut_base; - u32 word; - - if (state->gamma_lut) { - reg = readl(priv->regs + DISP_GAMMA_CFG); - reg = reg | GAMMA_LUT_EN; - writel(reg, priv->regs + DISP_GAMMA_CFG); - lut_base = priv->regs + DISP_GAMMA_LUT; - lut = (struct drm_color_lut *)state->gamma_lut->data; - for (i = 0; i < MTK_LUT_SIZE; i++) { - word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + - (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) + - ((lut[i].blue >> 6) & LUT_10BIT_MASK); - writel(word, (lut_base + i * 4)); - } - } -} - static const struct mtk_ddp_comp_funcs ddp_aal = { .clk_enable = mtk_ddp_clk_enable, .clk_disable = mtk_ddp_clk_disable, - .gamma_set = mtk_gamma_set, + .gamma_set = mtk_aal_gamma_set, .config = mtk_aal_config, .start = mtk_aal_start, .stop = mtk_aal_stop, @@ -425,8 +375,8 @@ static const struct mtk_ddp_comp_funcs ddp_dsi = { };
static const struct mtk_ddp_comp_funcs ddp_gamma = { - .clk_enable = mtk_ddp_clk_enable, - .clk_disable = mtk_ddp_clk_disable, + .clk_enable = mtk_gamma_clk_enable, + .clk_disable = mtk_gamma_clk_disable, .gamma_set = mtk_gamma_set, .config = mtk_gamma_config, .start = mtk_gamma_start, @@ -642,6 +592,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
if (type == MTK_DISP_BLS || type == MTK_DISP_COLOR || + type == MTK_DISP_GAMMA || type == MTK_DPI || type == MTK_DSI || type == MTK_DISP_OVL || diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 5d39dd54255d1..279d3e6f11563 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -486,11 +486,12 @@ static int mtk_drm_probe(struct platform_device *pdev) private->comp_node[comp_id] = of_node_get(node);
/* - * Currently only the COLOR, OVL, RDMA, DSI, and DPI blocks have + * Currently only the COLOR, GAMMA, OVL, RDMA, DSI, and DPI blocks have * separate component platform drivers and initialize their own * DDP component structure. The others are initialized here. */ if (comp_type == MTK_DISP_COLOR || + comp_type == MTK_DISP_GAMMA || comp_type == MTK_DISP_OVL || comp_type == MTK_DISP_OVL_2L || comp_type == MTK_DISP_RDMA || @@ -589,6 +590,7 @@ static struct platform_driver mtk_drm_platform_driver = {
static struct platform_driver * const mtk_drm_drivers[] = { &mtk_disp_color_driver, + &mtk_disp_gamma_driver, &mtk_disp_ovl_driver, &mtk_disp_rdma_driver, &mtk_dpi_driver, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index e8238fa4aa2ac..0e54e3d51014a 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -47,6 +47,7 @@ struct mtk_drm_private { };
extern struct platform_driver mtk_disp_color_driver; +extern struct platform_driver mtk_disp_gamma_driver; extern struct platform_driver mtk_disp_ovl_driver; extern struct platform_driver mtk_disp_rdma_driver; extern struct platform_driver mtk_dpi_driver;
From: Yongqiang Niu yongqiang.niu@mediatek.com
Not all SoC has dither function in gamma module. Add private data to control this function setting.
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index a7e2e326b2183..22199ef11f65d 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -26,7 +26,7 @@ #define LUT_10BIT_MASK 0x03ff
struct mtk_disp_gamma_data { - u32 reserved; + bool has_dither; };
/** @@ -92,7 +92,8 @@ void mtk_gamma_config(struct device *dev, unsigned int w,
mtk_ddp_write(cmdq_pkt, h << 16 | w, &gamma->cmdq_reg, gamma->regs, DISP_GAMMA_SIZE); - mtk_dither_set_common(gamma->regs, &gamma->cmdq_reg, bpc, DISP_GAMMA_CFG, cmdq_pkt); + if (gamma->data && gamma->data->has_dither) + mtk_dither_set_common(gamma->regs, &gamma->cmdq_reg, bpc, DISP_GAMMA_CFG, cmdq_pkt); }
void mtk_gamma_start(struct device *dev) @@ -172,8 +173,13 @@ static int mtk_disp_gamma_remove(struct platform_device *pdev) return 0; }
+static const struct mtk_disp_gamma_data mt8173_gamma_driver_data = { + .has_dither = true, +}; + static const struct of_device_id mtk_disp_gamma_driver_dt_match[] = { - { .compatible = "mediatek,mt8173-disp-gamma"}, + { .compatible = "mediatek,mt8173-disp-gamma", + .data = &mt8173_gamma_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_gamma_driver_dt_match);
From: Yongqiang Niu yongqiang.niu@mediatek.com
for 5 or 6 bpc panel, we need enable dither function to improve the display quality
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 ++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 8173f709272be..e85625704d611 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -53,7 +53,9 @@ #define DITHER_EN BIT(0) #define DISP_DITHER_CFG 0x0020 #define DITHER_RELAY_MODE BIT(0) +#define DITHER_ENGINE_EN BIT(1) #define DISP_DITHER_SIZE 0x0030 +#define DITHER_REG(idx) (0x100 + (idx) * 4)
#define LUT_10BIT_MASK 0x03ff
@@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev, unsigned int w, { struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+ bool enable = false; + + /* default value for dither reg 5 to 14 */ + const u32 dither_setting[] = { + 0x00000000, /* 5 */ + 0x00003002, /* 6 */ + 0x00000000, /* 7 */ + 0x00000000, /* 8 */ + 0x00000000, /* 9 */ + 0x00000000, /* 10 */ + 0x00000000, /* 11 */ + 0x00000011, /* 12 */ + 0x00000000, /* 13 */ + 0x00000000, /* 14 */ + }; + + if (bpc == 5 || bpc == 6) { + enable = true; + mtk_ddp_write(cmdq_pkt, + DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | + DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | + DITHER_NEW_BIT_MODE, + &priv->cmdq_reg, priv->regs, DITHER_REG(15)); + mtk_ddp_write(cmdq_pkt, + DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | + DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | + DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | + DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc), + &priv->cmdq_reg, priv->regs, DITHER_REG(16)); + } + + + if (enable) { + u32 idx; + + for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++) + mtk_ddp_write(cmdq_pkt, dither_setting[idx], &priv->cmdq_reg, priv->regs, + DITHER_REG(idx + 5)); + } + mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE); - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); + mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); }
static void mtk_dither_start(struct device *dev)
Hi, Hsin-Yi:
On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote:
From: Yongqiang Niu yongqiang.niu@mediatek.com
for 5 or 6 bpc panel, we need enable dither function to improve the display quality
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 ++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 8173f709272be..e85625704d611 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -53,7 +53,9 @@ #define DITHER_EN BIT(0) #define DISP_DITHER_CFG 0x0020 #define DITHER_RELAY_MODE BIT(0) +#define DITHER_ENGINE_EN BIT(1) #define DISP_DITHER_SIZE 0x0030 +#define DITHER_REG(idx) (0x100 + (idx) * 4)
#define LUT_10BIT_MASK 0x03ff
@@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev, unsigned int w, { struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
- bool enable = false;
- /* default value for dither reg 5 to 14 */
- const u32 dither_setting[] = {
0x00000000, /* 5 */0x00003002, /* 6 */0x00000000, /* 7 */0x00000000, /* 8 */0x00000000, /* 9 */0x00000000, /* 10 */0x00000000, /* 11 */0x00000011, /* 12 */0x00000000, /* 13 */0x00000000, /* 14 */
Could you explain what is this?
- };
- if (bpc == 5 || bpc == 6) {
enable = true;mtk_ddp_write(cmdq_pkt,DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |DITHER_NEW_BIT_MODE,&priv->cmdq_reg, priv->regs, DITHER_REG(15));mtk_ddp_write(cmdq_pkt,DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
This result in 0x50505050, but previous version is 0x50504040, so this version is correct and previous version is incorrect?
Regards, CK
&priv->cmdq_reg, priv->regs, DITHER_REG(16));- }
- if (enable) {
u32 idx;for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++)mtk_ddp_write(cmdq_pkt, dither_setting[idx], &priv->cmdq_reg, priv->regs,DITHER_REG(idx + 5));- }
- mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE);
- mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);
mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);}
static void mtk_dither_start(struct device *dev)
On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote:
Hi, Hsin-Yi:
On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote:
From: Yongqiang Niu yongqiang.niu@mediatek.com
for 5 or 6 bpc panel, we need enable dither function to improve the display quality
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 ++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 8173f709272be..e85625704d611 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -53,7 +53,9 @@ #define DITHER_EN BIT(0) #define DISP_DITHER_CFG 0x0020 #define DITHER_RELAY_MODE BIT(0) +#define DITHER_ENGINE_EN BIT(1) #define DISP_DITHER_SIZE 0x0030 +#define DITHER_REG(idx) (0x100 + (idx) * 4)
#define LUT_10BIT_MASK 0x03ff
@@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev, unsigned int w, { struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
- bool enable = false;
- /* default value for dither reg 5 to 14 */
- const u32 dither_setting[] = {
0x00000000, /* 5 */0x00003002, /* 6 */0x00000000, /* 7 */0x00000000, /* 8 */0x00000000, /* 9 */0x00000000, /* 10 */0x00000000, /* 11 */0x00000011, /* 12 */0x00000000, /* 13 */0x00000000, /* 14 */Could you explain what is this?
this is dither 5 to dither 14 setting this will be useless, we just need set dither 5 and dither 7 like mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5); mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7); other value is same with hardware default value.
- };
- if (bpc == 5 || bpc == 6) {
enable = true;mtk_ddp_write(cmdq_pkt,DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |DITHER_NEW_BIT_MODE,&priv->cmdq_reg, priv->regs, DITHER_REG(15));mtk_ddp_write(cmdq_pkt,DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),This result in 0x50505050, but previous version is 0x50504040, so this version is correct and previous version is incorrect?
the new version set r g b 3 channel same, seams more reasonable
Regards, CK
&priv->cmdq_reg, priv->regs, DITHER_REG(16));- }
- if (enable) {
u32 idx;for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++)mtk_ddp_write(cmdq_pkt, dither_setting[idx], &priv->cmdq_reg, priv->regs,DITHER_REG(idx + 5));- }
- mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE);
- mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);
mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);}
static void mtk_dither_start(struct device *dev)
On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote:
On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote:
Hi, Hsin-Yi:
On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote:
From: Yongqiang Niu yongqiang.niu@mediatek.com
for 5 or 6 bpc panel, we need enable dither function to improve the display quality
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 ++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 8173f709272be..e85625704d611 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -53,7 +53,9 @@ #define DITHER_EN BIT(0) #define DISP_DITHER_CFG 0x0020 #define DITHER_RELAY_MODE BIT(0) +#define DITHER_ENGINE_EN BIT(1) #define DISP_DITHER_SIZE 0x0030 +#define DITHER_REG(idx) (0x100 + (idx) * 4)
#define LUT_10BIT_MASK 0x03ff
@@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev, unsigned int w, { struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
- bool enable = false;
- /* default value for dither reg 5 to 14 */
- const u32 dither_setting[] = {
0x00000000, /* 5 */0x00003002, /* 6 */0x00000000, /* 7 */0x00000000, /* 8 */0x00000000, /* 9 */0x00000000, /* 10 */0x00000000, /* 11 */0x00000011, /* 12 */0x00000000, /* 13 */0x00000000, /* 14 */Could you explain what is this?
this is dither 5 to dither 14 setting this will be useless, we just need set dither 5 and dither 7 like mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5); mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7); other value is same with hardware default value.
- };
- if (bpc == 5 || bpc == 6) {
enable = true;mtk_ddp_write(cmdq_pkt,DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |DITHER_NEW_BIT_MODE,&priv->cmdq_reg, priv->regs, DITHER_REG(15));mtk_ddp_write(cmdq_pkt,DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),This result in 0x50505050, but previous version is 0x50504040, so this version is correct and previous version is incorrect?
the new version set r g b 3 channel same, seams more reasonable
So all the setting of DISP_DITHER_5, DISP_DITHER_7, DISP_DITHER_15, DISP_DITHER_16 is identical to mtk_dither_set(), so call mtk_dither_set() instead of duplication here.
Regards, CK
Regards, CK
&priv->cmdq_reg, priv->regs, DITHER_REG(16));- }
- if (enable) {
u32 idx;for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++)mtk_ddp_write(cmdq_pkt, dither_setting[idx], &priv->cmdq_reg, priv->regs,DITHER_REG(idx + 5));- }
- mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE);
- mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);
mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);}
static void mtk_dither_start(struct device *dev)
On Thu, 2021-01-28 at 16:07 +0800, CK Hu wrote:
On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote:
On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote:
Hi, Hsin-Yi:
On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote:
From: Yongqiang Niu yongqiang.niu@mediatek.com
for 5 or 6 bpc panel, we need enable dither function to improve the display quality
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 ++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 8173f709272be..e85625704d611 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -53,7 +53,9 @@ #define DITHER_EN BIT(0) #define DISP_DITHER_CFG 0x0020 #define DITHER_RELAY_MODE BIT(0) +#define DITHER_ENGINE_EN BIT(1) #define DISP_DITHER_SIZE 0x0030 +#define DITHER_REG(idx) (0x100 + (idx) * 4)
#define LUT_10BIT_MASK 0x03ff
@@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev, unsigned int w, { struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
- bool enable = false;
- /* default value for dither reg 5 to 14 */
- const u32 dither_setting[] = {
0x00000000, /* 5 */0x00003002, /* 6 */0x00000000, /* 7 */0x00000000, /* 8 */0x00000000, /* 9 */0x00000000, /* 10 */0x00000000, /* 11 */0x00000011, /* 12 */0x00000000, /* 13 */0x00000000, /* 14 */Could you explain what is this?
this is dither 5 to dither 14 setting this will be useless, we just need set dither 5 and dither 7 like mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5); mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7); other value is same with hardware default value.
- };
- if (bpc == 5 || bpc == 6) {
enable = true;mtk_ddp_write(cmdq_pkt,DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |DITHER_NEW_BIT_MODE,&priv->cmdq_reg, priv->regs, DITHER_REG(15));mtk_ddp_write(cmdq_pkt,DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),This result in 0x50505050, but previous version is 0x50504040, so this version is correct and previous version is incorrect?
the new version set r g b 3 channel same, seams more reasonable
So all the setting of DISP_DITHER_5, DISP_DITHER_7, DISP_DITHER_15, DISP_DITHER_16 is identical to mtk_dither_set(), so call mtk_dither_set() instead of duplication here.
dither enable set in mtk_dither_set is mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, CFG);
that is different 8183 and mt8192. mt8173 dither enable in gamma is bit2 mt8183 and mt8192 dither engine enable is bit 1
Regards, CK
Regards, CK
&priv->cmdq_reg, priv->regs, DITHER_REG(16));- }
- if (enable) {
u32 idx;for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++)mtk_ddp_write(cmdq_pkt, dither_setting[idx], &priv->cmdq_reg, priv->regs,DITHER_REG(idx + 5));- }
- mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE);
- mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);
mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);}
static void mtk_dither_start(struct device *dev)
On Thu, Jan 28, 2021 at 4:10 PM Yongqiang Niu yongqiang.niu@mediatek.com wrote:
On Thu, 2021-01-28 at 16:07 +0800, CK Hu wrote:
On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote:
On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote:
Hi, Hsin-Yi:
On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote:
From: Yongqiang Niu yongqiang.niu@mediatek.com
for 5 or 6 bpc panel, we need enable dither function to improve the display quality
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 ++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 8173f709272be..e85625704d611 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -53,7 +53,9 @@ #define DITHER_EN BIT(0) #define DISP_DITHER_CFG 0x0020 #define DITHER_RELAY_MODE BIT(0) +#define DITHER_ENGINE_EN BIT(1) #define DISP_DITHER_SIZE 0x0030 +#define DITHER_REG(idx) (0x100 + (idx) * 4)
#define LUT_10BIT_MASK 0x03ff
@@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev, unsigned int w, { struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
bool enable = false;/* default value for dither reg 5 to 14 */const u32 dither_setting[] = {0x00000000, /* 5 */0x00003002, /* 6 */0x00000000, /* 7 */0x00000000, /* 8 */0x00000000, /* 9 */0x00000000, /* 10 */0x00000000, /* 11 */0x00000011, /* 12 */0x00000000, /* 13 */0x00000000, /* 14 */Could you explain what is this?
this is dither 5 to dither 14 setting this will be useless, we just need set dither 5 and dither 7 like mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5); mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7); other value is same with hardware default value.
};if (bpc == 5 || bpc == 6) {enable = true;mtk_ddp_write(cmdq_pkt,DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |DITHER_NEW_BIT_MODE,&priv->cmdq_reg, priv->regs, DITHER_REG(15));mtk_ddp_write(cmdq_pkt,DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),This result in 0x50505050, but previous version is 0x50504040, so this version is correct and previous version is incorrect?
the new version set r g b 3 channel same, seams more reasonable
So all the setting of DISP_DITHER_5, DISP_DITHER_7, DISP_DITHER_15, DISP_DITHER_16 is identical to mtk_dither_set(), so call mtk_dither_set() instead of duplication here.
dither enable set in mtk_dither_set is mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, CFG);
that is different 8183 and mt8192. mt8173 dither enable in gamma is bit2 mt8183 and mt8192 dither engine enable is bit 1
We can still call mtk_dither_set() for bpc is 5 or 6 here, though it will be set to bit2, but later in mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); it will be correct back to bit 1.
Is this reasonable?
Regards, CK
Regards, CK
&priv->cmdq_reg, priv->regs, DITHER_REG(16));}if (enable) {u32 idx;for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++)mtk_ddp_write(cmdq_pkt, dither_setting[idx], &priv->cmdq_reg, priv->regs,DITHER_REG(idx + 5));}mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE);
mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);
mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);}
static void mtk_dither_start(struct device *dev)
On Thu, 2021-01-28 at 16:18 +0800, Hsin-Yi Wang wrote:
On Thu, Jan 28, 2021 at 4:10 PM Yongqiang Niu yongqiang.niu@mediatek.com wrote:
On Thu, 2021-01-28 at 16:07 +0800, CK Hu wrote:
On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote:
On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote:
Hi, Hsin-Yi:
On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote:
From: Yongqiang Niu yongqiang.niu@mediatek.com
for 5 or 6 bpc panel, we need enable dither function to improve the display quality
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 ++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 8173f709272be..e85625704d611 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -53,7 +53,9 @@ #define DITHER_EN BIT(0) #define DISP_DITHER_CFG 0x0020 #define DITHER_RELAY_MODE BIT(0) +#define DITHER_ENGINE_EN BIT(1) #define DISP_DITHER_SIZE 0x0030 +#define DITHER_REG(idx) (0x100 + (idx) * 4)
#define LUT_10BIT_MASK 0x03ff
@@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev, unsigned int w, { struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
bool enable = false;/* default value for dither reg 5 to 14 */const u32 dither_setting[] = {0x00000000, /* 5 */0x00003002, /* 6 */0x00000000, /* 7 */0x00000000, /* 8 */0x00000000, /* 9 */0x00000000, /* 10 */0x00000000, /* 11 */0x00000011, /* 12 */0x00000000, /* 13 */0x00000000, /* 14 */Could you explain what is this?
this is dither 5 to dither 14 setting this will be useless, we just need set dither 5 and dither 7 like mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5); mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7); other value is same with hardware default value.
};if (bpc == 5 || bpc == 6) {enable = true;mtk_ddp_write(cmdq_pkt,DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |DITHER_NEW_BIT_MODE,&priv->cmdq_reg, priv->regs, DITHER_REG(15));mtk_ddp_write(cmdq_pkt,DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),This result in 0x50505050, but previous version is 0x50504040, so this version is correct and previous version is incorrect?
the new version set r g b 3 channel same, seams more reasonable
So all the setting of DISP_DITHER_5, DISP_DITHER_7, DISP_DITHER_15, DISP_DITHER_16 is identical to mtk_dither_set(), so call mtk_dither_set() instead of duplication here.
dither enable set in mtk_dither_set is mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, CFG);
that is different 8183 and mt8192. mt8173 dither enable in gamma is bit2 mt8183 and mt8192 dither engine enable is bit 1
We can still call mtk_dither_set() for bpc is 5 or 6 here, though it will be set to bit2, but later in mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); it will be correct back to bit 1.
Is this reasonable?
the result is ok.
Regards, CK
Regards, CK
&priv->cmdq_reg, priv->regs, DITHER_REG(16));}if (enable) {u32 idx;for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++)mtk_ddp_write(cmdq_pkt, dither_setting[idx], &priv->cmdq_reg, priv->regs,DITHER_REG(idx + 5));}mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE);
mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);
mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);}
static void mtk_dither_start(struct device *dev)
On Thu, 2021-01-28 at 16:18 +0800, Hsin-Yi Wang wrote:
On Thu, Jan 28, 2021 at 4:10 PM Yongqiang Niu yongqiang.niu@mediatek.com wrote:
On Thu, 2021-01-28 at 16:07 +0800, CK Hu wrote:
On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote:
On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote:
Hi, Hsin-Yi:
On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote:
From: Yongqiang Niu yongqiang.niu@mediatek.com
for 5 or 6 bpc panel, we need enable dither function to improve the display quality
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 ++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 8173f709272be..e85625704d611 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -53,7 +53,9 @@ #define DITHER_EN BIT(0) #define DISP_DITHER_CFG 0x0020 #define DITHER_RELAY_MODE BIT(0) +#define DITHER_ENGINE_EN BIT(1) #define DISP_DITHER_SIZE 0x0030 +#define DITHER_REG(idx) (0x100 + (idx) * 4)
#define LUT_10BIT_MASK 0x03ff
@@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev, unsigned int w, { struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
bool enable = false;/* default value for dither reg 5 to 14 */const u32 dither_setting[] = {0x00000000, /* 5 */0x00003002, /* 6 */0x00000000, /* 7 */0x00000000, /* 8 */0x00000000, /* 9 */0x00000000, /* 10 */0x00000000, /* 11 */0x00000011, /* 12 */0x00000000, /* 13 */0x00000000, /* 14 */Could you explain what is this?
this is dither 5 to dither 14 setting this will be useless, we just need set dither 5 and dither 7 like mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5); mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7); other value is same with hardware default value.
};if (bpc == 5 || bpc == 6) {enable = true;mtk_ddp_write(cmdq_pkt,DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |DITHER_NEW_BIT_MODE,&priv->cmdq_reg, priv->regs, DITHER_REG(15));mtk_ddp_write(cmdq_pkt,DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),This result in 0x50505050, but previous version is 0x50504040, so this version is correct and previous version is incorrect?
the new version set r g b 3 channel same, seams more reasonable
So all the setting of DISP_DITHER_5, DISP_DITHER_7, DISP_DITHER_15, DISP_DITHER_16 is identical to mtk_dither_set(), so call mtk_dither_set() instead of duplication here.
dither enable set in mtk_dither_set is mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, CFG);
that is different 8183 and mt8192. mt8173 dither enable in gamma is bit2 mt8183 and mt8192 dither engine enable is bit 1
We can still call mtk_dither_set() for bpc is 5 or 6 here, though it will be set to bit2, but later in mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); it will be correct back to bit 1.
Is this reasonable?
Looks weird. Maybe pass some information into mtk_dither_set() to set DISP_DITHERING correctly.
I find one thing need to be fixed. CFG should be lower case.
Regards, CK
Regards, CK
Regards, CK
&priv->cmdq_reg, priv->regs, DITHER_REG(16));}if (enable) {u32 idx;for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++)mtk_ddp_write(cmdq_pkt, dither_setting[idx], &priv->cmdq_reg, priv->regs,DITHER_REG(idx + 5));}mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE);
mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);
mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);}
static void mtk_dither_start(struct device *dev)
On Thu, 2021-01-28 at 16:28 +0800, CK Hu wrote:
On Thu, 2021-01-28 at 16:18 +0800, Hsin-Yi Wang wrote:
On Thu, Jan 28, 2021 at 4:10 PM Yongqiang Niu yongqiang.niu@mediatek.com wrote:
On Thu, 2021-01-28 at 16:07 +0800, CK Hu wrote:
On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote:
On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote:
Hi, Hsin-Yi:
On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote: > From: Yongqiang Niu yongqiang.niu@mediatek.com > > for 5 or 6 bpc panel, we need enable dither function > to improve the display quality > > Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com > Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 ++++++++++++++++++++- > 1 file changed, 43 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index 8173f709272be..e85625704d611 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -53,7 +53,9 @@ > #define DITHER_EN BIT(0) > #define DISP_DITHER_CFG 0x0020 > #define DITHER_RELAY_MODE BIT(0) > +#define DITHER_ENGINE_EN BIT(1) > #define DISP_DITHER_SIZE 0x0030 > +#define DITHER_REG(idx) (0x100 + (idx) * 4) > > #define LUT_10BIT_MASK 0x03ff > > @@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev, unsigned int w, > { > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > > + bool enable = false; > + > + /* default value for dither reg 5 to 14 */ > + const u32 dither_setting[] = { > + 0x00000000, /* 5 */ > + 0x00003002, /* 6 */ > + 0x00000000, /* 7 */ > + 0x00000000, /* 8 */ > + 0x00000000, /* 9 */ > + 0x00000000, /* 10 */ > + 0x00000000, /* 11 */ > + 0x00000011, /* 12 */ > + 0x00000000, /* 13 */ > + 0x00000000, /* 14 */
Could you explain what is this?
this is dither 5 to dither 14 setting this will be useless, we just need set dither 5 and dither 7 like mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5); mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7); other value is same with hardware default value.
> + }; > + > + if (bpc == 5 || bpc == 6) { > + enable = true; > + mtk_ddp_write(cmdq_pkt, > + DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | > + DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | > + DITHER_NEW_BIT_MODE, > + &priv->cmdq_reg, priv->regs, DITHER_REG(15)); > + mtk_ddp_write(cmdq_pkt, > + DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | > + DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | > + DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | > + DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
This result in 0x50505050, but previous version is 0x50504040, so this version is correct and previous version is incorrect?
the new version set r g b 3 channel same, seams more reasonable
So all the setting of DISP_DITHER_5, DISP_DITHER_7, DISP_DITHER_15, DISP_DITHER_16 is identical to mtk_dither_set(), so call mtk_dither_set() instead of duplication here.
dither enable set in mtk_dither_set is mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, CFG);
that is different 8183 and mt8192. mt8173 dither enable in gamma is bit2 mt8183 and mt8192 dither engine enable is bit 1
We can still call mtk_dither_set() for bpc is 5 or 6 here, though it will be set to bit2, but later in mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); it will be correct back to bit 1.
Is this reasonable?
Looks weird. Maybe pass some information into mtk_dither_set() to set DISP_DITHERING correctly.
I find one thing need to be fixed. CFG should be lower case.
we could modify this like this:
void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc, unsigned int cfg, u32 dither_enable, struct cmdq_pkt *cmdq_pkt)
mtk_ddp_write(cmdq_pkt, dither_enable, comp, cfg);
Regards, CK
Regards, CK
Regards, CK
> + &priv->cmdq_reg, priv->regs, DITHER_REG(16)); > + } > + > + > + if (enable) { > + u32 idx; > + > + for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++) > + mtk_ddp_write(cmdq_pkt, dither_setting[idx], &priv->cmdq_reg, priv->regs, > + DITHER_REG(idx + 5)); > + } > + > mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE); > - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > + mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > } > > static void mtk_dither_start(struct device *dev)
On Thu, Jan 28, 2021 at 4:32 PM Yongqiang Niu yongqiang.niu@mediatek.com wrote:
On Thu, 2021-01-28 at 16:28 +0800, CK Hu wrote:
On Thu, 2021-01-28 at 16:18 +0800, Hsin-Yi Wang wrote:
On Thu, Jan 28, 2021 at 4:10 PM Yongqiang Niu yongqiang.niu@mediatek.com wrote:
On Thu, 2021-01-28 at 16:07 +0800, CK Hu wrote:
On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote:
On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote: > Hi, Hsin-Yi: > > On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote: > > From: Yongqiang Niu yongqiang.niu@mediatek.com > > > > for 5 or 6 bpc panel, we need enable dither function > > to improve the display quality > > > > Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com > > Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org > > --- > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 ++++++++++++++++++++- > > 1 file changed, 43 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > index 8173f709272be..e85625704d611 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > @@ -53,7 +53,9 @@ > > #define DITHER_EN BIT(0) > > #define DISP_DITHER_CFG 0x0020 > > #define DITHER_RELAY_MODE BIT(0) > > +#define DITHER_ENGINE_EN BIT(1) > > #define DISP_DITHER_SIZE 0x0030 > > +#define DITHER_REG(idx) (0x100 + (idx) * 4) > > > > #define LUT_10BIT_MASK 0x03ff > > > > @@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev, unsigned int w, > > { > > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > > > > + bool enable = false; > > + > > + /* default value for dither reg 5 to 14 */ > > + const u32 dither_setting[] = { > > + 0x00000000, /* 5 */ > > + 0x00003002, /* 6 */ > > + 0x00000000, /* 7 */ > > + 0x00000000, /* 8 */ > > + 0x00000000, /* 9 */ > > + 0x00000000, /* 10 */ > > + 0x00000000, /* 11 */ > > + 0x00000011, /* 12 */ > > + 0x00000000, /* 13 */ > > + 0x00000000, /* 14 */ > > Could you explain what is this?
this is dither 5 to dither 14 setting this will be useless, we just need set dither 5 and dither 7 like mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5); mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7); other value is same with hardware default value.
> > > + }; > > + > > + if (bpc == 5 || bpc == 6) { > > + enable = true; > > + mtk_ddp_write(cmdq_pkt, > > + DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | > > + DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | > > + DITHER_NEW_BIT_MODE, > > + &priv->cmdq_reg, priv->regs, DITHER_REG(15)); > > + mtk_ddp_write(cmdq_pkt, > > + DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | > > + DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | > > + DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | > > + DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc), > > This result in 0x50505050, but previous version is 0x50504040, so this > version is correct and previous version is incorrect?
the new version set r g b 3 channel same, seams more reasonable
So all the setting of DISP_DITHER_5, DISP_DITHER_7, DISP_DITHER_15, DISP_DITHER_16 is identical to mtk_dither_set(), so call mtk_dither_set() instead of duplication here.
dither enable set in mtk_dither_set is mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, CFG);
that is different 8183 and mt8192. mt8173 dither enable in gamma is bit2 mt8183 and mt8192 dither engine enable is bit 1
We can still call mtk_dither_set() for bpc is 5 or 6 here, though it will be set to bit2, but later in mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); it will be correct back to bit 1.
Is this reasonable?
Looks weird. Maybe pass some information into mtk_dither_set() to set DISP_DITHERING correctly.
I find one thing need to be fixed. CFG should be lower case.
we could modify this like this:
void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc, unsigned int cfg, u32 dither_enable, struct cmdq_pkt *cmdq_pkt)
mtk_ddp_write(cmdq_pkt, dither_enable, comp, cfg);
Thanks, I'll add another flag to mtk_dither_set_common.
Regards, CK
Regards, CK
> > Regards, > CK > > > + &priv->cmdq_reg, priv->regs, DITHER_REG(16)); > > + } > > + > > + > > + if (enable) { > > + u32 idx; > > + > > + for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++) > > + mtk_ddp_write(cmdq_pkt, dither_setting[idx], &priv->cmdq_reg, priv->regs, > > + DITHER_REG(idx + 5)); > > + } > > + > > mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE); > > - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > + mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > } > > > > static void mtk_dither_start(struct device *dev) > >
From: Yongqiang Niu yongqiang.niu@mediatek.com
Add mtk mutex support for MT8183 SoC.
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org --- drivers/soc/mediatek/mtk-mutex.c | 50 ++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index f531b119da7a9..b348f962f82a4 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -14,6 +14,8 @@
#define MT2701_MUTEX0_MOD0 0x2c #define MT2701_MUTEX0_SOF0 0x30 +#define MT8183_DISP_MUTEX0_MOD0 0x30 +#define MT8183_DISP_MUTEX0_SOF0 0x2c
#define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) @@ -37,6 +39,18 @@ #define MT8167_MUTEX_MOD_DISP_DITHER 15 #define MT8167_MUTEX_MOD_DISP_UFOE 16
+#define MT8183_MUTEX_MOD_DISP_RDMA0 0 +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 +#define MT8183_MUTEX_MOD_DISP_OVL0 9 +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 +#define MT8183_MUTEX_MOD_DISP_AAL0 15 +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 + #define MT8173_MUTEX_MOD_DISP_OVL0 11 #define MT8173_MUTEX_MOD_DISP_OVL1 12 #define MT8173_MUTEX_MOD_DISP_RDMA0 13 @@ -87,6 +101,11 @@ #define MT2712_MUTEX_SOF_DSI3 6 #define MT8167_MUTEX_SOF_DPI0 2 #define MT8167_MUTEX_SOF_DPI1 3 +#define MT8183_MUTEX_SOF_DSI0 1 +#define MT8183_MUTEX_SOF_DPI0 2 + +#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6) +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
struct mtk_mutex { int id; @@ -181,6 +200,20 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, };
+static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, +}; + static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, @@ -198,6 +231,13 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = { [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1, };
+/* Add EOF setting so overlay hardware can receive frame done irq */ +static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = { + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, + [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, + [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, +}; + static const struct mtk_mutex_data mt2701_mutex_driver_data = { .mutex_mod = mt2701_mutex_mod, .mutex_sof = mt2712_mutex_sof, @@ -227,6 +267,14 @@ static const struct mtk_mutex_data mt8173_mutex_driver_data = { .mutex_sof_reg = MT2701_MUTEX0_SOF0, };
+static const struct mtk_mutex_data mt8183_mutex_driver_data = { + .mutex_mod = mt8183_mutex_mod, + .mutex_sof = mt8183_mutex_sof, + .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0, + .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0, + .no_clk = true, +}; + struct mtk_mutex *mtk_mutex_get(struct device *dev) { struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); @@ -457,6 +505,8 @@ static const struct of_device_id mutex_driver_dt_match[] = { .data = &mt8167_mutex_driver_data}, { .compatible = "mediatek,mt8173-disp-mutex", .data = &mt8173_mutex_driver_data}, + { .compatible = "mediatek,mt8183-disp-mutex", + .data = &mt8183_mutex_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
Hi, Hsin-Yi:
On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote:
From: Yongqiang Niu yongqiang.niu@mediatek.com
Add mtk mutex support for MT8183 SoC.
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org
drivers/soc/mediatek/mtk-mutex.c | 50 ++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index f531b119da7a9..b348f962f82a4 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -14,6 +14,8 @@
#define MT2701_MUTEX0_MOD0 0x2c #define MT2701_MUTEX0_SOF0 0x30 +#define MT8183_DISP_MUTEX0_MOD0 0x30 +#define MT8183_DISP_MUTEX0_SOF0 0x2c
Modify 'DISP_MUTEX' to 'MUTEX'
Regards, CK
#define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) @@ -37,6 +39,18 @@ #define MT8167_MUTEX_MOD_DISP_DITHER 15 #define MT8167_MUTEX_MOD_DISP_UFOE 16
+#define MT8183_MUTEX_MOD_DISP_RDMA0 0 +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 +#define MT8183_MUTEX_MOD_DISP_OVL0 9 +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 +#define MT8183_MUTEX_MOD_DISP_AAL0 15 +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 +#define MT8183_MUTEX_MOD_DISP_DITHER0 17
#define MT8173_MUTEX_MOD_DISP_OVL0 11 #define MT8173_MUTEX_MOD_DISP_OVL1 12 #define MT8173_MUTEX_MOD_DISP_RDMA0 13 @@ -87,6 +101,11 @@ #define MT2712_MUTEX_SOF_DSI3 6 #define MT8167_MUTEX_SOF_DPI0 2 #define MT8167_MUTEX_SOF_DPI1 3 +#define MT8183_MUTEX_SOF_DSI0 1 +#define MT8183_MUTEX_SOF_DPI0 2
+#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6) +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
struct mtk_mutex { int id; @@ -181,6 +200,20 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, };
+static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
- [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
- [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
- [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
- [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
- [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
- [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
- [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
- [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L,
- [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0,
- [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1,
- [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
+};
static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, @@ -198,6 +231,13 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = { [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1, };
+/* Add EOF setting so overlay hardware can receive frame done irq */ +static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
- [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
- [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
- [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
+};
static const struct mtk_mutex_data mt2701_mutex_driver_data = { .mutex_mod = mt2701_mutex_mod, .mutex_sof = mt2712_mutex_sof, @@ -227,6 +267,14 @@ static const struct mtk_mutex_data mt8173_mutex_driver_data = { .mutex_sof_reg = MT2701_MUTEX0_SOF0, };
+static const struct mtk_mutex_data mt8183_mutex_driver_data = {
- .mutex_mod = mt8183_mutex_mod,
- .mutex_sof = mt8183_mutex_sof,
- .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0,
- .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0,
- .no_clk = true,
+};
struct mtk_mutex *mtk_mutex_get(struct device *dev) { struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); @@ -457,6 +505,8 @@ static const struct of_device_id mutex_driver_dt_match[] = { .data = &mt8167_mutex_driver_data}, { .compatible = "mediatek,mt8173-disp-mutex", .data = &mt8173_mutex_driver_data},
- { .compatible = "mediatek,mt8183-disp-mutex",
.data = &mt8183_mutex_driver_data},}; MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
From: Yongqiang Niu yongqiang.niu@mediatek.com
1. add ovl private data 2. add rdma private data 3. add gamma privte data 4. add main and external path module for crtc create
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 1 + drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 +++++++++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 45 +++++++++++++++++++++++ 4 files changed, 70 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 22199ef11f65d..16f73267bb202 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -180,6 +180,7 @@ static const struct mtk_disp_gamma_data mt8173_gamma_driver_data = { static const struct of_device_id mtk_disp_gamma_driver_dt_match[] = { { .compatible = "mediatek,mt8173-disp-gamma", .data = &mt8173_gamma_driver_data}, + { .compatible = "mediatek,mt8183-disp-gamma"}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_gamma_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 1c295c58a5e82..da7e38a28759b 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -424,11 +424,29 @@ static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = { .fmt_rgb565_is_0 = true, };
+static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = { + .addr = DISP_REG_OVL_ADDR_MT8173, + .gmc_bits = 10, + .layer_nr = 4, + .fmt_rgb565_is_0 = true, +}; + +static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { + .addr = DISP_REG_OVL_ADDR_MT8173, + .gmc_bits = 10, + .layer_nr = 2, + .fmt_rgb565_is_0 = true, +}; + static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-ovl", .data = &mt2701_ovl_driver_data}, { .compatible = "mediatek,mt8173-disp-ovl", .data = &mt8173_ovl_driver_data}, + { .compatible = "mediatek,mt8183-disp-ovl", + .data = &mt8183_ovl_driver_data}, + { .compatible = "mediatek,mt8183-disp-ovl-2l", + .data = &mt8183_ovl_2l_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 04b9542010b00..29fa5f3a05c30 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -355,11 +355,17 @@ static const struct mtk_disp_rdma_data mt8173_rdma_driver_data = { .fifo_size = SZ_8K, };
+static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { + .fifo_size = 5 * SZ_1K, +}; + static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-rdma", .data = &mt2701_rdma_driver_data}, { .compatible = "mediatek,mt8173-disp-rdma", .data = &mt8173_rdma_driver_data}, + { .compatible = "mediatek,mt8183-disp-rdma", + .data = &mt8183_rdma_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 279d3e6f11563..486e73e675ad5 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -129,6 +129,24 @@ static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = { DDP_COMPONENT_DPI0, };
+static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = { + DDP_COMPONENT_OVL0, + DDP_COMPONENT_OVL_2L0, + DDP_COMPONENT_RDMA0, + DDP_COMPONENT_COLOR0, + DDP_COMPONENT_CCORR, + DDP_COMPONENT_AAL0, + DDP_COMPONENT_GAMMA, + DDP_COMPONENT_DITHER, + DDP_COMPONENT_DSI0, +}; + +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { + DDP_COMPONENT_OVL_2L1, + DDP_COMPONENT_RDMA1, + DDP_COMPONENT_DPI0, +}; + static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .main_path = mt2701_mtk_ddp_main, .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), @@ -161,6 +179,13 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), };
+static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { + .main_path = mt8183_mtk_ddp_main, + .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main), + .ext_path = mt8183_mtk_ddp_ext, + .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), +}; + static int mtk_drm_kms_init(struct drm_device *drm) { struct mtk_drm_private *private = drm->dev_private; @@ -375,12 +400,20 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_OVL }, { .compatible = "mediatek,mt8173-disp-ovl", .data = (void *)MTK_DISP_OVL }, + { .compatible = "mediatek,mt8183-disp-ovl", + .data = (void *)MTK_DISP_OVL }, + { .compatible = "mediatek,mt8183-disp-ovl-2l", + .data = (void *)MTK_DISP_OVL_2L }, { .compatible = "mediatek,mt2701-disp-rdma", .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-rdma", .data = (void *)MTK_DISP_RDMA }, + { .compatible = "mediatek,mt8183-disp-rdma", + .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-wdma", .data = (void *)MTK_DISP_WDMA }, + { .compatible = "mediatek,mt8183-disp-ccorr", + .data = (void *)MTK_DISP_CCORR }, { .compatible = "mediatek,mt2701-disp-color", .data = (void *)MTK_DISP_COLOR }, { .compatible = "mediatek,mt8173-disp-color", @@ -389,22 +422,32 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_AAL}, { .compatible = "mediatek,mt8173-disp-gamma", .data = (void *)MTK_DISP_GAMMA, }, + { .compatible = "mediatek,mt8183-disp-gamma", + .data = (void *)MTK_DISP_GAMMA, }, + { .compatible = "mediatek,mt8183-disp-dither", + .data = (void *)MTK_DISP_DITHER }, { .compatible = "mediatek,mt8173-disp-ufoe", .data = (void *)MTK_DISP_UFOE }, { .compatible = "mediatek,mt2701-dsi", .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt8173-dsi", .data = (void *)MTK_DSI }, + { .compatible = "mediatek,mt8183-dsi", + .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt2701-dpi", .data = (void *)MTK_DPI }, { .compatible = "mediatek,mt8173-dpi", .data = (void *)MTK_DPI }, + { .compatible = "mediatek,mt8183-dpi", + .data = (void *)MTK_DPI }, { .compatible = "mediatek,mt2701-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt2712-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8173-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, + { .compatible = "mediatek,mt8183-disp-mutex", + .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_BLS }, { .compatible = "mediatek,mt8173-disp-pwm", @@ -423,6 +466,8 @@ static const struct of_device_id mtk_drm_of_ids[] = { .data = &mt2712_mmsys_driver_data}, { .compatible = "mediatek,mt8173-mmsys", .data = &mt8173_mmsys_driver_data}, + { .compatible = "mediatek,mt8183-mmsys", + .data = &mt8183_mmsys_driver_data}, { } };
dri-devel@lists.freedesktop.org
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CK Hu -
Enric Balletbo Serra -
Hsin-Yi Wang -
Yongqiang Niu