For various revisions of a chipset if the signal pattern is changed for every revision, then the phy setting need to be updated correspondingly by measuring the signal. For getting correct signals the clock level and data de-emphasis levels needs to be adjusted. Since only these 2 values matter,we can move the same to dt, wherein we can have different dt files for every revision.
This is an initial patchset towards achieving the same for exynos 5250 and can be later extended to future chipsets.
V2: replaced moving of entire phy config structure with only required and justifiable conf registers.
V3: Incorporated Mark Rutland's comments.
V4: Rebased and included cros5250-common.dtsi.
V5: removed nr-configs feild and also the constraint of having the exact number of configs in the dt file as in the driver, the programmer can add only the pixel clock that needs to be updated.
V6: V7: removed nr-configs form the dtsi files.
V8: Fixed build error
Shirish S (4): ARM: dts: smdk5250: Add hdmi phy settings ARM: dts: arndale: Add hdmi phy settings ARM: exynos: dts: cros5250: Add hdmi phy settings drm: exynos: hdmi: Add dt support for hdmiphy settings
.../devicetree/bindings/video/exynos_hdmi.txt | 31 ++++++++ arch/arm/boot/dts/cros5250-common.dtsi | 74 +++++++++++++++++++ arch/arm/boot/dts/exynos5250-arndale.dts | 74 +++++++++++++++++++ arch/arm/boot/dts/exynos5250-smdk5250.dts | 74 +++++++++++++++++++ drivers/gpu/drm/exynos/exynos_hdmi.c | 77 +++++++++++++++++++- 5 files changed, 326 insertions(+), 4 deletions(-)
This patch moves the hdmi phy setting to smdk5250 dts,as its more of a per board configuration and also shall be easier for supporting future chipsets.
Signed-off-by: Shirish S s.shirish@samsung.com --- arch/arm/boot/dts/exynos5250-smdk5250.dts | 74 +++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 2538b32..96e2cad 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -220,6 +220,80 @@
hdmi { hpd-gpio = <&gpx3 7 0>; + hdmiphy-configs { + /* + * Eye diagram test passed for: + * Data de-emphasis: -0.7dB & Data Level: 880mV + * i.e., 0010 0110 = 0x26 + * and Clock level of 515mV and diff 1030mV + * i.e., 0x66 + */ + config0: config0 { + pixel-clock = <25200000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config1: config1 { + pixel-clock = <27000000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config2: config2 { + pixel-clock = <27027000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config3: config3 { + pixel-clock = <36000000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config4: config4 { + pixel-clock = <40000000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config5: config5 { + pixel-clock = <65000000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config6: config6 { + pixel-clock = <74176000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config7: config7 { + pixel-clock = <74250000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config8: config8 { + pixel-clock = <83500000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config9: config9 { + pixel-clock = <106500000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config10: config10 { + pixel-clock = <108000000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config11: config11 { + pixel-clock = <146250000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config12: config12 { + pixel-clock = <148500000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + }; };
codec@11000000 {
This patch moves the hdmi phy setting to arndale dts, as its more of a per board configuration and also shall be easier for supporting future chipsets.
Signed-off-by: Shirish S s.shirish@samsung.com --- arch/arm/boot/dts/exynos5250-arndale.dts | 74 ++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index cee55fa..48b00f7 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -475,6 +475,80 @@ vdd_osc-supply = <&ldo10_reg>; vdd_pll-supply = <&ldo8_reg>; vdd-supply = <&ldo8_reg>; + hdmiphy-configs { + /* + * Eye diagram test passed for: + * Data de-emphasis: -0.7dB & Data Level: 880mV + * i.e., 0010 0110 = 0x26 + * and Clock level of 515mV and diff 1030mV + * i.e., 0x66 + */ + config0: config0 { + pixel-clock = <25200000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config1: config1 { + pixel-clock = <27000000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config2: config2 { + pixel-clock = <27027000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config3: config3 { + pixel-clock = <36000000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config4: config4 { + pixel-clock = <40000000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config5: config5 { + pixel-clock = <65000000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config6: config6 { + pixel-clock = <74176000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config7: config7 { + pixel-clock = <74250000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config8: config8 { + pixel-clock = <83500000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config9: config9 { + pixel-clock = <106500000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config10: config10 { + pixel-clock = <108000000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config11: config11 { + pixel-clock = <146250000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config12: config12 { + pixel-clock = <148500000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + }; };
regulators {
This patch moves the hdmi phy setting to arndale dts, as its more of a per board configuration and also shall be easier for supporting future chipsets.
Signed-off-by: Shirish S s.shirish@samsung.com --- arch/arm/boot/dts/cros5250-common.dtsi | 74 ++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+)
diff --git a/arch/arm/boot/dts/cros5250-common.dtsi b/arch/arm/boot/dts/cros5250-common.dtsi index dc259e8b..77408c6 100644 --- a/arch/arm/boot/dts/cros5250-common.dtsi +++ b/arch/arm/boot/dts/cros5250-common.dtsi @@ -301,6 +301,80 @@
hdmi { hpd-gpio = <&gpx3 7 0>; + hdmiphy-configs { + /* + * Eye diagram test passed for: + * Data de-emphasis: -0.7dB & Data Level: 880mV + * i.e., 0010 0110 = 0x26 + * and Clock level of 515mV and diff 1030mV + * i.e., 0x66 + */ + config0: config0 { + pixel-clock = <25200000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config1: config1 { + pixel-clock = <27000000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config2: config2 { + pixel-clock = <27027000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config3: config3 { + pixel-clock = <36000000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config4: config4 { + pixel-clock = <40000000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config5: config5 { + pixel-clock = <65000000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config6: config6 { + pixel-clock = <74176000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config7: config7 { + pixel-clock = <74250000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config8: config8 { + pixel-clock = <83500000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config9: config9 { + pixel-clock = <106500000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config10: config10 { + pixel-clock = <108000000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config11: config11 { + pixel-clock = <146250000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + config12: config12 { + pixel-clock = <148500000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + }; };
gpio-keys {
This patch adds dt support to hdmiphy config settings as it is board specific and depends on the signal pattern of board.
Signed-off-by: Shirish S s.shirish@samsung.com --- .../devicetree/bindings/video/exynos_hdmi.txt | 31 ++++++++ drivers/gpu/drm/exynos/exynos_hdmi.c | 77 +++++++++++++++++++- 2 files changed, 104 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt b/Documentation/devicetree/bindings/video/exynos_hdmi.txt index 323983b..6eeb333 100644 --- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt +++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt @@ -13,6 +13,30 @@ Required properties: b) pin number within the gpio controller. c) optional flags and pull up/down.
+- hdmiphy-configs: following information about the hdmiphy config settings. + a) "config<N>: config<N>" specifies the phy configuration settings, + where 'N' denotes the number of configuration, since every + pixel clock can have its unique configuration. + "pixel-clock" specifies the pixel clock + "conifig-de-emphasis-level" provides fine control of TMDS data + pre emphasis, below shown is example for + data de-emphasis register at address 0x145D0040. + hdmiphy@38[16] for bits[3:0] permitted values are in + the range of 760 mVdiff to 1400 mVdiff at 20mVdiff + increments for every LSB + hdmiphy@38[16] for bits[7:4] permitted values are in + the range of 0dB to -7.45dB at increments of -0.45dB + for every LSB. + "config-clock-level" provides fine control of TMDS data + amplitude for each channel, + for example if 0x145D005C is the address of clock level + register then, + hdmiphy@38[23] for bits [1:0] permitted values are in + the range of 0 mVdiff & 60 mVdiff for each channel at + increments 20 mVdiff of amplitude levels for every LSB, + hdmiphy@38[23] for bits [7:3] permitted values are in + the range of 790 and 1430 mV at 20mV increments for + every LSB. Example:
hdmi { @@ -20,4 +44,11 @@ Example: reg = <0x14530000 0x100000>; interrupts = <0 95 0>; hpd-gpio = <&gpx3 7 1>; + hdmiphy-configs { + config0: config0 { + pixel-clock = <25200000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + } }; diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index 32ce9a6..7934c6e 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -197,6 +197,9 @@ struct hdmi_context {
struct hdmi_resources res;
+ struct hdmiphy_config *confs; + int nr_confs; + int hpd_gpio;
enum hdmi_type type; @@ -256,7 +259,7 @@ static const struct hdmiphy_config hdmiphy_v13_configs[] = { }, };
-static const struct hdmiphy_config hdmiphy_v14_configs[] = { +static struct hdmiphy_config hdmiphy_v14_configs[] = { { .pixel_clock = 25200000, .conf = { @@ -785,8 +788,8 @@ static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock) confs = hdmiphy_v13_configs; count = ARRAY_SIZE(hdmiphy_v13_configs); } else if (hdata->type == HDMI_TYPE14) { - confs = hdmiphy_v14_configs; - count = ARRAY_SIZE(hdmiphy_v14_configs); + confs = hdata->confs; + count = hdata->nr_confs; } else return -EINVAL;
@@ -1415,7 +1418,7 @@ static void hdmiphy_conf_apply(struct hdmi_context *hdata) if (hdata->type == HDMI_TYPE13) hdmiphy_data = hdmiphy_v13_configs[i].conf; else - hdmiphy_data = hdmiphy_v14_configs[i].conf; + hdmiphy_data = hdata->confs[i].conf;
memcpy(buffer, hdmiphy_data, 32); ret = i2c_master_send(hdata->hdmiphy_port, buffer, 32); @@ -1894,6 +1897,63 @@ fail: return -ENODEV; }
+static int drm_hdmi_dt_parse_phy_conf(struct platform_device *pdev, + struct hdmi_context *hdata) +{ + struct device *dev = &pdev->dev; + struct device_node *dev_np = dev->of_node; + struct device_node *phy_conf, *cfg_np; + int i, pixel_clock = 0; + + /* Initialize with default config */ + hdata->confs = hdmiphy_v14_configs; + hdata->nr_confs = ARRAY_SIZE(hdmiphy_v14_configs); + + phy_conf = of_find_node_by_name(dev_np, "hdmiphy-configs"); + if (phy_conf == NULL) { + hdata->nr_confs = ARRAY_SIZE(hdmiphy_v14_configs); + DRM_ERROR("Did not find hdmiphy-configs node\n"); + return -ENODEV; + } + + for_each_child_of_node(phy_conf, cfg_np) { + if (!of_find_property(cfg_np, "pixel-clock", NULL)) + continue; + + if (of_property_read_u32(cfg_np, "pixel-clock", + &pixel_clock)) { + DRM_ERROR("Failed to get pixel clock\n"); + return -EINVAL; + } + + for (i = 0; i < ARRAY_SIZE(hdmiphy_v14_configs); i++) { + if (hdata->confs[i].pixel_clock == pixel_clock) + /* Update the data de-emphasis and data level */ + if (of_property_read_u8_array(cfg_np, + "config-de-emphasis-level", + &hdata->confs[i].conf[16], 1)) { + DRM_ERROR("Failed to get conf\n"); + return -EINVAL; + } + if (of_property_read_u8_array(cfg_np, + "config-de-emphasis-level", + &hdata->confs[i].conf[16], 1)) { + DRM_ERROR("Failed to get conf\n"); + return -EINVAL; + } + /* Update the clock level diff */ + if (of_property_read_u8_array(cfg_np, + "config-clock-level", + &hdata->confs[i].conf[23], 1)) { + DRM_ERROR("Failed to get conf\n"); + return -EINVAL; + } + } + } + return 0; + +} + static struct s5p_hdmi_platform_data *drm_hdmi_dt_parse_pdata (struct device *dev) { @@ -2024,6 +2084,15 @@ static int hdmi_probe(struct platform_device *pdev) goto err_hdmiphy; }
+ /* get hdmiphy confs */ + if (hdata->type == HDMI_TYPE14) { + ret = drm_hdmi_dt_parse_phy_conf(pdev, hdata); + if (ret) { + DRM_ERROR("failed to get user defined config,will use + default configs, eye diagram tests may fail\n"); + } + } + hdmi_display.dev = dev; exynos_drm_display_register(&hdmi_display);
dri-devel@lists.freedesktop.org
-
Shirish S