During board bringups its useful to have a DSI test pattern generator to isolate a DPU vs a DSI issue and focus on the relevant hardware block.
To facilitate this, add an API which triggers the DSI controller test pattern. The expected output is a rectangular checkered pattern.
This has been validated on a single DSI video mode panel by calling it right after drm_panel_enable() which is also the ideal location to use this as the DSI host and the panel have been initialized by then.
Further validation on dual DSI and command mode panel is pending. If there are any fix ups needed for those, it shall be applied on top of this change.
Signed-off-by: Abhinav Kumar abhinavk@codeaurora.org --- drivers/gpu/drm/msm/dsi/dsi.h | 3 ++ drivers/gpu/drm/msm/dsi/dsi.xml.h | 9 ++++++ drivers/gpu/drm/msm/dsi/dsi_host.c | 53 +++++++++++++++++++++++++++++++++++ drivers/gpu/drm/msm/dsi/dsi_manager.c | 13 +++++++++ 4 files changed, 78 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 9b8e9b0..663ccbd 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -84,6 +84,7 @@ void msm_dsi_manager_setup_encoder(int id); int msm_dsi_manager_register(struct msm_dsi *msm_dsi); void msm_dsi_manager_unregister(struct msm_dsi *msm_dsi); bool msm_dsi_manager_validate_current_config(u8 id); +void msm_dsi_manager_tpg_enable(void);
/* msm dsi */ static inline bool msm_dsi_device_connected(struct msm_dsi *msm_dsi) @@ -148,6 +149,8 @@ int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host); int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_dual_dsi); int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_dual_dsi); void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host); +void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host); + /* dsi phy */ struct msm_dsi_phy; struct msm_dsi_phy_shared_timings { diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h index eadbcc7..f7dcf49 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h @@ -624,6 +624,15 @@ static inline uint32_t DSI_RDBK_DATA_CTRL_COUNT(uint32_t val) #define REG_DSI_VERSION 0x000001f0 #define DSI_VERSION_MAJOR__MASK 0xff000000 #define DSI_VERSION_MAJOR__SHIFT 24 + +#define REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL 0x00000160 +#define REG_DSI_TPG_MAIN_CONTROL 0x00000198 +#define REG_DSI_TPG_VIDEO_CONFIG 0x000001a0 +#define REG_DSI_TEST_PATTERN_GEN_CTRL 0x00000158 +#define REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0 0x00000168 +#define REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER 0x00000180 +#define REG_DSI_TPG_MAIN_CONTROL2 0x0000019c + static inline uint32_t DSI_VERSION_MAJOR(uint32_t val) { return ((val) << DSI_VERSION_MAJOR__SHIFT) & DSI_VERSION_MAJOR__MASK; diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index ed504fe..24d44b0 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -2495,3 +2495,56 @@ void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_ho
pm_runtime_put_sync(&msm_host->pdev->dev); } + +static void msm_dsi_host_video_test_pattern_setup(struct msm_dsi_host *msm_host) +{ + u32 reg; + + reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); + + dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL, 0xff); + /* draw checkered rectangle pattern */ + dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL, 0x100); + /* use 24-bit RGB test pttern */ + dsi_write(msm_host, REG_DSI_TPG_VIDEO_CONFIG, 0x5); + + reg |= (0x3 << 4); + dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg); + + DBG("Video test pattern setup done\n"); +} + +static void msm_dsi_host_cmd_test_pattern_setup(struct msm_dsi_host *msm_host) +{ + u32 reg; + + reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); + + dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0, 0xff); + + reg |= (0x3 << 0x8); + dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg); + /* draw checkered rectangle pattern */ + dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL2, (0x1 << 0x7)); + DBG("Cmd test pattern setup done\n"); +} + +void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host) +{ + struct msm_dsi_host *msm_host = to_msm_dsi_host(host); + bool is_video_mode = !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO); + u32 reg; + + if (is_video_mode) + msm_dsi_host_video_test_pattern_setup(msm_host); + else + msm_dsi_host_cmd_test_pattern_setup(msm_host); + + reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); + /* enable the test pattern generator */ + dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, (reg | BIT(0))); + + /* for command mode need to trigger one frame from tpg */ + if (!is_video_mode) + dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER, 0x1); +} diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c index 4ebfedc..db80de6 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -441,6 +441,19 @@ static void dsi_mgr_bridge_pre_enable(struct drm_bridge *bridge) return; }
+void msm_dsi_manager_tpg_enable(void) +{ + struct msm_dsi *m_dsi = dsi_mgr_get_dsi(DSI_0); + struct msm_dsi *s_dsi = dsi_mgr_get_dsi(DSI_1); + + /* if dual dsi, trigger tpg on master first then slave */ + if (m_dsi) { + msm_dsi_host_test_pattern_en(m_dsi->host); + if (IS_DUAL_DSI() && s_dsi) + msm_dsi_host_test_pattern_en(s_dsi->host); + } +} + static void dsi_mgr_bridge_enable(struct drm_bridge *bridge) { int id = dsi_mgr_bridge_get_id(bridge);
On Tue, 29 Jun 2021 at 22:04, Abhinav Kumar abhinavk@codeaurora.org wrote:
During board bringups its useful to have a DSI test pattern generator to isolate a DPU vs a DSI issue and focus on the relevant hardware block.
To facilitate this, add an API which triggers the DSI controller test pattern. The expected output is a rectangular checkered pattern.
This has been validated on a single DSI video mode panel by calling it right after drm_panel_enable() which is also the ideal location to use this as the DSI host and the panel have been initialized by then.
Further validation on dual DSI and command mode panel is pending. If there are any fix ups needed for those, it shall be applied on top of this change.
Signed-off-by: Abhinav Kumar abhinavk@codeaurora.org
Reviewed-by: Dmitry Baryshkov dmitry.baryshkov@linaro.org
I'd follow Bjorn's suggestion of adding a debugfs file to toggle this pattern, but it surely can come in the following patch, not requiring to changing this one.
drivers/gpu/drm/msm/dsi/dsi.h | 3 ++ drivers/gpu/drm/msm/dsi/dsi.xml.h | 9 ++++++ drivers/gpu/drm/msm/dsi/dsi_host.c | 53 +++++++++++++++++++++++++++++++++++ drivers/gpu/drm/msm/dsi/dsi_manager.c | 13 +++++++++ 4 files changed, 78 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 9b8e9b0..663ccbd 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -84,6 +84,7 @@ void msm_dsi_manager_setup_encoder(int id); int msm_dsi_manager_register(struct msm_dsi *msm_dsi); void msm_dsi_manager_unregister(struct msm_dsi *msm_dsi); bool msm_dsi_manager_validate_current_config(u8 id); +void msm_dsi_manager_tpg_enable(void);
/* msm dsi */ static inline bool msm_dsi_device_connected(struct msm_dsi *msm_dsi) @@ -148,6 +149,8 @@ int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host); int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_dual_dsi); int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_dual_dsi); void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host); +void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host);
/* dsi phy */ struct msm_dsi_phy; struct msm_dsi_phy_shared_timings { diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h index eadbcc7..f7dcf49 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h @@ -624,6 +624,15 @@ static inline uint32_t DSI_RDBK_DATA_CTRL_COUNT(uint32_t val) #define REG_DSI_VERSION 0x000001f0 #define DSI_VERSION_MAJOR__MASK 0xff000000 #define DSI_VERSION_MAJOR__SHIFT 24
+#define REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL 0x00000160 +#define REG_DSI_TPG_MAIN_CONTROL 0x00000198 +#define REG_DSI_TPG_VIDEO_CONFIG 0x000001a0 +#define REG_DSI_TEST_PATTERN_GEN_CTRL 0x00000158 +#define REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0 0x00000168 +#define REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER 0x00000180 +#define REG_DSI_TPG_MAIN_CONTROL2 0x0000019c
static inline uint32_t DSI_VERSION_MAJOR(uint32_t val) { return ((val) << DSI_VERSION_MAJOR__SHIFT) & DSI_VERSION_MAJOR__MASK; diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index ed504fe..24d44b0 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -2495,3 +2495,56 @@ void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_ho
pm_runtime_put_sync(&msm_host->pdev->dev);}
+static void msm_dsi_host_video_test_pattern_setup(struct msm_dsi_host *msm_host) +{
u32 reg;reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL);dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL, 0xff);/* draw checkered rectangle pattern */dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL, 0x100);/* use 24-bit RGB test pttern */dsi_write(msm_host, REG_DSI_TPG_VIDEO_CONFIG, 0x5);reg |= (0x3 << 4);dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg);DBG("Video test pattern setup done\n");+}
+static void msm_dsi_host_cmd_test_pattern_setup(struct msm_dsi_host *msm_host) +{
u32 reg;reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL);dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0, 0xff);reg |= (0x3 << 0x8);dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg);/* draw checkered rectangle pattern */dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL2, (0x1 << 0x7));DBG("Cmd test pattern setup done\n");+}
+void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host) +{
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);bool is_video_mode = !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO);u32 reg;if (is_video_mode)msm_dsi_host_video_test_pattern_setup(msm_host);elsemsm_dsi_host_cmd_test_pattern_setup(msm_host);reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL);/* enable the test pattern generator */dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, (reg | BIT(0)));/* for command mode need to trigger one frame from tpg */if (!is_video_mode)dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER, 0x1);+} diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c index 4ebfedc..db80de6 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -441,6 +441,19 @@ static void dsi_mgr_bridge_pre_enable(struct drm_bridge *bridge) return; }
+void msm_dsi_manager_tpg_enable(void) +{
struct msm_dsi *m_dsi = dsi_mgr_get_dsi(DSI_0);struct msm_dsi *s_dsi = dsi_mgr_get_dsi(DSI_1);/* if dual dsi, trigger tpg on master first then slave */if (m_dsi) {msm_dsi_host_test_pattern_en(m_dsi->host);if (IS_DUAL_DSI() && s_dsi)msm_dsi_host_test_pattern_en(s_dsi->host);}+}
static void dsi_mgr_bridge_enable(struct drm_bridge *bridge) { int id = dsi_mgr_bridge_get_id(bridge); -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
On 6/29/21 9:04 PM, Abhinav Kumar wrote:
During board bringups its useful to have a DSI test pattern generator to isolate a DPU vs a DSI issue and focus on the relevant hardware block.
To facilitate this, add an API which triggers the DSI controller test pattern. The expected output is a rectangular checkered pattern.
This has been validated on a single DSI video mode panel by calling it right after drm_panel_enable() which is also the ideal location to use this as the DSI host and the panel have been initialized by then.
Further validation on dual DSI and command mode panel is pending. If there are any fix ups needed for those, it shall be applied on top of this change.
Signed-off-by: Abhinav Kumar abhinavk@codeaurora.org Reviewed-by: Dmitry Baryshkov dmitry.baryshkov@linaro.org
Tested-by: Marijn Suijten marijn.suijten@somainline.org
[...]
+static void msm_dsi_host_cmd_test_pattern_setup(struct msm_dsi_host *msm_host) +{
- u32 reg;
- reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL);
- dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0, 0xff);
- reg |= (0x3 << 0x8);
- dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg);
- /* draw checkered rectangle pattern */
- dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL2, (0x1 << 0x7));
How about BIT(7)?
On SM6125 this seems to change the color intensity of the pattern; it is always colored lines of a few pixels wide alternating R, B and G from left to right. Is it possible to document the meaning and available values of these registers, especially if they differ between SoC / DSI block?
Kind regards, Marijn
- DBG("Cmd test pattern setup done\n");
+}
[...]
Hi Marijn
Sorry for the late response.
On 2021-07-13 02:10, Marijn Suijten wrote:
On 6/29/21 9:04 PM, Abhinav Kumar wrote:
During board bringups its useful to have a DSI test pattern generator to isolate a DPU vs a DSI issue and focus on the relevant hardware block.
To facilitate this, add an API which triggers the DSI controller test pattern. The expected output is a rectangular checkered pattern.
This has been validated on a single DSI video mode panel by calling it right after drm_panel_enable() which is also the ideal location to use this as the DSI host and the panel have been initialized by then.
Further validation on dual DSI and command mode panel is pending. If there are any fix ups needed for those, it shall be applied on top of this change.
Signed-off-by: Abhinav Kumar abhinavk@codeaurora.org Reviewed-by: Dmitry Baryshkov dmitry.baryshkov@linaro.org
Tested-by: Marijn Suijten marijn.suijten@somainline.org
[...]
Thanks for testing this.
+static void msm_dsi_host_cmd_test_pattern_setup(struct msm_dsi_host *msm_host) +{
- u32 reg;
- reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL);
- dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0,
0xff);
- reg |= (0x3 << 0x8);
- dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg);
- /* draw checkered rectangle pattern */
- dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL2, (0x1 << 0x7));
How about BIT(7)?
You mean BIT(7) of REG_DSI_TPG_MAIN_CONTROL2? Thats what this is right? Did you mean some other bit?
On SM6125 this seems to change the color intensity of the pattern; it is always colored lines of a few pixels wide alternating R, B and G from left to right. Is it possible to document the meaning and available values of these registers, especially if they differ between SoC / DSI block?
I have requested access for SM6125, will check this register on that to see if there is any difference.
Are you saying you are not seeing a rectangular checkered pattern while testing? Also are you testing on command mode or video mode?
As requested by Rob, I will add the bit definitions and update the dsi.xml.h in the next patchset for the registers and the bits which I am using here.
With that the meaning of these bits will be more clear.
I dont think I will be able to document all the bits because the goal of this patch was only to draw a test pattern to help with validation. Different bits of the REG_DSI_TPG_MAIN_CONTROL2 register only draw different patterns so the goal wasnt that we can draw any pattern, it was just to draw some pattern on the screen.
When we add support for all other patterns, we can expose those bits as well but it should not be required in my opinion.
Kind regards, Marijn
- DBG("Cmd test pattern setup done\n");
+}
[...]
Hi Abhinav,
On 7/16/21 2:01 AM, abhinavk@codeaurora.org wrote:
Hi Marijn
Sorry for the late response.
Apologies from my side as well.
[...]
+static void msm_dsi_host_cmd_test_pattern_setup(struct msm_dsi_host *msm_host) +{
- u32 reg;
- reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL);
- dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0,
0xff);
- reg |= (0x3 << 0x8);
- dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg);
- /* draw checkered rectangle pattern */
- dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL2, (0x1 << 0x7));
How about BIT(7)?
You mean BIT(7) of REG_DSI_TPG_MAIN_CONTROL2? Thats what this is right? Did you mean some other bit?
I meant to replace (0x1 << 0x7) with BIT(7), but replacing it with DSI_TPG_MAIN_CONTROL2_CMD_MDP0_CHECKERED_RECTANGLE_PATTERN is even better, thanks.
On SM6125 this seems to change the color intensity of the pattern; it is always colored lines of a few pixels wide alternating R, B and G from left to right. Is it possible to document the meaning and available values of these registers, especially if they differ between SoC / DSI block?
I have requested access for SM6125, will check this register on that to see if there is any difference.
Are you saying you are not seeing a rectangular checkered pattern while testing?
Correct. It's fixed now, and this patch already proves its usefulness! We had two minor configuration issues, and are now seeing the squares just like on the other SoCs. Meaning we can finally move on to configuring the DPU, thanks!
Also are you testing on command mode or video mode?
Command mode, if it's still worth anything.
As requested by Rob, I will add the bit definitions and update the dsi.xml.h in the next patchset for the registers and the bits which I am using here.
With that the meaning of these bits will be more clear.
I dont think I will be able to document all the bits because the goal of this patch was only to draw a test pattern to help with validation. Different bits of the REG_DSI_TPG_MAIN_CONTROL2 register only draw different patterns so the goal wasnt that we can draw any pattern, it was just to draw some pattern on the screen.
When we add support for all other patterns, we can expose those bits as well but it should not be required in my opinion.
Understandable. I'm curious if other patterns are useful in certain situations, like DSC? Other than that, knowing that the DSI and PHY is correct is good enough for us.
Kind regards, Marijn
- DBG("Cmd test pattern setup done\n");
+}
[...]
Thanks! Marijn
Hi Marijn
Thanks for reviewing and testing the latest patchset.
On 2021-08-10 15:59, Marijn Suijten wrote:
Hi Abhinav,
On 7/16/21 2:01 AM, abhinavk@codeaurora.org wrote:
Hi Marijn
Sorry for the late response.
Apologies from my side as well.
[...]
+static void msm_dsi_host_cmd_test_pattern_setup(struct msm_dsi_host *msm_host) +{
- u32 reg;
- reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL);
- dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0,
0xff);
- reg |= (0x3 << 0x8);
- dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg);
- /* draw checkered rectangle pattern */
- dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL2, (0x1 << 0x7));
How about BIT(7)?
You mean BIT(7) of REG_DSI_TPG_MAIN_CONTROL2? Thats what this is right? Did you mean some other bit?
I meant to replace (0x1 << 0x7) with BIT(7), but replacing it with DSI_TPG_MAIN_CONTROL2_CMD_MDP0_CHECKERED_RECTANGLE_PATTERN is even better, thanks.
On SM6125 this seems to change the color intensity of the pattern; it is always colored lines of a few pixels wide alternating R, B and G from left to right. Is it possible to document the meaning and available values of these registers, especially if they differ between SoC / DSI block?
I have requested access for SM6125, will check this register on that to see if there is any difference.
Are you saying you are not seeing a rectangular checkered pattern while testing?
Correct. It's fixed now, and this patch already proves its usefulness! We had two minor configuration issues, and are now seeing the squares just like on the other SoCs. Meaning we can finally move on to configuring the DPU, thanks!
Thats good to know !
Also are you testing on command mode or video mode?
Command mode, if it's still worth anything.
Thats good to know too, as I had not been able to test command mode.
As requested by Rob, I will add the bit definitions and update the dsi.xml.h in the next patchset for the registers and the bits which I am using here.
With that the meaning of these bits will be more clear.
I dont think I will be able to document all the bits because the goal of this patch was only to draw a test pattern to help with validation. Different bits of the REG_DSI_TPG_MAIN_CONTROL2 register only draw different patterns so the goal wasnt that we can draw any pattern, it was just to draw some pattern on the screen.
When we add support for all other patterns, we can expose those bits as well but it should not be required in my opinion.
Understandable. I'm curious if other patterns are useful in certain situations, like DSC? Other than that, knowing that the DSI and PHY is correct is good enough for us.
The TPG in this patch is only for the DSI block which is after the DSC block. So any pattern we pick from the DSI_TPG_MAIN_CONTROL2 register (using any other bit) will only look different visually but will still be from DSI and no other block. So it will not help to validate DSC block individually.
Kind regards, Marijn
- DBG("Cmd test pattern setup done\n");
+}
[...]
Thanks! Marijn
On Tue, Jun 29, 2021 at 12:04 PM Abhinav Kumar abhinavk@codeaurora.org wrote:
During board bringups its useful to have a DSI test pattern generator to isolate a DPU vs a DSI issue and focus on the relevant hardware block.
To facilitate this, add an API which triggers the DSI controller test pattern. The expected output is a rectangular checkered pattern.
This has been validated on a single DSI video mode panel by calling it right after drm_panel_enable() which is also the ideal location to use this as the DSI host and the panel have been initialized by then.
Further validation on dual DSI and command mode panel is pending. If there are any fix ups needed for those, it shall be applied on top of this change.
Signed-off-by: Abhinav Kumar abhinavk@codeaurora.org
drivers/gpu/drm/msm/dsi/dsi.h | 3 ++ drivers/gpu/drm/msm/dsi/dsi.xml.h | 9 ++++++ drivers/gpu/drm/msm/dsi/dsi_host.c | 53 +++++++++++++++++++++++++++++++++++ drivers/gpu/drm/msm/dsi/dsi_manager.c | 13 +++++++++ 4 files changed, 78 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 9b8e9b0..663ccbd 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -84,6 +84,7 @@ void msm_dsi_manager_setup_encoder(int id); int msm_dsi_manager_register(struct msm_dsi *msm_dsi); void msm_dsi_manager_unregister(struct msm_dsi *msm_dsi); bool msm_dsi_manager_validate_current_config(u8 id); +void msm_dsi_manager_tpg_enable(void);
/* msm dsi */ static inline bool msm_dsi_device_connected(struct msm_dsi *msm_dsi) @@ -148,6 +149,8 @@ int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host); int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_dual_dsi); int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_dual_dsi); void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host); +void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host);
/* dsi phy */ struct msm_dsi_phy; struct msm_dsi_phy_shared_timings { diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h index eadbcc7..f7dcf49 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h @@ -624,6 +624,15 @@ static inline uint32_t DSI_RDBK_DATA_CTRL_COUNT(uint32_t val) #define REG_DSI_VERSION 0x000001f0 #define DSI_VERSION_MAJOR__MASK 0xff000000 #define DSI_VERSION_MAJOR__SHIFT 24
+#define REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL 0x00000160 +#define REG_DSI_TPG_MAIN_CONTROL 0x00000198 +#define REG_DSI_TPG_VIDEO_CONFIG 0x000001a0 +#define REG_DSI_TEST_PATTERN_GEN_CTRL 0x00000158 +#define REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0 0x00000168 +#define REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER 0x00000180 +#define REG_DSI_TPG_MAIN_CONTROL2 0x0000019c
We should add these in dsi.xml (either in mesa.git/src/freedreno/registers/dsi/dsi.xml or in envytools.git/registers/dsi/dsi.xml) and regenerate dsi.xml.h
And if possible, it would be nice to define the bitfields instead of just open-coding the register values
BR, -R
static inline uint32_t DSI_VERSION_MAJOR(uint32_t val) { return ((val) << DSI_VERSION_MAJOR__SHIFT) & DSI_VERSION_MAJOR__MASK; diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index ed504fe..24d44b0 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -2495,3 +2495,56 @@ void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_ho
pm_runtime_put_sync(&msm_host->pdev->dev);}
+static void msm_dsi_host_video_test_pattern_setup(struct msm_dsi_host *msm_host) +{
u32 reg;reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL);dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL, 0xff);/* draw checkered rectangle pattern */dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL, 0x100);/* use 24-bit RGB test pttern */dsi_write(msm_host, REG_DSI_TPG_VIDEO_CONFIG, 0x5);reg |= (0x3 << 4);dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg);DBG("Video test pattern setup done\n");+}
+static void msm_dsi_host_cmd_test_pattern_setup(struct msm_dsi_host *msm_host) +{
u32 reg;reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL);dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0, 0xff);reg |= (0x3 << 0x8);dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg);/* draw checkered rectangle pattern */dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL2, (0x1 << 0x7));DBG("Cmd test pattern setup done\n");+}
+void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host) +{
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);bool is_video_mode = !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO);u32 reg;if (is_video_mode)msm_dsi_host_video_test_pattern_setup(msm_host);elsemsm_dsi_host_cmd_test_pattern_setup(msm_host);reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL);/* enable the test pattern generator */dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, (reg | BIT(0)));/* for command mode need to trigger one frame from tpg */if (!is_video_mode)dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER, 0x1);+} diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c index 4ebfedc..db80de6 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -441,6 +441,19 @@ static void dsi_mgr_bridge_pre_enable(struct drm_bridge *bridge) return; }
+void msm_dsi_manager_tpg_enable(void) +{
struct msm_dsi *m_dsi = dsi_mgr_get_dsi(DSI_0);struct msm_dsi *s_dsi = dsi_mgr_get_dsi(DSI_1);/* if dual dsi, trigger tpg on master first then slave */if (m_dsi) {msm_dsi_host_test_pattern_en(m_dsi->host);if (IS_DUAL_DSI() && s_dsi)msm_dsi_host_test_pattern_en(s_dsi->host);}+}
static void dsi_mgr_bridge_enable(struct drm_bridge *bridge) { int id = dsi_mgr_bridge_get_id(bridge); -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
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Abhinav Kumar -
abhinavk＠codeaurora.org
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Dmitry Baryshkov -
Marijn Suijten -
Rob Clark