Hi Enric,

Thanks for your review.

On Fri, 2021-07-23 at 13:05 +0200, Enric Balletbo Serra wrote:

Hi Nancy,

Thank you for your patch.

Missatge de Nancy.Lin nancy.lin@mediatek.com del dia dj., 22 de jul. 2021 a les 11:45:

...

Add mt8195 vdosys1 clock driver name and routing table to the driver data of mtk-mmsys.

Signed-off-by: Nancy.Lin nancy.lin@mediatek.com

drivers/soc/mediatek/mt8195-mmsys.h | 83 ++++++++++++++++++++++++-- drivers/soc/mediatek/mtk-mmsys.c | 10 ++++ include/linux/soc/mediatek/mtk-mmsys.h | 2 + 3 files changed, 90 insertions(+), 5 deletions(-)

diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h index 73e9e8286d50..104ba575f765 100644 --- a/drivers/soc/mediatek/mt8195-mmsys.h +++ b/drivers/soc/mediatek/mt8195-mmsys.h @@ -64,16 +64,16 @@ #define SOUT_TO_VPP_MERGE0_P1_SEL (1 << 0)

#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40 -#define SOUT_TO_HDR_VDO_FE0 (0 << 0)

This definition was introduced in this patch [1] that didn't land yet. And you're removing it now. Could you sync with Jason and only introduce the bits that are needed for your patches. Also all the comments I made to the Jason's patch apply here.

[1] https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-media...

OK, I will sync with Jason and modify it.

...

+#define SOUT_TO_MIXER_IN1_SEL (1 << 0)

#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44 -#define SOUT_TO_HDR_VDO_FE1 (0 << 0) +#define SOUT_TO_MIXER_IN2_SEL (1 << 0)

#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48 -#define SOUT_TO_HDR_GFX_FE0 (0 << 0) +#define SOUT_TO_MIXER_IN3_SEL (1 << 0)

#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c -#define SOUT_TO_HDR_GFX_FE1 (0 << 0) +#define SOUT_TO_MIXER_IN4_SEL (1 << 0)

#define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58 #define MIXER_IN1_SOUT_TO_DISP_MIXER (0 << 0) @@ -88,7 +88,7 @@ #define MIXER_IN4_SOUT_TO_DISP_MIXER (0 << 0)

#define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34 -#define MIXER_SOUT_TO_HDR_VDO_BE0 (0 << 0) +#define MIXER_SOUT_TO_MERGE4_ASYNC_SEL (1 << 0)

#define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18 #define MERGE4_SOUT_TO_VDOSYS0 (0 << 0) @@ -185,6 +185,79 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = { }, { DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, MT8195_VDO0_SEL_OUT, SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE

•   },
  

•   {
  

•           DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
  

•           MT8195_VDO1_VPP_MERGE0_P0_SEL_IN,
  

VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0

•   },
  

•   {
  

•           DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
  

•           MT8195_VDO1_VPP_MERGE0_P1_SEL_IN,
  

VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1

•   },
  

•   {
  

•           DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
  

•           MT8195_VDO1_VPP_MERGE1_P0_SEL_IN,
  

VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2

•   },
  

•   {
  

•           DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
  

•           MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL,
  

SOUT_TO_MIXER_IN1_SEL

•   },
  

•   {
  

•           DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
  

•           MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL,
  

SOUT_TO_MIXER_IN2_SEL

•   },
  

•   {
  

•           DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
  

•           MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL,
  

SOUT_TO_MIXER_IN3_SEL

•   },
  

•   {
  

•           DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
  

•           MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL,
  

SOUT_TO_MIXER_IN4_SEL

•   },
  

•   {
  

•           DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
  

•           MT8195_VDO1_MIXER_OUT_SOUT_SEL,
  

MIXER_SOUT_TO_MERGE4_ASYNC_SEL

•   },
  

•   {
  

•           DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
  

•           MT8195_VDO1_MIXER_IN1_SEL_IN,
  

MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT

•   },
  

•   {
  

•           DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
  

•           MT8195_VDO1_MIXER_IN2_SEL_IN,
  

MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT

•   },
  

•   {
  

•           DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
  

•           MT8195_VDO1_MIXER_IN3_SEL_IN,
  

MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT

•   },
  

•   {
  

•           DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
  

•           MT8195_VDO1_MIXER_IN4_SEL_IN,
  

MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT

•   },
  

•   {
  

•           DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
  

•           MT8195_VDO1_MIXER_SOUT_SEL_IN,
  

MIXER_SOUT_SEL_IN_FROM_DISP_MIXER

•   },
  

•   {
  

•           DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
  

•           MT8195_VDO1_MERGE4_ASYNC_SEL_IN,
  

MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT

•   },
  

•   {
  

•           DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
  

•           MT8195_VDO1_DISP_DPI1_SEL_IN,
  

DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT

•   },
  

•   {
  

•           DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
  

•           MT8195_VDO1_MERGE4_SOUT_SEL,
  

MERGE4_SOUT_TO_DPI1_SEL

•   },
  

•   {
  

•           DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
  

•           MT8195_VDO1_DISP_DP_INTF0_SEL_IN,
  

•           DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
  

•   },
  

•   {
  

•           DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
  

•           MT8195_VDO1_MERGE4_SOUT_SEL,
  

MERGE4_SOUT_TO_DP_INTF0_SEL } };

diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 1fb241750897..9e31aad6c5c8 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -59,6 +59,12 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table), };

+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {

•   .clk_driver = "clk-mt8195-vdo1",
  

•   .routes = mmsys_mt8195_routing_table,
  

•   .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
  

+};

struct mtk_mmsys { void __iomem *regs; const struct mtk_mmsys_driver_data *data; @@ -168,6 +174,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = { .compatible = "mediatek,mt8195-vdosys0", .data = &mt8195_vdosys0_driver_data, },

•   {
  

•           .compatible = "mediatek,mt8195-vdosys1",
  

Why do you need a second compatible, isn't this the same IP block? I mean, I understand that you have 2 mmsys blocks, but both are the same IP block, right? or are they different?

Thanks, Enric

They(vdosys0 and vdosys1) are different IP block.

...

•           .data = &mt8195_vdosys1_driver_data,
  

•   },
    { }
  

};

diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 34cb605e5df9..338c71570aeb 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -49,6 +49,8 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_DSC1, DDP_COMPONENT_DSC1_VIRTUAL0, DDP_COMPONENT_DP_INTF0,

•   DDP_COMPONENT_DP_INTF1,
  

•   DDP_COMPONENT_PSEUDO_OVL,
    DDP_COMPONENT_ID_MAX,
  

};

-- 2.18.0

Hi Matthias,

Thanks for the review.

On Fri, 2021-08-06 at 14:20 +0200, Matthias Brugger wrote:

On 28/07/2021 07:34, Nancy.Lin wrote:

...

Hi Enric,

Thanks for your review.

On Fri, 2021-07-23 at 13:05 +0200, Enric Balletbo Serra wrote:

...

Hi Nancy,

Thank you for your patch.

Missatge de Nancy.Lin nancy.lin@mediatek.com del dia dj., 22 de jul. 2021 a les 11:45:

...

Add mt8195 vdosys1 clock driver name and routing table to the driver data of mtk-mmsys.

Signed-off-by: Nancy.Lin nancy.lin@mediatek.com

drivers/soc/mediatek/mt8195-mmsys.h | 83 ++++++++++++++++++++++++-- drivers/soc/mediatek/mtk-mmsys.c | 10 ++++ include/linux/soc/mediatek/mtk-mmsys.h | 2 + 3 files changed, 90 insertions(+), 5 deletions(-)

diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h index 73e9e8286d50..104ba575f765 100644 --- a/drivers/soc/mediatek/mt8195-mmsys.h +++ b/drivers/soc/mediatek/mt8195-mmsys.h @@ -64,16 +64,16 @@ #define SOUT_TO_VPP_MERGE0_P1_SEL (1 << 0)

#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40 -#define SOUT_TO_HDR_VDO_FE0 (0 << 0)

This definition was introduced in this patch [1] that didn't land yet. And you're removing it now. Could you sync with Jason and only introduce the bits that are needed for your patches. Also all the comments I made to the Jason's patch apply here.

[1]

https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-media...

...

...

OK, I will sync with Jason and modify it.

...

...

+#define SOUT_TO_MIXER_IN1_SEL (1 << 0)

#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44 -#define SOUT_TO_HDR_VDO_FE1 (0 << 0) +#define SOUT_TO_MIXER_IN2_SEL (1 << 0)

#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48 -#define SOUT_TO_HDR_GFX_FE0 (0 << 0) +#define SOUT_TO_MIXER_IN3_SEL (1 << 0)

#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c -#define SOUT_TO_HDR_GFX_FE1 (0 << 0) +#define SOUT_TO_MIXER_IN4_SEL (1 << 0)

#define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58 #define MIXER_IN1_SOUT_TO_DISP_MIXER (0 << 0) @@ -88,7 +88,7 @@ #define MIXER_IN4_SOUT_TO_DISP_MIXER (0 << 0)

#define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34 -#define MIXER_SOUT_TO_HDR_VDO_BE0 (0 << 0) +#define MIXER_SOUT_TO_MERGE4_ASYNC_SEL (1 << 0)

#define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18 #define MERGE4_SOUT_TO_VDOSYS0 (0 << 0) @@ -185,6 +185,79 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = { }, { DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, MT8195_VDO0_SEL_OUT, SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE

•   },
  

•   {
  

•           DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
  

•           MT8195_VDO1_VPP_MERGE0_P0_SEL_IN,
  

VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0

•   },
  

•   {
  

•           DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
  

•           MT8195_VDO1_VPP_MERGE0_P1_SEL_IN,
  

VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1

•   },
  

•   {
  

•           DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
  

•           MT8195_VDO1_VPP_MERGE1_P0_SEL_IN,
  

VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2

•   },
  

•   {
  

•           DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
  

•           MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL,
  

SOUT_TO_MIXER_IN1_SEL

•   },
  

•   {
  

•           DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
  

•           MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL,
  

SOUT_TO_MIXER_IN2_SEL

•   },
  

•   {
  

•           DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
  

•           MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL,
  

SOUT_TO_MIXER_IN3_SEL

•   },
  

•   {
  

•           DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
  

•           MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL,
  

SOUT_TO_MIXER_IN4_SEL

•   },
  

•   {
  

•           DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
  

•           MT8195_VDO1_MIXER_OUT_SOUT_SEL,
  

MIXER_SOUT_TO_MERGE4_ASYNC_SEL

•   },
  

•   {
  

•           DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
  

•           MT8195_VDO1_MIXER_IN1_SEL_IN,
  

MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT

•   },
  

•   {
  

•           DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
  

•           MT8195_VDO1_MIXER_IN2_SEL_IN,
  

MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT

•   },
  

•   {
  

•           DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
  

•           MT8195_VDO1_MIXER_IN3_SEL_IN,
  

MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT

•   },
  

•   {
  

•           DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
  

•           MT8195_VDO1_MIXER_IN4_SEL_IN,
  

MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT

•   },
  

•   {
  

•           DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
  

•           MT8195_VDO1_MIXER_SOUT_SEL_IN,
  

MIXER_SOUT_SEL_IN_FROM_DISP_MIXER

•   },
  

•   {
  

•           DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
  

•           MT8195_VDO1_MERGE4_ASYNC_SEL_IN,
  

MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT

•   },
  

•   {
  

•           DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
  

•           MT8195_VDO1_DISP_DPI1_SEL_IN,
  

DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT

•   },
  

•   {
  

•           DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
  

•           MT8195_VDO1_MERGE4_SOUT_SEL,
  

MERGE4_SOUT_TO_DPI1_SEL

•   },
  

•   {
  

•           DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
  

•           MT8195_VDO1_DISP_DP_INTF0_SEL_IN,
  

•           DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
  

•   },
  

•   {
  

•           DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
  

•           MT8195_VDO1_MERGE4_SOUT_SEL,
  

MERGE4_SOUT_TO_DP_INTF0_SEL } };

diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 1fb241750897..9e31aad6c5c8 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -59,6 +59,12 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table), };

+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {

•   .clk_driver = "clk-mt8195-vdo1",
  

•   .routes = mmsys_mt8195_routing_table,
  

•   .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
  

+};

struct mtk_mmsys { void __iomem *regs; const struct mtk_mmsys_driver_data *data; @@ -168,6 +174,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = { .compatible = "mediatek,mt8195-vdosys0", .data = &mt8195_vdosys0_driver_data, },

•   {
  

•           .compatible = "mediatek,mt8195-vdosys1",
  

Why do you need a second compatible, isn't this the same IP block? I mean, I understand that you have 2 mmsys blocks, but both are the same IP block, right? or are they different?

Thanks, Enric

They(vdosys0 and vdosys1) are different IP block.

Please explain in what they are different. From what I see, you use the same routing table for both compatibles and only register another platform device for a second clock. Is that correct?

Regards, Matthias

From a hardware point of view, the HW engines of vdosys0 and vdosys1 are different. 1. The components on meiatek-drm of vdosys0 are OVL0, RDMA0, COLOR0, CCORR, AAL0, GAMMA, DITHER, DSC0, MERGE0, DP_INTF0. Its output panel is eDP. 2. The components on meiatek-drm of vdosys1 are OVL_ADAPTOR, MERGE5, DP_INTF1. Its output panel is DP.

In the SoC before, such as mt8173, it has 2 pipelines binding to one mmsys with the same clock driver and the same power domain.

In mt8195, 2 pipelines are binding to different mmsys, such as vdosys0 and vdosys1. Each mmsys uses different clock drivers and different power domains.

So I think it is more appropriate to use 2 compatibles to identify which mmsys represents the pipeline. Another reason for using two compatibles is that we use different driver data in mtk-mmsys.c and mtk_drm_drv.c to identify the corresponding mmsys is vdosys0 or vdosys1.

Their driver data in mtk_drm_drv.c is defined here: [v7,13/13] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195

https://patchwork.kernel.org/project/linux-mediatek/patch/20210815145610.205...

[v2,14/14] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195

https://patchwork.kernel.org/project/linux-mediatek/patch/20210722094551.152...

There is another series talking about the two mmsys compatible.

https://patchwork.kernel.org/project/linux-mediatek/patch/20210722092624.144...

Regards, Nancy

...

...

...

•           .data = &mt8195_vdosys1_driver_data,
  

•   },
    { }
  

};

diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 34cb605e5df9..338c71570aeb 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -49,6 +49,8 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_DSC1, DDP_COMPONENT_DSC1_VIRTUAL0, DDP_COMPONENT_DP_INTF0,

•   DDP_COMPONENT_DP_INTF1,
  

•   DDP_COMPONENT_PSEUDO_OVL,
    DDP_COMPONENT_ID_MAX,
  

};

-- 2.18.0

On 22/07/2021 11:45, Nancy.Lin wrote:

Add mmsys config API.

This patch is doing a lot of things, it adds a "config" and it adds cmdq support. Please explain better in the commit message what the config is for. Please add comments to the different values of struct mtk_mmsys_config.

I understand that cmdq is optional, so please make addition to cmdq a separate patch. I'm a bit puzzled about that fact, can you please explain who you get the HW to behave the same way when you write the same value and offset to mmsys-regs and via cmdq.

Thanks, Matthias

Signed-off-by: Nancy.Lin nancy.lin@mediatek.com

drivers/soc/mediatek/mt8195-mmsys.h | 38 ++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 50 ++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.h | 10 ++++++ include/linux/soc/mediatek/mtk-mmsys.h | 18 ++++++++++ 4 files changed, 116 insertions(+)

diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h index 104ba575f765..4bdb2087250c 100644 --- a/drivers/soc/mediatek/mt8195-mmsys.h +++ b/drivers/soc/mediatek/mt8195-mmsys.h @@ -154,6 +154,18 @@ #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1 << 0) #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2 << 0)

+#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30 +#define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40 +#define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50 +#define MT8195_VDO1_MERGE3_ASYNC_CFG_WD 0xe60 +#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70 +#define MT8195_VDO1_HDR_TOP_CFG 0xd00 +#define MT8195_VDO1_MIXER_IN1_ALPHA 0xd30 +#define MT8195_VDO1_MIXER_IN2_ALPHA 0xd34 +#define MT8195_VDO1_MIXER_IN3_ALPHA 0xd38 +#define MT8195_VDO1_MIXER_IN4_ALPHA 0xd3c +#define MT8195_VDO1_MIXER_IN4_PAD 0xd4c

static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = { { DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, @@ -261,4 +273,30 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = { } };

+static const struct mtk_mmsys_config mmsys_mt8195_config_table[] = {

• { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 0, MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(13, 0), 0},
• { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 0, MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(29, 16), 16},
• { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 1, MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(13, 0), 0},
• { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 1, MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(29, 16), 16},
• { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 2, MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(13, 0), 0},
• { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 2, MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(29, 16), 16},
• { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 3, MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(13, 0), 0},
• { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 3, MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(29, 16), 16},
• { MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0, MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(13, 0), 0},
• { MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0, MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(29, 16), 16},
• { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 1, MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(8, 0), 0},
• { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 1, MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(24, 16), 16},
• { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 2, MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(8, 0), 0},
• { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 2, MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(24, 16), 16},
• { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 3, MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(8, 0), 0},
• { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 3, MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(24, 16), 16},
• { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 4, MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(8, 0), 0},
• { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 4, MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(24, 16), 16},
• { MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, MT8195_VDO1_MIXER_IN4_PAD, GENMASK(4, 4), 4},
• { MMSYS_CONFIG_HDR_ALPHA_SEL, 1, MT8195_VDO1_HDR_TOP_CFG, GENMASK(20, 20), 20},
• { MMSYS_CONFIG_HDR_ALPHA_SEL, 2, MT8195_VDO1_HDR_TOP_CFG, GENMASK(21, 21), 21},
• { MMSYS_CONFIG_HDR_ALPHA_SEL, 3, MT8195_VDO1_HDR_TOP_CFG, GENMASK(22, 22), 22},
• { MMSYS_CONFIG_HDR_ALPHA_SEL, 4, MT8195_VDO1_HDR_TOP_CFG, GENMASK(23, 23), 23},

+};

#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */ diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 9e31aad6c5c8..d0f4a407f8f8 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -63,10 +63,13 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { .clk_driver = "clk-mt8195-vdo1", .routes = mmsys_mt8195_routing_table, .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),

• .config = mmsys_mt8195_config_table,
• .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),

};

struct mtk_mmsys { void __iomem *regs;

• struct cmdq_client_reg cmdq_base; const struct mtk_mmsys_driver_data *data;

};

@@ -104,6 +107,47 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, } EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);

+void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,

• 	  u32 id, u32 val, struct cmdq_pkt *cmdq_pkt)
  

+{

• struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
• const struct mtk_mmsys_config *mmsys_config = mmsys->data->config;
• u32 reg_val;
• u32 mask;
• u32 offset;
• int i;
• if (!mmsys->data->num_configs)

• return;
  

• for (i = 0; i < mmsys->data->num_configs; i++)

• if (config == mmsys_config[i].config && id == mmsys_config[i].id)
  

• 	break;
  

• if (i == mmsys->data->num_configs)

• return;
  

• offset = mmsys_config[i].addr;
• mask = mmsys_config[i].mask;
• reg_val = val << mmsys_config[i].shift;

+#if IS_REACHABLE(CONFIG_MTK_CMDQ)

• if (cmdq_pkt && mmsys->cmdq_base.size) {

• cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys,
  

• 		    mmsys->cmdq_base.offset + offset, reg_val,
  

• 		    mask);
  

• } else {

+#endif

• u32 tmp = readl(mmsys->regs + offset);
  

• tmp = (tmp & ~mask) | reg_val;
  

• writel(tmp, mmsys->regs + offset);
  

+#if IS_REACHABLE(CONFIG_MTK_CMDQ)

• }

+#endif +} +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);

static int mtk_mmsys_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -124,6 +168,12 @@ static int mtk_mmsys_probe(struct platform_device *pdev) }

mmsys->data = of_device_get_match_data(&pdev->dev);

+#if IS_REACHABLE(CONFIG_MTK_CMDQ)

• ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
• if (ret)

• dev_dbg(dev, "No mediatek,gce-client-reg!\n");
  

+#endif platform_set_drvdata(pdev, mmsys);

clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver, diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h index a760a34e6eca..084b1f5f3c88 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -73,10 +73,20 @@ struct mtk_mmsys_routes { u32 val; };

+struct mtk_mmsys_config {

• enum mtk_mmsys_config_type config;
• u32 id;
• u32 addr;
• u32 mask;
• u32 shift;

+};

struct mtk_mmsys_driver_data { const char *clk_driver; const struct mtk_mmsys_routes *routes; const unsigned int num_routes;

• const struct mtk_mmsys_config *config;
• const unsigned int num_configs;

};

/* diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 338c71570aeb..ba3925661cc9 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -6,6 +6,10 @@ #ifndef __MTK_MMSYS_H #define __MTK_MMSYS_H

+#include <linux/mailbox_controller.h> +#include <linux/mailbox/mtk-cmdq-mailbox.h> +#include <linux/soc/mediatek/mtk-cmdq.h>

enum mtk_ddp_comp_id; struct device;

@@ -54,6 +58,17 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_ID_MAX, };

+enum mtk_mmsys_config_type {

• MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
• MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
• MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH,
• MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT,
• MMSYS_CONFIG_HDR_ALPHA_SEL,
• MMSYS_CONFIG_MIXER_IN_ALPHA_ODD,
• MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN,
• MMSYS_CONFIG_MIXER_IN_CH_SWAP,

+};

void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next); @@ -62,4 +77,7 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next);

+void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,

• 	  u32 id, u32 val, struct cmdq_pkt *cmdq_pkt);
  

#endif /* __MTK_MMSYS_H */

Hi Enric,

Thanks for your review.

On Fri, 2021-07-23 at 12:57 +0200, Enric Balletbo Serra wrote:

Hi Nancy,

Thank you for your patch.

Missatge de Nancy.Lin nancy.lin@mediatek.com del dia dj., 22 de jul. 2021 a les 11:46:

...

Among other features the mmsys driver should implement a reset controller to be able to reset different bits from their space.

I'm working on a series that does the same, it should be nice if we can coordinate [1]

[1] https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-media...

OK, I will add this series to my reference base in the next patch revision.

...

Signed-off-by: Nancy.Lin nancy.lin@mediatek.com

drivers/soc/mediatek/mt8195-mmsys.h | 1 + drivers/soc/mediatek/mtk-mmsys.c | 77 +++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.h | 1 + 3 files changed, 79 insertions(+)

diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h index 4bdb2087250c..a7f6e275bfe5 100644 --- a/drivers/soc/mediatek/mt8195-mmsys.h +++ b/drivers/soc/mediatek/mt8195-mmsys.h @@ -154,6 +154,7 @@ #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1 << 0) #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2 << 0)

+#define MT8195_VDO1_SW0_RST_B 0x1d0 #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30 #define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40 #define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50 diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index d0f4a407f8f8..1ae04efeadab 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -4,10 +4,12 @@

• Author: James Liao jamesjj.liao@mediatek.com

*/

+#include <linux/delay.h> #include <linux/device.h> #include <linux/io.h> #include <linux/of_device.h> #include <linux/platform_device.h> +#include <linux/reset-controller.h> #include <linux/soc/mediatek/mtk-mmsys.h>

#include "mtk-mmsys.h" @@ -15,6 +17,8 @@ #include "mt8183-mmsys.h" #include "mt8195-mmsys.h"

+#define MMSYS_SW_RESET_PER_REG 32

static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .clk_driver = "clk-mt2701-mm", .routes = mmsys_default_routing_table, @@ -65,12 +69,15 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table), .config = mmsys_mt8195_config_table, .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),

•   .sw_reset_start = MT8195_VDO1_SW0_RST_B,
  

That change is interesting and I think I should also take it into consideration with my series.

...

};

struct mtk_mmsys { void __iomem *regs; struct cmdq_client_reg cmdq_base; const struct mtk_mmsys_driver_data *data;

•   spinlock_t lock; /* protects mmsys_sw_rst_b reg */
  

Seems that mmsys_sw_rst_b reg has different names for different SoCs? I mean I know that for MT8173 and MT8183 the register is called mmsys_sw0_rst_b but looks like for MT8195 the name is vdo1_sw0_rst_b? So maybe we should update this comment to be more generic.

Yes, the name of MT8195 vdosys1 sw reset is called VDOSYS1_SW0_RST_B and the name of vdosys0 sw reset is called GLOBAL0_SW0_RST_B. They have a different name. Maybe we can change the comment to "protects mmsys sw reset reg".

...

...

•   struct reset_controller_dev rcdev;
  

};

void mtk_mmsys_ddp_connect(struct device *dev, @@ -148,6 +155,63 @@ void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config, } EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);

+static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,

•                             bool assert)
  

+{

•   struct mtk_mmsys *mmsys = container_of(rcdev, struct
  

mtk_mmsys, rcdev);

•   unsigned long flags;
  

•   u32 reg;
  

•   int i;
  

•   u32 offset;
  

•   offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
  

•   id = 1 << (id % MMSYS_SW_RESET_PER_REG);
  

•   spin_lock_irqsave(&mmsys->lock, flags);
  

•   reg = readl_relaxed(mmsys->regs + mmsys->data-
  

...

sw_reset_start + offset);

•   if (assert)
  

•           reg &= ~BIT(id);
  

•   else
  

•           reg |= BIT(id);
  

•   writel_relaxed(reg, mmsys->regs + mmsys->data-
  

...

sw_reset_start + offset);

•   spin_unlock_irqrestore(&mmsys->lock, flags);
  

•   return 0;
  

+}

+static int mtk_mmsys_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) +{

•   return mtk_mmsys_reset_update(rcdev, id, true);
  

+}

+static int mtk_mmsys_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) +{

•   return mtk_mmsys_reset_update(rcdev, id, false);
  

+}

+static int mtk_mmsys_reset(struct reset_controller_dev *rcdev, unsigned long id) +{

•   int ret;
  

•   ret = mtk_mmsys_reset_assert(rcdev, id);
  

•   if (ret)
  

•           return ret;
  

•   usleep_range(1000, 1100);
  

One question that I received in my series, and I couldn't answer because I don't have the datasheet, is if is this known to be enough for all IP cores that can be reset by this controller? Is this time specified in the datasheet?

It only takes few cycles for the reset. The 1000us is enough for the reset to take effect.

...

•   return mtk_mmsys_reset_deassert(rcdev, id);
  

+}

+static const struct reset_control_ops mtk_mmsys_reset_ops = {

•   .assert = mtk_mmsys_reset_assert,
  

•   .deassert = mtk_mmsys_reset_deassert,
  

•   .reset = mtk_mmsys_reset,
  

+};

static int mtk_mmsys_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -174,6 +238,19 @@ static int mtk_mmsys_probe(struct platform_device *pdev) if (ret) dev_dbg(dev, "No mediatek,gce-client-reg!\n"); #endif

•   spin_lock_init(&mmsys->lock);
  

•   mmsys->rcdev.owner = THIS_MODULE;
  

•   mmsys->rcdev.nr_resets = 64;
  

Is the number of resets 64 for MT8195? I think is 32 for MT8173 and MT8183. Can you confirm?

Thanks, Enric

The number of resets in MT8195 vdosys1 is 64 (43 resets are used, 21 are not used).

...

•   mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
  

•   mmsys->rcdev.of_node = pdev->dev.of_node;
  

•   ret = devm_reset_controller_register(&pdev->dev, &mmsys-
  

...

rcdev);

•   if (ret) {
  

•           dev_err(&pdev->dev, "Couldn't register mmsys reset
  

controller: %d\n", ret);

•           return ret;
  

•   }
  

•   platform_set_drvdata(pdev, mmsys);
  
    clks = platform_device_register_data(&pdev->dev, mmsys-
  

...

data->clk_driver,

diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h index 084b1f5f3c88..cc57c3895c51 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -87,6 +87,7 @@ struct mtk_mmsys_driver_data { const unsigned int num_routes; const struct mtk_mmsys_config *config; const unsigned int num_configs;

•   u32 sw_reset_start;
  

};

/*

2.18.0

Hi Enric,

On Wed, 2021-07-28 at 12:31 +0200, Enric Balletbo Serra wrote:

Hi Nancy,

Missatge de Nancy.Lin nancy.lin@mediatek.com del dia dc., 28 de jul. 2021 a les 8:01:

...

Hi Enric,

Thanks for your review.

On Fri, 2021-07-23 at 12:57 +0200, Enric Balletbo Serra wrote:

...

Hi Nancy,

Thank you for your patch.

Missatge de Nancy.Lin nancy.lin@mediatek.com del dia dj., 22 de jul. 2021 a les 11:46:

...

Among other features the mmsys driver should implement a reset controller to be able to reset different bits from their space.

I'm working on a series that does the same, it should be nice if we can coordinate [1]

[1]

https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-media...

...

...

OK, I will add this series to my reference base in the next patch revision.

...

...

Signed-off-by: Nancy.Lin nancy.lin@mediatek.com

drivers/soc/mediatek/mt8195-mmsys.h | 1 + drivers/soc/mediatek/mtk-mmsys.c | 77 +++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.h | 1 + 3 files changed, 79 insertions(+)

diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h index 4bdb2087250c..a7f6e275bfe5 100644 --- a/drivers/soc/mediatek/mt8195-mmsys.h +++ b/drivers/soc/mediatek/mt8195-mmsys.h @@ -154,6 +154,7 @@ #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1 << 0) #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2 << 0)

+#define MT8195_VDO1_SW0_RST_B 0x1d0 #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30 #define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40 #define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50 diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index d0f4a407f8f8..1ae04efeadab 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -4,10 +4,12 @@

• Author: James Liao jamesjj.liao@mediatek.com

*/

+#include <linux/delay.h> #include <linux/device.h> #include <linux/io.h> #include <linux/of_device.h> #include <linux/platform_device.h> +#include <linux/reset-controller.h> #include <linux/soc/mediatek/mtk-mmsys.h>

#include "mtk-mmsys.h" @@ -15,6 +17,8 @@ #include "mt8183-mmsys.h" #include "mt8195-mmsys.h"

+#define MMSYS_SW_RESET_PER_REG 32

static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .clk_driver = "clk-mt2701-mm", .routes = mmsys_default_routing_table, @@ -65,12 +69,15 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table), .config = mmsys_mt8195_config_table, .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),

•   .sw_reset_start = MT8195_VDO1_SW0_RST_B,
  

That change is interesting and I think I should also take it into consideration with my series.

...

};

struct mtk_mmsys { void __iomem *regs; struct cmdq_client_reg cmdq_base; const struct mtk_mmsys_driver_data *data;

•   spinlock_t lock; /* protects mmsys_sw_rst_b reg */
  

Seems that mmsys_sw_rst_b reg has different names for different SoCs? I mean I know that for MT8173 and MT8183 the register is called mmsys_sw0_rst_b but looks like for MT8195 the name is vdo1_sw0_rst_b? So maybe we should update this comment to be more generic.

Yes, the name of MT8195 vdosys1 sw reset is called VDOSYS1_SW0_RST_B and the name of vdosys0 sw reset is called GLOBAL0_SW0_RST_B. They have a different name. Maybe we can change the comment to "protects mmsys sw reset reg".

...

...

•   struct reset_controller_dev rcdev;
  

};

void mtk_mmsys_ddp_connect(struct device *dev, @@ -148,6 +155,63 @@ void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config, } EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);

+static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,

•                             bool assert)
  

+{

•   struct mtk_mmsys *mmsys = container_of(rcdev, struct
  

mtk_mmsys, rcdev);

•   unsigned long flags;
  

•   u32 reg;
  

•   int i;
  

•   u32 offset;
  

•   offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
  

•   id = 1 << (id % MMSYS_SW_RESET_PER_REG);
  

•   spin_lock_irqsave(&mmsys->lock, flags);
  

•   reg = readl_relaxed(mmsys->regs + mmsys->data-
  

...

sw_reset_start + offset);

•   if (assert)
  

•           reg &= ~BIT(id);
  

•   else
  

•           reg |= BIT(id);
  

•   writel_relaxed(reg, mmsys->regs + mmsys->data-
  

...

sw_reset_start + offset);

•   spin_unlock_irqrestore(&mmsys->lock, flags);
  

•   return 0;
  

+}

+static int mtk_mmsys_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) +{

•   return mtk_mmsys_reset_update(rcdev, id, true);
  

+}

+static int mtk_mmsys_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) +{

•   return mtk_mmsys_reset_update(rcdev, id, false);
  

+}

+static int mtk_mmsys_reset(struct reset_controller_dev *rcdev, unsigned long id) +{

•   int ret;
  

•   ret = mtk_mmsys_reset_assert(rcdev, id);
  

•   if (ret)
  

•           return ret;
  

•   usleep_range(1000, 1100);
  

One question that I received in my series, and I couldn't answer because I don't have the datasheet, is if is this known to be enough for all IP cores that can be reset by this controller? Is this time specified in the datasheet?

It only takes few cycles for the reset. The 1000us is enough for the reset to take effect.

Saying enough looks to me that 1000us is a random number, is there any specific real number in the datasheet?

Note that I'm not against it, just want to make sure the number makes sense.

No real number is specified in the datasheet. I checked with the hardware designer, and the reset takes four cycles of mm IP cores.

For example: If the mm IP cores run at 200MHz, it will take 20ns(4/200M) for the reset to take effect.

...

...

...

•   return mtk_mmsys_reset_deassert(rcdev, id);
  

+}

+static const struct reset_control_ops mtk_mmsys_reset_ops = {

•   .assert = mtk_mmsys_reset_assert,
  

•   .deassert = mtk_mmsys_reset_deassert,
  

•   .reset = mtk_mmsys_reset,
  

+};

static int mtk_mmsys_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -174,6 +238,19 @@ static int mtk_mmsys_probe(struct platform_device *pdev) if (ret) dev_dbg(dev, "No mediatek,gce-client-reg!\n"); #endif

•   spin_lock_init(&mmsys->lock);
  

•   mmsys->rcdev.owner = THIS_MODULE;
  

•   mmsys->rcdev.nr_resets = 64;
  

Is the number of resets 64 for MT8195? I think is 32 for MT8173 and MT8183. Can you confirm?

Thanks, Enric

The number of resets in MT8195 vdosys1 is 64 (43 resets are used, 21 are not used).

Ok, thanks for the information.

...

...

...

•   mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
  

•   mmsys->rcdev.of_node = pdev->dev.of_node;
  

•   ret = devm_reset_controller_register(&pdev->dev,
  

&mmsys-

...

rcdev);

•   if (ret) {
  

•           dev_err(&pdev->dev, "Couldn't register mmsys
  

reset controller: %d\n", ret);

•           return ret;
  

•   }
  

•   platform_set_drvdata(pdev, mmsys);
  
    clks = platform_device_register_data(&pdev->dev, mmsys-
  

...

data->clk_driver,

diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h index 084b1f5f3c88..cc57c3895c51 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -87,6 +87,7 @@ struct mtk_mmsys_driver_data { const unsigned int num_routes; const struct mtk_mmsys_config *config; const unsigned int num_configs;

•   u32 sw_reset_start;
  

};

/*

2.18.0

Hi, Nancy:

Nancy.Lin nancy.lin@mediatek.com 於 2021年7月22日 週四 下午5:46寫道：

Add pseudo ovl module files:

My English is not good. The word 'pseudo' seems like 'looks like but indeed not the same'. I think the 'real' ovl also has rdma and mixer inside it, so I prefer to treat these two ovl as different kind of ovl, not a real one and a pseudo one. Does I misunderstanding the word 'pseudo'?

Pseudo ovl is an encapsulated module and designed for simplified DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and an ETHDR. Two RDMAs merge into one layer, so this module support 4 layers.

Signed-off-by: Nancy.Lin nancy.lin@mediatek.com

drivers/gpu/drm/mediatek/Makefile | 4 +- .../gpu/drm/mediatek/mtk_disp_pseudo_ovl.c | 593 ++++++++++++++++++ .../gpu/drm/mediatek/mtk_disp_pseudo_ovl.h | 23 + drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 456 ++++++++++++++ drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 109 ++++ drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h | 160 +++++

Seperate mtk_dmp_rdma driver to an independent patch.

6 files changed, 1344 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h

diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index 27c89847d43b..31613564f499 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -13,7 +13,9 @@ mediatek-drm-y := mtk_disp_ccorr.o \ mtk_drm_gem.o \ mtk_drm_plane.o \ mtk_dsi.o \

•             mtk_dpi.o
  

•             mtk_dpi.o \
  

•             mtk_disp_pseudo_ovl.o \
  

•             mtk_mdp_rdma.o
  
  

obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c new file mode 100644 index 000000000000..0446fa99dd0a --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c @@ -0,0 +1,593 @@ +// SPDX-License-Identifier: GPL-2.0-only +/*

• • Copyright (c) 2021 MediaTek Inc.
• */

+#include <drm/drm_fourcc.h> +#include <linux/clk.h> +#include <linux/reset.h> +#include <linux/component.h> +#include <linux/of_device.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/soc/mediatek/mtk-mmsys.h> +#include <linux/soc/mediatek/mtk-cmdq.h>

+#include "mtk_drm_drv.h" +#include "mtk_drm_crtc.h" +#include "mtk_drm_ddp_comp.h" +#include "mtk_mdp_rdma.h" +#include "mtk_disp_pseudo_ovl.h"

+#define DISP_MERGE_ENABLE 0x0

•   #define MERGE_ENABLE BIT(0)
  

+#define DISP_MERGE_CFG_0 0x10 +#define DISP_MERGE_CFG_1 0x14 +#define DISP_MERGE_CFG_4 0x20 +#define DISP_MERGE_CFG_5 0x24 +#define DISP_MERGE_CFG_10 0x38

•   #define CFG_10_NO_SWAP 0
  

+#define DISP_MERGE_CFG_12 0x40

•   #define CFG12_10_10_1PI_2PO_BUF_MODE 6
  

•   #define CFG12_11_10_1PI_2PO_MERGE 18
  

+#define DISP_MERGE_CFG_24 0x70 +#define DISP_MERGE_CFG_25 0x74 +#define DISP_MERGE_CFG_26 0x78 +#define DISP_MERGE_CFG_27 0x7c +#define DISP_MERGE_MUTE_0 0xf00

+#define MTK_PSEUDO_OVL_SINGLE_PIPE_MAX_WIDTH 1920

Which hardware has this limitation? I would like this naming to reflect which hardware has this limitation.

+enum mtk_pseudo_ovl_comp_type {

•   PSEUDO_OVL_TYPE_RDMA = 0,
  

•   PSEUDO_OVL_TYPE_MERGE,
  

•   PSEUDO_OVL_TYPE_NUM,
  

+};

+enum mtk_pseudo_ovl_comp_id {

•   PSEUDO_OVL_RDMA_BASE = 0,
  

•   PSEUDO_OVL_MDP_RDMA0 = PSEUDO_OVL_RDMA_BASE,
  

I think you could directly use PSEUDO_OVL_MDP_RDMA0 and remove PSEUDO_OVL_RDMA_BASE.

•   PSEUDO_OVL_MDP_RDMA1,
  

•   PSEUDO_OVL_MDP_RDMA2,
  

•   PSEUDO_OVL_MDP_RDMA3,
  

•   PSEUDO_OVL_MDP_RDMA4,
  

•   PSEUDO_OVL_MDP_RDMA5,
  

•   PSEUDO_OVL_MDP_RDMA6,
  

•   PSEUDO_OVL_MDP_RDMA7,
  

•   PSEUDO_OVL_MERGE_BASE,
  

•   PSEUDO_OVL_MERGE0 = PSEUDO_OVL_MERGE_BASE,
  

Ditto.

•   PSEUDO_OVL_MERGE1,
  

•   PSEUDO_OVL_MERGE2,
  

•   PSEUDO_OVL_MERGE3,
  

•   PSEUDO_OVL_ID_MAX
  

+};

+struct pseudo_ovl_data {

•   unsigned int layer_nr;
  

•   struct mtk_mdp_rdma_fifo fifo;
  

+};

+struct pseudo_ovl_comp_match {

•   enum mtk_pseudo_ovl_comp_type type;
  

•   int alias_id;
  

+};

+struct pseudo_ovl_merge_config {

•   unsigned int fmt;
  

•   unsigned int merge_mode;
  

•   unsigned int in_w[2];
  

•   unsigned int out_w[2];
  

•   unsigned int in_h;
  

+};

+struct mtk_pseudo_ovl_comp {

•   struct device *dev;
  

•   struct clk *clks[2];
  

•   struct cmdq_client_reg cmdq_base;
  

•   void __iomem *regs;
  

+};

+struct mtk_disp_pseudo_ovl {

•   struct mtk_pseudo_ovl_comp pseudo_ovl_comp[PSEUDO_OVL_ID_MAX];
  

•   const struct pseudo_ovl_data *data;
  

•   struct device *mmsys_dev;
  

+};

+static const char * const pseudo_ovl_comp_str[] = {

•   "PSEUDO_OVL_MDP_RDMA0",
  

•   "PSEUDO_OVL_MDP_RDMA1",
  

•   "PSEUDO_OVL_MDP_RDMA2",
  

•   "PSEUDO_OVL_MDP_RDMA3",
  

•   "PSEUDO_OVL_MDP_RDMA4",
  

•   "PSEUDO_OVL_MDP_RDMA5",
  

•   "PSEUDO_OVL_MDP_RDMA6",
  

•   "PSEUDO_OVL_MDP_RDMA7",
  

•   "PSEUDO_OVL_MERGE0",
  

•   "PSEUDO_OVL_MERGE1",
  

•   "PSEUDO_OVL_MERGE2",
  

•   "PSEUDO_OVL_MERGE3",
  

•   "PSEUDO_OVL_ID_MAX"
  

+};

+static const char * const private_comp_stem[PSEUDO_OVL_TYPE_NUM] = {

•   [PSEUDO_OVL_TYPE_RDMA] = "vdo1_rdma",
  

•   [PSEUDO_OVL_TYPE_MERGE] = "merge",
  

+};

+static const struct pseudo_ovl_comp_match comp_matches[PSEUDO_OVL_ID_MAX] = {

•   [PSEUDO_OVL_MDP_RDMA0] =        { PSEUDO_OVL_TYPE_RDMA, 0 },
  

•   [PSEUDO_OVL_MDP_RDMA1] =        { PSEUDO_OVL_TYPE_RDMA, 1 },
  

•   [PSEUDO_OVL_MDP_RDMA2] =        { PSEUDO_OVL_TYPE_RDMA, 2 },
  

•   [PSEUDO_OVL_MDP_RDMA3] =        { PSEUDO_OVL_TYPE_RDMA, 3 },
  

•   [PSEUDO_OVL_MDP_RDMA4] =        { PSEUDO_OVL_TYPE_RDMA, 4 },
  

•   [PSEUDO_OVL_MDP_RDMA5] =        { PSEUDO_OVL_TYPE_RDMA, 5 },
  

•   [PSEUDO_OVL_MDP_RDMA6] =        { PSEUDO_OVL_TYPE_RDMA, 6 },
  

•   [PSEUDO_OVL_MDP_RDMA7] =        { PSEUDO_OVL_TYPE_RDMA, 7 },
  

•   [PSEUDO_OVL_MERGE0] =   { PSEUDO_OVL_TYPE_MERGE, 1 },
  

•   [PSEUDO_OVL_MERGE1] =   { PSEUDO_OVL_TYPE_MERGE, 2 },
  

•   [PSEUDO_OVL_MERGE2] =   { PSEUDO_OVL_TYPE_MERGE, 3 },
  

•   [PSEUDO_OVL_MERGE3] =   { PSEUDO_OVL_TYPE_MERGE, 4 },
  

+};

+static int mtk_pseudo_ovl_fifo_setting(struct mtk_disp_pseudo_ovl *pseudo_ovl,

•                                  struct cmdq_pkt *handle)
  

+{

•   struct mtk_pseudo_ovl_comp *rdma = NULL;
  

•   const struct pseudo_ovl_data *data = pseudo_ovl->data;
  

•   const struct mtk_mdp_rdma_fifo *fifo = &data->fifo;
  

•   int i;
  

•   for (i = PSEUDO_OVL_MDP_RDMA0; i <= PSEUDO_OVL_MDP_RDMA7; i++) {
  

•           rdma = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + i];
  

•           mtk_mdp_rdma_fifo_config(rdma->regs, handle, &rdma->cmdq_base, fifo);
  

•   }
  

•   return 0;
  

+}

+static void mtk_pseudo_ovl_merge_config(struct mtk_pseudo_ovl_comp *comp,

•                                   struct pseudo_ovl_merge_config *merge_cfg,
  

•                                   struct cmdq_pkt *cmdq_pkt)
  

+{

•   switch (merge_cfg->merge_mode) {
  

•   case 6:
  

•           mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
  

•                         &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
  

•           mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
  

•                         &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4);
  

•           mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
  

•                         &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24);
  

•           mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
  

•                         &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25);
  

•           break;
  

•   case 18:
  

•           mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
  

•                         &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
  

•           mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
  

•                         &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_1);
  

•           mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
  

•                         &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4);
  

•           mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
  

•                         &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24);
  

•           mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
  

•                         &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25);
  

•           mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
  

•                         &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_26);
  

•           mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
  

•                         &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_27);
  

•           break;
  

•   default:
  

•           mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
  

•                         &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
  

•           mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
  

•                         &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_1);
  

•           mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
  

•                         &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4);
  

•           mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[1]),
  

•                         &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_5);
  

•           break;
  

•   }
  

•   mtk_ddp_write(cmdq_pkt, merge_cfg->merge_mode, &comp->cmdq_base,
  

•                 comp->regs, DISP_MERGE_CFG_12);
  

•   mtk_ddp_write(cmdq_pkt, CFG_10_NO_SWAP, &comp->cmdq_base,
  

•                 comp->regs, DISP_MERGE_CFG_10);
  

•   mtk_ddp_write_mask(cmdq_pkt, 1, &comp->cmdq_base, comp->regs,
  

•                      DISP_MERGE_ENABLE, MERGE_ENABLE);
  

+}

+void mtk_pseudo_ovl_layer_config(struct device *dev, unsigned int idx,

•                            struct mtk_plane_state *state,
  

•                            struct cmdq_pkt *cmdq_pkt)
  

+{

•   struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
  

•   struct mtk_plane_pending_state *pending = &state->pending;
  

•   struct pseudo_ovl_merge_config merge_cfg = {0};
  

•   struct mtk_mdp_rdma_cfg rdma_config = {0};
  

•   struct mtk_pseudo_ovl_comp *rdma_l;
  

•   struct mtk_pseudo_ovl_comp *rdma_r;
  

•   struct mtk_pseudo_ovl_comp *merge;
  

•   const struct drm_format_info *fmt_info = drm_format_info(pending->format);
  

•   bool use_dual_pipe = false;
  

•   dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__, idx,
  

•           pending->enable, pending->format);
  

•   dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
  

•           pending->addr, (pending->pitch / fmt_info->cpp[0]),
  

•           pending->x, pending->y, pending->width, pending->height);
  

•   rdma_l = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * idx];
  

•   rdma_r = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * idx + 1];
  

•   merge = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_MERGE_BASE + idx];
  

•   if (!pending->enable) {
  

•           mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
  

•                              DISP_MERGE_ENABLE, MERGE_ENABLE);
  

•           mtk_mdp_rdma_stop(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
  

•           mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
  

•           return;
  

•   }
  

•   if (pending->width > MTK_PSEUDO_OVL_SINGLE_PIPE_MAX_WIDTH)
  

•           use_dual_pipe = true;
  

•   merge_cfg.out_w[0] = pending->width;
  

•   merge_cfg.in_h = pending->height;
  

•   merge_cfg.fmt = pending->format;
  

•   if (use_dual_pipe) {
  

•           merge_cfg.merge_mode = CFG12_11_10_1PI_2PO_MERGE;
  

•           merge_cfg.in_w[0] = (pending->width / 2) + ((pending->width / 2) % 2);
  

•           merge_cfg.in_w[1] = (pending->width / 2) - ((pending->width / 2) % 2);
  

•   } else {
  

•           merge_cfg.merge_mode = CFG12_10_10_1PI_2PO_BUF_MODE;
  

•           merge_cfg.in_w[0] = pending->width;
  

•   }
  

•   mtk_pseudo_ovl_merge_config(merge, &merge_cfg, cmdq_pkt);
  

•   mtk_mmsys_ddp_config(pseudo_ovl->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
  

•                        idx, pending->width / 2, cmdq_pkt);
  

•   mtk_mmsys_ddp_config(pseudo_ovl->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
  

•                        idx, pending->height, cmdq_pkt);
  

•   rdma_config.source_width = pending->pitch / fmt_info->cpp[0];
  

•   rdma_config.csc_enable = fmt_info->is_yuv ? true : false;
  

•   rdma_config.profile = RDMA_CSC_FULL709_TO_RGB;
  

•   rdma_config.encode_type = RDMA_ENCODE_NONE;
  

•   rdma_config.block_size = RDMA_BLOCK_NONE;
  

•   rdma_config.width = merge_cfg.in_w[0];
  

•   rdma_config.height = pending->height;
  

•   rdma_config.addr0 = pending->addr;
  

•   rdma_config.fmt = pending->format;
  

•   mtk_mdp_rdma_config(rdma_l->regs, &rdma_config, cmdq_pkt, &rdma_l->cmdq_base);
  

•   rdma_config.x_left = merge_cfg.in_w[0];
  

•   rdma_config.width = merge_cfg.in_w[1];
  

•   mtk_mdp_rdma_config(rdma_r->regs, &rdma_config, cmdq_pkt, &rdma_r->cmdq_base);
  

•   mtk_ddp_write_mask(cmdq_pkt, 0x1, &merge->cmdq_base, merge->regs,
  

•                      DISP_MERGE_ENABLE, MERGE_ENABLE);
  

•   mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
  

•                      DISP_MERGE_MUTE_0, 0x1);
  

•   mtk_mdp_rdma_start(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
  

•   if (use_dual_pipe)
  

•           mtk_mdp_rdma_start(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
  

•   else
  

•           mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
  

+}

+void mtk_pseudo_ovl_config(struct device *dev, unsigned int w, unsigned int h,

•                      unsigned int vrefresh, unsigned int bpc,
  

•                      struct cmdq_pkt *cmdq_pkt)
  

+{

•   struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
  

•   dev_info(dev, "%s w:%d, h:%d\n", __func__, w, h);
  

•   mtk_pseudo_ovl_fifo_setting(pseudo_ovl, cmdq_pkt);
  

+}

+void mtk_pseudo_ovl_start(struct device *dev) +{ +}

+void mtk_pseudo_ovl_stop(struct device *dev) +{

•   struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
  

•   struct mtk_pseudo_ovl_comp *rdma_l;
  

•   struct mtk_pseudo_ovl_comp *rdma_r;
  

•   struct mtk_pseudo_ovl_comp *merge;
  

•   unsigned int reg;
  

•   u32 i;
  

•   for (i = 0; i < pseudo_ovl->data->layer_nr; i++) {
  

•           rdma_l = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * i];
  

•           rdma_r = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * i + 1];
  

•           merge = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_MERGE_BASE + i];
  

•           mtk_mdp_rdma_stop(rdma_l->regs, NULL, &rdma_l->cmdq_base);
  

•           mtk_mdp_rdma_stop(rdma_r->regs, NULL, &rdma_r->cmdq_base);
  

•           reg = readl(merge->regs + DISP_MERGE_ENABLE);
  

•           reg = reg & ~MERGE_ENABLE;
  

•           writel_relaxed(reg, merge->regs + DISP_MERGE_ENABLE);
  

•           device_reset_optional(merge->dev);
  

•   }
  

+}

+int mtk_pseudo_ovl_clk_enable(struct device *dev) +{

•   struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
  

•   struct mtk_pseudo_ovl_comp *comp;
  

•   int ret;
  

•   int i;
  

•   int j;
  

•   for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_ID_MAX; i++) {
  

•           comp = &pseudo_ovl->pseudo_ovl_comp[i];
  

•           if (!comp->dev)
  

•                   continue;
  

•           /* Need to power on for private rdma devices */
  

•           if (i < PSEUDO_OVL_MERGE_BASE) {
  

•                   ret = pm_runtime_get_sync(comp->dev);
  

•                   if (ret < 0)
  

•                           dev_err(dev,
  

•                                   "Failed to power on, err %d-%s\n",
  

•                                   ret, pseudo_ovl_comp_str[i]);
  

•           }
  

•           for (j = 0; j < ARRAY_SIZE(comp->clks); j++) {
  

•                   if (IS_ERR(comp->clks[j]))
  

•                           break;
  

•                   ret = clk_prepare_enable(comp->clks[j]);
  

•                   if (ret)
  

•                           dev_err(dev,
  

•                                   "Failed to enable clock %d, err %d-%s\n",
  

•                                   i, ret, pseudo_ovl_comp_str[i]);
  

•           }
  

•   }
  

•   return ret;
  

+}

+void mtk_pseudo_ovl_clk_disable(struct device *dev) +{

•   struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
  

•   struct mtk_pseudo_ovl_comp *comp;
  

•   int ret;
  

•   int i;
  

•   int j;
  

•   for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_ID_MAX; i++) {
  

•           comp = &pseudo_ovl->pseudo_ovl_comp[i];
  

•           if (!comp->dev)
  

•                   continue;
  

•           for (j = 0; i < ARRAY_SIZE(comp->clks); j++) {
  

•                   if (IS_ERR(comp->clks[j]))
  

•                           break;
  

•                   clk_disable_unprepare(comp->clks[j]);
  

•           }
  

•           /* Need to power off for private rdma devices */
  

•           if (i < PSEUDO_OVL_MERGE_BASE) {
  

•                   ret = pm_runtime_put(comp->dev);
  

•                   if (ret < 0)
  

•                           dev_err(dev,
  

•                                   "Failed to power off, err-%s\n",
  

•                                   ret, pseudo_ovl_comp_str[i]);
  

•           }
  

•   }
  

+}

+static int pseudo_ovl_comp_get_id(struct device *dev, struct device_node *node,

•                             enum mtk_pseudo_ovl_comp_type type)
  

+{

•   int alias_id = of_alias_get_id(node, private_comp_stem[type]);
  

•   int ret;
  

•   int i;
  

•   for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
  

•           if (comp_matches[i].type == type &&
  

•               comp_matches[i].alias_id == alias_id)
  

•                   return i;
  

•   dev_err(dev, "Failed to get id. type: %d, alias: %d\n", type, alias_id);
  

•   return -EINVAL;
  

+}

+static int private_comp_init(struct device *dev, struct device_node *node,

•                        struct mtk_pseudo_ovl_comp *comp,
  

•                        enum mtk_pseudo_ovl_comp_id id)
  

+{

•   struct platform_device *comp_pdev;
  

•   int ret;
  

•   int i;
  

•   if (id < 0 || id >= PSEUDO_OVL_ID_MAX) {
  

•           dev_err(dev, "Invalid component id %d\n", id);
  

•           return -EINVAL;
  

•   }
  

•   comp_pdev = of_find_device_by_node(node);
  

•   if (!comp_pdev) {
  

•           dev_warn(dev, "can't find platform device of node:%s\n",
  

•                    node->name);
  

•           return -ENODEV;
  

•   }
  

•   comp->dev = &comp_pdev->dev;
  

•   comp->regs = of_iomap(node, 0);
  

•   for (i = 0; i < ARRAY_SIZE(comp->clks); i++) {
  

•           comp->clks[i] = of_clk_get(node, i);
  

•           if (IS_ERR(comp->clks[i]))
  

•                   break;
  

•   }
  

+#if IS_REACHABLE(CONFIG_MTK_CMDQ)

•   ret = cmdq_dev_get_client_reg(comp->dev, &comp->cmdq_base, 0);
  

•   if (ret)
  

•           dev_info(dev, "get mediatek,gce-client-reg fail!\n");
  

+#endif

•   if (id < PSEUDO_OVL_MERGE_BASE)
  

•           pm_runtime_enable(comp->dev);
  

•   dev_info(dev, "[DRM]regs:0x%p, node:%s\n", comp->regs, pseudo_ovl_comp_str[id]);
  

•   return 0;
  

+}

+static int mtk_disp_pseudo_ovl_comp_probe(struct platform_device *pdev) +{

•   return 0;
  

+}

+static int mtk_disp_pseudo_ovl_comp_remove(struct platform_device *pdev) +{

•   return 0;
  

+}

+static const struct of_device_id mtk_pseudo_ovl_comp_dt_ids[] = {

•   {
  

•           .compatible = "mediatek,mt8195-vdo1-rdma",
  

•           .data = (void *)PSEUDO_OVL_TYPE_RDMA,
  

•   }, {
  

•           .compatible = "mediatek,mt8195-vdo1-merge",
  

•           .data = (void *)PSEUDO_OVL_TYPE_MERGE,
  

•   },
  

•   {},
  

+};

+static struct platform_driver mtk_disp_pseudo_ovl_comp_driver = {

•   .probe          = mtk_disp_pseudo_ovl_comp_probe,
  

•   .remove         = mtk_disp_pseudo_ovl_comp_remove,
  

•   .driver = {
  

•           .name   = "mediatek-disp-pseudo-ovl-comp",
  

•           .owner  = THIS_MODULE,
  

•           .of_match_table = mtk_pseudo_ovl_comp_dt_ids,
  

•   },
  

+}; +module_platform_driver(mtk_disp_pseudo_ovl_comp_driver);

+static int pseudo_ovl_comp_init(struct device *dev) +{

•   struct mtk_disp_pseudo_ovl *priv = dev_get_drvdata(dev);
  

•   struct device_node *node, *parent;
  

•   int i, ret;
  

•   parent = dev->parent->of_node->parent;
  

•   for_each_child_of_node(parent, node) {
  

•           const struct of_device_id *of_id;
  

•           enum mtk_pseudo_ovl_comp_type type;
  

•           struct mtk_pseudo_ovl_comp *comp;
  

•           int id;
  

•           of_id = of_match_node(mtk_pseudo_ovl_comp_dt_ids, node);
  

•           if (!of_id)
  

•                   continue;
  

•           if (!of_device_is_available(node)) {
  

•                   dev_info(dev, "Skipping disabled component %pOF\n",
  

•                            node);
  

•                   continue;
  

•           }
  

•           type = (enum mtk_pseudo_ovl_comp_type)of_id->data;
  

•           id = pseudo_ovl_comp_get_id(dev, node, type);
  

•           if (id < 0) {
  

•                   dev_warn(dev, "Skipping unknown component %pOF\n",
  

•                            node);
  

•                   continue;
  

•           }
  

•           ret = private_comp_init(dev, node, &priv->pseudo_ovl_comp[id], id);
  

•           if (ret)
  

•                   return ret;
  

•   }
  

•   return 0;
  

+}

+static const struct pseudo_ovl_data mt8195_pseudo_ovl_driver_data = {

•   .layer_nr = 4,
  

•   .fifo.read_request_type = 7,
  

•   .fifo.command_div = 1,
  

•   .fifo.ext_preutra_en = 1,
  

•   .fifo.ultra_en = 0,
  

•   .fifo.pre_ultra_en = 1,
  

•   .fifo.ext_ultra_en = 1,
  

•   .fifo.extrd_arb_max_0 = 3,
  

•   .fifo.buf_resv_size_0 = 0,
  

•   .fifo.issue_req_th_0 = 0,
  

•   .fifo.ultra_h_con_0 = 156,
  

•   .fifo.ultra_l_con_0 = 104,
  

+};

Now only support one SoC, so remove driver data and change these to definition instead of variable.

+static const struct of_device_id pseudo_ovl_driver_dt_match[] = {

•   { .compatible = "mediatek,mt8195-disp-ethdr",
  

•     .data = &mt8195_pseudo_ovl_driver_data},
  

•   {},
  

+}; +MODULE_DEVICE_TABLE(of, mtk_disp_pseudo_ovl_driver_dt_match);

+static int mtk_disp_pseudo_ovl_probe(struct platform_device *pdev) +{

•   struct mtk_disp_pseudo_ovl *priv;
  

•   struct device *dev = &pdev->dev;
  

•   struct device_node *phandle = dev->parent->of_node;
  

•   const struct of_device_id *of_id;
  

•   int ret;
  

•   int i;
  

•   dev_info(dev, "%s+\n", __func__);
  

•   of_id = of_match_node(pseudo_ovl_driver_dt_match, phandle);
  

•   if (!of_id)
  

•           return -ENODEV;
  

•   priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  

•   if (!priv)
  

•           return -ENOMEM;
  

•   priv->mmsys_dev = pdev->dev.platform_data;
  

•   priv->data = of_id->data;
  

•   platform_set_drvdata(pdev, priv);
  

•   ret = pseudo_ovl_comp_init(dev);
  

•   if (ret) {
  

•           dev_notice(dev, "pseudo_ovl comp init fail\n");
  

•           return ret;
  

•   }
  

•   dev_info(dev, "%s-\n", __func__);
  

•   return ret;
  

+}

+static int mtk_disp_pseudo_ovl_remove(struct platform_device *pdev) +{

•   struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(&pdev->dev);
  

•   int i;
  

•   for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_MERGE_BASE; i++)
  

•           pm_runtime_disable(pseudo_ovl->pseudo_ovl_comp[i].dev);
  

•   return 0;
  

+}

+struct platform_driver mtk_disp_pseudo_ovl_driver = {

•   .probe = mtk_disp_pseudo_ovl_probe,
  

•   .remove = mtk_disp_pseudo_ovl_remove,
  

•   .driver = {
  

•                   .name = "mediatek-disp-pseudo-ovl",
  

•                   .owner = THIS_MODULE,
  

•           },
  

+}; +module_platform_driver(mtk_disp_pseudo_ovl_driver); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h new file mode 100644 index 000000000000..b3fe1e1702b8 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/*

• • Copyright (c) 2021 MediaTek Inc.
• */

+#ifndef __MTK_DISP_PSEUDO_OVL_H__ +#define __MTK_DISP_PSEUDO_OVL_H__

+#include <drm/mediatek_drm.h>

+void mtk_pseudo_ovl_start(struct device *dev); +void mtk_pseudo_ovl_stop(struct device *dev); +int mtk_pseudo_ovl_clk_enable(struct device *dev); +void mtk_pseudo_ovl_clk_disable(struct device *dev); +void mtk_pseudo_ovl_config(struct device *dev, unsigned int w, unsigned int h,

•                      unsigned int vrefresh, unsigned int bpc,
  

•                      struct cmdq_pkt *cmdq_pkt);
  

+void mtk_pseudo_ovl_layer_config(struct device *dev, unsigned int idx,

•                            struct mtk_plane_state *state,
  

•                            struct cmdq_pkt *cmdq_pkt);
  

+#endif

diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c new file mode 100644 index 000000000000..81d3cc4872eb --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c @@ -0,0 +1,456 @@ +// SPDX-License-Identifier: GPL-2.0-only +/*

• • Copyright (c) 2021 MediaTek Inc.
• */

+#include <drm/drm_fourcc.h> +#include "mtk_drm_drv.h" +#include "mtk_mdp_reg_rdma.h" +#include "mtk_mdp_rdma.h"

+#define RDMA_INPUT_SWAP BIT(14) +#define RDMA_INPUT_10BIT BIT(18) +#define IRQ_INT_EN_ALL \

•   (REG_FLD_MASK(FLD_UNDERRUN_INT_EN) |\
  

•    REG_FLD_MASK(FLD_REG_UPDATE_INT_EN) |\
  

•    REG_FLD_MASK(FLD_FRAME_COMPLETE_INT_EN))
  

+static unsigned int rdma_get_y_pitch(unsigned int fmt, unsigned int width) +{

•   switch (fmt) {
  

•   default:
  

•   case DRM_FORMAT_RGB565:
  

•   case DRM_FORMAT_BGR565:
  

•           return 2 * width;
  

•   case DRM_FORMAT_RGB888:
  

•   case DRM_FORMAT_BGR888:
  

•           return 3 * width;
  

•   case DRM_FORMAT_RGBX8888:
  

•   case DRM_FORMAT_RGBA8888:
  

•   case DRM_FORMAT_BGRX8888:
  

•   case DRM_FORMAT_BGRA8888:
  

•   case DRM_FORMAT_XRGB8888:
  

•   case DRM_FORMAT_ARGB8888:
  

•   case DRM_FORMAT_XBGR8888:
  

•   case DRM_FORMAT_ABGR8888:
  

•   case DRM_FORMAT_ARGB2101010:
  

•   case DRM_FORMAT_ABGR2101010:
  

•   case DRM_FORMAT_RGBA1010102:
  

•   case DRM_FORMAT_BGRA1010102:
  

•           return 4 * width;
  

•   case DRM_FORMAT_UYVY:
  

•   case DRM_FORMAT_YUYV:
  

•           return 2 * width;
  

•   case DRM_FORMAT_NV12:
  

•   case DRM_FORMAT_NV21:
  

•           return 1 * width;
  

•   }
  

+}

+static unsigned int rdma_get_uv_pitch(unsigned int fmt, unsigned int width) +{

•   switch (fmt) {
  

•   default:
  

•           return 0;
  

•   case DRM_FORMAT_NV12:
  

•   case DRM_FORMAT_NV21:
  

•           return 4 * width;
  

•   }
  

+}

+static unsigned int rdma_get_block_h(unsigned int mode) +{

•   switch (mode) {
  

•   default:
  

•           return 0;
  

•   case RDMA_BLOCK_8x8:
  

•   case RDMA_BLOCK_16x8:
  

•   case RDMA_BLOCK_32x8:
  

•           return 8;
  

•   case RDMA_BLOCK_8x16:
  

•   case RDMA_BLOCK_16x16:
  

•   case RDMA_BLOCK_32x16:
  

•           return 16;
  

•   case RDMA_BLOCK_8x32:
  

•   case RDMA_BLOCK_16x32:
  

•   case RDMA_BLOCK_32x32:
  

•           return 32;
  

•   }
  

+}

+static unsigned int rdma_get_horizontal_shift_uv(unsigned int fmt) +{

•   switch (fmt) {
  

•   default:
  

•           return 0;
  

•   case DRM_FORMAT_NV12:
  

•   case DRM_FORMAT_NV21:
  

•           return 1;
  

•   }
  

+}

+static unsigned int rdma_get_vertical_shift_uv(unsigned int fmt) +{

•   switch (fmt) {
  

•   default:
  

•           return 0;
  

•   case DRM_FORMAT_NV12:
  

•   case DRM_FORMAT_NV21:
  

•           return 1;
  

•   }
  

+}

+static unsigned int rdma_get_bits_per_pixel_y(unsigned int fmt) +{

•   switch (fmt) {
  

•   default:
  

•   case DRM_FORMAT_RGB565:
  

•   case DRM_FORMAT_BGR565:
  

•           return 16;
  

•   case DRM_FORMAT_RGB888:
  

•   case DRM_FORMAT_BGR888:
  

•           return 24;
  

•   case DRM_FORMAT_RGBX8888:
  

•   case DRM_FORMAT_RGBA8888:
  

•   case DRM_FORMAT_BGRX8888:
  

•   case DRM_FORMAT_BGRA8888:
  

•   case DRM_FORMAT_XRGB8888:
  

•   case DRM_FORMAT_ARGB8888:
  

•   case DRM_FORMAT_XBGR8888:
  

•   case DRM_FORMAT_ABGR8888:
  

•           return 32;
  

•   case DRM_FORMAT_UYVY:
  

•   case DRM_FORMAT_YUYV:
  

•           return 16;
  

•   case DRM_FORMAT_NV12:
  

•   case DRM_FORMAT_NV21:
  

•           return 8;
  

•   }
  

+}

+static unsigned int rdma_get_bits_per_pixel_uv(unsigned int fmt) +{

•   switch (fmt) {
  

•   default:
  

•           return 0;
  

•   case DRM_FORMAT_NV12:
  

•   case DRM_FORMAT_NV21:
  

•           return 16;
  

•   }
  

+}

+static bool with_alpha(uint32_t format) +{

•   const struct drm_format_info *fmt_info = drm_format_info(format);
  

•   return fmt_info->has_alpha;
  

+}

+static unsigned int rdma_fmt_convert(unsigned int fmt) +{

•   switch (fmt) {
  

•   default:
  

•   case DRM_FORMAT_RGB565:
  

•           return RDMA_INPUT_FORMAT_RGB565;
  

•   case DRM_FORMAT_BGR565:
  

•           return RDMA_INPUT_FORMAT_RGB565 | RDMA_INPUT_SWAP;
  

•   case DRM_FORMAT_RGB888:
  

•           return RDMA_INPUT_FORMAT_RGB888;
  

•   case DRM_FORMAT_BGR888:
  

•           return RDMA_INPUT_FORMAT_RGB888 | RDMA_INPUT_SWAP;
  

•   case DRM_FORMAT_RGBX8888:
  

•   case DRM_FORMAT_RGBA8888:
  

•           return RDMA_INPUT_FORMAT_ARGB8888;
  

•   case DRM_FORMAT_BGRX8888:
  

•   case DRM_FORMAT_BGRA8888:
  

•           return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP;
  

•   case DRM_FORMAT_XRGB8888:
  

•   case DRM_FORMAT_ARGB8888:
  

•           return RDMA_INPUT_FORMAT_RGBA8888;
  

•   case DRM_FORMAT_XBGR8888:
  

•   case DRM_FORMAT_ABGR8888:
  

•           return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP;
  

•   case DRM_FORMAT_ABGR2101010:
  

•           return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP |
  

•                           RDMA_INPUT_10BIT;
  

•   case DRM_FORMAT_ARGB2101010:
  

•           return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_10BIT;
  

•   case DRM_FORMAT_RGBA1010102:
  

•           return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP |
  

•                           RDMA_INPUT_10BIT;
  

•   case DRM_FORMAT_BGRA1010102:
  

•           return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_10BIT;
  

•   case DRM_FORMAT_UYVY:
  

•           return RDMA_INPUT_FORMAT_UYVY;
  

•   case DRM_FORMAT_YUYV:
  

•           return RDMA_INPUT_FORMAT_YUY2;
  

•   }
  

+}

+void mtk_mdp_rdma_start(void __iomem *base, struct cmdq_pkt *cmdq_pkt,

•                   struct cmdq_client_reg *cmdq_base)
  

+{

•   unsigned int inten = IRQ_INT_EN_ALL;
  

•   mtk_ddp_write_mask(cmdq_pkt, inten, cmdq_base, base,
  

•                      MDP_RDMA_INTERRUPT_ENABLE, IRQ_INT_EN_ALL);
  

Why do you enable rdma interrupt?

•   mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE, 1), cmdq_base,
  

•                      base, MDP_RDMA_EN, REG_FLD_MASK(FLD_ROT_ENABLE));
  

+}

+void mtk_mdp_rdma_stop(void __iomem *base, struct cmdq_pkt *cmdq_pkt,

•                  struct cmdq_client_reg *cmdq_base)
  

+{

•   mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE, 0), cmdq_base,
  

•                      base, MDP_RDMA_EN, REG_FLD_MASK(FLD_ROT_ENABLE));
  

•   mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
  

•                      MDP_RDMA_INTERRUPT_ENABLE, IRQ_INT_EN_ALL);
  

•   mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
  

•                      MDP_RDMA_INTERRUPT_STATUS, IRQ_INT_EN_ALL);
  

•   mtk_ddp_write_mask(cmdq_pkt, 1, cmdq_base, base, MDP_RDMA_RESET, ~0);
  

•   mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base, MDP_RDMA_RESET, ~0);
  

+}

+void mtk_mdp_rdma_fifo_config(void __iomem *base, struct cmdq_pkt *cmdq_pkt,

•                         struct cmdq_client_reg *cmdq_base,
  

•                         const struct mtk_mdp_rdma_fifo *fifo)
  

Why do you pass fifo config from ovl to rdma? I think just rdma know how to set these fifo parameter.

+{

•   int reg;
  

•   int reg_val;
  

•   int reg_mask;
  

•   reg = MDP_RDMA_GMCIF_CON;
  

•   reg_val = REG_FLD_VAL(FLD_RD_REQ_TYPE, fifo->read_request_type) |
  

•             REG_FLD_VAL(FLD_COMMAND_DIV, fifo->command_div) |
  

•             REG_FLD_VAL(FLD_EXT_PREULTRA_EN, fifo->ext_preutra_en) |
  

•             REG_FLD_VAL(FLD_ULTRA_EN, fifo->ultra_en) |
  

•             REG_FLD_VAL(PRE_ULTRA_EN, fifo->pre_ultra_en) |
  

•             REG_FLD_VAL(FLD_EXT_ULTRA_EN, fifo->ext_ultra_en);
  

•   reg_mask = REG_FLD_MASK(FLD_RD_REQ_TYPE) |
  

•              REG_FLD_MASK(FLD_COMMAND_DIV) |
  

•              REG_FLD_MASK(FLD_EXT_PREULTRA_EN) |
  

•              REG_FLD_MASK(FLD_ULTRA_EN) |
  

•              REG_FLD_MASK(PRE_ULTRA_EN) |
  

•              REG_FLD_MASK(FLD_EXT_ULTRA_EN);
  

•   mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
  

•   reg = MDP_RDMA_DMA_CON_0;
  

•   reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX, fifo->extrd_arb_max_0) |
  

•             REG_FLD_VAL(FLD_BUF_RESV_SIZE, fifo->buf_resv_size_0) |
  

•             REG_FLD_VAL(FLD_ISSUE_REQ_TH, fifo->issue_req_th_0);
  

•   reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX) |
  

•              REG_FLD_MASK(FLD_BUF_RESV_SIZE) |
  

•              REG_FLD_MASK(FLD_ISSUE_REQ_TH);
  

•   mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
  

•   reg = MDP_RDMA_UTRA_H_CON_0;
  

•   reg_val = REG_FLD_VAL(FLD_PREUTRA_H_OFS_0, fifo->ultra_h_con_0);
  

•   reg_mask = REG_FLD_MASK(FLD_PREUTRA_H_OFS_0);
  

•   mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
  

•   reg = MDP_RDMA_UTRA_L_CON_0;
  

•   reg_val = REG_FLD_VAL(FLD_PREUTRA_L_OFS_0, fifo->ultra_l_con_0);
  

•   reg_mask = REG_FLD_MASK(FLD_PREUTRA_L_OFS_0);
  

•   mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
  

•   reg = MDP_RDMA_DMABUF_CON_1;
  

•   reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_1, 0) |
  

•             REG_FLD_VAL(FLD_BUF_RESV_SIZE_1, 0) |
  

•             REG_FLD_VAL(FLD_ISSUE_REQ_TH_1, 0);
  

•   reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_1) |
  

•              REG_FLD_MASK(FLD_BUF_RESV_SIZE_1) |
  

•              REG_FLD_MASK(FLD_ISSUE_REQ_TH_1);
  

•   mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
  

•   reg = MDP_RDMA_ULTRA_TH_HIGH_CON_1;
  

•   reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_1, 0);
  

•   reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_1);
  

•   mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
  

•   reg = MDP_RDMA_ULTRA_TH_LOW_CON_1;
  

•   reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_1, 0);
  

•   reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_1);
  

•   mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
  

•   reg = MDP_RDMA_DMABUF_CON_2;
  

•   reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_2, 0) |
  

•             REG_FLD_VAL(FLD_BUF_RESV_SIZE_2, 0) |
  

•             REG_FLD_VAL(FLD_ISSUE_REQ_TH_2, 0);
  

•   reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_2) |
  

•              REG_FLD_MASK(FLD_BUF_RESV_SIZE_2) |
  

•              REG_FLD_MASK(FLD_ISSUE_REQ_TH_2);
  

•   mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
  

•   reg = MDP_RDMA_UTRA_H_CON_2;
  

•   reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_2, 0);
  

•   reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_2);
  

•   mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
  

•   reg = MDP_RDMA_ULTRA_TH_LOW_CON_2;
  

•   reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_2, 0);
  

•   reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_2);
  

•   mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
  

•   reg = MDP_RDMA_DMABUF_CON_3;
  

•   reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_3, 0) |
  

•             REG_FLD_VAL(FLD_BUF_RESV_SIZE_3, 0) |
  

•             REG_FLD_VAL(FLD_ISSUE_REQ_TH_3, 0);
  

•   reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_3) |
  

•              REG_FLD_MASK(FLD_BUF_RESV_SIZE_3) |
  

•              REG_FLD_MASK(FLD_ISSUE_REQ_TH_3);
  

•   mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
  

•   reg = MDP_RDMA_UTRA_H_CON_3;
  

•   reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_3, 0);
  

•   reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_3);
  

•   mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
  

•   reg = MDP_RDMA_ULTRA_TH_LOW_CON_3;
  

•   reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_3, 0);
  

•   reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_3);
  

•   mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
  

+}

+void mtk_mdp_rdma_config(void __iomem *base, struct mtk_mdp_rdma_cfg *cfg,

•                    struct cmdq_pkt *cmdq_pkt,
  

•                    struct cmdq_client_reg *cmdq_base)
  

+{

•   unsigned int src_pitch_uv = rdma_get_uv_pitch(cfg->fmt, cfg->source_width);
  

•   unsigned int src_pitch_y = rdma_get_y_pitch(cfg->fmt, cfg->source_width);
  

This is got from mtk_plane_atomic_update().

•   unsigned int h_shift_uv = rdma_get_horizontal_shift_uv(cfg->fmt);
  

•   unsigned int v_shift_uv = rdma_get_vertical_shift_uv(cfg->fmt);
  

•   unsigned int bpp_uv = rdma_get_bits_per_pixel_uv(cfg->fmt);
  

•   unsigned int block_h = rdma_get_block_h(cfg->block_size);
  

block_h = 0;

•   unsigned int bpp_y = rdma_get_bits_per_pixel_y(cfg->fmt);
  

drm_format_info().

•   unsigned int y_start_line = 0;
  

•   unsigned int offset_y = 0;
  

•   unsigned int offset_u = 0;
  

•   unsigned int offset_v = 0;
  

•   mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UNIFORM_CONFIG, 1),
  

•                      cmdq_base, base, MDP_RDMA_SRC_CON,
  

•                      REG_FLD_MASK(FLD_UNIFORM_CONFIG));
  

•   mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), cmdq_base,
  

•                      base, MDP_RDMA_SRC_CON, REG_FLD_MASK(FLD_SWAP) |
  

•                      REG_FLD_MASK(FLD_SRC_FORMAT) |
  

•                      REG_FLD_MASK(FLD_BIT_NUMBER));
  

•   if (!cfg->csc_enable && with_alpha(cfg->fmt))
  

•           mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_ARGB, 1),
  

•                              cmdq_base, base, MDP_RDMA_SRC_CON,
  

•                              REG_FLD_MASK(FLD_OUTPUT_ARGB));
  

•   else
  

•           mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_ARGB, 0),
  

•                              cmdq_base, base, MDP_RDMA_SRC_CON,
  

•                              REG_FLD_MASK(FLD_OUTPUT_ARGB));
  

•   mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, cmdq_base, base,
  

•                      MDP_RDMA_SRC_BASE_0, REG_FLD_MASK(FLD_SRC_BASE_0));
  

•   mtk_ddp_write_mask(cmdq_pkt, cfg->addr1, cmdq_base, base,
  

•                      MDP_RDMA_SRC_BASE_1, REG_FLD_MASK(FLD_SRC_BASE_1));
  

•   mtk_ddp_write_mask(cmdq_pkt, cfg->addr2, cmdq_base, base,
  

•                      MDP_RDMA_SRC_BASE_2, REG_FLD_MASK(FLD_SRC_BASE_2));
  

•   mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, cmdq_base, base,
  

•                      MDP_RDMA_MF_BKGD_SIZE_IN_BYTE,
  

•                      REG_FLD_MASK(FLD_MF_BKGD_WB));
  

•   mtk_ddp_write_mask(cmdq_pkt, src_pitch_uv, cmdq_base, base,
  

•                      MDP_RDMA_SF_BKGD_SIZE_IN_BYTE,
  

•                      REG_FLD_MASK(FLD_SF_BKGD_WB));
  

•   if (cfg->encode_type == RDMA_ENCODE_AFBC) {
  

Never be here, so remove.

•           mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_BKGD_WP, cfg->source_width),
  

•                              cmdq_base, base, MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL,
  

•                              REG_FLD_MASK(FLD_MF_BKGD_WP));
  

•           mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_BKGD_HP, cfg->height),
  

•                              cmdq_base, base, MDP_RDMA_MF_BKGD_H_SIZE_IN_PIXEL,
  

•                              REG_FLD_MASK(FLD_BKGD_HP));
  

•           mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 1),
  

•                              cmdq_base, base, MDP_RDMA_COMP_CON,
  

•                              REG_FLD_MASK(FLD_AFBC_YUV_TRANSFORM));
  

•           mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UFBDC_EN, 1), cmdq_base,
  

•                              base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_UFBDC_EN));
  

•           mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_EN, 1), cmdq_base,
  

•                              base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_AFBC_EN));
  

•   } else {
  

•           mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 0),
  

•                              cmdq_base, base, MDP_RDMA_COMP_CON,
  

•                              REG_FLD_MASK(FLD_AFBC_YUV_TRANSFORM));
  

•           mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UFBDC_EN, 0), cmdq_base,
  

•                              base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_UFBDC_EN));
  

•           mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_EN, 0), cmdq_base,
  

•                              base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_AFBC_EN));
  

•   }
  

•   mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_10B, 1), cmdq_base,
  

•                      base, MDP_RDMA_CON, REG_FLD_MASK(FLD_OUTPUT_10B));
  

•   mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SIMPLE_MODE, 1), cmdq_base,
  

•                      base, MDP_RDMA_CON, REG_FLD_MASK(FLD_SIMPLE_MODE));
  

•   mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TRANS_EN, cfg->csc_enable),
  

•                      cmdq_base, base, MDP_RDMA_TRANSFORM_0,
  

•                      REG_FLD_MASK(FLD_TRANS_EN));
  

•   mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_INT_MATRIX_SEL, cfg->profile),
  

•                      cmdq_base, base, MDP_RDMA_TRANSFORM_0,
  

•                      REG_FLD_MASK(FLD_INT_MATRIX_SEL));
  

•   if (cfg->block_size == RDMA_BLOCK_NONE) {
  

•           y_start_line = cfg->y_top;
  

•           offset_y  = (cfg->x_left * bpp_y >> 3) + y_start_line * src_pitch_y;
  

•           offset_u  = ((cfg->x_left >> h_shift_uv) * bpp_uv >> 3) +
  

•                       (y_start_line >> v_shift_uv) * src_pitch_uv;
  

•           offset_v  = ((cfg->x_left >> h_shift_uv) * bpp_uv >> 3) +
  

•                       (y_start_line >> v_shift_uv) * src_pitch_uv;
  

•   } else {
  

Never be here, so remove.

•           offset_y = (cfg->x_left * block_h * bpp_y >> 3) +
  

•                      (cfg->y_top) * src_pitch_y;
  

•           offset_u = ((cfg->x_left >> h_shift_uv) * (block_h >> v_shift_uv) *
  

•                      bpp_uv >> 3) + (cfg->y_top) * src_pitch_uv;
  

•           offset_v = ((cfg->x_left >> h_shift_uv) * (block_h >> v_shift_uv) *
  

•                      bpp_uv >> 3) + (cfg->y_top) * src_pitch_uv;
  

•   }
  

•   if (cfg->encode_type == RDMA_ENCODE_AFBC) {
  

Never be here, so remove.

•           mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_WP, cfg->x_left),
  

•                              cmdq_base, base, MDP_RDMA_SRC_OFFSET_WP,
  

•                              REG_FLD_MASK(FLD_SRC_OFFSET_WP));
  

•           mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_HP, cfg->y_top),
  

•                              cmdq_base, base, MDP_RDMA_SRC_OFFSET_HP,
  

•                              REG_FLD_MASK(FLD_SRC_OFFSET_HP));
  

•   }
  

•   mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_0, offset_y),
  

•                      cmdq_base, base, MDP_RDMA_SRC_OFFSET_0,
  

•                      REG_FLD_MASK(FLD_SRC_OFFSET_0));
  

•   mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_1, offset_u),
  

•                      cmdq_base, base, MDP_RDMA_SRC_OFFSET_1,
  

•                      REG_FLD_MASK(FLD_SRC_OFFSET_1));
  

•   mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_2, offset_v),
  

•                      cmdq_base, base, MDP_RDMA_SRC_OFFSET_2,
  

•                      REG_FLD_MASK(FLD_SRC_OFFSET_2));
  

•   mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_W, cfg->width),
  

•                      cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
  

•                      REG_FLD_MASK(FLD_MF_SRC_W));
  

•   mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_H, cfg->height),
  

•                      cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
  

•                      REG_FLD_MASK(FLD_MF_SRC_H));
  

•   mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_W, cfg->width),
  

•                      cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
  

•                      REG_FLD_MASK(FLD_MF_CLIP_W));
  

•   mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_H, cfg->height),
  

•                      cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
  

•                      REG_FLD_MASK(FLD_MF_CLIP_H));
  

•   mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_OFFSET_W_1, 0),
  

•                      cmdq_base, base, MDP_RDMA_MF_OFFSET_1,
  

•                      REG_FLD_MASK(FLD_MF_OFFSET_W_1));
  

•   mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_OFFSET_H_1, 0),
  

•                      cmdq_base, base, MDP_RDMA_MF_OFFSET_1,
  

•                      REG_FLD_MASK(FLD_MF_OFFSET_H_1));
  

•   mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_LINE_THRESHOLD, cfg->height),
  

•                      cmdq_base, base, MDP_RDMA_TARGET_LINE,
  

•                      REG_FLD_MASK(FLD_LINE_THRESHOLD));
  

•   mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TARGET_LINE_EN, 1),
  

•                      cmdq_base, base, MDP_RDMA_TARGET_LINE,
  

•                      REG_FLD_MASK(FLD_TARGET_LINE_EN));
  

+} diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h new file mode 100644 index 000000000000..c16bfb716610 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/*

• • Copyright (c) 2021 MediaTek Inc.
• */

+#ifndef __MTK_MDP_RDMA_H__ +#define __MTK_MDP_RDMA_H__

+enum rdma_format {

•   RDMA_INPUT_FORMAT_RGB565 = 0,
  

•   RDMA_INPUT_FORMAT_RGB888 = 1,
  

•   RDMA_INPUT_FORMAT_RGBA8888 = 2,
  

•   RDMA_INPUT_FORMAT_ARGB8888 = 3,
  

•   RDMA_INPUT_FORMAT_UYVY = 4,
  

•   RDMA_INPUT_FORMAT_YUY2 = 5,
  

•   RDMA_INPUT_FORMAT_Y8 = 7,
  

•   RDMA_INPUT_FORMAT_YV12 = 8,
  

•   RDMA_INPUT_FORMAT_UYVY_3PL = 9,
  

•   RDMA_INPUT_FORMAT_NV12 = 12,
  

•   RDMA_INPUT_FORMAT_UYVY_2PL = 13,
  

•   RDMA_INPUT_FORMAT_Y410 = 14
  

+};

+enum rdma_profile {

•   RDMA_CSC_RGB_TO_JPEG = 0,
  

•   RDMA_CSC_RGB_TO_FULL709 = 1,
  

•   RDMA_CSC_RGB_TO_BT601 = 2,
  

•   RDMA_CSC_RGB_TO_BT709 = 3,
  

•   RDMA_CSC_JPEG_TO_RGB = 4,
  

•   RDMA_CSC_FULL709_TO_RGB = 5,
  

•   RDMA_CSC_BT601_TO_RGB = 6,
  

•   RDMA_CSC_BT709_TO_RGB = 7,
  

•   RDMA_CSC_JPEG_TO_BT601 = 8,
  

•   RDMA_CSC_JPEG_TO_BT709 = 9,
  

•   RDMA_CSC_BT601_TO_JPEG = 10,
  

•   RDMA_CSC_BT709_TO_BT601 = 11,
  

•   RDMA_CSC_BT601_TO_BT709 = 12
  

+};

+enum rdma_encode {

•   RDMA_ENCODE_NONE = 0,
  

•   RDMA_ENCODE_AFBC = 1,
  

•   RDMA_ENCODE_HYFBC = 2,
  

•   RDMA_ENCODE_UFO_DCP = 3
  

+};

+enum rdma_block {

•   RDMA_BLOCK_NONE = 0,
  

•   RDMA_BLOCK_8x8 = 1,
  

•   RDMA_BLOCK_8x16 = 2,
  

•   RDMA_BLOCK_8x32 = 3,
  

•   RDMA_BLOCK_16x8 = 4,
  

•   RDMA_BLOCK_16x16 = 5,
  

•   RDMA_BLOCK_16x32 = 6,
  

•   RDMA_BLOCK_32x8 = 7,
  

•   RDMA_BLOCK_32x16 = 8,
  

•   RDMA_BLOCK_32x32 = 9
  

+};

+struct mtk_mdp_rdma_cfg {

•   enum rdma_encode encode_type;
  

•   enum rdma_block block_size;
  

•   enum rdma_profile profile;
  

•   unsigned int source_width;
  

•   unsigned int addr0;
  

•   unsigned int addr1;
  

•   unsigned int addr2;
  

•   unsigned int width;
  

•   unsigned int height;
  

•   unsigned int x_left;
  

•   unsigned int y_top;
  

•   bool csc_enable;
  

•   int fmt;
  

+};

+struct mtk_mdp_rdma_fifo {

•   int read_request_type;
  

•   int command_div;
  

•   int ext_preutra_en;
  

•   int ultra_en;
  

•   int pre_ultra_en;
  

•   int ext_ultra_en;
  

•   int extrd_arb_max_0;
  

•   int buf_resv_size_0;
  

•   int issue_req_th_0;
  

•   int ultra_h_con_0;
  

•   int ultra_l_con_0;
  

+};

Move rdma internal definition in .c file.

+void mtk_mdp_rdma_start(void __iomem *base,

•                   struct cmdq_pkt *cmdq_pkt,
  

•                   struct cmdq_client_reg *cmdq_base);
  

+void mtk_mdp_rdma_stop(void __iomem *base,

•                  struct cmdq_pkt *cmdq_pkt,
  

•                  struct cmdq_client_reg *cmdq_base);
  

+void mtk_mdp_rdma_fifo_config(void __iomem *base,

•                         struct cmdq_pkt *cmdq_pkt,
  

•                         struct cmdq_client_reg *cmdq_base,
  

•                         const struct mtk_mdp_rdma_fifo *fifo);
  

+void mtk_mdp_rdma_config(void __iomem *base,

•                    struct mtk_mdp_rdma_cfg *cfg,
  

•                    struct cmdq_pkt *cmdq_pkt,
  

•                    struct cmdq_client_reg *cmdq_base);
  

Move these prototype to mtk_disp_drv.h

+#endif // __MTK_MDP_RDMA_H__

diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h new file mode 100644 index 000000000000..08abd9f39bd8 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h @@ -0,0 +1,160 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/*

• • Copyright (c) 2021 MediaTek Inc.
• */

+#ifndef __MDP_RDMA_REGS_H__ +#define __MDP_RDMA_REGS_H__

+#define REG_FLD(width, shift) \

•   ((unsigned int)((((width) & 0xff) << 16) | ((shift) & 0xff)))
  

+#define REG_FLD_WIDTH(field) ((unsigned int)(((field) >> 16) & 0xff))

+#define REG_FLD_SHIFT(field) ((unsigned int)((field) & 0xff))

+#define REG_FLD_MASK(field) \

•   ((unsigned int)((1ULL << REG_FLD_WIDTH(field)) - 1) \
  

•    << REG_FLD_SHIFT(field))
  

+#define REG_FLD_VAL(field, val) \

•   (((val) << REG_FLD_SHIFT(field)) & REG_FLD_MASK(field))
  

+#define MDP_RDMA_EN 0x000 +#define FLD_ROT_ENABLE REG_FLD(1, 0)

+#define MDP_RDMA_RESET 0x008

+#define MDP_RDMA_INTERRUPT_ENABLE 0x010 +#define FLD_UNDERRUN_INT_EN REG_FLD(1, 2) +#define FLD_REG_UPDATE_INT_EN REG_FLD(1, 1) +#define FLD_FRAME_COMPLETE_INT_EN REG_FLD(1, 0)

+#define MDP_RDMA_INTERRUPT_STATUS 0x018

+#define MDP_RDMA_CON 0x020 +#define FLD_OUTPUT_10B REG_FLD(1, 5) +#define FLD_SIMPLE_MODE REG_FLD(1, 4)

+#define MDP_RDMA_GMCIF_CON 0x028 +#define FLD_EXT_ULTRA_EN REG_FLD(1, 18) +#define PRE_ULTRA_EN REG_FLD(2, 16) +#define FLD_ULTRA_EN REG_FLD(2, 12) +#define FLD_RD_REQ_TYPE REG_FLD(4, 4) +#define FLD_EXT_PREULTRA_EN REG_FLD(1, 3) +#define FLD_COMMAND_DIV REG_FLD(1, 0)

+#define MDP_RDMA_SRC_CON 0x030 +#define FLD_OUTPUT_ARGB REG_FLD(1, 25) +#define FLD_BIT_NUMBER REG_FLD(2, 18) +#define FLD_UNIFORM_CONFIG REG_FLD(1, 17) +#define FLD_SWAP REG_FLD(1, 14) +#define FLD_SRC_FORMAT REG_FLD(4, 0)

+#define MDP_RDMA_COMP_CON 0x038 +#define FLD_AFBC_EN REG_FLD(1, 22) +#define FLD_AFBC_YUV_TRANSFORM REG_FLD(1, 21) +#define FLD_UFBDC_EN REG_FLD(1, 12)

+#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060 +#define FLD_MF_BKGD_WB REG_FLD(23, 0)

+#define MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL 0x068 +#define FLD_MF_BKGD_WP REG_FLD(23, 0)

+#define MDP_RDMA_MF_SRC_SIZE 0x070 +#define FLD_MF_SRC_H REG_FLD(15, 16) +#define FLD_MF_SRC_W REG_FLD(15, 0)

+#define MDP_RDMA_MF_CLIP_SIZE 0x078 +#define FLD_MF_CLIP_H REG_FLD(15, 16) +#define FLD_MF_CLIP_W REG_FLD(15, 0)

+#define MDP_RDMA_MF_OFFSET_1 0x080 +#define FLD_MF_OFFSET_H_1 REG_FLD(6, 16) +#define FLD_MF_OFFSET_W_1 REG_FLD(5, 0)

+#define MDP_RDMA_SF_BKGD_SIZE_IN_BYTE 0x090 +#define FLD_SF_BKGD_WB REG_FLD(23, 0)

+#define MDP_RDMA_MF_BKGD_H_SIZE_IN_PIXEL 0x098 +#define FLD_BKGD_HP REG_FLD(23, 0)

+#define MDP_RDMA_TARGET_LINE 0x0a0 +#define FLD_LINE_THRESHOLD REG_FLD(15, 17) +#define FLD_TARGET_LINE_EN REG_FLD(1, 16)

+#define MDP_RDMA_SRC_OFFSET_0 0x118 +#define FLD_SRC_OFFSET_0 REG_FLD(32, 0)

+#define MDP_RDMA_SRC_OFFSET_1 0x120 +#define FLD_SRC_OFFSET_1 REG_FLD(32, 0)

+#define MDP_RDMA_SRC_OFFSET_2 0x128 +#define FLD_SRC_OFFSET_2 REG_FLD(32, 0)

+#define MDP_RDMA_SRC_OFFSET_WP 0x148 +#define FLD_SRC_OFFSET_WP REG_FLD(32, 0)

+#define MDP_RDMA_SRC_OFFSET_HP 0x150 +#define FLD_SRC_OFFSET_HP REG_FLD(32, 0)

+#define MDP_RDMA_TRANSFORM_0 0x200 +#define FLD_INT_MATRIX_SEL REG_FLD(5, 23) +#define FLD_TRANS_EN REG_FLD(1, 16)

+#define MDP_RDMA_DMA_CON_0 0x240 +#define FLD_EXTRD_ARB_MAX REG_FLD(4, 24) +#define FLD_BUF_RESV_SIZE REG_FLD(8, 16) +#define FLD_ISSUE_REQ_TH REG_FLD(8, 0)

+#define MDP_RDMA_UTRA_H_CON_0 0x248 +#define FLD_PREUTRA_H_OFS_0 REG_FLD(10, 10)

+#define MDP_RDMA_UTRA_L_CON_0 0x250 +#define FLD_PREUTRA_L_OFS_0 REG_FLD(10, 10)

+#define MDP_RDMA_DMABUF_CON_1 0x258 +#define FLD_EXTRD_ARB_MAX_1 REG_FLD(4, 24) +#define FLD_BUF_RESV_SIZE_1 REG_FLD(7, 16) +#define FLD_ISSUE_REQ_TH_1 REG_FLD(7, 0)

+#define MDP_RDMA_ULTRA_TH_HIGH_CON_1 0x260 +#define FLD_PRE_ULTRA_TH_HIGH_OFS_1 REG_FLD(10, 10)

+#define MDP_RDMA_ULTRA_TH_LOW_CON_1 0x268 +#define FLD_PRE_ULTRA_TH_LOW_OFS_1 REG_FLD(10, 10)

+#define MDP_RDMA_DMABUF_CON_2 0x270 +#define FLD_EXTRD_ARB_MAX_2 REG_FLD(4, 24) +#define FLD_BUF_RESV_SIZE_2 REG_FLD(6, 16) +#define FLD_ISSUE_REQ_TH_2 REG_FLD(6, 0)

+#define MDP_RDMA_UTRA_H_CON_2 0x278 +#define FLD_PRE_ULTRA_TH_HIGH_OFS_2 REG_FLD(10, 10)

+#define MDP_RDMA_ULTRA_TH_LOW_CON_2 0x280 +#define FLD_PRE_ULTRA_TH_LOW_OFS_2 REG_FLD(10, 10)

+#define MDP_RDMA_DMABUF_CON_3 0x288 +#define FLD_EXTRD_ARB_MAX_3 REG_FLD(4, 24) +#define FLD_BUF_RESV_SIZE_3 REG_FLD(6, 16) +#define FLD_ISSUE_REQ_TH_3 REG_FLD(6, 0)

+#define MDP_RDMA_UTRA_H_CON_3 0x290 +#define FLD_PRE_ULTRA_TH_HIGH_OFS_3 REG_FLD(10, 10)

+#define MDP_RDMA_ULTRA_TH_LOW_CON_3 0x298 +#define FLD_PRE_ULTRA_TH_LOW_OFS_3 REG_FLD(10, 10)

+#define MDP_RDMA_SRC_BASE_0 0xf00 +#define FLD_SRC_BASE_0 REG_FLD(32, 0)

+#define MDP_RDMA_SRC_BASE_1 0xf08 +#define FLD_SRC_BASE_1 REG_FLD(32, 0)

+#define MDP_RDMA_SRC_BASE_2 0xf10 +#define FLD_SRC_BASE_2 REG_FLD(32, 0)

+#endif /* __MDP_RDMA_REGS_H__ */

Only one file need these, so move register definiton in .c file.

Regards, Chun-Kuang.

-- 2.18.0