Add DP device node on sc7180.
Changes in v2:
- Add assigned-clocks and assigned-clock-parents - Remove cell-index and pixel_rcg - Change compatible to qcom,sc7180-dp
Changes in v3: - Update commit text - Make DP child node of MDSS - Remove data-lanes property from SOC dts - Disable DP node in SOC dts - Assign DP to Port2 in MDP node - Add MDSS AHB clock in DP device node
This patch depends-on: https://patchwork.freedesktop.org/series/78953/
Signed-off-by: Tanmay Shah tanmay@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 49 ++++++++++++++++++++++++++-- 1 file changed, 47 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 31b9217bb5bf..271d55db62ab 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2371,6 +2371,13 @@ dpu_intf1_out: endpoint { remote-endpoint = <&dsi0_in>; }; }; + + port@2 { + reg = <2>; + dpu_intf0_out: endpoint { + remote-endpoint = <&dp_in>; + }; + }; }; };
@@ -2440,6 +2447,44 @@ dsi_phy: dsi-phy@ae94400 {
status = "disabled"; }; + + msm_dp: displayport-controller@ae90000{ + status = "disabled"; + compatible = "qcom,sc7180-dp"; + + reg = <0 0xae90000 0 0x1400>; + reg-names = "dp_controller"; + + interrupt-parent = <&mdss>; + interrupts = <12 0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + clock-names = "core_iface", "core_aux", "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + #clock-cells = <1>; + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + assigned-clock-parents = <&msm_dp 1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dp_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + dp_out: endpoint { }; + }; + }; + }; };
dispcc: clock-controller@af00000 { @@ -2449,8 +2494,8 @@ dispcc: clock-controller@af00000 { <&gcc GCC_DISP_GPLL0_CLK_SRC>, <&dsi_phy 0>, <&dsi_phy 1>, - <0>, - <0>; + <&msm_dp 0>, + <&msm_dp 1>; clock-names = "bi_tcxo", "gcc_disp_gpll0_clk_src", "dsi0_phy_pll_out_byteclk",
Quoting Tanmay Shah (2020-06-30 12:51:51)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 31b9217bb5bf..271d55db62ab 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2440,6 +2447,44 @@ dsi_phy: dsi-phy@ae94400 {
status = "disabled"; };
msm_dp: displayport-controller@ae90000{status = "disabled";compatible = "qcom,sc7180-dp";reg = <0 0xae90000 0 0x1400>;
Please use full 8 digits in address, i.e. 0x0ae90000.
reg-names = "dp_controller";
reg-names is pretty useless here. Please remove it.
interrupt-parent = <&mdss>;interrupts = <12 0>;
Please use irq flags instead of 0.
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;clock-names = "core_iface", "core_aux", "ctrl_link","ctrl_link_iface", "stream_pixel";#clock-cells = <1>;assigned-clocks = <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;assigned-clock-parents = <&msm_dp 1>;
Why don't we assign both clk parents here (&msm_dp 0) so that we don't need any clk_set_parent() calls in the code?
ports {#address-cells = <1>;#size-cells = <0>;port@0 {reg = <0>;dp_in: endpoint {remote-endpoint = <&dpu_intf0_out>;};};port@1 {reg = <1>;dp_out: endpoint { };};};}; }; dispcc: clock-controller@af00000 {
dri-devel@lists.freedesktop.org
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Stephen Boyd -
Tanmay Shah