From: Seung-Woo Kim sw0312.kim@samsung.com

At probe time, gsc clock is not enabled, so pm_runtime state should be deactive. So this patch removes pm_runtime_set_active() from gsc_probe().

Signed-off-by: Seung-Woo Kim sw0312.kim@samsung.com Signed-off-by: Marek Szyprowski m.szyprowski@samsung.com Reviewed-by: Gustavo Padovan gustavo.padovan@collabora.co.uk --- drivers/gpu/drm/exynos/exynos_drm_gsc.c | 1 - 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_gsc.c b/drivers/gpu/drm/exynos/exynos_drm_gsc.c index 72a9c84e06b6..ed55d37b6330 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_gsc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_gsc.c @@ -1713,7 +1713,6 @@ static int gsc_probe(struct platform_device *pdev) mutex_init(&ctx->lock); platform_set_drvdata(pdev, ctx);

- pm_runtime_set_active(dev); pm_runtime_enable(dev);

ret = exynos_drm_ippdrv_register(ippdrv);

This driver was not used after introduction of common clock framework. This patch adds missing prepare/unprepare calls and allows to use it again with current kernel code.

Signed-off-by: Marek Szyprowski m.szyprowski@samsung.com Reviewed-by: Gustavo Padovan gustavo.padovan@collabora.co.uk --- drivers/gpu/drm/exynos/exynos_drm_rotator.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_rotator.c b/drivers/gpu/drm/exynos/exynos_drm_rotator.c index 2f5c118f4c8e..bea0f7826d30 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_rotator.c +++ b/drivers/gpu/drm/exynos/exynos_drm_rotator.c @@ -790,10 +790,10 @@ static int rotator_remove(struct platform_device *pdev) static int rotator_clk_crtl(struct rot_context *rot, bool enable) { if (enable) { - clk_enable(rot->clock); + clk_prepare_enable(rot->clock); rot->suspended = false; } else { - clk_disable(rot->clock); + clk_disable_unprepare(rot->clock); rot->suspended = true; }

DMA address is a framebuffer attribute and the right place for it is exynos_drm_framebuffer not exynos_drm_plane. This patch also introduces helper function for getting dma address of the given framebuffer.

Signed-off-by: Marek Szyprowski m.szyprowski@samsung.com Reviewed-by: Gustavo Padovan gustavo.padovan@collabora.co.uk --- drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 13 ++++++++----- drivers/gpu/drm/exynos/exynos7_drm_decon.c | 16 +++++++++------- drivers/gpu/drm/exynos/exynos_drm_drv.h | 3 --- drivers/gpu/drm/exynos/exynos_drm_fb.c | 16 ++++++---------- drivers/gpu/drm/exynos/exynos_drm_fb.h | 3 +-- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 10 ++++++---- drivers/gpu/drm/exynos/exynos_drm_plane.c | 18 ------------------ drivers/gpu/drm/exynos/exynos_drm_vidi.c | 5 ++++- drivers/gpu/drm/exynos/exynos_mixer.c | 7 ++++--- 9 files changed, 38 insertions(+), 53 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c index edfd6e390ef7..320efc3d0659 100644 --- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c @@ -21,6 +21,7 @@

#include "exynos_drm_drv.h" #include "exynos_drm_crtc.h" +#include "exynos_drm_fb.h" #include "exynos_drm_plane.h" #include "exynos_drm_iommu.h"

@@ -261,9 +262,11 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc, { struct decon_context *ctx = crtc->ctx; struct drm_plane_state *state = plane->base.state; + struct drm_framebuffer *fb = state->fb; unsigned int win = plane->zpos; - unsigned int bpp = state->fb->bits_per_pixel >> 3; - unsigned int pitch = state->fb->pitches[0]; + unsigned int bpp = fb->bits_per_pixel >> 3; + unsigned int pitch = fb->pitches[0]; + dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0); u32 val;

if (test_bit(BIT_SUSPENDED, &ctx->flags)) @@ -284,9 +287,9 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc, VIDOSD_Wx_ALPHA_B_F(0x0); writel(val, ctx->addr + DECON_VIDOSDxD(win));

- writel(plane->dma_addr[0], ctx->addr + DECON_VIDW0xADD0B0(win)); + writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win));

- val = plane->dma_addr[0] + pitch * plane->crtc_h; + val = dma_addr + pitch * plane->crtc_h; writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));

if (ctx->out_type != IFTYPE_HDMI) @@ -297,7 +300,7 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc, | BIT_VAL(plane->crtc_w * bpp, 14, 0); writel(val, ctx->addr + DECON_VIDW0xADD2(win));

- decon_win_set_pixfmt(ctx, win, state->fb); + decon_win_set_pixfmt(ctx, win, fb);

/* window enable */ decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0); diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c b/drivers/gpu/drm/exynos/exynos7_drm_decon.c index 4db04f244c17..1629732574e0 100644 --- a/drivers/gpu/drm/exynos/exynos7_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos7_drm_decon.c @@ -30,6 +30,7 @@ #include "exynos_drm_crtc.h" #include "exynos_drm_plane.h" #include "exynos_drm_drv.h" +#include "exynos_drm_fb.h" #include "exynos_drm_fbdev.h" #include "exynos_drm_iommu.h"

@@ -395,13 +396,14 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc, { struct decon_context *ctx = crtc->ctx; struct drm_plane_state *state = plane->base.state; + struct drm_framebuffer *fb = state->fb; int padding; unsigned long val, alpha; unsigned int last_x; unsigned int last_y; unsigned int win = plane->zpos; - unsigned int bpp = state->fb->bits_per_pixel >> 3; - unsigned int pitch = state->fb->pitches[0]; + unsigned int bpp = fb->bits_per_pixel >> 3; + unsigned int pitch = fb->pitches[0];

if (ctx->suspended) return; @@ -417,14 +419,14 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc, */

/* buffer start address */ - val = (unsigned long)plane->dma_addr[0]; + val = (unsigned long)exynos_drm_fb_dma_addr(fb, 0); writel(val, ctx->regs + VIDW_BUF_START(win));

- padding = (pitch / bpp) - state->fb->width; + padding = (pitch / bpp) - fb->width;

/* buffer size */ - writel(state->fb->width + padding, ctx->regs + VIDW_WHOLE_X(win)); - writel(state->fb->height, ctx->regs + VIDW_WHOLE_Y(win)); + writel(fb->width + padding, ctx->regs + VIDW_WHOLE_X(win)); + writel(fb->height, ctx->regs + VIDW_WHOLE_Y(win));

/* offset from the start of the buffer to read */ writel(plane->src_x, ctx->regs + VIDW_OFFSET_X(win)); @@ -466,7 +468,7 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc,

writel(alpha, ctx->regs + VIDOSD_D(win));

- decon_win_set_pixfmt(ctx, win, state->fb); + decon_win_set_pixfmt(ctx, win, fb);

/* hardware window 0 doesn't support color key. */ if (win != 0) diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h index f1eda7fa4e3c..dc41ffb26eb9 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.h +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h @@ -54,8 +54,6 @@ enum exynos_drm_output_type { * @crtc_h: window height to be displayed (hardware screen). * @h_ratio: horizontal scaling ratio, 16.16 fixed point * @v_ratio: vertical scaling ratio, 16.16 fixed point - * @dma_addr: array of bus(accessed by dma) address to the memory region - * allocated for a overlay. * @zpos: order of overlay layer(z position). * * this structure is common to exynos SoC and its contents would be copied @@ -74,7 +72,6 @@ struct exynos_drm_plane { unsigned int crtc_h; unsigned int h_ratio; unsigned int v_ratio; - dma_addr_t dma_addr[MAX_FB_BUFFER]; unsigned int zpos; struct drm_framebuffer *pending_fb; }; diff --git a/drivers/gpu/drm/exynos/exynos_drm_fb.c b/drivers/gpu/drm/exynos/exynos_drm_fb.c index 49b9bc302e87..f6bdb0d6f142 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fb.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fb.c @@ -37,6 +37,7 @@ struct exynos_drm_fb { struct drm_framebuffer fb; struct exynos_drm_gem *exynos_gem[MAX_FB_BUFFER]; + dma_addr_t dma_addr[MAX_FB_BUFFER]; };

static int check_fb_gem_memory_type(struct drm_device *drm_dev, @@ -135,6 +136,8 @@ exynos_drm_framebuffer_init(struct drm_device *dev, goto err;

exynos_fb->exynos_gem[i] = exynos_gem[i]; + exynos_fb->dma_addr[i] = exynos_gem[i]->dma_addr + + mode_cmd->offsets[i]; }

drm_helper_mode_fill_fb_struct(&exynos_fb->fb, mode_cmd); @@ -189,21 +192,14 @@ err: return ERR_PTR(ret); }

-struct exynos_drm_gem *exynos_drm_fb_gem(struct drm_framebuffer *fb, int index) +dma_addr_t exynos_drm_fb_dma_addr(struct drm_framebuffer *fb, int index) { struct exynos_drm_fb *exynos_fb = to_exynos_fb(fb); - struct exynos_drm_gem *exynos_gem;

if (index >= MAX_FB_BUFFER) - return NULL; + return DMA_ERROR_CODE;

- exynos_gem = exynos_fb->exynos_gem[index]; - if (!exynos_gem) - return NULL; - - DRM_DEBUG_KMS("dma_addr: 0x%lx\n", (unsigned long)exynos_gem->dma_addr); - - return exynos_gem; + return exynos_fb->dma_addr[index]; }

static void exynos_drm_output_poll_changed(struct drm_device *dev) diff --git a/drivers/gpu/drm/exynos/exynos_drm_fb.h b/drivers/gpu/drm/exynos/exynos_drm_fb.h index a8a75ac87e59..4aae9dd2b0d1 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fb.h +++ b/drivers/gpu/drm/exynos/exynos_drm_fb.h @@ -22,8 +22,7 @@ exynos_drm_framebuffer_init(struct drm_device *dev, struct exynos_drm_gem **exynos_gem, int count);

-/* get gem object of a drm framebuffer */ -struct exynos_drm_gem *exynos_drm_fb_gem(struct drm_framebuffer *fb, int index); +dma_addr_t exynos_drm_fb_dma_addr(struct drm_framebuffer *fb, int index);

void exynos_drm_mode_config_init(struct drm_device *dev);

diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index 2c383238efff..ffcc498f5afe 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -29,6 +29,7 @@ #include <drm/exynos_drm.h>

#include "exynos_drm_drv.h" +#include "exynos_drm_fb.h" #include "exynos_drm_fbdev.h" #include "exynos_drm_crtc.h" #include "exynos_drm_plane.h" @@ -642,12 +643,13 @@ static void fimd_update_plane(struct exynos_drm_crtc *crtc, { struct fimd_context *ctx = crtc->ctx; struct drm_plane_state *state = plane->base.state; + struct drm_framebuffer *fb = state->fb; dma_addr_t dma_addr; unsigned long val, size, offset; unsigned int last_x, last_y, buf_offsize, line_size; unsigned int win = plane->zpos; - unsigned int bpp = state->fb->bits_per_pixel >> 3; - unsigned int pitch = state->fb->pitches[0]; + unsigned int bpp = fb->bits_per_pixel >> 3; + unsigned int pitch = fb->pitches[0];

if (ctx->suspended) return; @@ -656,7 +658,7 @@ static void fimd_update_plane(struct exynos_drm_crtc *crtc, offset += plane->src_y * pitch;

/* buffer start address */ - dma_addr = plane->dma_addr[0] + offset; + dma_addr = exynos_drm_fb_dma_addr(fb, 0) + offset; val = (unsigned long)dma_addr; writel(val, ctx->regs + VIDWx_BUF_START(win, 0));

@@ -712,7 +714,7 @@ static void fimd_update_plane(struct exynos_drm_crtc *crtc, DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val); }

- fimd_win_set_pixfmt(ctx, win, state->fb); + fimd_win_set_pixfmt(ctx, win, fb);

/* hardware window 0 doesn't support color key. */ if (win != 0) diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c index 179311760bb7..c725409421b8 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_plane.c +++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c @@ -120,28 +120,10 @@ static int exynos_plane_atomic_check(struct drm_plane *plane, struct drm_plane_state *state) { struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane); - int nr; - int i;

if (!state->fb) return 0;

- nr = drm_format_num_planes(state->fb->pixel_format); - for (i = 0; i < nr; i++) { - struct exynos_drm_gem *exynos_gem = - exynos_drm_fb_gem(state->fb, i); - if (!exynos_gem) { - DRM_DEBUG_KMS("gem object is null\n"); - return -EFAULT; - } - - exynos_plane->dma_addr[i] = exynos_gem->dma_addr + - state->fb->offsets[i]; - - DRM_DEBUG_KMS("buffer: %d, dma_addr = 0x%lx\n", - i, (unsigned long)exynos_plane->dma_addr[i]); - } - return 0; }

diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.c b/drivers/gpu/drm/exynos/exynos_drm_vidi.c index 669362c53f49..3ce141236fad 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_vidi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_vidi.c @@ -24,6 +24,7 @@

#include "exynos_drm_drv.h" #include "exynos_drm_crtc.h" +#include "exynos_drm_fb.h" #include "exynos_drm_plane.h" #include "exynos_drm_vidi.h"

@@ -126,11 +127,13 @@ static void vidi_update_plane(struct exynos_drm_crtc *crtc, struct exynos_drm_plane *plane) { struct vidi_context *ctx = crtc->ctx; + dma_addr_t addr;

if (ctx->suspended) return;

- DRM_DEBUG_KMS("dma_addr = %pad\n", plane->dma_addr); + addr = exynos_drm_fb_dma_addr(plane->base.fb, 0); + DRM_DEBUG_KMS("dma_addr = %pad\n", &addr);

if (ctx->vblank_on) schedule_work(&ctx->work); diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index 47777be1a754..f40de82848dc 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c @@ -37,6 +37,7 @@

#include "exynos_drm_drv.h" #include "exynos_drm_crtc.h" +#include "exynos_drm_fb.h" #include "exynos_drm_plane.h" #include "exynos_drm_iommu.h"

@@ -422,8 +423,8 @@ static void vp_video_buffer(struct mixer_context *ctx, return; }

- luma_addr[0] = plane->dma_addr[0]; - chroma_addr[0] = plane->dma_addr[1]; + luma_addr[0] = exynos_drm_fb_dma_addr(fb, 0); + chroma_addr[0] = exynos_drm_fb_dma_addr(fb, 1);

if (mode->flags & DRM_MODE_FLAG_INTERLACE) { ctx->interlace = true; @@ -575,7 +576,7 @@ static void mixer_graph_buffer(struct mixer_context *ctx, dst_y_offset = plane->crtc_y;

/* converting dma address base and source offset */ - dma_addr = plane->dma_addr[0] + dma_addr = exynos_drm_fb_dma_addr(fb, 0) + (plane->src_x * fb->bits_per_pixel >> 3) + (plane->src_y * fb->pitches[0]); src_x_offset = 0;

This patch replaces usage of crtc->mode with crtc->state->adjusted_mode like it is already done in common plane code.

Signed-off-by: Marek Szyprowski m.szyprowski@samsung.com Reviewed-by: Gustavo Padovan gustavo.padovan@collabora.co.uk --- drivers/gpu/drm/exynos/exynos_mixer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index 154537a23c90..84ee3396c429 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c @@ -402,9 +402,9 @@ static void vp_video_buffer(struct mixer_context *ctx, { struct exynos_drm_plane_state *state = to_exynos_plane_state(plane->base.state); + struct drm_display_mode *mode = &state->base.crtc->state->adjusted_mode; struct mixer_resources *res = &ctx->mixer_res; struct drm_framebuffer *fb = state->base.fb; - struct drm_display_mode *mode = &state->base.crtc->mode; unsigned long flags; dma_addr_t luma_addr[2], chroma_addr[2]; bool tiled_mode = false; @@ -539,9 +539,9 @@ static void mixer_graph_buffer(struct mixer_context *ctx, { struct exynos_drm_plane_state *state = to_exynos_plane_state(plane->base.state); + struct drm_display_mode *mode = &state->base.crtc->state->adjusted_mode; struct mixer_resources *res = &ctx->mixer_res; struct drm_framebuffer *fb = state->base.fb; - struct drm_display_mode *mode = &state->base.crtc->mode; unsigned long flags; unsigned int win = plane->zpos; unsigned int x_ratio = 0, y_ratio = 0;

This patch adds common structure for keeping plane configuration and capabilities data. This patch is inspired by similar code developed by Tobias Jakobi.

Signed-off-by: Marek Szyprowski m.szyprowski@samsung.com --- drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 18 ++++++++--- drivers/gpu/drm/exynos/exynos7_drm_decon.c | 23 +++++++++----- drivers/gpu/drm/exynos/exynos_drm_drv.h | 19 ++++++++++++ drivers/gpu/drm/exynos/exynos_drm_fimd.c | 25 ++++++++++----- drivers/gpu/drm/exynos/exynos_drm_plane.c | 34 +++++++++------------ drivers/gpu/drm/exynos/exynos_drm_plane.h | 7 ++--- drivers/gpu/drm/exynos/exynos_drm_vidi.c | 25 ++++++++++----- drivers/gpu/drm/exynos/exynos_mixer.c | 44 +++++++++++++++------------ 8 files changed, 121 insertions(+), 74 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c index 12f558fc3ef6..189ee5ca0a7a 100644 --- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c @@ -26,7 +26,6 @@ #include "exynos_drm_iommu.h"

#define WINDOWS_NR 3 -#define CURSOR_WIN 2 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128

static const char * const decon_clks_name[] = { @@ -57,6 +56,7 @@ struct decon_context { struct drm_device *drm_dev; struct exynos_drm_crtc *crtc; struct exynos_drm_plane planes[WINDOWS_NR]; + struct exynos_drm_plane_config configs[WINDOWS_NR]; void __iomem *addr; struct clk *clks[ARRAY_SIZE(decon_clks_name)]; int pipe; @@ -72,6 +72,12 @@ static const uint32_t decon_formats[] = { DRM_FORMAT_ARGB8888, };

+static const enum drm_plane_type decon_win_types[WINDOWS_NR] = { + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_OVERLAY, + DRM_PLANE_TYPE_CURSOR, +}; + static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask, u32 val) { @@ -484,7 +490,6 @@ static int decon_bind(struct device *dev, struct device *master, void *data) struct exynos_drm_private *priv = drm_dev->dev_private; struct exynos_drm_plane *exynos_plane; enum exynos_drm_output_type out_type; - enum drm_plane_type type; unsigned int win; int ret;

@@ -494,10 +499,13 @@ static int decon_bind(struct device *dev, struct device *master, void *data) for (win = ctx->first_win; win < WINDOWS_NR; win++) { int tmp = (win == ctx->first_win) ? 0 : win;

- type = exynos_plane_get_type(tmp, CURSOR_WIN); + ctx->configs[win].pixel_formats = decon_formats; + ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats); + ctx->configs[win].zpos = win; + ctx->configs[win].type = decon_win_types[tmp]; + ret = exynos_plane_init(drm_dev, &ctx->planes[win], - 1 << ctx->pipe, type, decon_formats, - ARRAY_SIZE(decon_formats), win); + 1 << ctx->pipe, &ctx->configs[win]); if (ret) return ret; } diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c b/drivers/gpu/drm/exynos/exynos7_drm_decon.c index 1c62de1a0839..c47f9af8170b 100644 --- a/drivers/gpu/drm/exynos/exynos7_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos7_drm_decon.c @@ -41,13 +41,13 @@ #define MIN_FB_WIDTH_FOR_16WORD_BURST 128

#define WINDOWS_NR 2 -#define CURSOR_WIN 1

struct decon_context { struct device *dev; struct drm_device *drm_dev; struct exynos_drm_crtc *crtc; struct exynos_drm_plane planes[WINDOWS_NR]; + struct exynos_drm_plane_config configs[WINDOWS_NR]; struct clk *pclk; struct clk *aclk; struct clk *eclk; @@ -82,6 +82,11 @@ static const uint32_t decon_formats[] = { DRM_FORMAT_BGRA8888, };

+static const enum drm_plane_type decon_win_types[WINDOWS_NR] = { + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_CURSOR, +}; + static void decon_wait_for_vblank(struct exynos_drm_crtc *crtc) { struct decon_context *ctx = crtc->ctx; @@ -637,8 +642,7 @@ static int decon_bind(struct device *dev, struct device *master, void *data) struct decon_context *ctx = dev_get_drvdata(dev); struct drm_device *drm_dev = data; struct exynos_drm_plane *exynos_plane; - enum drm_plane_type type; - unsigned int zpos; + unsigned int i; int ret;

ret = decon_ctx_initialize(ctx, drm_dev); @@ -647,11 +651,14 @@ static int decon_bind(struct device *dev, struct device *master, void *data) return ret; }

- for (zpos = 0; zpos < WINDOWS_NR; zpos++) { - type = exynos_plane_get_type(zpos, CURSOR_WIN); - ret = exynos_plane_init(drm_dev, &ctx->planes[zpos], - 1 << ctx->pipe, type, decon_formats, - ARRAY_SIZE(decon_formats), zpos); + for (i = 0; i < WINDOWS_NR; i++) { + ctx->configs[i].pixel_formats = decon_formats; + ctx->configs[i].num_pixel_formats = ARRAY_SIZE(decon_formats); + ctx->configs[i].zpos = i; + ctx->configs[i].type = decon_win_types[i]; + + ret = exynos_plane_init(drm_dev, &ctx->planes[i], + 1 << ctx->pipe, &ctx->configs[i]); if (ret) return ret; } diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h index 482ed2c2ed89..6f8a296a3115 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.h +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h @@ -84,11 +84,30 @@ to_exynos_plane_state(struct drm_plane_state *state)

struct exynos_drm_plane { struct drm_plane base; + const struct exynos_drm_plane_config *config; unsigned int zpos; struct drm_framebuffer *pending_fb; };

/* + * Exynos DRM plane configuration structure. + * + * @zpos: z-position of the plane. + * @type: type of the plane (primary, cursor or overlay). + * @pixel_formats: supported pixel formats. + * @num_pixel_formats: number of elements in 'pixel_formats'. + * @capabilities: supported features (see EXYNOS_DRM_PLANE_CAP_*) + */ + +struct exynos_drm_plane_config { + unsigned int zpos; + enum drm_plane_type type; + const uint32_t *pixel_formats; + unsigned int num_pixel_formats; + unsigned int capabilities; +}; + +/* * Exynos drm crtc ops * * @enable: enable the device diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index 739544871589..70cd2681e343 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -88,7 +88,6 @@

/* FIMD has totally five hardware windows. */ #define WINDOWS_NR 5 -#define CURSOR_WIN 4

struct fimd_driver_data { unsigned int timing_base; @@ -151,6 +150,7 @@ struct fimd_context { struct drm_device *drm_dev; struct exynos_drm_crtc *crtc; struct exynos_drm_plane planes[WINDOWS_NR]; + struct exynos_drm_plane_config configs[WINDOWS_NR]; struct clk *bus_clk; struct clk *lcd_clk; void __iomem *regs; @@ -188,6 +188,14 @@ static const struct of_device_id fimd_driver_dt_match[] = { }; MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);

+static const enum drm_plane_type fimd_win_types[WINDOWS_NR] = { + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_OVERLAY, + DRM_PLANE_TYPE_OVERLAY, + DRM_PLANE_TYPE_OVERLAY, + DRM_PLANE_TYPE_CURSOR, +}; + static const uint32_t fimd_formats[] = { DRM_FORMAT_C8, DRM_FORMAT_XRGB1555, @@ -927,18 +935,19 @@ static int fimd_bind(struct device *dev, struct device *master, void *data) struct drm_device *drm_dev = data; struct exynos_drm_private *priv = drm_dev->dev_private; struct exynos_drm_plane *exynos_plane; - enum drm_plane_type type; - unsigned int zpos; + unsigned int i; int ret;

ctx->drm_dev = drm_dev; ctx->pipe = priv->pipe++;

- for (zpos = 0; zpos < WINDOWS_NR; zpos++) { - type = exynos_plane_get_type(zpos, CURSOR_WIN); - ret = exynos_plane_init(drm_dev, &ctx->planes[zpos], - 1 << ctx->pipe, type, fimd_formats, - ARRAY_SIZE(fimd_formats), zpos); + for (i = 0; i < WINDOWS_NR; i++) { + ctx->configs[i].pixel_formats = fimd_formats; + ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats); + ctx->configs[i].zpos = i; + ctx->configs[i].type = fimd_win_types[i]; + ret = exynos_plane_init(drm_dev, &ctx->planes[i], + 1 << ctx->pipe, &ctx->configs[i]); if (ret) return ret; } diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c index 365a738042e2..b620d7a76799 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_plane.c +++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c @@ -246,28 +246,20 @@ static void exynos_plane_attach_zpos_property(struct drm_plane *plane, drm_object_attach_property(&plane->base, prop, zpos); }

-enum drm_plane_type exynos_plane_get_type(unsigned int zpos, - unsigned int cursor_win) -{ - if (zpos == DEFAULT_WIN) - return DRM_PLANE_TYPE_PRIMARY; - else if (zpos == cursor_win) - return DRM_PLANE_TYPE_CURSOR; - else - return DRM_PLANE_TYPE_OVERLAY; -} - int exynos_plane_init(struct drm_device *dev, struct exynos_drm_plane *exynos_plane, - unsigned long possible_crtcs, enum drm_plane_type type, - const uint32_t *formats, unsigned int fcount, - unsigned int zpos) + unsigned long possible_crtcs, + const struct exynos_drm_plane_config *config) { int err;

- err = drm_universal_plane_init(dev, &exynos_plane->base, possible_crtcs, - &exynos_plane_funcs, formats, fcount, - type); + err = drm_universal_plane_init(dev, &exynos_plane->base, + possible_crtcs, + &exynos_plane_funcs, + config->pixel_formats, + config->num_pixel_formats, + config->type); + if (err) { DRM_ERROR("failed to initialize plane\n"); return err; @@ -275,10 +267,12 @@ int exynos_plane_init(struct drm_device *dev,

drm_plane_helper_add(&exynos_plane->base, &plane_helper_funcs);

- exynos_plane->zpos = zpos; + exynos_plane->zpos = config->zpos; + exynos_plane->config = config;

- if (type == DRM_PLANE_TYPE_OVERLAY) - exynos_plane_attach_zpos_property(&exynos_plane->base, zpos); + if (config->type == DRM_PLANE_TYPE_OVERLAY) + exynos_plane_attach_zpos_property(&exynos_plane->base, + config->zpos);

return 0; } diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.h b/drivers/gpu/drm/exynos/exynos_drm_plane.h index abb641e64c23..0dd096548284 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_plane.h +++ b/drivers/gpu/drm/exynos/exynos_drm_plane.h @@ -9,10 +9,7 @@ * */

-enum drm_plane_type exynos_plane_get_type(unsigned int zpos, - unsigned int cursor_win); int exynos_plane_init(struct drm_device *dev, struct exynos_drm_plane *exynos_plane, - unsigned long possible_crtcs, enum drm_plane_type type, - const uint32_t *formats, unsigned int fcount, - unsigned int zpos); + unsigned long possible_crtcs, + const struct exynos_drm_plane_config *config); diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.c b/drivers/gpu/drm/exynos/exynos_drm_vidi.c index 3ce141236fad..90701647aef1 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_vidi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_vidi.c @@ -30,7 +30,6 @@

/* vidi has totally three virtual windows. */ #define WINDOWS_NR 3 -#define CURSOR_WIN 2

#define ctx_from_connector(c) container_of(c, struct vidi_context, \ connector) @@ -90,6 +89,12 @@ static const uint32_t formats[] = { DRM_FORMAT_NV12, };

+static const enum drm_plane_type vidi_win_types[WINDOWS_NR] = { + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_OVERLAY, + DRM_PLANE_TYPE_CURSOR, +}; + static int vidi_enable_vblank(struct exynos_drm_crtc *crtc) { struct vidi_context *ctx = crtc->ctx; @@ -442,17 +447,21 @@ static int vidi_bind(struct device *dev, struct device *master, void *data) struct drm_device *drm_dev = data; struct drm_encoder *encoder = &ctx->encoder; struct exynos_drm_plane *exynos_plane; - enum drm_plane_type type; - unsigned int zpos; + struct exynos_drm_plane_config plane_config = { 0 }; + unsigned int i; int pipe, ret;

vidi_ctx_initialize(ctx, drm_dev);

- for (zpos = 0; zpos < WINDOWS_NR; zpos++) { - type = exynos_plane_get_type(zpos, CURSOR_WIN); - ret = exynos_plane_init(drm_dev, &ctx->planes[zpos], - 1 << ctx->pipe, type, formats, - ARRAY_SIZE(formats), zpos); + plane_config.pixel_formats = formats; + plane_config.num_pixel_formats = ARRAY_SIZE(formats); + + for (i = 0; i < WINDOWS_NR; i++) { + plane_config.zpos = i; + plane_config.type = vidi_win_types(i); + + ret = exynos_plane_init(drm_dev, &ctx->planes[i], + 1 << ctx->pipe, &plane_config); if (ret) return ret; } diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index 8d2ce13eb725..a229f86d221a 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c @@ -43,7 +43,6 @@

#define MIXER_WIN_NR 3 #define VP_DEFAULT_WIN 2 -#define CURSOR_WIN 1

/* The pixelformats that are natively supported by the mixer. */ #define MXR_FORMAT_RGB565 4 @@ -112,6 +111,25 @@ struct mixer_drv_data { bool has_sclk; };

+static const struct exynos_drm_plane_config plane_configs[MIXER_WIN_NR] = { + { + .zpos = 0, + .type = DRM_PLANE_TYPE_PRIMARY, + .pixel_formats = mixer_formats, + .num_pixel_formats = ARRAY_SIZE(mixer_formats), + }, { + .zpos = 1, + .type = DRM_PLANE_TYPE_CURSOR, + .pixel_formats = mixer_formats, + .num_pixel_formats = ARRAY_SIZE(mixer_formats), + }, { + .zpos = 2, + .type = DRM_PLANE_TYPE_OVERLAY, + .pixel_formats = vp_formats, + .num_pixel_formats = ARRAY_SIZE(vp_formats), + }, +}; + static const u8 filter_y_horiz_tap8[] = { 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, 0, 0, @@ -1155,33 +1173,19 @@ static int mixer_bind(struct device *dev, struct device *manager, void *data) struct mixer_context *ctx = dev_get_drvdata(dev); struct drm_device *drm_dev = data; struct exynos_drm_plane *exynos_plane; - unsigned int zpos; + unsigned int i; int ret;

ret = mixer_initialize(ctx, drm_dev); if (ret) return ret;

- for (zpos = 0; zpos < MIXER_WIN_NR; zpos++) { - enum drm_plane_type type; - const uint32_t *formats; - unsigned int fcount; - - if (zpos == VP_DEFAULT_WIN && !ctx->vp_enabled) + for (i = 0; i < MIXER_WIN_NR; i++) { + if (i == VP_DEFAULT_WIN && !ctx->vp_enabled) continue;

- if (zpos < VP_DEFAULT_WIN) { - formats = mixer_formats; - fcount = ARRAY_SIZE(mixer_formats); - } else { - formats = vp_formats; - fcount = ARRAY_SIZE(vp_formats); - } - - type = exynos_plane_get_type(zpos, CURSOR_WIN); - ret = exynos_plane_init(drm_dev, &ctx->planes[zpos], - 1 << ctx->pipe, type, formats, fcount, - zpos); + ret = exynos_plane_init(drm_dev, &ctx->planes[i], + 1 << ctx->pipe, &plane_configs[i]); if (ret) return ret; }

This patch adds generic check for plane state - display area dimensions, so drivers can always assume that they get valid plane state to set.

Signed-off-by: Marek Szyprowski m.szyprowski@samsung.com Reviewed-by: Gustavo Padovan gustavo.padovan@collabora.co.uk --- drivers/gpu/drm/exynos/exynos_drm_drv.h | 3 +++ drivers/gpu/drm/exynos/exynos_drm_plane.c | 31 +++++++++++++++++++++++++++++++ drivers/gpu/drm/exynos/exynos_mixer.c | 3 +++ 3 files changed, 37 insertions(+)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h index 6f8a296a3115..82bbd7f4b316 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.h +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h @@ -89,6 +89,9 @@ struct exynos_drm_plane { struct drm_framebuffer *pending_fb; };

+#define EXYNOS_DRM_PLANE_CAP_DOUBLE (1 << 0) +#define EXYNOS_DRM_PLANE_CAP_SCALE (1 << 1) + /* * Exynos DRM plane configuration structure. * diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c index b620d7a76799..9eaa8627175f 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_plane.c +++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c @@ -173,6 +173,36 @@ static struct drm_plane_funcs exynos_plane_funcs = { .atomic_destroy_state = exynos_drm_plane_destroy_state, };

+static int +exynos_drm_plane_check_size(const struct exynos_drm_plane_config *config, + struct exynos_drm_plane_state *state) +{ + bool width_ok = false, height_ok = false; + + if (config->capabilities & EXYNOS_DRM_PLANE_CAP_SCALE) + return 0; + + if (state->src.w == state->crtc.w) + width_ok = true; + + if (state->src.h == state->crtc.h) + height_ok = true; + + if ((config->capabilities & EXYNOS_DRM_PLANE_CAP_DOUBLE) && + state->h_ratio == (1 << 15)) + width_ok = true; + + if ((config->capabilities & EXYNOS_DRM_PLANE_CAP_DOUBLE) && + state->v_ratio == (1 << 15)) + height_ok = true; + + if (width_ok & height_ok) + return 0; + + DRM_DEBUG_KMS("scaling mode is not supported"); + return -ENOTSUPP; +} + static int exynos_plane_atomic_check(struct drm_plane *plane, struct drm_plane_state *state) { @@ -187,6 +217,7 @@ static int exynos_plane_atomic_check(struct drm_plane *plane, /* translate state into exynos_state */ exynos_plane_mode_set(exynos_state);

+ ret = exynos_drm_plane_check_size(exynos_plane->config, exynos_state); return ret; }

diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index a229f86d221a..4190285798ef 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c @@ -117,16 +117,19 @@ static const struct exynos_drm_plane_config plane_configs[MIXER_WIN_NR] = { .type = DRM_PLANE_TYPE_PRIMARY, .pixel_formats = mixer_formats, .num_pixel_formats = ARRAY_SIZE(mixer_formats), + .capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE, }, { .zpos = 1, .type = DRM_PLANE_TYPE_CURSOR, .pixel_formats = mixer_formats, .num_pixel_formats = ARRAY_SIZE(mixer_formats), + .capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE, }, { .zpos = 2, .type = DRM_PLANE_TYPE_OVERLAY, .pixel_formats = vp_formats, .num_pixel_formats = ARRAY_SIZE(vp_formats), + .capabilities = EXYNOS_DRM_PLANE_CAP_SCALE, }, };

This patch fixes calculation of src x/y offset for negative crtc x/y values when scaling is enabled. This fixes possible IOMMU fault when scaling is enabled.

Signed-off-by: Marek Szyprowski m.szyprowski@samsung.com --- drivers/gpu/drm/exynos/exynos_drm_plane.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c index 9eaa8627175f..427aeec78a28 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_plane.c +++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c @@ -85,25 +85,26 @@ static void exynos_plane_mode_set(struct exynos_drm_plane_state *exynos_state) src_w = state->src_w >> 16; src_h = state->src_h >> 16;

+ /* set ratio */ + exynos_state->h_ratio = (src_w << 16) / crtc_w; + exynos_state->v_ratio = (src_h << 16) / crtc_h; + + /* clip to visible area */ actual_w = exynos_plane_get_size(crtc_x, crtc_w, mode->hdisplay); actual_h = exynos_plane_get_size(crtc_y, crtc_h, mode->vdisplay);

if (crtc_x < 0) { if (actual_w) - src_x -= crtc_x; + src_x += ((-crtc_x) * exynos_state->h_ratio) >> 16; crtc_x = 0; }

if (crtc_y < 0) { if (actual_h) - src_y -= crtc_y; + src_y += ((-crtc_y) * exynos_state->v_ratio) >> 16; crtc_y = 0; }

- /* set ratio */ - exynos_state->h_ratio = (src_w << 16) / crtc_w; - exynos_state->v_ratio = (src_h << 16) / crtc_h; - /* set drm framebuffer data. */ exynos_state->src.x = src_x; exynos_state->src.y = src_y;

Add framebuffer pointer to exynos_drm_plane_state and tell drivers to use it. This lets common plane code to set temporary framebuffer in the future and drivers will use it without additional changes.

Signed-off-by: Marek Szyprowski m.szyprowski@samsung.com --- drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 2 +- drivers/gpu/drm/exynos/exynos7_drm_decon.c | 2 +- drivers/gpu/drm/exynos/exynos_drm_drv.h | 8 ++++++-- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 2 +- drivers/gpu/drm/exynos/exynos_drm_plane.c | 2 ++ drivers/gpu/drm/exynos/exynos_mixer.c | 4 ++-- 6 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c index 189ee5ca0a7a..1f705bede7dd 100644 --- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c @@ -269,7 +269,7 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc, struct exynos_drm_plane_state *state = to_exynos_plane_state(plane->base.state); struct decon_context *ctx = crtc->ctx; - struct drm_framebuffer *fb = state->base.fb; + struct drm_framebuffer *fb = state->fb; unsigned int win = plane->zpos; unsigned int bpp = fb->bits_per_pixel >> 3; unsigned int pitch = fb->pitches[0]; diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c b/drivers/gpu/drm/exynos/exynos7_drm_decon.c index c47f9af8170b..17aa11702a40 100644 --- a/drivers/gpu/drm/exynos/exynos7_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos7_drm_decon.c @@ -402,7 +402,7 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc, struct exynos_drm_plane_state *state = to_exynos_plane_state(plane->base.state); struct decon_context *ctx = crtc->ctx; - struct drm_framebuffer *fb = state->base.fb; + struct drm_framebuffer *fb = state->fb; int padding; unsigned long val, alpha; unsigned int last_x; diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h index 82bbd7f4b316..bb2e449a20c3 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.h +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h @@ -53,9 +53,12 @@ struct exynos_drm_rect { * (clipped to visible part). * @h_ratio: horizontal scaling ratio, 16.16 fixed point * @v_ratio: vertical scaling ratio, 16.16 fixed point + * @fb: framebuffer with image data to be displayed (drivers should use this + * instead of .base->fb) * - * this structure consists plane state data that will be applied to hardware - * specific overlay info. + * This structure consists plane state data that will be applied to hardware + * specific overlay info. Some data is duplicated (comparing with base state) + * to let common code to modify it for internal use. */

struct exynos_drm_plane_state { @@ -64,6 +67,7 @@ struct exynos_drm_plane_state { struct exynos_drm_rect src; unsigned int h_ratio; unsigned int v_ratio; + struct drm_framebuffer *fb; };

static inline struct exynos_drm_plane_state * diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index 2e2247126581..0046495173f3 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -650,7 +650,7 @@ static void fimd_update_plane(struct exynos_drm_crtc *crtc, struct exynos_drm_plane_state *state = to_exynos_plane_state(plane->base.state); struct fimd_context *ctx = crtc->ctx; - struct drm_framebuffer *fb = state->base.fb; + struct drm_framebuffer *fb = state->fb; dma_addr_t dma_addr; unsigned long val, size, offset; unsigned int last_x, last_y, buf_offsize, line_size; diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c index 427aeec78a28..8a1242b5a938 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_plane.c +++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c @@ -117,6 +117,8 @@ static void exynos_plane_mode_set(struct exynos_drm_plane_state *exynos_state) exynos_state->crtc.w = actual_w; exynos_state->crtc.h = actual_h;

+ exynos_state->fb = state->fb; + DRM_DEBUG_KMS("plane : offset_x/y(%d,%d), width/height(%d,%d)", exynos_state->crtc.x, exynos_state->crtc.y, exynos_state->crtc.w, exynos_state->crtc.h); diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index dfb35e2da4db..787aa03f4359 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c @@ -425,7 +425,7 @@ static void vp_video_buffer(struct mixer_context *ctx, to_exynos_plane_state(plane->base.state); struct drm_display_mode *mode = &state->base.crtc->state->adjusted_mode; struct mixer_resources *res = &ctx->mixer_res; - struct drm_framebuffer *fb = state->base.fb; + struct drm_framebuffer *fb = state->fb; unsigned long flags; dma_addr_t luma_addr[2], chroma_addr[2]; bool tiled_mode = false; @@ -535,7 +535,7 @@ static void mixer_graph_buffer(struct mixer_context *ctx, to_exynos_plane_state(plane->base.state); struct drm_display_mode *mode = &state->base.crtc->state->adjusted_mode; struct mixer_resources *res = &ctx->mixer_res; - struct drm_framebuffer *fb = state->base.fb; + struct drm_framebuffer *fb = state->fb; unsigned long flags; unsigned int win = plane->zpos; unsigned int x_ratio = 0, y_ratio = 0;

From: Seung-Woo Kim sw0312.kim@samsung.com

NV12 and YUV420 formats are need to calculate offset of each plane for ipp fimc in a gem buffer. Without proper offset, only Y plane can be processed, so result shows green frame. This patch fixes to calculate offset for cbcr planes for NV12 and YUV420 formats.

Signed-off-by: Seung-Woo Kim sw0312.kim@samsung.com Signed-off-by: Marek Szyprowski m.szyprowski@samsung.com --- drivers/gpu/drm/exynos/exynos_drm_fimc.c | 106 +++++++++++++++++++++++++++++++ drivers/gpu/drm/exynos/exynos_drm_ipp.c | 15 ++++- drivers/gpu/drm/exynos/exynos_drm_ipp.h | 2 + 3 files changed, 121 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimc.c b/drivers/gpu/drm/exynos/exynos_drm_fimc.c index c747824f3c98..72a7ca188be5 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimc.c @@ -403,6 +403,97 @@ static void fimc_handle_lastend(struct fimc_context *ctx, bool enable) fimc_write(ctx, cfg, EXYNOS_CIOCTRL); }

+static int fimc_set_planar_addr(struct drm_exynos_ipp_buf_info *buf_info, + u32 fmt, struct drm_exynos_sz *sz) +{ + dma_addr_t *base[EXYNOS_DRM_PLANAR_MAX]; + uint64_t size[EXYNOS_DRM_PLANAR_MAX]; + uint64_t ofs[EXYNOS_DRM_PLANAR_MAX]; + bool bypass = false; + uint64_t tsize = 0; + int i; + + for_each_ipp_planar(i) { + base[i] = &buf_info->base[i]; + size[i] = buf_info->size[i]; + ofs[i] = 0; + tsize += size[i]; + } + + if (!tsize) { + DRM_INFO("%s:failed to get buffer size.\n", __func__); + return 0; + } + + switch (fmt) { + case DRM_FORMAT_NV12: + case DRM_FORMAT_NV21: + case DRM_FORMAT_NV16: + case DRM_FORMAT_NV61: + ofs[0] = sz->hsize * sz->vsize; + ofs[1] = ofs[0] >> 1; + if (*base[0] && *base[1]) { + if (size[0] + size[1] < ofs[0] + ofs[1]) + goto err_info; + bypass = true; + } + break; + case DRM_FORMAT_YUV410: + case DRM_FORMAT_YVU410: + case DRM_FORMAT_YUV411: + case DRM_FORMAT_YVU411: + case DRM_FORMAT_YUV420: + case DRM_FORMAT_YVU420: + case DRM_FORMAT_YUV422: + case DRM_FORMAT_YVU422: + case DRM_FORMAT_YUV444: + case DRM_FORMAT_YVU444: + ofs[0] = sz->hsize * sz->vsize; + ofs[1] = ofs[2] = ofs[0] >> 2; + if (*base[0] && *base[1] && *base[2]) { + if (size[0]+size[1]+size[2] < ofs[0]+ofs[1]+ofs[2]) + goto err_info; + bypass = true; + } + break; + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_ARGB8888: + ofs[0] = sz->hsize * sz->vsize << 2; + if (*base[0]) { + if (size[0] < ofs[0]) + goto err_info; + } + bypass = true; + break; + default: + bypass = true; + break; + } + + if (!bypass) { + *base[1] = *base[0] + ofs[0]; + if (ofs[1] && ofs[2]) + *base[2] = *base[1] + ofs[1]; + } + + DRM_DEBUG_KMS("%s:y[0x%x],cb[0x%x],cr[0x%x]\n", __func__, + *base[0], *base[1], *base[2]); + + return 0; + +err_info: + DRM_ERROR("invalid size for fmt[0x%x]\n", fmt); + + for_each_ipp_planar(i) { + base[i] = &buf_info->base[i]; + size[i] = buf_info->size[i]; + + DRM_ERROR("buf[%d] - base[0x%x] sz[%llu] ofs[%llu]\n", + i, *base[i], size[i], ofs[i]); + } + + return -EINVAL; +}

static int fimc_src_set_fmt_order(struct fimc_context *ctx, u32 fmt) { @@ -689,6 +780,7 @@ static int fimc_src_set_addr(struct device *dev, struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node; struct drm_exynos_ipp_property *property; struct drm_exynos_ipp_config *config; + int ret;

if (!c_node) { DRM_ERROR("failed to get c_node.\n"); @@ -709,6 +801,12 @@ static int fimc_src_set_addr(struct device *dev, switch (buf_type) { case IPP_BUF_ENQUEUE: config = &property->config[EXYNOS_DRM_OPS_SRC]; + ret = fimc_set_planar_addr(buf_info, config->fmt, &config->sz); + if (ret) { + dev_err(dev, "failed to set plane src addr.\n"); + return ret; + } + fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_Y], EXYNOS_CIIYSA0);

@@ -1148,6 +1246,7 @@ static int fimc_dst_set_addr(struct device *dev, struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node; struct drm_exynos_ipp_property *property; struct drm_exynos_ipp_config *config; + int ret;

if (!c_node) { DRM_ERROR("failed to get c_node.\n"); @@ -1168,6 +1267,11 @@ static int fimc_dst_set_addr(struct device *dev, switch (buf_type) { case IPP_BUF_ENQUEUE: config = &property->config[EXYNOS_DRM_OPS_DST]; + ret = fimc_set_planar_addr(buf_info, config->fmt, &config->sz); + if (ret) { + dev_err(dev, "failed to set plane dst addr.\n"); + return ret; + }

fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_Y], EXYNOS_CIOYSA(buf_id)); @@ -1562,6 +1666,8 @@ static void fimc_ippdrv_stop(struct device *dev, enum drm_exynos_ipp_cmd cmd) /* reset sequence */ fimc_write(ctx, 0x0, EXYNOS_CIFCNTSEQ);

+ fimc_clear_addr(ctx); + /* Scaler disable */ fimc_clear_bits(ctx, EXYNOS_CISCCTRL, EXYNOS_CISCCTRL_SCALERSTART);

diff --git a/drivers/gpu/drm/exynos/exynos_drm_ipp.c b/drivers/gpu/drm/exynos/exynos_drm_ipp.c index 67d24236e745..408a14a9a180 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_ipp.c +++ b/drivers/gpu/drm/exynos/exynos_drm_ipp.c @@ -571,6 +571,7 @@ static struct drm_exynos_ipp_mem_node /* get dma address by handle */ if (qbuf->handle[i]) { dma_addr_t *addr; + unsigned long size;

addr = exynos_drm_gem_get_dma_addr(drm_dev, qbuf->handle[i], c_node->filp); @@ -580,10 +581,20 @@ static struct drm_exynos_ipp_mem_node return ERR_PTR(-EFAULT); }

+ size = exynos_drm_gem_get_size(drm_dev, + qbuf->handle[i], c_node->filp); + if (!size) { + DRM_ERROR("failed to get size.\n"); + ipp_put_mem_node(drm_dev, c_node, m_node); + return ERR_PTR(-EFAULT); + } + buf_info->handles[i] = qbuf->handle[i]; buf_info->base[i] = *addr; - DRM_DEBUG_KMS("i[%d]base[0x%x]hd[0x%lx]\n", i, - buf_info->base[i], buf_info->handles[i]); + buf_info->size[i] = (uint64_t)size; + DRM_DEBUG_KMS("i[%d]base[%pad]hd[0x%lx]sz[%llx]\n", i, + &buf_info->base[i], buf_info->handles[i], + buf_info->size[i]); } }

diff --git a/drivers/gpu/drm/exynos/exynos_drm_ipp.h b/drivers/gpu/drm/exynos/exynos_drm_ipp.h index 2a61547a39d0..d4f0b588220b 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_ipp.h +++ b/drivers/gpu/drm/exynos/exynos_drm_ipp.h @@ -85,10 +85,12 @@ struct drm_exynos_ipp_cmd_node { * * @handles: Y, Cb, Cr each gem object handle. * @base: Y, Cb, Cr each planar address. + * @size: Y, Cb, Cr each planar size. */ struct drm_exynos_ipp_buf_info { unsigned long handles[EXYNOS_DRM_PLANAR_MAX]; dma_addr_t base[EXYNOS_DRM_PLANAR_MAX]; + uint64_t size[EXYNOS_DRM_PLANAR_MAX]; };

/*

Replace calls to exynos_drm_gem_get_{dma_addr,size}, by a simpler function exynos_drm_gem_get(). This lets the caller to get access to exynos_drm_gem object and extract any information about GEM object without searching object tree for getting each parameter.

Signed-off-by: Marek Szyprowski m.szyprowski@samsung.com --- drivers/gpu/drm/exynos/exynos_drm_g2d.c | 48 +++++++++++++----------------- drivers/gpu/drm/exynos/exynos_drm_gem.c | 52 +++++---------------------------- drivers/gpu/drm/exynos/exynos_drm_gem.h | 23 +++++---------- drivers/gpu/drm/exynos/exynos_drm_ipp.c | 41 ++++++++++---------------- drivers/gpu/drm/exynos/exynos_drm_ipp.h | 2 +- 5 files changed, 52 insertions(+), 114 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_g2d.c b/drivers/gpu/drm/exynos/exynos_drm_g2d.c index c17efdb238a6..7c83e64f9f1c 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_g2d.c +++ b/drivers/gpu/drm/exynos/exynos_drm_g2d.c @@ -179,7 +179,7 @@ struct g2d_buf_desc { struct g2d_buf_info { unsigned int map_nr; enum g2d_reg_type reg_types[MAX_REG_TYPE_NR]; - unsigned long handles[MAX_REG_TYPE_NR]; + void *obj[MAX_REG_TYPE_NR]; unsigned int types[MAX_REG_TYPE_NR]; struct g2d_buf_desc descs[MAX_REG_TYPE_NR]; }; @@ -360,11 +360,10 @@ add_to_list: }

static void g2d_userptr_put_dma_addr(struct drm_device *drm_dev, - unsigned long obj, + void *obj, bool force) { - struct g2d_cmdlist_userptr *g2d_userptr = - (struct g2d_cmdlist_userptr *)obj; + struct g2d_cmdlist_userptr *g2d_userptr = obj; struct page **pages;

if (!obj) @@ -407,7 +406,7 @@ static dma_addr_t *g2d_userptr_get_dma_addr(struct drm_device *drm_dev, unsigned long userptr, unsigned long size, struct drm_file *filp, - unsigned long *obj) + void **obj) { struct drm_exynos_file_private *file_priv = filp->driver_priv; struct exynos_drm_g2d_private *g2d_priv = file_priv->g2d_priv; @@ -434,7 +433,7 @@ static dma_addr_t *g2d_userptr_get_dma_addr(struct drm_device *drm_dev, */ if (g2d_userptr->size == size) { atomic_inc(&g2d_userptr->refcount); - *obj = (unsigned long)g2d_userptr; + *obj = g2d_userptr;

return &g2d_userptr->dma_addr; } @@ -517,7 +516,7 @@ static dma_addr_t *g2d_userptr_get_dma_addr(struct drm_device *drm_dev, g2d_userptr->in_pool = true; }

- *obj = (unsigned long)g2d_userptr; + *obj = g2d_userptr;

return &g2d_userptr->dma_addr;

@@ -549,9 +548,7 @@ static void g2d_userptr_free_all(struct drm_device *drm_dev,

list_for_each_entry_safe(g2d_userptr, n, &g2d_priv->userptr_list, list) if (g2d_userptr->in_pool) - g2d_userptr_put_dma_addr(drm_dev, - (unsigned long)g2d_userptr, - true); + g2d_userptr_put_dma_addr(drm_dev, g2d_userptr, true);

g2d->current_pool = 0; } @@ -706,26 +703,23 @@ static int g2d_map_cmdlist_gem(struct g2d_data *g2d, buf_desc = &buf_info->descs[reg_type];

if (buf_info->types[reg_type] == BUF_TYPE_GEM) { - unsigned long size; + struct exynos_drm_gem *exynos_gem;

- size = exynos_drm_gem_get_size(drm_dev, handle, file); - if (!size) { + exynos_gem = exynos_drm_gem_get(drm_dev, handle, file); + if (IS_ERR(exynos_gem)) { ret = -EFAULT; goto err; }

if (!g2d_check_buf_desc_is_valid(buf_desc, reg_type, - size)) { + exynos_gem->size)) { + exynos_drm_gem_put(drm_dev, exynos_gem); ret = -EFAULT; goto err; }

- addr = exynos_drm_gem_get_dma_addr(drm_dev, handle, - file); - if (IS_ERR(addr)) { - ret = -EFAULT; - goto err; - } + addr = &exynos_gem->dma_addr; + buf_info->obj[reg_type] = exynos_gem; } else { struct drm_exynos_g2d_userptr g2d_userptr;

@@ -745,7 +739,7 @@ static int g2d_map_cmdlist_gem(struct g2d_data *g2d, g2d_userptr.userptr, g2d_userptr.size, file, - &handle); + &buf_info->obj[reg_type]); if (IS_ERR(addr)) { ret = -EFAULT; goto err; @@ -754,7 +748,6 @@ static int g2d_map_cmdlist_gem(struct g2d_data *g2d,

cmdlist->data[reg_pos + 1] = *addr; buf_info->reg_types[i] = reg_type; - buf_info->handles[reg_type] = handle; }

return 0; @@ -775,22 +768,21 @@ static void g2d_unmap_cmdlist_gem(struct g2d_data *g2d, for (i = 0; i < buf_info->map_nr; i++) { struct g2d_buf_desc *buf_desc; enum g2d_reg_type reg_type; - unsigned long handle; + void *obj;

reg_type = buf_info->reg_types[i];

buf_desc = &buf_info->descs[reg_type]; - handle = buf_info->handles[reg_type]; + obj = buf_info->obj[reg_type];

if (buf_info->types[reg_type] == BUF_TYPE_GEM) - exynos_drm_gem_put_dma_addr(subdrv->drm_dev, handle, - filp); + exynos_drm_gem_put(subdrv->drm_dev, obj); else - g2d_userptr_put_dma_addr(subdrv->drm_dev, handle, + g2d_userptr_put_dma_addr(subdrv->drm_dev, obj, false);

buf_info->reg_types[i] = REG_TYPE_NONE; - buf_info->handles[reg_type] = 0; + buf_info->obj[reg_type] = NULL; buf_info->types[reg_type] = 0; memset(buf_desc, 0x00, sizeof(*buf_desc)); } diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.c b/drivers/gpu/drm/exynos/exynos_drm_gem.c index b5db6e6cc043..382e65df5c03 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_gem.c +++ b/drivers/gpu/drm/exynos/exynos_drm_gem.c @@ -169,26 +169,6 @@ void exynos_drm_gem_destroy(struct exynos_drm_gem *exynos_gem) kfree(exynos_gem); }

-unsigned long exynos_drm_gem_get_size(struct drm_device *dev, - unsigned int gem_handle, - struct drm_file *file_priv) -{ - struct exynos_drm_gem *exynos_gem; - struct drm_gem_object *obj; - - obj = drm_gem_object_lookup(dev, file_priv, gem_handle); - if (!obj) { - DRM_ERROR("failed to lookup gem object.\n"); - return 0; - } - - exynos_gem = to_exynos_gem(obj); - - drm_gem_object_unreference_unlocked(obj); - - return exynos_gem->size; -} - static struct exynos_drm_gem *exynos_drm_gem_init(struct drm_device *dev, unsigned long size) { @@ -279,11 +259,10 @@ int exynos_drm_gem_create_ioctl(struct drm_device *dev, void *data, return 0; }

-dma_addr_t *exynos_drm_gem_get_dma_addr(struct drm_device *dev, - unsigned int gem_handle, - struct drm_file *filp) +struct exynos_drm_gem *exynos_drm_gem_get(struct drm_device *dev, + unsigned int gem_handle, + struct drm_file *filp) { - struct exynos_drm_gem *exynos_gem; struct drm_gem_object *obj;

obj = drm_gem_object_lookup(dev, filp, gem_handle); @@ -292,30 +271,13 @@ dma_addr_t *exynos_drm_gem_get_dma_addr(struct drm_device *dev, return ERR_PTR(-EINVAL); }

- exynos_gem = to_exynos_gem(obj); - - return &exynos_gem->dma_addr; + return to_exynos_gem(obj); }

-void exynos_drm_gem_put_dma_addr(struct drm_device *dev, - unsigned int gem_handle, - struct drm_file *filp) +void exynos_drm_gem_put(struct drm_device *dev, + struct exynos_drm_gem *exynos_gem) { - struct drm_gem_object *obj; - - obj = drm_gem_object_lookup(dev, filp, gem_handle); - if (!obj) { - DRM_ERROR("failed to lookup gem object.\n"); - return; - } - - drm_gem_object_unreference_unlocked(obj); - - /* - * decrease obj->refcount one more time because we has already - * increased it at exynos_drm_gem_get_dma_addr(). - */ - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_unreference_unlocked(&exynos_gem->base); }

static int exynos_drm_gem_mmap_buffer(struct exynos_drm_gem *exynos_gem, diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.h b/drivers/gpu/drm/exynos/exynos_drm_gem.h index 9ca5047959ec..d4a49985c8ab 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_gem.h +++ b/drivers/gpu/drm/exynos/exynos_drm_gem.h @@ -72,32 +72,25 @@ int exynos_drm_gem_create_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);

/* - * get dma address from gem handle and this function could be used for + * get exynos drm object from gem handle, this function could be used for * other drivers such as 2d/3d acceleration drivers. * with this function call, gem object reference count would be increased. */ -dma_addr_t *exynos_drm_gem_get_dma_addr(struct drm_device *dev, - unsigned int gem_handle, - struct drm_file *filp); +struct exynos_drm_gem *exynos_drm_gem_get(struct drm_device *dev, + unsigned int gem_handle, + struct drm_file *filp);

/* - * put dma address from gem handle and this function could be used for - * other drivers such as 2d/3d acceleration drivers. - * with this function call, gem object reference count would be decreased. + * put exynos drm object acquired from exynos_drm_gem_get(), + * gem object reference count would be decreased. */ -void exynos_drm_gem_put_dma_addr(struct drm_device *dev, - unsigned int gem_handle, - struct drm_file *filp); +void exynos_drm_gem_put(struct drm_device *dev, + struct exynos_drm_gem *exynos_gem);

/* get buffer information to memory region allocated by gem. */ int exynos_drm_gem_get_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);

-/* get buffer size to gem handle. */ -unsigned long exynos_drm_gem_get_size(struct drm_device *dev, - unsigned int gem_handle, - struct drm_file *file_priv); - /* free gem object. */ void exynos_drm_gem_free_object(struct drm_gem_object *obj);

diff --git a/drivers/gpu/drm/exynos/exynos_drm_ipp.c b/drivers/gpu/drm/exynos/exynos_drm_ipp.c index 408a14a9a180..0404e18d84cc 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_ipp.c +++ b/drivers/gpu/drm/exynos/exynos_drm_ipp.c @@ -488,10 +488,9 @@ static int ipp_validate_mem_node(struct drm_device *drm_dev, plane_size = width * height * bpp; img_size += plane_size;

- if (m_node->buf_info.handles[i]) { - size = exynos_drm_gem_get_size(drm_dev, - m_node->buf_info.handles[i], - c_node->filp); + if (m_node->buf_info.obj[i]) { + size = m_node->buf_info.obj[i]->size; + if (plane_size > size) { DRM_ERROR( "buffer %d is smaller than required\n", @@ -529,10 +528,9 @@ static int ipp_put_mem_node(struct drm_device *drm_dev,

/* put gem buffer */ for_each_ipp_planar(i) { - unsigned long handle = m_node->buf_info.handles[i]; - if (handle) - exynos_drm_gem_put_dma_addr(drm_dev, handle, - c_node->filp); + struct exynos_drm_gem *obj = m_node->buf_info.obj[i]; + if (obj) + exynos_drm_gem_put(drm_dev, obj); }

list_del(&m_node->list); @@ -570,30 +568,23 @@ static struct drm_exynos_ipp_mem_node

/* get dma address by handle */ if (qbuf->handle[i]) { - dma_addr_t *addr; - unsigned long size; + struct exynos_drm_gem *exynos_gem;

- addr = exynos_drm_gem_get_dma_addr(drm_dev, - qbuf->handle[i], c_node->filp); - if (IS_ERR(addr)) { - DRM_ERROR("failed to get addr.\n"); - ipp_put_mem_node(drm_dev, c_node, m_node); - return ERR_PTR(-EFAULT); - } + exynos_gem = exynos_drm_gem_get(drm_dev, + qbuf->handle[i], c_node->filp);

- size = exynos_drm_gem_get_size(drm_dev, - qbuf->handle[i], c_node->filp); - if (!size) { - DRM_ERROR("failed to get size.\n"); + if (IS_ERR(exynos_gem)) { + DRM_ERROR("failed to get gem.\n"); ipp_put_mem_node(drm_dev, c_node, m_node); return ERR_PTR(-EFAULT); }

- buf_info->handles[i] = qbuf->handle[i]; - buf_info->base[i] = *addr; - buf_info->size[i] = (uint64_t)size; + buf_info->obj[i] = exynos_gem; + buf_info->base[i] = exynos_gem->dma_addr; + buf_info->size[i] = exynos_gem->size; DRM_DEBUG_KMS("i[%d]base[%pad]hd[0x%lx]sz[%llx]\n", i, - &buf_info->base[i], buf_info->handles[i], + &buf_info->base[i], + (long unsigned)qbuf->handle[i], buf_info->size[i]); } } diff --git a/drivers/gpu/drm/exynos/exynos_drm_ipp.h b/drivers/gpu/drm/exynos/exynos_drm_ipp.h index d4f0b588220b..1dc13bf57b16 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_ipp.h +++ b/drivers/gpu/drm/exynos/exynos_drm_ipp.h @@ -88,7 +88,7 @@ struct drm_exynos_ipp_cmd_node { * @size: Y, Cb, Cr each planar size. */ struct drm_exynos_ipp_buf_info { - unsigned long handles[EXYNOS_DRM_PLANAR_MAX]; + struct exynos_drm_gem *obj[EXYNOS_DRM_PLANAR_MAX]; dma_addr_t base[EXYNOS_DRM_PLANAR_MAX]; uint64_t size[EXYNOS_DRM_PLANAR_MAX]; };

This patch adds generic plane rotation property for all supported drivers. This has been implemented with additional help from Exynos IPP (Exynos Image Post-Processing subsystem) with temporary framebuffers. Besides rotation, scaling and color space conversion are also supported.

Signed-off-by: Marek Szyprowski m.szyprowski@samsung.com --- drivers/gpu/drm/exynos/Kconfig | 8 + drivers/gpu/drm/exynos/Makefile | 1 + drivers/gpu/drm/exynos/exynos_drm_drv.h | 9 + drivers/gpu/drm/exynos/exynos_drm_ipp.c | 154 ++++++++++- drivers/gpu/drm/exynos/exynos_drm_ipp.h | 4 + drivers/gpu/drm/exynos/exynos_drm_plane.c | 28 +- drivers/gpu/drm/exynos/exynos_drm_plane_ipp.c | 369 ++++++++++++++++++++++++++ drivers/gpu/drm/exynos/exynos_drm_plane_ipp.h | 73 +++++ 8 files changed, 641 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/exynos/exynos_drm_plane_ipp.c create mode 100644 drivers/gpu/drm/exynos/exynos_drm_plane_ipp.h

diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig index 83efca941388..e7d414aefbdc 100644 --- a/drivers/gpu/drm/exynos/Kconfig +++ b/drivers/gpu/drm/exynos/Kconfig @@ -104,6 +104,14 @@ config DRM_EXYNOS_IPP help Choose this option if you want to use IPP feature for DRM.

+config DRM_EXYNOS_PLANE_IPP + depends on DRM_EXYNOS_IPP + bool "Use IPP framework for implementing unsupported plane properties" + help + Choose this option if you want to let IPP framework to provide plane + properties (like rotation, overlay scaling and more pixel formats), + which are not supported by hardware CRTC drivers. + config DRM_EXYNOS_FIMC bool "FIMC" depends on DRM_EXYNOS_IPP && MFD_SYSCON diff --git a/drivers/gpu/drm/exynos/Makefile b/drivers/gpu/drm/exynos/Makefile index 6496532aaa91..92c3f7cac7a9 100644 --- a/drivers/gpu/drm/exynos/Makefile +++ b/drivers/gpu/drm/exynos/Makefile @@ -19,6 +19,7 @@ exynosdrm-$(CONFIG_DRM_EXYNOS_HDMI) += exynos_hdmi.o exynosdrm-$(CONFIG_DRM_EXYNOS_VIDI) += exynos_drm_vidi.o exynosdrm-$(CONFIG_DRM_EXYNOS_G2D) += exynos_drm_g2d.o exynosdrm-$(CONFIG_DRM_EXYNOS_IPP) += exynos_drm_ipp.o +exynosdrm-$(CONFIG_DRM_EXYNOS_PLANE_IPP) += exynos_drm_plane_ipp.o exynosdrm-$(CONFIG_DRM_EXYNOS_FIMC) += exynos_drm_fimc.o exynosdrm-$(CONFIG_DRM_EXYNOS_ROTATOR) += exynos_drm_rotator.o exynosdrm-$(CONFIG_DRM_EXYNOS_GSC) += exynos_drm_gsc.o diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h index 670f6d06a2a9..b17e419935db 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.h +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h @@ -70,6 +70,13 @@ struct exynos_drm_plane_state { unsigned int h_ratio; unsigned int v_ratio; struct drm_framebuffer *fb; + unsigned int rotation; + + unsigned int ipp_needed; + uint32_t ipp_pixel_format; + struct exynos_drm_rect ipp_src; + struct exynos_drm_rect ipp_dst; + struct drm_framebuffer *ipp_fb; };

static inline struct exynos_drm_plane_state * @@ -93,6 +100,8 @@ struct exynos_drm_plane { const struct exynos_drm_plane_config *config; unsigned int zpos; struct drm_framebuffer *pending_fb; + struct drm_framebuffer *ipp_cur_fb; + struct drm_framebuffer *ipp_next_fb; };

#define EXYNOS_DRM_PLANE_CAP_DOUBLE (1 << 0) diff --git a/drivers/gpu/drm/exynos/exynos_drm_ipp.c b/drivers/gpu/drm/exynos/exynos_drm_ipp.c index 44a6689e0f4c..231cfbfe036c 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_ipp.c +++ b/drivers/gpu/drm/exynos/exynos_drm_ipp.c @@ -20,6 +20,7 @@ #include <drm/drmP.h> #include <drm/exynos_drm.h> #include "exynos_drm_drv.h" +#include "exynos_drm_fb.h" #include "exynos_drm_gem.h" #include "exynos_drm_ipp.h" #include "exynos_drm_iommu.h" @@ -1513,7 +1514,7 @@ static int ipp_send_event(struct exynos_drm_ippdrv *ippdrv,

spin_lock_irqsave(&drm_dev->event_lock, flags); list_move_tail(&e->base.link, &e->base.file_priv->event_list); - wake_up_interruptible(&e->base.file_priv->event_wait); + wake_up(&e->base.file_priv->event_wait); spin_unlock_irqrestore(&drm_dev->event_lock, flags); mutex_unlock(&c_node->event_lock);

@@ -1579,6 +1580,157 @@ err_completion: complete(&c_node->start_complete); }

+static struct drm_exynos_ipp_mem_node + *ipp_get_internal_mem_node(struct drm_device *drm_dev, + struct drm_exynos_ipp_cmd_node *c_node, + __u32 prop_id, enum drm_exynos_ops_id ops_id, + struct drm_framebuffer *fb) +{ + struct drm_exynos_ipp_mem_node *m_node; + struct drm_exynos_ipp_buf_info *buf_info; + int i; + + m_node = kzalloc(sizeof(*m_node), GFP_KERNEL); + if (!m_node) + return ERR_PTR(-ENOMEM); + + buf_info = &m_node->buf_info; + + m_node->ops_id = ops_id; + m_node->prop_id = prop_id; + INIT_LIST_HEAD(&m_node->list); + + DRM_DEBUG_KMS("m_node[0x%x]ops_id[%d]prop_id[%d]\n", (int)m_node, ops_id, prop_id); + + for_each_ipp_planar(i) { + buf_info->obj[i] = NULL; + buf_info->base[i] = exynos_drm_fb_dma_addr(fb, i); + buf_info->size[i] = fb->pitches[i] * fb->height; + } + + mutex_lock(&c_node->mem_lock); + list_add_tail(&m_node->list, &c_node->mem_list[ops_id]); + mutex_unlock(&c_node->mem_lock); + + return m_node; +} + + +static int exynos_drm_ipp_internal_enqueue_buf(struct drm_device *drm_dev, + __u32 prop_id, enum drm_exynos_ops_id ops_id, + struct drm_framebuffer *fb) +{ + struct drm_exynos_ipp_cmd_node *c_node; + struct drm_exynos_ipp_mem_node *m_node; + int ret; + struct drm_exynos_ipp_queue_buf qbuf = { + .ops_id = ops_id, + .buf_type = IPP_BUF_ENQUEUE, + .prop_id = prop_id, + }; + + DRM_DEBUG_KMS("prop_id[%d]ops_id[%s]\n", + prop_id, ops_id ? "dst" : "src"); + + c_node = ipp_find_obj(&ctx->prop_idr, &ctx->prop_lock, prop_id); + if (!c_node) { + DRM_ERROR("failed to get command node.\n"); + return -ENODEV; + } + + m_node = ipp_get_internal_mem_node(drm_dev, c_node, prop_id, + ops_id, fb); + if (IS_ERR(m_node)) { + DRM_ERROR("failed to get m_node.\n"); + return PTR_ERR(m_node); + } + + if (ops_id == EXYNOS_DRM_OPS_DST) { + ret = ipp_get_event(drm_dev, c_node, &qbuf); + if (ret) { + DRM_ERROR("failed to get event.\n"); + goto err_clean_node; + } + + ret = ipp_queue_buf_with_run(c_node, m_node, &qbuf); + if (ret) { + DRM_ERROR("failed to run command.\n"); + goto err_clean_node; + } + } + + return 0; + +err_clean_node: + DRM_ERROR("clean memory nodes.\n"); + + ipp_clean_queue_buf(drm_dev, c_node, &qbuf); + return ret; +} + +int exynos_ipp_process_internal(struct drm_device *drm_dev, + struct drm_exynos_ipp_config *src_conf, struct drm_framebuffer *src_fb, + struct drm_exynos_ipp_config *dst_conf, struct drm_framebuffer *dst_fb) +{ + int ret; + struct drm_exynos_ipp_property property = { + .config = { + *src_conf, + *dst_conf, + }, + .cmd = IPP_CMD_M2M, + }; + struct drm_exynos_ipp_cmd_ctrl ctrl = { + /* .prop_id */ + .ctrl = IPP_CTRL_PLAY, + }; + struct drm_exynos_ipp_cmd_ctrl ctrl_stop = { + /* .prop_id */ + .ctrl = IPP_CTRL_STOP, + }; + struct drm_file virt_file = { }; + + INIT_LIST_HEAD(&virt_file.lhead); + INIT_LIST_HEAD(&virt_file.fbs); + mutex_init(&virt_file.fbs_lock); + INIT_LIST_HEAD(&virt_file.blobs); + INIT_LIST_HEAD(&virt_file.event_list); + init_waitqueue_head(&virt_file.event_wait); + virt_file.event_space = 4096; + virt_file.uid = current_euid(); + virt_file.pid = get_pid(task_pid(current)); + virt_file.authenticated = capable(CAP_SYS_ADMIN); + virt_file.lock_count = 0; + + ret = exynos_drm_ipp_set_property(drm_dev, &property, &virt_file); + if (ret) + return ret; + + ctrl.prop_id = property.prop_id; + ctrl_stop.prop_id = property.prop_id; + + ret = exynos_drm_ipp_internal_enqueue_buf(drm_dev, property.prop_id, + EXYNOS_DRM_OPS_SRC, src_fb); + if (ret) + goto cleanup; + + ret = exynos_drm_ipp_internal_enqueue_buf(drm_dev, property.prop_id, + EXYNOS_DRM_OPS_DST, dst_fb); + if (ret) + goto cleanup; + + ret = exynos_drm_ipp_cmd_ctrl(drm_dev, &ctrl, &virt_file); + if (ret) + goto cleanup; + + wait_event(virt_file.event_wait, !list_empty(&virt_file.event_list)); + +cleanup: + exynos_drm_ipp_cmd_ctrl(drm_dev, &ctrl_stop, &virt_file); + + return ret; +} + static int ipp_subdrv_probe(struct drm_device *drm_dev, struct device *dev) { struct exynos_drm_ippdrv *ippdrv; diff --git a/drivers/gpu/drm/exynos/exynos_drm_ipp.h b/drivers/gpu/drm/exynos/exynos_drm_ipp.h index 1dc13bf57b16..7e95437edecb 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_ipp.h +++ b/drivers/gpu/drm/exynos/exynos_drm_ipp.h @@ -24,6 +24,10 @@ #define IPP_GET_LCD_HEIGHT _IOR('F', 303, int) #define IPP_SET_WRITEBACK _IOW('F', 304, u32)

+int exynos_ipp_process_internal(struct drm_device *drm_dev, + struct drm_exynos_ipp_config *src_conf, struct drm_framebuffer *src_fb, + struct drm_exynos_ipp_config *dst_conf, struct drm_framebuffer *dst_fb); + /* definition of state */ enum drm_exynos_ipp_state { IPP_STATE_IDLE, diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c index 8a1242b5a938..34ed1d6b8184 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_plane.c +++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c @@ -19,6 +19,7 @@ #include "exynos_drm_fb.h" #include "exynos_drm_gem.h" #include "exynos_drm_plane.h" +#include "exynos_drm_plane_ipp.h"

/* * This function is to get X or Y size shown via screen. This needs length and @@ -56,7 +57,8 @@ static int exynos_plane_get_size(int start, unsigned length, unsigned last) return size; }

-static void exynos_plane_mode_set(struct exynos_drm_plane_state *exynos_state) +static void exynos_plane_mode_set(struct exynos_drm_plane_state *exynos_state, + const struct exynos_drm_plane_config *config)

{ struct drm_plane_state *state = &exynos_state->base; @@ -85,6 +87,9 @@ static void exynos_plane_mode_set(struct exynos_drm_plane_state *exynos_state) src_w = state->src_w >> 16; src_h = state->src_h >> 16;

+ exynos_plane_ipp_setup(exynos_state, config, &src_x, &src_y, &src_w, + &src_h, &crtc_w, &crtc_h); + /* set ratio */ exynos_state->h_ratio = (src_w << 16) / crtc_w; exynos_state->v_ratio = (src_h << 16) / crtc_h; @@ -163,6 +168,13 @@ static void exynos_drm_plane_destroy_state(struct drm_plane *plane, { struct exynos_drm_plane_state *old_exynos_state = to_exynos_plane_state(old_state); + struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane); + /* + * This is the only place in the code, where all temporary objects + * used for processing are no longer used and can be freed. + */ + exynos_plane_ipp_cleanup(exynos_plane, old_exynos_state); + __drm_atomic_helper_plane_destroy_state(plane, old_state); kfree(old_exynos_state); } @@ -174,6 +186,7 @@ static struct drm_plane_funcs exynos_plane_funcs = { .reset = exynos_drm_plane_reset, .atomic_duplicate_state = exynos_drm_plane_duplicate_state, .atomic_destroy_state = exynos_drm_plane_destroy_state, + .set_property = drm_atomic_helper_plane_set_property, };

static int @@ -218,16 +231,21 @@ static int exynos_plane_atomic_check(struct drm_plane *plane, return 0;

/* translate state into exynos_state */ - exynos_plane_mode_set(exynos_state); + exynos_plane_mode_set(exynos_state, exynos_plane->config);

ret = exynos_drm_plane_check_size(exynos_plane->config, exynos_state); - return ret; + if (ret) + return ret; + + return exynos_plane_ipp_check(exynos_plane, exynos_state); }

static void exynos_plane_atomic_update(struct drm_plane *plane, struct drm_plane_state *old_state) { struct drm_plane_state *state = plane->state; + struct exynos_drm_plane_state *exynos_state = + to_exynos_plane_state(state); struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(state->crtc); struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane);

@@ -237,6 +255,8 @@ static void exynos_plane_atomic_update(struct drm_plane *plane, plane->crtc = state->crtc; exynos_plane->pending_fb = state->fb;

+ exynos_plane_ipp_update(exynos_plane, exynos_state); + if (exynos_crtc->ops->update_plane) exynos_crtc->ops->update_plane(exynos_crtc, exynos_plane); } @@ -308,5 +328,5 @@ int exynos_plane_init(struct drm_device *dev, exynos_plane_attach_zpos_property(&exynos_plane->base, config->zpos);

- return 0; + return exynos_plane_ipp_init(dev, exynos_plane); } diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane_ipp.c b/drivers/gpu/drm/exynos/exynos_drm_plane_ipp.c new file mode 100644 index 000000000000..3086fd29f482 --- /dev/null +++ b/drivers/gpu/drm/exynos/exynos_drm_plane_ipp.c @@ -0,0 +1,369 @@ +/* + * Copyright (C) 2015 Samsung Electronics Co.Ltd + * Authors: Marek Szyprowski m.szyprowski@samsung.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include <drm/drmP.h> + +#include <drm/exynos_drm.h> +#include "exynos_drm_drv.h" +#include "exynos_drm_fb.h" +#include "exynos_drm_gem.h" +#include "exynos_drm_ipp.h" +#include "exynos_drm_plane.h" +#include "exynos_drm_plane_ipp.h" +#include "exynos_drm_iommu.h" + +static uint32_t preferred_formats[] = { + DRM_FORMAT_XRGB8888, + DRM_FORMAT_RGB565, + DRM_FORMAT_NV12, +}; + +static uint32_t supported_formats[] = { + DRM_FORMAT_RGB565, + DRM_FORMAT_XRGB8888, + DRM_FORMAT_YUYV, + DRM_FORMAT_YVYU, + DRM_FORMAT_UYVY, + DRM_FORMAT_VYUY, + DRM_FORMAT_NV12, + DRM_FORMAT_NV16, + DRM_FORMAT_NV21, + DRM_FORMAT_NV61, + DRM_FORMAT_YUV422, + DRM_FORMAT_YUV420, + DRM_FORMAT_YVU420, +}; + +static bool +exynos_plane_check_format(const struct exynos_drm_plane_config *config, + uint32_t format) +{ + int i; + + for (i = 0; i < config->num_pixel_formats; i++) + if (config->pixel_formats[i] == format) + return true; + return false; +} + +static struct drm_framebuffer *exynos_plane_ipp_alloc_fb(struct drm_device *dev, + struct exynos_drm_plane_state *state) +{ + struct exynos_drm_gem *exynos_gem[MAX_FB_BUFFER] = { NULL }; + struct drm_mode_fb_cmd2 mode_cmd = { 0 }; + struct drm_framebuffer *fb; + unsigned int size; + unsigned int flags; + int i, cpp; + int num_planes = drm_format_num_planes(state->ipp_pixel_format); + int ret = 0; + + + if (is_drm_iommu_supported(dev)) + flags = EXYNOS_BO_NONCONTIG | EXYNOS_BO_WC; + else + flags = EXYNOS_BO_CONTIG | EXYNOS_BO_WC; + + mode_cmd.width = state->ipp_dst.x + state->ipp_dst.w; + mode_cmd.height = state->ipp_dst.y + state->ipp_dst.h; + mode_cmd.pixel_format = state->ipp_pixel_format; + + for (i = 0; i < num_planes; i++) { + cpp = drm_format_plane_cpp(state->ipp_pixel_format, i); + mode_cmd.pitches[i] = roundup(mode_cmd.width, + EXYNOS_DRM_PITCH_ALIGN) * cpp; + mode_cmd.offsets[i] = 0; + size = mode_cmd.height * mode_cmd.pitches[i]; + exynos_gem[i] = exynos_drm_gem_create(dev, flags, size); + if (IS_ERR(exynos_gem[i])) { + ret = PTR_ERR(exynos_gem[i]); + goto err_free; + } + } + + fb = exynos_drm_framebuffer_init(dev, &mode_cmd, exynos_gem, num_planes); + if (IS_ERR(fb)) { + ret = PTR_ERR(fb); + goto err_free; + } + + return fb; + +err_free: + for (;i >= 0; i--) + exynos_drm_gem_destroy(exynos_gem[i]); + return ERR_PTR(ret); +} + +static bool exynos_plane_ipp_check_fb(struct drm_framebuffer *ipp_fb, + struct exynos_drm_plane_state *state) +{ + if (state->ipp_dst.x + state->ipp_dst.w <= ipp_fb->width && + state->ipp_dst.y + state->ipp_dst.h <= ipp_fb->height && + state->base.fb->pixel_format == ipp_fb->pixel_format) + return true; + return false; +} + +static int exynos_plane_ipp_transform(struct exynos_drm_plane_state *state) +{ + struct drm_framebuffer *src_fb = state->base.fb; + struct drm_framebuffer *dst_fb = state->ipp_fb; + struct drm_exynos_ipp_config src_config = { + .ops_id = EXYNOS_DRM_OPS_SRC, + .sz = { + .hsize = src_fb->pitches[0] / + drm_format_plane_cpp(src_fb->pixel_format, 0), + .vsize = src_fb->height, + }, + .fmt = src_fb->pixel_format, + .pos = { + .x = state->ipp_src.x, + .y = state->ipp_src.y, + .w = state->ipp_src.w, + .h = state->ipp_src.h, + }, + }; + struct drm_exynos_ipp_config dst_config = { + .sz = { + .hsize = dst_fb->pitches[0] / + drm_format_plane_cpp(dst_fb->pixel_format, 0), + .vsize = dst_fb->height, + }, + .fmt = dst_fb->pixel_format, + .pos = { + .x = state->ipp_dst.x, + .y = state->ipp_dst.y, + .w = state->ipp_dst.w, + .h = state->ipp_dst.h, + }, + }; + int degree = 0, flip = 0; + + if (state->rotation & BIT(DRM_ROTATE_180)) + degree = EXYNOS_DRM_DEGREE_180; + else if (state->rotation & BIT(DRM_ROTATE_90)) + degree = EXYNOS_DRM_DEGREE_90; + else if (state->rotation & BIT(DRM_ROTATE_270)) + degree = EXYNOS_DRM_DEGREE_270; + + if (state->rotation & BIT(DRM_REFLECT_X)) + flip |= EXYNOS_DRM_FLIP_HORIZONTAL; + if (state->rotation & BIT(DRM_REFLECT_Y)) + flip |= EXYNOS_DRM_FLIP_VERTICAL; + + dst_config.flip = flip; + dst_config.degree = degree; + + return exynos_ipp_process_internal(src_fb->dev, &src_config, src_fb, + &dst_config, dst_fb); +} + +void exynos_plane_ipp_setup(struct exynos_drm_plane_state *state, + const struct exynos_drm_plane_config *config, + unsigned int *src_x, unsigned int *src_y, + unsigned int *src_w, unsigned int *src_h, + unsigned int *crtc_w, unsigned int *crtc_h) +{ + int rotation = state->base.rotation; + int pre_x, pre_y, post_x, post_y; + int i; + bool supported_pixel_format = + exynos_plane_check_format(config, state->base.fb->pixel_format); + + state->rotation = rotation; + + /* check if ipp is really needed */ + if (rotation == BIT(DRM_ROTATE_0) && supported_pixel_format && + (*src_w == *crtc_w || + ((config->capabilities & EXYNOS_DRM_PLANE_CAP_DOUBLE) && + *src_w * 2 == *crtc_w) || + config->capabilities & EXYNOS_DRM_PLANE_CAP_SCALE) && + (*src_h == *crtc_h || + ((config->capabilities & EXYNOS_DRM_PLANE_CAP_DOUBLE) && + *src_h * 2 == *crtc_h) || + config->capabilities & EXYNOS_DRM_PLANE_CAP_SCALE)) + return; + + state->ipp_needed = true; + + state->ipp_pixel_format = state->base.fb->pixel_format; + if (!supported_pixel_format) { + for (i = 0; i < ARRAY_SIZE(preferred_formats); i++) + if (exynos_plane_check_format(config, + preferred_formats[i])) { + state->ipp_pixel_format = preferred_formats[i]; + break; + } + } + + state->ipp_src.x = rounddown(*src_x, EXYNOS_DRM_PITCH_ALIGN); + state->ipp_src.y = rounddown(*src_y, EXYNOS_DRM_PITCH_ALIGN); + state->ipp_dst.x = 0; + state->ipp_dst.y = 0; + + pre_x = *src_x & (EXYNOS_DRM_PITCH_ALIGN - 1); + pre_y = *src_y & (EXYNOS_DRM_PITCH_ALIGN - 1); + + state->ipp_src.w = roundup(*src_w + pre_x, EXYNOS_DRM_PITCH_ALIGN); + state->ipp_src.h = roundup(*src_h + pre_y, EXYNOS_DRM_PITCH_ALIGN); + if (state->ipp_src.w > state->base.fb->pitches[0]) + state->ipp_src.w = state->base.fb->pitches[0]; + if (state->ipp_src.h > state->base.fb->height) + state->ipp_src.h = state->base.fb->height; + + state->ipp_dst.w = state->ipp_src.w; + state->ipp_dst.h = state->ipp_src.h; + + post_x = state->ipp_src.w - pre_x - *src_w; + post_y = state->ipp_src.h - pre_y - *src_h; + + if (rotation & BIT(DRM_REFLECT_Y)) + swap(pre_y, post_y); + + if (rotation & BIT(DRM_REFLECT_X)) + swap(pre_x, post_x); + + switch (rotation & 0xf) { + case BIT(DRM_ROTATE_0): + *src_x = pre_x; + *src_y = pre_y; + break; + case BIT(DRM_ROTATE_90): + *src_x = post_y; + *src_y = pre_x; + swap(*src_w, *src_h); + swap(state->ipp_dst.w, state->ipp_dst.h); + break; + case BIT(DRM_ROTATE_180): + *src_x = post_x; + *src_y = post_y; + break; + case BIT(DRM_ROTATE_270): + *src_x = pre_y; + *src_y = post_x; + swap(*src_w, *src_h); + swap(state->ipp_dst.w, state->ipp_dst.h); + break; + } + + /* apply scalling */ + state->ipp_dst.w = state->ipp_dst.w * *crtc_w / *src_w; + state->ipp_dst.h = state->ipp_dst.h * *crtc_h / *src_h; + + *src_x = *src_x * *crtc_w / *src_w; + *src_y = *src_y * *crtc_h / *src_h; + *src_w = *crtc_w; + *src_h = *crtc_h; +} + +int exynos_plane_ipp_check(struct exynos_drm_plane *plane, + struct exynos_drm_plane_state *state) +{ + if (!state->ipp_needed) + return 0; + + /* check if currently allocated ipp fb can be reused */ + if (plane->ipp_next_fb && + !exynos_plane_ipp_check_fb(plane->ipp_next_fb, state)) { + drm_framebuffer_unreference(plane->ipp_next_fb); + plane->ipp_next_fb = NULL; + } + + /* allocate new ipp fb */ + if (!plane->ipp_next_fb) { + struct drm_framebuffer *ipp_fb; + + ipp_fb = exynos_plane_ipp_alloc_fb(plane->base.dev, state); + if (IS_ERR(ipp_fb)) + return PTR_ERR(ipp_fb); + plane->ipp_next_fb = ipp_fb; + } + + state->fb = state->ipp_fb = plane->ipp_next_fb; + + /* perform transformation */ + return exynos_plane_ipp_transform(state); +} + +void exynos_plane_ipp_update(struct exynos_drm_plane *plane, + struct exynos_drm_plane_state *state) +{ + if (!state->ipp_needed) + return; + + if (plane->ipp_next_fb) + swap(plane->ipp_next_fb, plane->ipp_cur_fb); +} + +void exynos_plane_ipp_cleanup(struct exynos_drm_plane *plane, + struct exynos_drm_plane_state *old_state) +{ + struct exynos_drm_plane_state *state; + + /* get current plane state */ + state = to_exynos_plane_state(plane->base.state); + + if (!state->ipp_needed) { + if (plane->ipp_cur_fb) { + drm_framebuffer_unreference(plane->ipp_cur_fb); + plane->ipp_cur_fb = NULL; + } + if (plane->ipp_next_fb) { + drm_framebuffer_unreference(plane->ipp_next_fb); + plane->ipp_next_fb = NULL; + } + } +} + +int exynos_plane_ipp_init(struct drm_device *dev, + struct exynos_drm_plane *plane) +{ + int i, j, num_formats, ipp_formats = 0; + uint32_t *formats; + + for (i = 0; i < ARRAY_SIZE(supported_formats); i++) + if (!exynos_plane_check_format(plane->config, + supported_formats[i])) + ipp_formats++; + + num_formats = plane->config->num_pixel_formats + ipp_formats; + formats = kmalloc_array(num_formats, sizeof(uint32_t), GFP_KERNEL); + if (!formats) + return -ENOMEM; + + memcpy(formats, plane->config->pixel_formats, + plane->config->num_pixel_formats * sizeof(uint32_t)); + j = plane->config->num_pixel_formats; + + for (i = 0; i < ARRAY_SIZE(supported_formats); i++) + if (!exynos_plane_check_format(plane->config, + supported_formats[i])) + formats[j++] = supported_formats[i]; + + kfree(plane->base.format_types); + plane->base.format_types = formats; + plane->base.format_count = num_formats; + + if (!dev->mode_config.rotation_property) + dev->mode_config.rotation_property = + drm_mode_create_rotation_property(dev, + BIT(DRM_ROTATE_0) | BIT(DRM_ROTATE_90) | + BIT(DRM_ROTATE_180) | BIT(DRM_ROTATE_270) | + BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y)); + + if (dev->mode_config.rotation_property) + drm_object_attach_property(&plane->base.base, + dev->mode_config.rotation_property, + BIT(DRM_ROTATE_0)); + + return 0; +} diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane_ipp.h b/drivers/gpu/drm/exynos/exynos_drm_plane_ipp.h new file mode 100644 index 000000000000..44b7f2c53829 --- /dev/null +++ b/drivers/gpu/drm/exynos/exynos_drm_plane_ipp.h @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2015 Samsung Electronics Co.Ltd + * Authors: Marek Szyprowski m.szyprowski@samsung.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef _EXYNOS_DRM_PLANE_IPP_H_ +#define _EXYNOS_DRM_PLANE_IPP_H_ + +#ifdef CONFIG_DRM_EXYNOS_PLANE_IPP + +void exynos_plane_ipp_setup(struct exynos_drm_plane_state *state, + const struct exynos_drm_plane_config *config, + unsigned int *src_x, unsigned int *src_y, + unsigned int *src_w, unsigned int *src_h, + unsigned int *crtc_w, unsigned int *crtc_h); + +int exynos_plane_ipp_check(struct exynos_drm_plane *plane, + struct exynos_drm_plane_state *state); + +void exynos_plane_ipp_update(struct exynos_drm_plane *plane, + struct exynos_drm_plane_state *state); + +void exynos_plane_ipp_cleanup(struct exynos_drm_plane *plane, + struct exynos_drm_plane_state *old_state); + +int exynos_plane_ipp_init(struct drm_device *dev, + struct exynos_drm_plane *plane); + +#else + +static inline +void exynos_plane_ipp_setup(struct exynos_drm_plane_state *state, + const struct exynos_drm_plane_config *config, + unsigned int *src_x, unsigned int *src_y, + unsigned int *src_w, unsigned int *src_h, + unsigned int *crtc_w, unsigned int *crtc_h) +{ +} + +static inline +int exynos_plane_ipp_check(struct exynos_drm_plane *plane, + struct exynos_drm_plane_state *state) +{ + return 0; +} + +static inline +void exynos_plane_ipp_update(struct exynos_drm_plane *plane, + struct exynos_drm_plane_state *state) +{ +} + +static inline +void exynos_plane_ipp_cleanup(struct exynos_drm_plane *plane, + struct exynos_drm_plane_state *old_state) +{ +} + +static inline +int exynos_plane_ipp_init(struct drm_device *dev, + struct exynos_drm_plane *plane) +{ + return 0; +} + +#endif +#endif