On Fri, 29 Oct 2021 at 15:30, Kalyan Thota quic_kalyant@quicinc.com wrote:

New required programming in CTL for SC7280. Group ID informs HW of which VM owns that CTL. Force this group ID to default/disabled until virtualization support is enabled in SW.

Changes in v1:

• Fix documentation and add descritpion for the change (Stephen)

Signed-off-by: Kalyan Thota quic_kalyant@quicinc.com

Reviewed-by: Dmitry Baryshkov dmitry.baryshkov@linaro.org

---

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 5 ++++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 8 ++++++++ 3 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index ce6f32a..283605c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -45,7 +45,7 @@ (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))

#define CTL_SC7280_MASK \

•   (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE))
  

•   (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | BIT(DPU_CTL_VM_CFG))
  
  

#define MERGE_3D_SM8150_MASK (0)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 4ade44b..31af04a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -179,13 +179,16 @@ enum {

/**

• CTL sub-blocks

• • @DPU_CTL_SPLIT_DISPLAY CTL supports video mode split display

• • @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display
• • @DPU_CTL_FETCH_ACTIVE: Active CTL for fetch HW (SSPPs)
• • @DPU_CTL_VM_CFG: CTL config to support multiple VMs
  • @DPU_CTL_MAX
  */

enum { DPU_CTL_SPLIT_DISPLAY = 0x1, DPU_CTL_ACTIVE_CFG, DPU_CTL_FETCH_ACTIVE,

•   DPU_CTL_VM_CFG,
    DPU_CTL_MAX
  

};

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index 64740ddb..02da9ec 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -36,6 +36,7 @@ #define MERGE_3D_IDX 23 #define INTF_IDX 31 #define CTL_INVALID_BIT 0xffff +#define CTL_DEFAULT_GROUP_ID 0xf

static const u32 fetch_tbl[SSPP_MAX] = {CTL_INVALID_BIT, 16, 17, 18, 19, CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, 0, @@ -498,6 +499,13 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, u32 intf_active = 0; u32 mode_sel = 0;

•   /* CTL_TOP[31:28] carries group_id to collate CTL paths
  

•    * per VM. Explicitly disable it until VM support is
  

•    * added in SW. Power on reset value is not disable.
  

•    */
  

•   if ((test_bit(DPU_CTL_VM_CFG, &ctx->caps->features)))
  

•           mode_sel = CTL_DEFAULT_GROUP_ID  << 28;
  

•   if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD)
            mode_sel |= BIT(17);
  
  

-- 2.7.4