--- radeon/radeon_surface.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index 874a092..499e994 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c @@ -154,7 +154,7 @@ static void surf_minify(struct radeon_surface *surf, surf->level[level].nblk_x = (surf->level[level].npix_x + surf->blk_w - 1) / surf->blk_w; surf->level[level].nblk_y = (surf->level[level].npix_y + surf->blk_h - 1) / surf->blk_h; surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1) / surf->blk_d; - if (surf->level[level].mode == RADEON_SURF_MODE_2D) { + if (surf->nsamples == 1 && surf->level[level].mode == RADEON_SURF_MODE_2D) { if (surf->level[level].nblk_x < xalign || surf->level[level].nblk_y < yalign) { surf->level[level].mode = RADEON_SURF_MODE_1D; return; @@ -382,6 +382,12 @@ static int r6_surface_init(struct radeon_surface_manager *surf_man, unsigned mode; int r;
+ /* MSAA surfaces support the 2D mode only. */ + if (surf->nsamples > 1) { + surf->flags = RADEON_SURF_CLR(surf->flags, MODE); + surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); + } + /* tiling mode */ mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
@@ -401,6 +407,10 @@ static int r6_surface_init(struct radeon_surface_manager *surf_man,
/* force 1d on kernel that can't do 2d */ if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) { + if (surf->nsamples > 1) { + fprintf(stderr, "radeon: Cannot use 2D tiling for an MSAA surface (%i).\n", __LINE__); + return -EFAULT; + } mode = RADEON_SURF_MODE_1D; surf->flags = RADEON_SURF_CLR(surf->flags, MODE); surf->flags |= RADEON_SURF_SET(mode, MODE); @@ -548,7 +558,7 @@ static void eg_surf_minify(struct radeon_surface *surf, surf->level[level].nblk_x = (surf->level[level].npix_x + surf->blk_w - 1) / surf->blk_w; surf->level[level].nblk_y = (surf->level[level].npix_y + surf->blk_h - 1) / surf->blk_h; surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1) / surf->blk_d; - if (surf->level[level].mode == RADEON_SURF_MODE_2D) { + if (surf->nsamples == 1 && surf->level[level].mode == RADEON_SURF_MODE_2D) { if (surf->level[level].nblk_x < mtilew || surf->level[level].nblk_y < mtileh) { surf->level[level].mode = RADEON_SURF_MODE_1D; return; @@ -687,6 +697,10 @@ static int eg_surface_sanity(struct radeon_surface_manager *surf_man,
/* force 1d on kernel that can't do 2d */ if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) { + if (surf->nsamples > 1) { + fprintf(stderr, "radeon: Cannot use 2D tiling for an MSAA surface (%i).\n", __LINE__); + return -EFAULT; + } mode = RADEON_SURF_MODE_1D; surf->flags = RADEON_SURF_CLR(surf->flags, MODE); surf->flags |= RADEON_SURF_SET(mode, MODE); @@ -754,6 +768,12 @@ static int eg_surface_init(struct radeon_surface_manager *surf_man, unsigned mode; int r;
+ /* MSAA surfaces support the 2D mode only. */ + if (surf->nsamples > 1) { + surf->flags = RADEON_SURF_CLR(surf->flags, MODE); + surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); + } + /* tiling mode */ mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
--- radeon/radeon_surface.c | 37 +++++++++++++++++++++++++++++++------ 1 file changed, 31 insertions(+), 6 deletions(-)
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index 499e994..892dca6 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c @@ -871,12 +871,37 @@ static int eg_surface_best(struct radeon_surface_manager *surf_man, return 0; }
- /* set tile split to row size, optimize latter for multi-sample surface - * tile split >= 256 for render buffer surface. Also depth surface want - * smaller value for optimal performances. - */ - surf->tile_split = surf_man->hw_info.row_size; - surf->stencil_tile_split = surf_man->hw_info.row_size / 2; + /* Tweak TILE_SPLIT for performance here. */ + if (surf->nsamples > 1) { + if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { + switch (surf->nsamples) { + case 2: + surf->tile_split = 128; + break; + case 4: + surf->tile_split = 128; + break; + case 8: + surf->tile_split = 256; + break; + case 16: /* cayman only */ + surf->tile_split = 512; + break; + default: + fprintf(stderr, "radeon: Wrong number of samples %i (%i)\n", + surf->nsamples, __LINE__); + return -EINVAL; + } + surf->stencil_tile_split = 64; + } else { + /* tile split must be >= 256 for colorbuffer surfaces */ + surf->tile_split = MAX2(surf->nsamples * surf->bpe * 64, 256); + } + } else { + /* set tile split to row size */ + surf->tile_split = surf_man->hw_info.row_size; + surf->stencil_tile_split = surf_man->hw_info.row_size / 2; + }
/* bankw or bankh greater than 1 increase alignment requirement, not * sure if it's worth using smaller bankw & bankh to stick with 2D
Reviewed-by: Jerome Glisse jglisse@redhat.com
On Thu, Aug 9, 2012 at 10:38 AM, Marek Olšák maraeo@gmail.com wrote:
radeon/radeon_surface.c | 37 +++++++++++++++++++++++++++++++------ 1 file changed, 31 insertions(+), 6 deletions(-)
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index 499e994..892dca6 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c @@ -871,12 +871,37 @@ static int eg_surface_best(struct radeon_surface_manager *surf_man, return 0; }
- /* set tile split to row size, optimize latter for multi-sample surface
* tile split >= 256 for render buffer surface. Also depth surface want* smaller value for optimal performances.*/- surf->tile_split = surf_man->hw_info.row_size;
- surf->stencil_tile_split = surf_man->hw_info.row_size / 2;
/* Tweak TILE_SPLIT for performance here. */
if (surf->nsamples > 1) {
if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {switch (surf->nsamples) {case 2:surf->tile_split = 128;break;case 4:surf->tile_split = 128;break;case 8:surf->tile_split = 256;break;case 16: /* cayman only */surf->tile_split = 512;break;default:fprintf(stderr, "radeon: Wrong number of samples %i (%i)\n",surf->nsamples, __LINE__);return -EINVAL;}surf->stencil_tile_split = 64;} else {/* tile split must be >= 256 for colorbuffer surfaces */surf->tile_split = MAX2(surf->nsamples * surf->bpe * 64, 256);}} else {
/* set tile split to row size */surf->tile_split = surf_man->hw_info.row_size;surf->stencil_tile_split = surf_man->hw_info.row_size / 2;}
/* bankw or bankh greater than 1 increase alignment requirement, not
- sure if it's worth using smaller bankw & bankh to stick with 2D
-- 1.7.9.5
dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
On Thu, Aug 9, 2012 at 10:37 AM, Marek Olšák maraeo@gmail.com wrote:
Reviewed-by: Jerome Glisse jglisse@redhat.com
radeon/radeon_surface.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index 874a092..499e994 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c @@ -154,7 +154,7 @@ static void surf_minify(struct radeon_surface *surf, surf->level[level].nblk_x = (surf->level[level].npix_x + surf->blk_w - 1) / surf->blk_w; surf->level[level].nblk_y = (surf->level[level].npix_y + surf->blk_h - 1) / surf->blk_h; surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1) / surf->blk_d;
- if (surf->level[level].mode == RADEON_SURF_MODE_2D) {
- if (surf->nsamples == 1 && surf->level[level].mode == RADEON_SURF_MODE_2D) { if (surf->level[level].nblk_x < xalign || surf->level[level].nblk_y < yalign) { surf->level[level].mode = RADEON_SURF_MODE_1D; return;
@@ -382,6 +382,12 @@ static int r6_surface_init(struct radeon_surface_manager *surf_man, unsigned mode; int r;
- /* MSAA surfaces support the 2D mode only. */
- if (surf->nsamples > 1) {
surf->flags = RADEON_SURF_CLR(surf->flags, MODE);surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);- }
- /* tiling mode */ mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
@@ -401,6 +407,10 @@ static int r6_surface_init(struct radeon_surface_manager *surf_man,
/* force 1d on kernel that can't do 2d */ if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) {
if (surf->nsamples > 1) {fprintf(stderr, "radeon: Cannot use 2D tiling for an MSAA surface (%i).\n", __LINE__);return -EFAULT;} mode = RADEON_SURF_MODE_1D; surf->flags = RADEON_SURF_CLR(surf->flags, MODE); surf->flags |= RADEON_SURF_SET(mode, MODE);@@ -548,7 +558,7 @@ static void eg_surf_minify(struct radeon_surface *surf, surf->level[level].nblk_x = (surf->level[level].npix_x + surf->blk_w - 1) / surf->blk_w; surf->level[level].nblk_y = (surf->level[level].npix_y + surf->blk_h - 1) / surf->blk_h; surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1) / surf->blk_d;
- if (surf->level[level].mode == RADEON_SURF_MODE_2D) {
- if (surf->nsamples == 1 && surf->level[level].mode == RADEON_SURF_MODE_2D) { if (surf->level[level].nblk_x < mtilew || surf->level[level].nblk_y < mtileh) { surf->level[level].mode = RADEON_SURF_MODE_1D; return;
@@ -687,6 +697,10 @@ static int eg_surface_sanity(struct radeon_surface_manager *surf_man,
/* force 1d on kernel that can't do 2d */ if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) {
if (surf->nsamples > 1) {fprintf(stderr, "radeon: Cannot use 2D tiling for an MSAA surface (%i).\n", __LINE__);return -EFAULT;} mode = RADEON_SURF_MODE_1D; surf->flags = RADEON_SURF_CLR(surf->flags, MODE); surf->flags |= RADEON_SURF_SET(mode, MODE);@@ -754,6 +768,12 @@ static int eg_surface_init(struct radeon_surface_manager *surf_man, unsigned mode; int r;
- /* MSAA surfaces support the 2D mode only. */
- if (surf->nsamples > 1) {
surf->flags = RADEON_SURF_CLR(surf->flags, MODE);surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);- }
- /* tiling mode */ mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
-- 1.7.9.5
dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
Dear Marek,
Am Donnerstag, den 09.08.2012, 16:37 +0200 schrieb Marek Olšák:
radeon/radeon_surface.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-)
[…]
do you have some numbers indicating an improvement with this change? On what hardware did you test?
Thanks,
Paul
On Thu, Aug 9, 2012 at 5:41 PM, Paul Menzel paulepanter@users.sourceforge.net wrote:
Dear Marek,
Am Donnerstag, den 09.08.2012, 16:37 +0200 schrieb Marek Olšák:
radeon/radeon_surface.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-)
[…]
do you have some numbers indicating an improvement with this change? On what hardware did you test?
I wasn't measuring performance. This patch is actually a fix, because AFAIK 2D tiling is the only mode available for MSAA surfaces. The other tiling modes hang my GPU.
Marek
On Thu, Aug 9, 2012 at 12:14 PM, Marek Olšák maraeo@gmail.com wrote:
On Thu, Aug 9, 2012 at 5:41 PM, Paul Menzel paulepanter@users.sourceforge.net wrote:
Dear Marek,
Am Donnerstag, den 09.08.2012, 16:37 +0200 schrieb Marek Olšák:
radeon/radeon_surface.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-)
[…]
do you have some numbers indicating an improvement with this change? On what hardware did you test?
I wasn't measuring performance. This patch is actually a fix, because AFAIK 2D tiling is the only mode available for MSAA surfaces. The other tiling modes hang my GPU.
AA surfaces can't use linear or 1D tiling modes. They have to be 2D. Resolve targets can use other tiling modes however.
Alex
dri-devel@lists.freedesktop.org
-
Alex Deucher -
Jerome Glisse -
Marek Olšák -
Paul Menzel