Signed-off-by: Denis Carikli denis@eukrea.com Acked-by: Philipp Zabel p.zabel@pengutronix.de --- ChangeLog v9->v13: - Rebased ChangeLog v8->v9: - Rebased. - Added Philipp Zabel's ack. - Shortened the patch title.

ChangeLog v8->v9: - Removed the Cc. They are now set in git-send-email directly. - Rebased.

ChangeLog v7->v8: - Shrinked even more the Cc list.

ChangeLog v6->v7: - Shrinked even more the Cc list.

ChangeLog v5->v6: - Remove people not concerned by this patch from the Cc list.

ChangeLog v3->v5: - Use the correct RGB order.

ChangeLog v2->v3: - Added some interested people in the Cc list. - Removed the commit message long desciption that was just a copy of the short description. - Rebased the patch. - Fixed a copy-paste error in the ipu_dc_map_clear parameter. --- .../bindings/staging/imx-drm/fsl-imx-drm.txt | 4 ++-- drivers/staging/imx-drm/ipu-v3/ipu-dc.c | 9 +++++++++ drivers/staging/imx-drm/parallel-display.c | 2 ++ 3 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt b/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt index e75f0e5..c0eb95a 100644 --- a/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt +++ b/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt @@ -60,8 +60,8 @@ Required properties: - compatible: Should be "fsl,imx-parallel-display" Optional properties: - interface_pix_fmt: How this display is connected to the - display interface. Currently supported types: "rgb24", "rgb565", "bgr666" - and "lvds666". + display interface. Currently supported types: "rgb24", "rgb565", "bgr666", + "rgb666" and "lvds666". - edid: verbatim EDID data block describing attached display. - ddc: phandle describing the i2c bus handling the display data channel diff --git a/drivers/staging/imx-drm/ipu-v3/ipu-dc.c b/drivers/staging/imx-drm/ipu-v3/ipu-dc.c index 784a4a1..9d0324d 100644 --- a/drivers/staging/imx-drm/ipu-v3/ipu-dc.c +++ b/drivers/staging/imx-drm/ipu-v3/ipu-dc.c @@ -94,6 +94,7 @@ enum ipu_dc_map { IPU_DC_MAP_BGR666, IPU_DC_MAP_LVDS666, IPU_DC_MAP_BGR24, + IPU_DC_MAP_RGB666, };

struct ipu_dc { @@ -162,6 +163,8 @@ static int ipu_pixfmt_to_map(u32 fmt) return IPU_DC_MAP_LVDS666; case V4L2_PIX_FMT_BGR24: return IPU_DC_MAP_BGR24; + case V4L2_PIX_FMT_RGB666: + return IPU_DC_MAP_RGB666; default: return -EINVAL; } @@ -453,6 +456,12 @@ int ipu_dc_init(struct ipu_soc *ipu, struct device *dev, ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 1, 15, 0xff); /* green */ ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 0, 23, 0xff); /* blue */

+ /* rgb666 */ + ipu_dc_map_clear(priv, IPU_DC_MAP_RGB666); + ipu_dc_map_config(priv, IPU_DC_MAP_RGB666, 0, 5, 0xfc); /* blue */ + ipu_dc_map_config(priv, IPU_DC_MAP_RGB666, 1, 11, 0xfc); /* green */ + ipu_dc_map_config(priv, IPU_DC_MAP_RGB666, 2, 17, 0xfc); /* red */ + return 0; }

diff --git a/drivers/staging/imx-drm/parallel-display.c b/drivers/staging/imx-drm/parallel-display.c index b567832..64b34336 100644 --- a/drivers/staging/imx-drm/parallel-display.c +++ b/drivers/staging/imx-drm/parallel-display.c @@ -218,6 +218,8 @@ static int imx_pd_bind(struct device *dev, struct device *master, void *data) imxpd->interface_pix_fmt = V4L2_PIX_FMT_RGB565; else if (!strcmp(fmt, "bgr666")) imxpd->interface_pix_fmt = V4L2_PIX_FMT_BGR666; + else if (!strcmp(fmt, "rgb666")) + imxpd->interface_pix_fmt = V4L2_PIX_FMT_RGB666; else if (!strcmp(fmt, "lvds666")) imxpd->interface_pix_fmt = v4l2_fourcc('L', 'V', 'D', '6'); }

Signed-off-by: Denis Carikli denis@eukrea.com --- ChangeLog 12->v13: - No changes ChangeLog 11->v12: - Improved the define names to match the hardware: ENABLE_POL is not a clock signal but instead an enable signal.

ChangeLog v9->v10: - New patch which was splitted out from: "staging: imx-drm: Use de-active and pixelclk-active display-timings.". - Fixes many issues in "staging: imx-drm: Use de-active and pixelclk-active display-timings.": - More clear meaning of the polarity settings. - The SET_CLK_POL and SET_DE_POL masks are not needed anymore. --- drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.h | 8 +++++++- drivers/staging/imx-drm/ipu-v3/ipu-di.c | 4 ++-- drivers/staging/imx-drm/ipuv3-crtc.c | 4 ++-- 3 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.h b/drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.h index c2c6fab..015e3bf 100644 --- a/drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.h +++ b/drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.h @@ -27,6 +27,12 @@ enum ipuv3_type {

#define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3')

+#define CLK_POL_NEGEDGE 0 +#define CLK_POL_POSEDGE 1 + +#define ENABLE_POL_LOW 0 +#define ENABLE_POL_HIGH 1 + /* * Bitfield of Display Interface signal polarities. */ @@ -37,7 +43,7 @@ struct ipu_di_signal_cfg { unsigned clksel_en:1; unsigned clkidle_en:1; unsigned data_pol:1; /* true = inverted */ - unsigned clk_pol:1; /* true = rising edge */ + unsigned clk_pol:1; unsigned enable_pol:1; unsigned Hsync_pol:1; /* true = active high */ unsigned Vsync_pol:1; diff --git a/drivers/staging/imx-drm/ipu-v3/ipu-di.c b/drivers/staging/imx-drm/ipu-v3/ipu-di.c index 849b3e1..0ce3f52 100644 --- a/drivers/staging/imx-drm/ipu-v3/ipu-di.c +++ b/drivers/staging/imx-drm/ipu-v3/ipu-di.c @@ -595,7 +595,7 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig) } }

- if (sig->clk_pol) + if (sig->clk_pol == CLK_POL_POSEDGE) di_gen |= DI_GEN_POLARITY_DISP_CLK;

ipu_di_write(di, di_gen, DI_GENERAL); @@ -606,7 +606,7 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig) reg = ipu_di_read(di, DI_POL); reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15);

- if (sig->enable_pol) + if (sig->enable_pol == ENABLE_POL_HIGH) reg |= DI_POL_DRDY_POLARITY_15; if (sig->data_pol) reg |= DI_POL_DRDY_DATA_POLARITY; diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c b/drivers/staging/imx-drm/ipuv3-crtc.c index 47bec5e..ba9eea3 100644 --- a/drivers/staging/imx-drm/ipuv3-crtc.c +++ b/drivers/staging/imx-drm/ipuv3-crtc.c @@ -165,8 +165,8 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc, if (mode->flags & DRM_MODE_FLAG_PVSYNC) sig_cfg.Vsync_pol = 1;

- sig_cfg.enable_pol = 1; - sig_cfg.clk_pol = 0; + sig_cfg.enable_pol = ENABLE_POL_HIGH; + sig_cfg.clk_pol = CLK_POL_NEGEDGE; sig_cfg.width = mode->hdisplay; sig_cfg.height = mode->vdisplay; sig_cfg.pixel_fmt = out_pixel_fmt;

We need a way to pass signal polarity informations between DRM panels, and the display drivers.

To do that, a pol_flags field was added to drm_display_mode.

Signed-off-by: Denis Carikli denis@eukrea.com --- ChangeLog v12->v13: - Added Docbook documentation for pol_flags the struct field. - Removed the _PRESERVE defines: it was used by patches against the imx_drm driver. Now theses patches have been adapted not to require that defines. ChangeLog v11->v12: - Rebased: This patch now applies against drm_modes.h - Rebased: It now uses the new DRM_MODE_FLAG_POL_DE flags defines names

ChangeLog v10->v11: - Since the imx-drm won't be able to retrive its regulators from the device tree when using display-timings nodes, and that I was told that the drm simple-panel driver already supported that, I then, instead, added what was lacking to make the eukrea displays work with the drm-simple-panel driver.

That required a way to get back the display polarity informations from the imx-drm driver without affecting userspace. --- Documentation/DocBook/drm.tmpl | 30 ++++++++++++++++++++++++++++++ include/drm/drm_modes.h | 6 ++++++ 2 files changed, 36 insertions(+)

diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl index c526d81..29c0e5a 100644 --- a/Documentation/DocBook/drm.tmpl +++ b/Documentation/DocBook/drm.tmpl @@ -2292,6 +2292,36 @@ void intel_crt_init(struct drm_device *dev) and <structfield>height_mm</structfield> fields are only used internally during EDID parsing and should not be set when creating modes manually. </para> + <para> + The <structfield>pol_flags</structfield> value represents the display + signal polarity flags, it can be a combination of + <variablelist> + <varlistentry> + <term>DRM_MODE_FLAG_POL_PIXDATA_NEGEDGE</term> + <listitem><para> + drive pixel data on falling edge, sample data on rising edge. + </para></listitem> + </varlistentry> + <varlistentry> + <term>DRM_MODE_FLAG_POL_PIXDATA_POSEDGE</term> + <listitem><para> + Drive pixel data on rising edge, sample data on falling edge. + </para></listitem> + </varlistentry> + <varlistentry> + <term>DRM_MODE_FLAG_POL_DE_LOW</term> + <listitem><para> + data-enable pulse is active low + </para></listitem> + </varlistentry> + <varlistentry> + <term>DRM_MODE_FLAG_POL_DE_HIGH</term> + <listitem><para> + data-enable pulse is active low + </para></listitem> + </varlistentry> + </variablelist> + </para> </listitem> <listitem> <synopsis>int (*mode_valid)(struct drm_connector *connector, diff --git a/include/drm/drm_modes.h b/include/drm/drm_modes.h index 91d0582..c5cbe31 100644 --- a/include/drm/drm_modes.h +++ b/include/drm/drm_modes.h @@ -93,6 +93,11 @@ enum drm_mode_status {

#define DRM_MODE_FLAG_3D_MAX DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF

+#define DRM_MODE_FLAG_POL_PIXDATA_NEGEDGE BIT(1) +#define DRM_MODE_FLAG_POL_PIXDATA_POSEDGE BIT(2) +#define DRM_MODE_FLAG_POL_DE_LOW BIT(3) +#define DRM_MODE_FLAG_POL_DE_HIGH BIT(4) + struct drm_display_mode { /* Header */ struct list_head head; @@ -144,6 +149,7 @@ struct drm_display_mode { int vrefresh; /* in Hz */ int hsync; /* in kHz */ enum hdmi_picture_aspect picture_aspect_ratio; + unsigned int pol_flags; };

/* mode specified on the command line */

The previous hardware behaviour was kept if the flags are not set.

Signed-off-by: Denis Carikli denis@eukrea.com --- ChangeLog v12->v13: - This patch doesn't need the DRM_MODE_FLAG_POL_*_PRESERVE flags anymore. - code cleanup to improve readability: - ENABLE_POL_PRESERVE is now gone - Less modifications in ipu_di_init_sync_panel - more readable modifications in int ipu_crtc_mode_set ChangeLog v11->v12: - Rebased: It now uses the following new flags defines names: CLK_POL, ENABLE_POL - The inversions in ipuv3-crtc.c are now fixed. - ipuv3-crtc.c was still using mode->private_flags from the previous versions of this patchset, that's now fixed.

ChangeLog v10->v11: - This patch was splitted-out and adapted from: "Prepare imx-drm for extra display-timings retrival." - The display-timings dt specific part was removed. - The flags names were changed to use the DRM ones from: "drm: drm_display_mode: add signal polarity flags" --- drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.h | 4 ++-- drivers/staging/imx-drm/ipu-v3/ipu-di.c | 2 ++ drivers/staging/imx-drm/ipuv3-crtc.c | 18 ++++++++++++++++-- 3 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.h b/drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.h index 015e3bf..94b0d8e 100644 --- a/drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.h +++ b/drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.h @@ -43,10 +43,10 @@ struct ipu_di_signal_cfg { unsigned clksel_en:1; unsigned clkidle_en:1; unsigned data_pol:1; /* true = inverted */ - unsigned clk_pol:1; - unsigned enable_pol:1; unsigned Hsync_pol:1; /* true = active high */ unsigned Vsync_pol:1; + u8 clk_pol; + u8 enable_pol;

u16 width; u16 height; diff --git a/drivers/staging/imx-drm/ipu-v3/ipu-di.c b/drivers/staging/imx-drm/ipu-v3/ipu-di.c index 0ce3f52..faf08e2 100644 --- a/drivers/staging/imx-drm/ipu-v3/ipu-di.c +++ b/drivers/staging/imx-drm/ipu-v3/ipu-di.c @@ -597,6 +597,8 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)

if (sig->clk_pol == CLK_POL_POSEDGE) di_gen |= DI_GEN_POLARITY_DISP_CLK; + else if (sig->clk_pol == CLK_POL_NEGEDGE) + di_gen &= ~DI_GEN_POLARITY_DISP_CLK;

ipu_di_write(di, di_gen, DI_GENERAL);

diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c b/drivers/staging/imx-drm/ipuv3-crtc.c index ba9eea3..10b46b5 100644 --- a/drivers/staging/imx-drm/ipuv3-crtc.c +++ b/drivers/staging/imx-drm/ipuv3-crtc.c @@ -165,8 +165,22 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc, if (mode->flags & DRM_MODE_FLAG_PVSYNC) sig_cfg.Vsync_pol = 1;

- sig_cfg.enable_pol = ENABLE_POL_HIGH; - sig_cfg.clk_pol = CLK_POL_NEGEDGE; + if (mode->pol_flags & DRM_MODE_FLAG_POL_PIXDATA_POSEDGE) + sig_cfg.clk_pol = CLK_POL_POSEDGE; + else if (mode->pol_flags & DRM_MODE_FLAG_POL_PIXDATA_NEGEDGE) + sig_cfg.clk_pol = CLK_POL_NEGEDGE; + else + /* If no PIXDATA flags were set, keep the old behaviour */ + sig_cfg.clk_pol = CLK_POL_NEGEDGE; + + if (mode->pol_flags & DRM_MODE_FLAG_POL_DE_HIGH) + sig_cfg.enable_pol = ENABLE_POL_HIGH; + else if (mode->pol_flags & DRM_MODE_FLAG_POL_DE_LOW) + sig_cfg.enable_pol = ENABLE_POL_LOW; + else + /* If no DE flags were set, keep the old behaviour */ + sig_cfg.enable_pol = ENABLE_POL_HIGH; + sig_cfg.width = mode->hdisplay; sig_cfg.height = mode->vdisplay; sig_cfg.pixel_fmt = out_pixel_fmt;

The CMO-QVGA, DVI-SVGA and DVI-VGA are added.

Signed-off-by: Denis Carikli denis@eukrea.com --- ChangeLog v10->v13: - Rebased - Removed enable-active-high in reg_lcd_3v3: its GPIO already has the GPIO_ACTIVE_HIGH flag. Without this removal, the display was off at boot and powering it off and on was necessary to get an image on it after the boot.

ChangeLog v10->v11: - Now uses the drm-panel instead of the display-timings. This is to get regulator support, which is lacking in the imx-drm driver when using the display-timings.

ChangeLog v9->v10: - Rebased - Now enables the cmo-qvga regulator at boot.

ChangeLog v8->v9: - Removed the Cc. They are now set in git-send-email directly. - updated pixelclk-active after the following patch: "imx-drm: Match ipu_di_signal_cfg's clk_pol with its description."

ChangeLog v7->v8: - Rebased the patch: added the now required imx-drm node. - Adapted the svga clock-frequency value in order to still be able to display an image after the following commit: "imx-drm: ipu-v3: more inteligent DI clock selection"

ChangeLog v6->v7: - Shrinked even more the Cc list. - Since the pingrp headers were removed, the references to it where replaced by the actual pins. - Added the targets to arch/arm/boot/dts/Makefile

ChangeLog v5->v6: - Reordered the Cc list.

ChangeLog v3->v5: - Updated to new GPIO defines. - Updated to new licenses checkpatch requirements. - one whitespace cleanup.

ChangeLog v2->v3: - Splitted out from the patch that added support for the cpuimx51/mbimxsd51 boards. - This patch now only adds display support. - Added some interested people in the Cc list, and removed some people that might be annoyed by the receiving of that patch which is unrelated to their subsystem. - rebased and reworked the dts displays addition. - Also rebased and reworked the fsl,pins usage. --- arch/arm/boot/dts/Makefile | 3 ++ .../imx51-eukrea-mbimxsd51-baseboard-cmo-qvga.dts | 40 ++++++++++++++++ .../imx51-eukrea-mbimxsd51-baseboard-dvi-svga.dts | 28 +++++++++++ .../imx51-eukrea-mbimxsd51-baseboard-dvi-vga.dts | 28 +++++++++++ .../boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts | 49 ++++++++++++++++++++ 5 files changed, 148 insertions(+) create mode 100644 arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-cmo-qvga.dts create mode 100644 arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-dvi-svga.dts create mode 100644 arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-dvi-vga.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0f1e8be..f0ec7b7 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -177,6 +177,9 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx51-babbage.dtb \ imx51-digi-connectcore-jsk.dtb \ imx51-eukrea-mbimxsd51-baseboard.dtb \ + imx51-eukrea-mbimxsd51-baseboard-cmo-qvga.dtb \ + imx51-eukrea-mbimxsd51-baseboard-dvi-svga.dtb \ + imx51-eukrea-mbimxsd51-baseboard-dvi-vga.dtb \ imx53-ard.dtb \ imx53-m53evk.dtb \ imx53-mba53.dtb \ diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-cmo-qvga.dts b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-cmo-qvga.dts new file mode 100644 index 0000000..d273d09 --- /dev/null +++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-cmo-qvga.dts @@ -0,0 +1,40 @@ +/* + * Copyright 2013 Eukréa Electromatique denis@eukrea.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx51-eukrea-mbimxsd51-baseboard.dts" + +/ { + model = "Eukrea MBIMXSD51 with the CMO-QVGA Display"; + compatible = "eukrea,mbimxsd51-baseboard-cmo-qvga", "eukrea,mbimxsd51-baseboard", "eukrea,cpuimx51", "fsl,imx51"; + + panel: panel { + compatible = "eukrea,mbimxsd51-cmo-qvga", "simple-panel"; + power-supply = <&reg_lcd_3v3>; + }; + + reg_lcd_3v3: lcd-en { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_lcd_3v3>; + regulator-name = "lcd-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + }; +}; + +&display { + status = "okay"; + fsl,panel = <&panel>; +}; diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-dvi-svga.dts b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-dvi-svga.dts new file mode 100644 index 0000000..323ebf4 --- /dev/null +++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-dvi-svga.dts @@ -0,0 +1,28 @@ +/* + * Copyright 2013 Eukréa Electromatique denis@eukrea.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx51-eukrea-mbimxsd51-baseboard.dts" + +/ { + model = "Eukrea MBIMXSD51 with the DVI-SVGA Display"; + compatible = "eukrea,mbimxsd51-baseboard-dvi-svga", "eukrea,mbimxsd51-baseboard", "eukrea,cpuimx51", "fsl,imx51"; + + panel: panel { + compatible = "eukrea,mbimxsd51-dvi-svga", "simple-panel"; + }; +}; + +&display { + status = "okay"; + fsl,panel = <&panel>; +}; diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-dvi-vga.dts b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-dvi-vga.dts new file mode 100644 index 0000000..f065500 --- /dev/null +++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-dvi-vga.dts @@ -0,0 +1,28 @@ +/* + * Copyright 2013 Eukréa Electromatique denis@eukrea.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx51-eukrea-mbimxsd51-baseboard.dts" + +/ { + model = "Eukrea MBIMXSD51 with the DVI-VGA Display"; + compatible = "eukrea,mbimxsd51-baseboard-dvi-vga", "eukrea,mbimxsd51-baseboard", "eukrea,cpuimx51", "fsl,imx51"; + + panel: panel { + compatible = "eukrea,mbimxsd51-dvi-vga", "simple-panel"; + }; +}; + +&display { + status = "okay"; + fsl,panel = <&panel>; +}; diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts index 75e66c9..02ff24a 100644 --- a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts +++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts @@ -32,6 +32,20 @@ }; };

+ display: display@di0 { + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "rgb666"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp1>; + status = "disabled"; + + port { + display0_in: endpoint { + remote-endpoint = <&ipu_di0_disp0>; + }; + }; + }; + gpio_keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -222,6 +236,37 @@ >; };

+ pinctrl_ipu_disp1: ipudisp1grp { + fsl,pins = < + MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 + MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 + MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 + MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 + MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 + MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 + MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 + MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 + MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 + MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 + MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 + MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 + MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 + MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 + MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 + MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 + MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 + MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 + MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 + MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 + MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 + MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 + MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 + MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 + MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 + MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 + >; + }; + pinctrl_reg_lcd_3v3: reg_lcd_3v3 { fsl,pins = < MX51_PAD_CSI1_D9__GPIO3_13 0x1f5 @@ -253,6 +298,10 @@ }; };

+&ipu_di0_disp0 { + remote-endpoint = <&display0_in>; +}; + &ssi2 { codec-handle = <&tlv320aic23>; fsl,mode = "i2s-slave";