Soft reset the display subsystem controller on startup and wait for the reset to complete. This helps the scenario where display was already in use by some other core before the linux was booted.
Signed-off-by: Devarsh Thakkar devarsht@ti.com --- drivers/gpu/drm/tidss/tidss_dispc.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c index 60b92df615aa..dae47853b728 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -2650,6 +2650,20 @@ static void dispc_init_errata(struct dispc_device *dispc) } }
+static void dispc_softreset(struct dispc_device *dispc) +{ + u32 val; + int ret = 0; + + /* Soft reset */ + REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, 1, 1); + /* Wait for reset to complete */ + ret = readl_poll_timeout(dispc->base_common + DSS_SYSSTATUS, + val, val & 1, 100, 5000); + if (ret) + dev_warn(dispc->dev, "failed to reset dispc\n"); +} + int dispc_init(struct tidss_device *tidss) { struct device *dev = tidss->dev; @@ -2709,6 +2723,10 @@ int dispc_init(struct tidss_device *tidss) return r; }
+ /* K2G display controller does not support soft reset */ + if (feat->subrev != DISPC_K2G) + dispc_softreset(dispc); + for (i = 0; i < dispc->feat->num_vps; i++) { u32 gamma_size = dispc->feat->vp_feat.color.gamma_size; u32 *gamma_table;
Hi Laurent, Tomi,
On 14/03/22 17:07, Devarsh Thakkar wrote:
Soft reset the display subsystem controller on startup and wait for the reset to complete. This helps the scenario where display was already in use by some other core before the linux was booted.
Could you please help review this patch ?
Regards,
Devarsh
Signed-off-by: Devarsh Thakkar devarsht@ti.com
drivers/gpu/drm/tidss/tidss_dispc.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c index 60b92df615aa..dae47853b728 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -2650,6 +2650,20 @@ static void dispc_init_errata(struct dispc_device *dispc) } }
+static void dispc_softreset(struct dispc_device *dispc) +{
- u32 val;
- int ret = 0;
- /* Soft reset */
- REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, 1, 1);
- /* Wait for reset to complete */
- ret = readl_poll_timeout(dispc->base_common + DSS_SYSSTATUS,
val, val & 1, 100, 5000);- if (ret)
dev_warn(dispc->dev, "failed to reset dispc\n");+}
int dispc_init(struct tidss_device *tidss) { struct device *dev = tidss->dev; @@ -2709,6 +2723,10 @@ int dispc_init(struct tidss_device *tidss) return r; }
- /* K2G display controller does not support soft reset */
- if (feat->subrev != DISPC_K2G)
dispc_softreset(dispc);- for (i = 0; i < dispc->feat->num_vps; i++) { u32 gamma_size = dispc->feat->vp_feat.color.gamma_size; u32 *gamma_table;
Hi,
On 14/03/2022 13:37, Devarsh Thakkar wrote:
Soft reset the display subsystem controller on startup and wait for the reset to complete. This helps the scenario where display was already in use by some other core before the linux was booted.
The reason the omapdrm doesn't do a reset is that the PM features on some of the DSS registers were set and controlled outside dss driver, so the dss driver could not do a reset just like that. That design was carried to the tidss driver, although I'm not sure if the reason is valid on AM6 and J7 platforms.
If that reasoning is not valid, this patch is ok and:
Reviewed-by: Tomi Valkeinen tomi.valkeinen@ideasonboard.com
Tomi
Signed-off-by: Devarsh Thakkar devarsht@ti.com
drivers/gpu/drm/tidss/tidss_dispc.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c index 60b92df615aa..dae47853b728 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -2650,6 +2650,20 @@ static void dispc_init_errata(struct dispc_device *dispc) } }
+static void dispc_softreset(struct dispc_device *dispc) +{
- u32 val;
- int ret = 0;
- /* Soft reset */
- REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, 1, 1);
- /* Wait for reset to complete */
- ret = readl_poll_timeout(dispc->base_common + DSS_SYSSTATUS,
val, val & 1, 100, 5000);- if (ret)
dev_warn(dispc->dev, "failed to reset dispc\n");+}
- int dispc_init(struct tidss_device *tidss) { struct device *dev = tidss->dev;
@@ -2709,6 +2723,10 @@ int dispc_init(struct tidss_device *tidss) return r; }
- /* K2G display controller does not support soft reset */
- if (feat->subrev != DISPC_K2G)
dispc_softreset(dispc);- for (i = 0; i < dispc->feat->num_vps; i++) { u32 gamma_size = dispc->feat->vp_feat.color.gamma_size; u32 *gamma_table;
On 17:24-20220412, Tomi Valkeinen wrote:
Hi,
On 14/03/2022 13:37, Devarsh Thakkar wrote:
Soft reset the display subsystem controller on startup and wait for the reset to complete. This helps the scenario where display was already in use by some other core before the linux was booted.
The reason the omapdrm doesn't do a reset is that the PM features on some of the DSS registers were set and controlled outside dss driver, so the dss driver could not do a reset just like that. That design was carried to the tidss driver, although I'm not sure if the reason is valid on AM6 and J7 platforms.
If that reasoning is not valid, this patch is ok and:
Reviewed-by: Tomi Valkeinen tomi.valkeinen@ideasonboard.com
Tony - sysc control for older omap devices still control this directly?
* Nishanth Menon nm@ti.com [220412 21:18]:
On 17:24-20220412, Tomi Valkeinen wrote:
Hi,
On 14/03/2022 13:37, Devarsh Thakkar wrote:
Soft reset the display subsystem controller on startup and wait for the reset to complete. This helps the scenario where display was already in use by some other core before the linux was booted.
The reason the omapdrm doesn't do a reset is that the PM features on some of the DSS registers were set and controlled outside dss driver, so the dss driver could not do a reset just like that. That design was carried to the tidss driver, although I'm not sure if the reason is valid on AM6 and J7 platforms.
If that reasoning is not valid, this patch is ok and:
Reviewed-by: Tomi Valkeinen tomi.valkeinen@ideasonboard.com
Yeah seems OK to me for tidss, I don't think there's any other layer to do this in a generic way for k3 devices currently.
The thing to check here is that the sysconfig register gets properly initialized to the right state after reset. For PM, likely the syconfig value after reset is not correct, but that can be reconfigured later on as needed.
Tony - sysc control for older omap devices still control this directly?
Yes, for a reason. The reset affects the entire interconnect target module, and disabling clockdomain autoidle needs to be considered for enable. For omaps, the resets are handled in a generic way for all the TI devices by ti-sysc.
With ti-sysc, the reset is done before probing dss devices on init in sysc_init_module(). The dss related quirk handling is done in sysc_pre_reset_quirk_dss(). If needed, we could add support for reset framework to ti-sysc for omapdrm to call. But so far there has not been much of a need for that, I think 8250_omap could use reset framework if available though.
Anyways, sounds like there's no need to do a similar dss reset in omapdrm.
Regards,
Tony
On 14/03/2022 13:37, Devarsh Thakkar wrote:
Soft reset the display subsystem controller on startup and wait for the reset to complete. This helps the scenario where display was already in use by some other core before the linux was booted.
Signed-off-by: Devarsh Thakkar devarsht@ti.com
drivers/gpu/drm/tidss/tidss_dispc.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
Thanks, I have pushed this to drm-misc-next.
Tomi
dri-devel@lists.freedesktop.org
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Devarsh Thakkar -
Nishanth Menon -
Tomi Valkeinen -
Tony Lindgren