https://bugs.freedesktop.org/show_bug.cgi?id=91749
Bug ID: 91749 Summary: Tonga IH ring misaligned Product: DRI Version: DRI git Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component: DRM/AMDgpu Assignee: dri-devel@lists.freedesktop.org Reporter: jay@jcornwall.me
From amdgpu_ih.c:
adev->irq.ih.ring = kzalloc(adev->irq.ih.ring_size + 8, GFP_KERNEL); if (adev->irq.ih.ring == NULL) return -ENOMEM; adev->irq.ih.rb_dma_addr = pci_map_single(adev->pdev, (void *)adev->irq.ih.ring, adev->irq.ih.ring_size, PCI_DMA_BIDIRECTIONAL);
The Tonga IH_RB_BASE register requires 256B alignment. kzalloc does not guarantee this, e.g.:
adev->irq.ih.ring: 0xFFFF880835B22148 adev->irq.ih.rb_dma_addr: 0x835B22148 IH_RB_BASE: 0835b221
This causes amdgpu_ih_decode_iv to read ahead of the last written IV, missing it, when this misalignment occurs.
https://bugs.freedesktop.org/show_bug.cgi?id=91749
--- Comment #1 from Alex Deucher alexdeucher@gmail.com --- Created attachment 117903 --> https://bugs.freedesktop.org/attachment.cgi?id=117903&action=edit possible fix
This should fix it.
https://bugs.freedesktop.org/show_bug.cgi?id=91749
--- Comment #2 from Jay Cornwall jay@jcornwall.me --- Works good, thanks.
https://bugs.freedesktop.org/show_bug.cgi?id=91749
Alex Deucher alexdeucher@gmail.com changed:
What |Removed |Added ---------------------------------------------------------------------------- Status|NEW |RESOLVED Resolution|--- |FIXED
--- Comment #3 from Alex Deucher alexdeucher@gmail.com --- Fixed long ago.
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