On 2/16/2022 4:08 PM, Dmitry Baryshkov wrote:

The dsi_7nm_phy_enable() disagrees with downstream for glbl_str_swi_cal_sel_ctrl and glbl_hstx_str_ctrl_0 values. Update programmed settings to match downstream driver. To remove the possibility for such errors in future drop less_than_1500_mhz assignment and specify settings explicitly.

Fixes: 5ac178381d26 ("drm/msm/dsi: support CPHY mode for 7nm pll/phy") Signed-off-by: Dmitry Baryshkov dmitry.baryshkov@linaro.org

Yes, this matches what we have downstream Reviewed-by: Abhinav Kumar quic_abhinavk@quicinc.com

---

drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index 36eb6109cb88..6e506feb111f 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -864,20 +864,26 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, /* Alter PHY configurations if data rate less than 1.5GHZ*/ less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000);

• /* For C-PHY, no low power settings for lower clk rate */
• if (phy->cphy_mode)

• less_than_1500_mhz = false;
  

• if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;

• glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d :  0x00;
  

• glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 :  0x3c;
  

• if (phy->cphy_mode) {
  

• 	glbl_rescode_top_ctrl = 0x00;
  

• 	glbl_rescode_bot_ctrl = 0x3c;
  

• } else {
  

• 	glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d :  0x00;
  

• 	glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 :  0x3c;
  

• }
  

  glbl_str_swi_cal_sel_ctrl = 0x00; glbl_hstx_str_ctrl_0 = 0x88; } else { vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59;

• glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00;
  

• glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88;
  

• if (phy->cphy_mode) {
  

• 	glbl_str_swi_cal_sel_ctrl = 0x03;
  

• 	glbl_hstx_str_ctrl_0 = 0x66;
  

• } else {
  

• 	glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00;
  

• 	glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88;
  

• }
  

  glbl_rescode_top_ctrl = 0x03; glbl_rescode_bot_ctrl = 0x3c; }