From: Matt Roper matthew.d.roper@intel.com
The render/media engines on DG2 unify render compression and media compression into a single format for the first time, using the Tile 4 layout for main surfaces. The compression algorithm is different from any previous platform and the display engine must still be configured to decompress either a render or media compressed surface; as such, we need new RC and MC framebuffer modifiers to represent buffers in this format.
v2: Clarify modifier layout description.
Cc: dri-devel@lists.freedesktop.org Signed-off-by: Matt Roper matthew.d.roper@intel.com Signed-off-by: Imre Deak imre.deak@intel.com Acked-by: Nanley Chery nanley.g.chery@intel.com --- include/uapi/drm/drm_fourcc.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index b73fe6797fc37..4a5117715db3c 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -583,6 +583,28 @@ extern "C" { */ #define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9)
+/* + * Intel color control surfaces (CCS) for DG2 render compression. + * + * The main surface is Tile 4 and at plane index 0. The CCS data is stored + * outside of the GEM object in a reserved memory area dedicated for the + * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The + * main surface pitch is required to be a multiple of four Tile 4 widths. + */ +#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10) + +/* + * Intel color control surfaces (CCS) for DG2 media compression. + * + * The main surface is Tile 4 and at plane index 0. For semi-planar formats + * like NV12, the Y and UV planes are Tile 4 and are located at plane indices + * 0 and 1, respectively. The CCS for all planes are stored outside of the + * GEM object in a reserved memory area dedicated for the storage of the + * CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface + * pitch is required to be a multiple of four Tile 4 widths. + */ +#define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11) + /* * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks *
Reviewed-by: Juha-Pekka Heikkila juhapekka.heikkila@gmail.com
On 4.4.2022 16.38, Imre Deak wrote:
From: Matt Roper matthew.d.roper@intel.com
The render/media engines on DG2 unify render compression and media compression into a single format for the first time, using the Tile 4 layout for main surfaces. The compression algorithm is different from any previous platform and the display engine must still be configured to decompress either a render or media compressed surface; as such, we need new RC and MC framebuffer modifiers to represent buffers in this format.
v2: Clarify modifier layout description.
Cc: dri-devel@lists.freedesktop.org Signed-off-by: Matt Roper matthew.d.roper@intel.com Signed-off-by: Imre Deak imre.deak@intel.com Acked-by: Nanley Chery nanley.g.chery@intel.com
include/uapi/drm/drm_fourcc.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index b73fe6797fc37..4a5117715db3c 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -583,6 +583,28 @@ extern "C" { */ #define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9)
+/*
- Intel color control surfaces (CCS) for DG2 render compression.
- The main surface is Tile 4 and at plane index 0. The CCS data is stored
- outside of the GEM object in a reserved memory area dedicated for the
- storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
- main surface pitch is required to be a multiple of four Tile 4 widths.
- */
+#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10)
+/*
- Intel color control surfaces (CCS) for DG2 media compression.
- The main surface is Tile 4 and at plane index 0. For semi-planar formats
- like NV12, the Y and UV planes are Tile 4 and are located at plane indices
- 0 and 1, respectively. The CCS for all planes are stored outside of the
- GEM object in a reserved memory area dedicated for the storage of the
- CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface
- pitch is required to be a multiple of four Tile 4 widths.
- */
+#define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
- /*
- Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
Seems my first mail didn't come through so here's second time for this patch:
Reviewed-by: Juha-Pekka Heikkila juhapekka.heikkila@gmail.com
On Mon, Apr 4, 2022 at 4:39 PM Imre Deak imre.deak@intel.com wrote:
From: Matt Roper matthew.d.roper@intel.com
The render/media engines on DG2 unify render compression and media compression into a single format for the first time, using the Tile 4 layout for main surfaces. The compression algorithm is different from any previous platform and the display engine must still be configured to decompress either a render or media compressed surface; as such, we need new RC and MC framebuffer modifiers to represent buffers in this format.
v2: Clarify modifier layout description.
Cc: dri-devel@lists.freedesktop.org Signed-off-by: Matt Roper matthew.d.roper@intel.com Signed-off-by: Imre Deak imre.deak@intel.com Acked-by: Nanley Chery nanley.g.chery@intel.com
include/uapi/drm/drm_fourcc.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index b73fe6797fc37..4a5117715db3c 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -583,6 +583,28 @@ extern "C" { */ #define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9)
+/*
- Intel color control surfaces (CCS) for DG2 render compression.
- The main surface is Tile 4 and at plane index 0. The CCS data is stored
- outside of the GEM object in a reserved memory area dedicated for the
- storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
- main surface pitch is required to be a multiple of four Tile 4 widths.
- */
+#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10)
+/*
- Intel color control surfaces (CCS) for DG2 media compression.
- The main surface is Tile 4 and at plane index 0. For semi-planar formats
- like NV12, the Y and UV planes are Tile 4 and are located at plane indices
- 0 and 1, respectively. The CCS for all planes are stored outside of the
- GEM object in a reserved memory area dedicated for the storage of the
- CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface
- pitch is required to be a multiple of four Tile 4 widths.
- */
+#define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
/*
- Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
-- 2.30.2
dri-devel@lists.freedesktop.org
-
Imre Deak -
Juha-Pekka Heikkila -
Juha-Pekka Heikkilä