The plane base address needs to be calculated using the source coordinates to position the source correctly - it's possible to have a larger source buffer than the CRTC size, and have several CRTCs reading from different parts of the buffer.

In such a case, the pitch may be larger, and we will use the source position to select an area of the buffer to scan out.

In order for this to work correctly, we need to also fix the atomic check to do a fuller validation of the new state.

Signed-off-by: Russell King rmk+kernel@armlinux.org.uk --- drivers/gpu/drm/arm/hdlcd_crtc.c | 41 ++++++++++++++++++++++++++++------------ 1 file changed, 29 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/arm/hdlcd_crtc.c b/drivers/gpu/drm/arm/hdlcd_crtc.c index 48019ae22ddb..c239616f5334 100644 --- a/drivers/gpu/drm/arm/hdlcd_crtc.c +++ b/drivers/gpu/drm/arm/hdlcd_crtc.c @@ -10,6 +10,7 @@ */

#include <drm/drmP.h> +#include <drm/drm_atomic.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_crtc.h> #include <drm/drm_crtc_helper.h> @@ -206,13 +207,30 @@ static const struct drm_crtc_helper_funcs hdlcd_crtc_helper_funcs = { static int hdlcd_plane_atomic_check(struct drm_plane *plane, struct drm_plane_state *state) { - u32 src_w, src_h; + struct drm_crtc_state *crtc_state; + struct drm_crtc *crtc; + struct drm_rect clip = { 0 }; + int ret;

- src_w = state->src_w >> 16; - src_h = state->src_h >> 16; + crtc = state->crtc; + if (!crtc) + return 0;

- /* we can't do any scaling of the plane source */ - if ((src_w != state->crtc_w) || (src_h != state->crtc_h)) + crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); + if (!crtc_state->enable) + return -EINVAL; + + clip.x2 = crtc_state->adjusted_mode.hdisplay; + clip.y2 = crtc_state->adjusted_mode.vdisplay; + + ret = drm_plane_helper_check_state(state, &clip, + DRM_PLANE_HELPER_NO_SCALING, + DRM_PLANE_HELPER_NO_SCALING, + false, true); + if (ret) + return ret; + + if (!state->visible) return -EINVAL;

return 0; @@ -224,21 +242,20 @@ static void hdlcd_plane_atomic_update(struct drm_plane *plane, struct hdlcd_drm_private *hdlcd; struct drm_gem_cma_object *gem; unsigned int depth, bpp; - u32 src_w, src_h, dest_w, dest_h; + u32 src_x, src_y, dest_h; dma_addr_t scanout_start;

if (!plane->state->fb) return;

drm_fb_get_bpp_depth(plane->state->fb->pixel_format, &depth, &bpp); - src_w = plane->state->src_w >> 16; - src_h = plane->state->src_h >> 16; - dest_w = plane->state->crtc_w; - dest_h = plane->state->crtc_h; gem = drm_fb_cma_get_gem_obj(plane->state->fb, 0); + src_x = plane->state->src_x >> 16; + src_y = plane->state->src_y >> 16; + dest_h = plane->state->crtc_h; scanout_start = gem->paddr + plane->state->fb->offsets[0] + - plane->state->crtc_y * plane->state->fb->pitches[0] + - plane->state->crtc_x * bpp / 8; + src_y * plane->state->fb->pitches[0] + + src_x * bpp / 8;

hdlcd = plane->dev->dev_private; hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_LENGTH, plane->state->fb->pitches[0]);