Add 'bus-type' and 'data-lanes' define for port0. Define DP tx lane0, lane1 swing register array define, and audio enable flag.

The device which cannot pass DP tx PHY CTS caused by long PCB trace or embedded MUX, adjusting ANX7625 PHY parameters can pass the CTS test. The adjusting type include Pre-emphasis, Vp-p, Rterm(Resistor Termination) and Rsel(Driven Strength). Each lane has maximum 20 registers for these settings.

For the DP tx swing setting, each lane has 10 different combination for swing, as Pre0: swing3|swing2|swing1|swing0, Pre1: swing2|swing1|swing0, Pre2: swing1|swing0, Pre3: swing0.

Register definition as: [Boost_ctrl] These registers control post cursor manual, increase the Boost_Ctrl setting can increase Pre-emphasis value separately. Lane Condition Register address Lane0 Swing0_Pre0 0x7a:0x00 bit[3:0] Lane0 Swing1_Pre0 0x7a:0x01 bit[3:0] Lane0 Swing2_Pre0 0x7a:0x02 bit[3:0] Lane0 Swing3_Pre0 0x7a:0x03 bit[3:0] Lane0 Swing0_Pre1 0x7a:0x04 bit[3:0] Lane0 Swing1_Pre1 0x7a:0x05 bit[3:0] Lane0 Swing2_Pre1 0x7a:0x06 bit[3:0] Lane0 Swing0_Pre2 0x7a:0x07 bit[3:0] Lane0 Swing1_Pre2 0x7a:0x08 bit[3:0] Lane0 Swing0_Pre3 0x7a:0x09 bit[3:0] Lane1 Swing0_Pre0 0x7a:0x14 bit[3:0] Lane1 Swing1_Pre0 0x7a:0x15 bit[3:0] Lane1 Swing2_Pre0 0x7a:0x16 bit[3:0] Lane1 Swing3_Pre0 0x7a:0x17 bit[3:0] Lane1 Swing0_Pre1 0x7a:0x18 bit[3:0] Lane1 Swing1_Pre1 0x7a:0x19 bit[3:0] Lane1 Swing2_Pre1 0x7a:0x1a bit[3:0] Lane1 Swing0_Pre2 0x7a:0x1b bit[3:0] Lane1 Swing1_Pre2 0x7a:0x1c bit[3:0] Lane1 Swing0_Pre3 0x7a:0x1d bit[3:0]

[Swing_ctrl] These registers control swing manual, increase Swing_Ctrl setting can increase Vp-p value separately. Lane Condition Register address Lane0 Swing0_Pre0 0x7a:0x00 bit[6:4] Lane0 Swing1_Pre0 0x7a:0x01 bit[6:4] Lane0 Swing2_Pre0 0x7a:0x02 bit[6:4] Lane0 Swing3_Pre0 0x7a:0x03 bit[6:4] Lane0 Swing0_Pre1 0x7a:0x04 bit[6:4] Lane0 Swing1_Pre1 0x7a:0x05 bit[6:4] Lane0 Swing2_Pre1 0x7a:0x06 bit[6:4] Lane0 Swing0_Pre2 0x7a:0x07 bit[6:4] Lane0 Swing1_Pre2 0x7a:0x08 bit[6:4] Lane0 Swing0_Pre3 0x7a:0x09 bit[6:4] Lane1 Swing0_Pre0 0x7a:0x14 bit[6:4] Lane1 Swing1_Pre0 0x7a:0x15 bit[6:4] Lane1 Swing2_Pre0 0x7a:0x16 bit[6:4] Lane1 Swing3_Pre0 0x7a:0x17 bit[6:4] Lane1 Swing0_Pre1 0x7a:0x18 bit[6:4] Lane1 Swing1_Pre1 0x7a:0x19 bit[6:4] Lane1 Swing2_Pre1 0x7a:0x1a bit[6:4] Lane1 Swing0_Pre2 0x7a:0x1b bit[6:4] Lane1 Swing1_Pre2 0x7a:0x1c bit[6:4] Lane1 Swing0_Pre3 0x7a:0x1d bit[6:4]

[Rsel_ctrl] These registers control resistor compensation manual, increase Rsel_ctrl can increase the IO driven strength, increase Vp-p simultaneously. Lane Condition Register address Lane0 Swing0_Pre0 0x7a:0x0a bit[4:0] Lane0 Swing1_Pre0 0x7a:0x0b bit[4:0] Lane0 Swing2_Pre0 0x7a:0x0c bit[4:0] Lane0 Swing3_Pre0 0x7a:0x0d bit[4:0] Lane0 Swing0_Pre1 0x7a:0x0e bit[4:0] Lane0 Swing1_Pre1 0x7a:0x0f bit[4:0] Lane0 Swing2_Pre1 0x7a:0x10 bit[4:0] Lane0 Swing0_Pre2 0x7a:0x11 bit[4:0] Lane0 Swing1_Pre2 0x7a:0x12 bit[4:0] Lane0 Swing0_Pre3 0x7a:0x13 bit[4:0] Lane1 Swing0_Pre0 0x7a:0x1e bit[4:0] Lane1 Swing1_Pre0 0x7a:0x1f bit[4:0] Lane1 Swing2_Pre0 0x7a:0x20 bit[4:0] Lane1 Swing3_Pre0 0x7a:0x21 bit[4:0] Lane1 Swing0_Pre1 0x7a:0x22 bit[4:0] Lane1 Swing1_Pre1 0x7a:0x23 bit[4:0] Lane1 Swing2_Pre1 0x7a:0x24 bit[4:0] Lane1 Swing0_Pre2 0x7a:0x25 bit[4:0] Lane1 Swing1_Pre2 0x7a:0x26 bit[4:0] Lane1 Swing0_Pre3 0x7a:0x27 bit[4:0]

[Rterm_ctrl] These registers adjust 50ohm impedance of DP tx 00:55 ohm 01:50 ohm(default) 10:45 ohm 11:40 ohm Lane Condition Register address Lane0 Swing0_Pre0 0x7a:0x0a bit[6:5] Lane0 Swing1_Pre0 0x7a:0x0b bit[6:5] Lane0 Swing2_Pre0 0x7a:0x0c bit[6:5] Lane0 Swing3_Pre0 0x7a:0x0d bit[6:5] Lane0 Swing0_Pre1 0x7a:0x0e bit[6:5] Lane0 Swing1_Pre1 0x7a:0x0f bit[6:5] Lane0 Swing2_Pre1 0x7a:0x10 bit[6:5] Lane0 Swing0_Pre2 0x7a:0x11 bit[6:5] Lane0 Swing1_Pre2 0x7a:0x12 bit[6:5] Lane0 Swing0_Pre3 0x7a:0x13 bit[6:5] lane1 Swing0_Pre0 0x7a:0x1e bit[6:5] Lane1 Swing1_Pre0 0x7a:0x1f bit[6:5] Lane1 Swing2_Pre0 0x7a:0x20 bit[6:5] Lane1 Swing3_Pre0 0x7a:0x21 bit[6:5] Lane1 Swing0_Pre1 0x7a:0x22 bit[6:5] Lane1 Swing1_Pre1 0x7a:0x23 bit[6:5] Lane1 Swing2_Pre1 0x7a:0x24 bit[6:5] Lane1 Swing0_Pre2 0x7a:0x25 bit[6:5] Lane1 Swing1_Pre2 0x7a:0x26 bit[6:5] Lane1 Swing0_Pre3 0x7a:0x27 bit[6:5]

Signed-off-by: Xin Ji xji@analogixsemi.com --- .../display/bridge/analogix,anx7625.yaml | 55 ++++++++++++++++++- 1 file changed, 54 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml b/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml index ab48ab2f4240..77b160d7c269 100644 --- a/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml +++ b/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml @@ -43,6 +43,24 @@ properties: vdd33-supply: description: Regulator that provides the supply 3.3V power.

+ analogix,lane0-swing: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 20 + description: + an array of swing register setting for DP tx lane0 PHY. + + analogix,lane1-swing: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 20 + description: + an array of swing register setting for DP tx lane1 PHY. + + analogix,audio-enable: + type: boolean + description: let the driver enable audio HDMI codec function or not. + ports: $ref: /schemas/graph.yaml#/properties/ports

@@ -50,13 +68,43 @@ properties: port@0: $ref: /schemas/graph.yaml#/properties/port description: - Video port for MIPI DSI input. + MIPI DSI/DPI input. + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + type: object + additionalProperties: false + + properties: + remote-endpoint: true + bus-type: true + data-lanes: true + + required: + - remote-endpoint + + required: + - endpoint +

port@1: $ref: /schemas/graph.yaml#/properties/port description: Video port for panel or connector.

+ properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + type: object + additionalProperties: false + + properties: + remote-endpoint: true + + required: + - remote-endpoint + required: - port@0 - port@1 @@ -87,6 +135,9 @@ examples: vdd10-supply = <&pp1000_mipibrdg>; vdd18-supply = <&pp1800_mipibrdg>; vdd33-supply = <&pp3300_mipibrdg>; + analogix,audio-enable; + analogix,lane0-swing = <0x14 0x54 0x64 0x74 0x29 0x7b 0x77 0x5b>; + analogix,lane1-swing = <0x14 0x54 0x64 0x74 0x29 0x7b 0x77 0x5b>;

ports { #address-cells = <1>; @@ -96,6 +147,8 @@ examples: reg = <0>; anx7625_in: endpoint { remote-endpoint = <&mipi_dsi>; + bus-type = <5>; + data-lanes = <0 1 2 3>; }; };

The basic anx7625 driver only support MIPI DSI rx signal input. This patch add MIPI DPI rx input configuration support, after apply this patch, the driver can support DSI rx or DPI rx by adding 'bus-type' in DT.

Reviewed-by: Robert Foss robert.foss@linaro.org Signed-off-by: Xin Ji xji@analogixsemi.com --- drivers/gpu/drm/bridge/analogix/anx7625.c | 246 ++++++++++++++++------ drivers/gpu/drm/bridge/analogix/anx7625.h | 18 +- 2 files changed, 204 insertions(+), 60 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c index 3fc6b7ce7fc7..a5a20cc0f3e0 100644 --- a/drivers/gpu/drm/bridge/analogix/anx7625.c +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c @@ -32,6 +32,7 @@ #include <drm/drm_print.h> #include <drm/drm_probe_helper.h>

+#include <media/v4l2-fwnode.h> #include <video/display_timing.h>

#include "anx7625.h" @@ -152,18 +153,18 @@ static int anx7625_write_and(struct anx7625_data *ctx, return anx7625_reg_write(ctx, client, offset, (val & (mask))); }

-static int anx7625_write_and_or(struct anx7625_data *ctx, - struct i2c_client *client, - u8 offset, u8 and_mask, u8 or_mask) +static int anx7625_config_bit_matrix(struct anx7625_data *ctx) { - int val; + int i, ret;

- val = anx7625_reg_read(ctx, client, offset); - if (val < 0) - return val; + ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, + AUDIO_CONTROL_REGISTER, 0x80); + for (i = 0; i < 13; i++) + ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, + VIDEO_BIT_MATRIX_12 + i, + 0x18 + i);

- return anx7625_reg_write(ctx, client, - offset, (val & and_mask) | (or_mask)); + return ret; }

static int anx7625_read_ctrl_status_p0(struct anx7625_data *ctx) @@ -221,38 +222,6 @@ static int anx7625_video_mute_control(struct anx7625_data *ctx, return ret; }

-static int anx7625_config_audio_input(struct anx7625_data *ctx) -{ - struct device *dev = &ctx->client->dev; - int ret; - - /* Channel num */ - ret = anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, - AUDIO_CHANNEL_STATUS_6, I2S_CH_2 << 5); - - /* FS */ - ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, - AUDIO_CHANNEL_STATUS_4, - 0xf0, AUDIO_FS_48K); - /* Word length */ - ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, - AUDIO_CHANNEL_STATUS_5, - 0xf0, AUDIO_W_LEN_24_24MAX); - /* I2S */ - ret |= anx7625_write_or(ctx, ctx->i2c.tx_p2_client, - AUDIO_CHANNEL_STATUS_6, I2S_SLAVE_MODE); - ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, - AUDIO_CONTROL_REGISTER, ~TDM_TIMING_MODE); - /* Audio change flag */ - ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, - AP_AV_STATUS, AP_AUDIO_CHG); - - if (ret < 0) - DRM_DEV_ERROR(dev, "fail to config audio.\n"); - - return ret; -} - /* Reduction of fraction a/b */ static void anx7625_reduction_of_a_fraction(unsigned long *a, unsigned long *b) { @@ -412,7 +381,7 @@ static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx) ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_LANE_CTRL_0, 0xfc); ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, - MIPI_LANE_CTRL_0, 3); + MIPI_LANE_CTRL_0, ctx->pdata.mipi_lanes - 1);

/* Htotal */ htotal = ctx->dt.hactive.min + ctx->dt.hfront_porch.min + @@ -597,6 +566,76 @@ static int anx7625_dsi_config(struct anx7625_data *ctx) return ret; }

+static int anx7625_api_dpi_config(struct anx7625_data *ctx) +{ + struct device *dev = &ctx->client->dev; + u16 freq = ctx->dt.pixelclock.min / 1000; + int ret; + + /* configure pixel clock */ + ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, + PIXEL_CLOCK_L, freq & 0xFF); + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, + PIXEL_CLOCK_H, (freq >> 8)); + + /* set DPI mode */ + /* set to DPI PLL module sel */ + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, + MIPI_DIGITAL_PLL_9, 0x20); + /* power down MIPI */ + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, + MIPI_LANE_CTRL_10, 0x08); + /* enable DPI mode */ + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, + MIPI_DIGITAL_PLL_18, 0x1C); + /* set first edge */ + ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, + VIDEO_CONTROL_0, 0x06); + if (ret < 0) + DRM_DEV_ERROR(dev, "IO error : dpi phy set failed.\n"); + + return ret; +} + +static int anx7625_dpi_config(struct anx7625_data *ctx) +{ + struct device *dev = &ctx->client->dev; + int ret; + + DRM_DEV_DEBUG_DRIVER(dev, "config dpi\n"); + + /* DSC disable */ + ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, + R_DSC_CTRL_0, ~DSC_EN); + if (ret < 0) { + DRM_DEV_ERROR(dev, "IO error : disable dsc failed.\n"); + return ret; + } + + ret = anx7625_config_bit_matrix(ctx); + if (ret < 0) { + DRM_DEV_ERROR(dev, "config bit matrix failed.\n"); + return ret; + } + + ret = anx7625_api_dpi_config(ctx); + if (ret < 0) { + DRM_DEV_ERROR(dev, "mipi phy(dpi) setup failed.\n"); + return ret; + } + + /* set MIPI RX EN */ + ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, + AP_AV_STATUS, AP_MIPI_RX_EN); + /* clear mute flag */ + ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, + AP_AV_STATUS, (u8)~AP_MIPI_MUTE); + if (ret < 0) + DRM_DEV_ERROR(dev, "IO error : enable mipi rx failed.\n"); + + return ret; +} + static void anx7625_dp_start(struct anx7625_data *ctx) { int ret; @@ -607,9 +646,10 @@ static void anx7625_dp_start(struct anx7625_data *ctx) return; }

- anx7625_config_audio_input(ctx); - - ret = anx7625_dsi_config(ctx); + if (ctx->pdata.is_dpi) + ret = anx7625_dpi_config(ctx); + else + ret = anx7625_dsi_config(ctx);

if (ret < 0) DRM_DEV_ERROR(dev, "MIPI phy setup error.\n"); @@ -1047,6 +1087,7 @@ static void anx7625_start_dp_work(struct anx7625_data *ctx) return; }

+ ctx->hpd_status = 1; ctx->hpd_high_cnt++;

/* Not support HDCP */ @@ -1056,8 +1097,10 @@ static void anx7625_start_dp_work(struct anx7625_data *ctx) ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); /* Interrupt for DRM */ ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); - if (ret < 0) + if (ret < 0) { + DRM_DEV_ERROR(dev, "fail to setting HDCP/auth\n"); return; + }

ret = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, 0x86); if (ret < 0) @@ -1076,6 +1119,10 @@ static void anx7625_hpd_polling(struct anx7625_data *ctx) int ret, val; struct device *dev = &ctx->client->dev;

+ /* Interrupt mode, no need poll HPD status, just return */ + if (ctx->pdata.intp_irq) + return; + ret = readx_poll_timeout(anx7625_read_hpd_status_p0, ctx, val, ((val & HPD_STATUS) || (val < 0)), @@ -1103,6 +1150,21 @@ static void anx7625_remove_edid(struct anx7625_data *ctx) ctx->slimport_edid_p.edid_block_num = -1; }

+static void anx7625_dp_adjust_swing(struct anx7625_data *ctx) +{ + int i; + + for (i = 0; i < ctx->pdata.dp_lane0_swing_reg_cnt; i++) + anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, + DP_TX_LANE0_SWING_REG0 + i, + ctx->pdata.lane0_reg_data[i] & 0xFF); + + for (i = 0; i < ctx->pdata.dp_lane1_swing_reg_cnt; i++) + anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, + DP_TX_LANE1_SWING_REG0 + i, + ctx->pdata.lane1_reg_data[i] & 0xFF); +} + static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on) { struct device *dev = &ctx->client->dev; @@ -1118,9 +1180,8 @@ static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on) } else { DRM_DEV_DEBUG_DRIVER(dev, " HPD high\n"); anx7625_start_dp_work(ctx); + anx7625_dp_adjust_swing(ctx); } - - ctx->hpd_status = 1; }

static int anx7625_hpd_change_detect(struct anx7625_data *ctx) @@ -1197,20 +1258,72 @@ static irqreturn_t anx7625_intr_hpd_isr(int irq, void *data) return IRQ_HANDLED; }

+static int anx7625_get_swing_setting(struct device *dev, + struct anx7625_platform_data *pdata) +{ + int num_regs; + + if (of_get_property(dev->of_node, + "analogix,lane0-swing", &num_regs)) { + if (num_regs > DP_TX_SWING_REG_CNT) + num_regs = DP_TX_SWING_REG_CNT; + + pdata->dp_lane0_swing_reg_cnt = num_regs; + of_property_read_u32_array(dev->of_node, "analogix,lane0-swing", + pdata->lane0_reg_data, num_regs); + } + + if (of_get_property(dev->of_node, + "analogix,lane1-swing", &num_regs)) { + if (num_regs > DP_TX_SWING_REG_CNT) + num_regs = DP_TX_SWING_REG_CNT; + + pdata->dp_lane1_swing_reg_cnt = num_regs; + of_property_read_u32_array(dev->of_node, "analogix,lane1-swing", + pdata->lane1_reg_data, num_regs); + } + + return 0; +} + static int anx7625_parse_dt(struct device *dev, struct anx7625_platform_data *pdata) { - struct device_node *np = dev->of_node; + struct device_node *np = dev->of_node, *ep0; struct drm_panel *panel; int ret; + int bus_type, mipi_lanes;

+ anx7625_get_swing_setting(dev, pdata); + + pdata->is_dpi = 1; /* default dpi mode */ pdata->mipi_host_node = of_graph_get_remote_node(np, 0, 0); if (!pdata->mipi_host_node) { DRM_DEV_ERROR(dev, "fail to get internal panel.\n"); return -ENODEV; }

- DRM_DEV_DEBUG_DRIVER(dev, "found dsi host node.\n"); + bus_type = V4L2_FWNODE_BUS_TYPE_PARALLEL; + mipi_lanes = MAX_LANES_SUPPORT; + ep0 = of_graph_get_endpoint_by_regs(np, 0, 0); + if (ep0) { + if (of_property_read_u32(ep0, "bus-type", &bus_type)) + bus_type = 0; + + mipi_lanes = of_property_count_u32_elems(ep0, "data-lanes"); + } + + if (bus_type == V4L2_FWNODE_BUS_TYPE_PARALLEL) /* bus type is Parallel(DSI) */ + pdata->is_dpi = 0; + + pdata->mipi_lanes = mipi_lanes; + if (pdata->mipi_lanes > MAX_LANES_SUPPORT || pdata->mipi_lanes <= 0) + pdata->mipi_lanes = MAX_LANES_SUPPORT; + + if (pdata->is_dpi) + DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DPI host node.\n"); + else + DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DSI host node.\n");

ret = drm_of_find_panel_or_bridge(np, 1, 0, &panel, NULL); if (ret < 0) { @@ -1273,9 +1386,13 @@ static enum drm_connector_status anx7625_sink_detect(struct anx7625_data *ctx) { struct device *dev = &ctx->client->dev;

- DRM_DEV_DEBUG_DRIVER(dev, "sink detect, return connected\n"); + DRM_DEV_DEBUG_DRIVER(dev, "sink detect\n"); + + if (ctx->pdata.panel_bridge) + return connector_status_connected;

- return connector_status_connected; + return ctx->hpd_status ? connector_status_connected : + connector_status_disconnected; }

static int anx7625_attach_dsi(struct anx7625_data *ctx) @@ -1303,7 +1420,7 @@ static int anx7625_attach_dsi(struct anx7625_data *ctx) return -EINVAL; }

- dsi->lanes = 4; + dsi->lanes = ctx->pdata.mipi_lanes; dsi->format = MIPI_DSI_FMT_RGB888; dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | @@ -1349,10 +1466,12 @@ static int anx7625_bridge_attach(struct drm_bridge *bridge, return -ENODEV; }

- err = anx7625_attach_dsi(ctx); - if (err) { - DRM_DEV_ERROR(dev, "Fail to attach to dsi : %d\n", err); - return err; + if (!ctx->pdata.is_dpi) { + err = anx7625_attach_dsi(ctx); + if (err) { + DRM_DEV_ERROR(dev, "Fail to attach to dsi : %d\n", err); + return err; + } }

if (ctx->pdata.panel_bridge) { @@ -1451,6 +1570,10 @@ static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge,

DRM_DEV_DEBUG_DRIVER(dev, "drm mode fixup set\n");

+ /* No need fixup for external monitor */ + if (!ctx->pdata.panel_bridge) + return true; + hsync = mode->hsync_end - mode->hsync_start; hfp = mode->hsync_start - mode->hdisplay; hbp = mode->htotal - mode->hsync_end; @@ -1827,8 +1950,13 @@ static int anx7625_i2c_probe(struct i2c_client *client,

platform->bridge.funcs = &anx7625_bridge_funcs; platform->bridge.of_node = client->dev.of_node; - platform->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD; - platform->bridge.type = DRM_MODE_CONNECTOR_eDP; + platform->bridge.ops = DRM_BRIDGE_OP_EDID; + if (!platform->pdata.panel_bridge) + platform->bridge.ops |= DRM_BRIDGE_OP_HPD | + DRM_BRIDGE_OP_DETECT; + platform->bridge.type = platform->pdata.panel_bridge ? + DRM_MODE_CONNECTOR_eDP : + DRM_MODE_CONNECTOR_DisplayPort; drm_bridge_add(&platform->bridge);

DRM_DEV_DEBUG_DRIVER(dev, "probe done\n"); diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.h b/drivers/gpu/drm/bridge/analogix/anx7625.h index 034c3840028f..65db38e5da9a 100644 --- a/drivers/gpu/drm/bridge/analogix/anx7625.h +++ b/drivers/gpu/drm/bridge/analogix/anx7625.h @@ -141,12 +141,20 @@ #define HORIZONTAL_BACK_PORCH_H 0x22 /* Bit[7:4] are reserved */

/******** END of I2C Address 0x72 *********/ + +/***************************************************************/ +/* Register definition of device address 0x7a */ +#define DP_TX_SWING_REG_CNT 0x14 +#define DP_TX_LANE0_SWING_REG0 0x00 +#define DP_TX_LANE1_SWING_REG0 0x14 +/******** END of I2C Address 0x7a *********/ + /***************************************************************/ /* Register definition of device address 0x7e */

#define I2C_ADDR_7E_FLASH_CONTROLLER 0x7E

-#define FLASH_LOAD_STA 0x05 +#define FLASH_LOAD_STA 0x05 #define FLASH_LOAD_STA_CHK BIT(7)

#define XTAL_FRQ_SEL 0x3F @@ -347,12 +355,20 @@ struct s_edid_data {

/***************** Display End *****************/

+#define MAX_LANES_SUPPORT 4 + struct anx7625_platform_data { struct gpio_desc *gpio_p_on; struct gpio_desc *gpio_reset; struct regulator_bulk_data supplies[3]; struct drm_bridge *panel_bridge; int intp_irq; + int is_dpi; + int mipi_lanes; + int dp_lane0_swing_reg_cnt; + int lane0_reg_data[DP_TX_SWING_REG_CNT]; + int dp_lane1_swing_reg_cnt; + int lane1_reg_data[DP_TX_SWING_REG_CNT]; u32 low_power_mode; struct device_node *mipi_host_node; };