Hi!
Follow-up on the v4: https://patchwork.kernel.org/cover/11369777/, some of the core patches got merged already (thanks Rob!).
The main purpose of this series is to upstream the dts change and the binding document, but I wanted to see how far I could probe the GPU, to check that the binding is indeed correct. The rest of the patches are RFC/work-in-progress.
So this is tested on MT8183 with a chromeos-4.19 kernel, and a ton of backports to get the latest panfrost driver (I should probably try on linux-next at some point but this was the path of least resistance).
I tested it as a module as it's more challenging (originally probing would work built-in, on boot, but not as a module, as I didn't have the power domain changes, and all power domains are on by default during boot).
Probing logs looks like this, currently. They look sane. [ 501.319728] panfrost 13040000.gpu: clock rate = 511999970 [ 501.320041] panfrost 13040000.gpu: Linked as a consumer to regulator.14 [ 501.320102] panfrost 13040000.gpu: Linked as a consumer to regulator.31 [ 501.320651] panfrost 13040000.gpu: Linked as a consumer to genpd:0:13040000.gpu [ 501.320954] panfrost 13040000.gpu: Linked as a consumer to genpd:1:13040000.gpu [ 501.321062] panfrost 13040000.gpu: Linked as a consumer to genpd:2:13040000.gpu [ 501.321734] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0 [ 501.321741] panfrost 13040000.gpu: features: 00000000,13de77ff, issues: 00000000,00000400 [ 501.321747] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7 [ 501.321752] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1 [ 501.324951] [drm] Initialized panfrost 1.1.0 20180908 for 13040000.gpu on minor 2
Some more changes are still required to get devfreq working, and of course I do not have a userspace driver to test this with.
I believe at least patches 1 & 2 can be merged (2 depends on another patch series, so maybe we could start with 1 only for now...).
Thanks!
Nicolas Boichat (4): dt-bindings: gpu: mali-bifrost: Add Mediatek MT8183 arm64: dts: mt8183: Add node for the Mali GPU RFC: drm/panfrost: Add mt8183-mali compatible string RFC: drm/panfrost: devfreq: Add support for 2 regulators
.../bindings/gpu/arm,mali-bifrost.yaml | 25 +++++ arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 7 ++ arch/arm64/boot/dts/mediatek/mt8183.dtsi | 105 ++++++++++++++++++ drivers/gpu/drm/panfrost/panfrost_devfreq.c | 17 +++ drivers/gpu/drm/panfrost/panfrost_device.h | 1 + drivers/gpu/drm/panfrost/panfrost_drv.c | 11 ++ 6 files changed, 166 insertions(+)
Define a compatible string for the Mali Bifrost GPU found in Mediatek's MT8183 SoCs.
Signed-off-by: Nicolas Boichat drinkcat@chromium.org Reviewed-by: Alyssa Rosenzweig alyssa.rosenzweig@collabora.com ---
v5: - Rename "2d" power domain to "core2" v4: - Add power-domain-names description (kept Alyssa's reviewed-by as the change is minor) v3: - No change
.../bindings/gpu/arm,mali-bifrost.yaml | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+)
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index e8b99adcb1bd292..c5ceca513192f99 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -17,6 +17,7 @@ properties: items: - enum: - amlogic,meson-g12a-mali + - mediatek,mt8183-mali - realtek,rtd1619-mali - rockchip,px30-mali - const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable @@ -62,6 +63,30 @@ allOf: minItems: 2 required: - resets + - if: + properties: + compatible: + contains: + const: mediatek,mt8183-mali + then: + properties: + sram-supply: true + power-domains: + description: + List of phandle and PM domain specifier as documented in + Documentation/devicetree/bindings/power/power_domain.txt + minItems: 3 + maxItems: 3 + power-domain-names: + items: + - const: core0 + - const: core1 + - const: core2 + + required: + - sram-supply + - power-domains + - power-domains-names
examples: - |
Add a basic GPU node for mt8183.
Signed-off-by: Nicolas Boichat drinkcat@chromium.org Reviewed-by: Alyssa Rosenzweig alyssa.rosenzweig@collabora.com --- Upstreaming what matches existing bindings from our Chromium OS tree: https://chromium.googlesource.com/chromiumos/third_party/kernel/+/chromeos-4...
The evb part of this change depends on this patch to add PMIC dtsi: https://patchwork.kernel.org/patch/10928161/
The binding we use with out-of-tree Mali drivers includes more clocks, this is used for devfreq: the out-of-tree driver switches clk_mux to clk_sub_parent (26Mhz), adjusts clk_main_parent, then switches clk_mux back to clk_main_parent: (see https://chromium.googlesource.com/chromiumos/third_party/kernel/+/chromeos-4...) clocks = <&topckgen CLK_TOP_MFGPLL_CK>, <&topckgen CLK_TOP_MUX_MFG>, <&clk26m>, <&mfgcfg CLK_MFG_BG3D>; clock-names = "clk_main_parent", "clk_mux", "clk_sub_parent", "subsys_mfg_cg"; (based on discussions, this probably belongs in the clock core)
v5: - Rename "2d" power domain to "core2" (keep R-B again).
v4: - Add power-domain-names to describe the 3 domains. (kept Alyssa's reviewed-by as the change is minor)
v3: - No changes
v2: - Use sram instead of mali_sram as SRAM supply name. - Rename mali@ to gpu@.
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 7 ++ arch/arm64/boot/dts/mediatek/mt8183.dtsi | 105 ++++++++++++++++++++ 2 files changed, 112 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts index 1fb195c683c3d01..7d609e0cd9b4975 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts @@ -7,6 +7,7 @@
/dts-v1/; #include "mt8183.dtsi" +#include "mt6358.dtsi"
/ { model = "MediaTek MT8183 evaluation board"; @@ -30,6 +31,12 @@ &auxadc { status = "okay"; };
+&gpu { + supply-names = "mali", "sram"; + mali-supply = <&mt6358_vgpu_reg>; + sram-supply = <&mt6358_vsram_gpu_reg>; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c_pins_0>; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 97863adb7bc02b4..fc690c54988c8cc 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -652,6 +652,111 @@ mfgcfg: syscon@13000000 { #clock-cells = <1>; };
+ gpu: gpu@13040000 { + compatible = "mediatek,mt8183-mali", "arm,mali-bifrost"; + reg = <0 0x13040000 0 0x4000>; + interrupts = + <GIC_SPI 280 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 279 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "job", "mmu", "gpu"; + + clocks = <&topckgen CLK_TOP_MFGPLL_CK>; + + power-domains = + <&scpsys MT8183_POWER_DOMAIN_MFG_CORE0>, + <&scpsys MT8183_POWER_DOMAIN_MFG_CORE1>, + <&scpsys MT8183_POWER_DOMAIN_MFG_2D>; + power-domain-names = "core0", "core1", "core2"; + + operating-points-v2 = <&gpu_opp_table>; + }; + + gpu_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <625000>, <850000>; + }; + + opp-320000000 { + opp-hz = /bits/ 64 <320000000>; + opp-microvolt = <631250>, <850000>; + }; + + opp-340000000 { + opp-hz = /bits/ 64 <340000000>; + opp-microvolt = <637500>, <850000>; + }; + + opp-360000000 { + opp-hz = /bits/ 64 <360000000>; + opp-microvolt = <643750>, <850000>; + }; + + opp-380000000 { + opp-hz = /bits/ 64 <380000000>; + opp-microvolt = <650000>, <850000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <656250>, <850000>; + }; + + opp-420000000 { + opp-hz = /bits/ 64 <420000000>; + opp-microvolt = <662500>, <850000>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + opp-microvolt = <675000>, <850000>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <687500>, <850000>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + opp-microvolt = <700000>, <850000>; + }; + + opp-580000000 { + opp-hz = /bits/ 64 <580000000>; + opp-microvolt = <712500>, <850000>; + }; + + opp-620000000 { + opp-hz = /bits/ 64 <620000000>; + opp-microvolt = <725000>, <850000>; + }; + + opp-653000000 { + opp-hz = /bits/ 64 <653000000>; + opp-microvolt = <743750>, <850000>; + }; + + opp-698000000 { + opp-hz = /bits/ 64 <698000000>; + opp-microvolt = <768750>, <868750>; + }; + + opp-743000000 { + opp-hz = /bits/ 64 <743000000>; + opp-microvolt = <793750>, <893750>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <825000>, <925000>; + }; + }; + mmsys: syscon@14000000 { compatible = "mediatek,mt8183-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>;
Hi Nicolas,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on next-20200305] [also build test ERROR on v5.6-rc4] [cannot apply to robh/for-next linux/master linus/master v5.6-rc4 v5.6-rc3 v5.6-rc2] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to use '--base' option to specify the base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Nicolas-Boichat/Add-dts-for-mt8183-... base: 47466dcf84ee66a973ea7d2fca7e582fe9328932 config: arm64-defconfig (attached as .config) compiler: aarch64-linux-gcc (GCC) 7.5.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree GCC_VERSION=7.5.0 make.cross ARCH=arm64
If you fix the issue, kindly add following tag Reported-by: kbuild test robot lkp@intel.com
All errors (new ones prefixed by >>):
arch/arm64/boot/dts/mediatek/mt8183-evb.dts:10:10: fatal error: mt6358.dtsi: No such file or directory
#include "mt6358.dtsi" ^~~~~~~~~~~~~ compilation terminated.
vim +10 arch/arm64/boot/dts/mediatek/mt8183-evb.dts
10 #include "mt6358.dtsi"
11
--- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
For testing only, the driver doesn't really work yet, AFAICT.
Signed-off-by: Nicolas Boichat drinkcat@chromium.org
---
v5: - Change power domain name from 2d to core2. v4: - Add power domain names. v3: - Match mt8183-mali instead of bifrost, as we require special handling for the 2 regulators and 3 power domains.
drivers/gpu/drm/panfrost/panfrost_drv.c | 11 +++++++++++ 1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c index a6e162236d67fdf..ff76b29b373e105 100644 --- a/drivers/gpu/drm/panfrost/panfrost_drv.c +++ b/drivers/gpu/drm/panfrost/panfrost_drv.c @@ -667,6 +667,15 @@ static const struct panfrost_compatible default_data = { .pm_domain_names = NULL, };
+const char * const mediatek_mt8183_supplies[] = { "mali", "sram" }; +const char * const mediatek_mt8183_pm_domains[] = { "core0", "core1", "core2" }; +static const struct panfrost_compatible mediatek_mt8183_data = { + .num_supplies = ARRAY_SIZE(mediatek_mt8183_supplies), + .supply_names = mediatek_mt8183_supplies, + .num_pm_domains = 3, + .pm_domain_names = mediatek_mt8183_pm_domains, +}; + static const struct of_device_id dt_match[] = { { .compatible = "arm,mali-t604", .data = &default_data, }, { .compatible = "arm,mali-t624", .data = &default_data, }, @@ -677,6 +686,8 @@ static const struct of_device_id dt_match[] = { { .compatible = "arm,mali-t830", .data = &default_data, }, { .compatible = "arm,mali-t860", .data = &default_data, }, { .compatible = "arm,mali-t880", .data = &default_data, }, + { .compatible = "mediatek,mt8183-mali", + .data = &mediatek_mt8183_data }, {} }; MODULE_DEVICE_TABLE(of, dt_match);
The Bifrost GPU on MT8183 uses 2 regulators (core and SRAM) for devfreq, and provides OPP table with 2 sets of voltages.
TODO: This is incomplete as we'll need add support for setting a pair of voltages as well. I also realized that the out-of-tree driver has complex logic to ensure voltage delta between the regulators stays within a specific range, so we'd need to port that as well.
Signed-off-by: Nicolas Boichat drinkcat@chromium.org --- drivers/gpu/drm/panfrost/panfrost_devfreq.c | 17 +++++++++++++++++ drivers/gpu/drm/panfrost/panfrost_device.h | 1 + 2 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c b/drivers/gpu/drm/panfrost/panfrost_devfreq.c index 413987038fbfccb..9c0987a3d71c597 100644 --- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c +++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c @@ -79,6 +79,21 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev) struct devfreq *devfreq; struct thermal_cooling_device *cooling;
+ /* If we have 2 regulator, we need an OPP table with 2 voltages. */ + if (pfdev->comp->num_supplies > 1) { + pfdev->devfreq.dev_opp_table = + dev_pm_opp_set_regulators(dev, + pfdev->comp->supply_names, + pfdev->comp->num_supplies); + if (IS_ERR(pfdev->devfreq.dev_opp_table)) { + ret = PTR_ERR(pfdev->devfreq.dev_opp_table); + pfdev->devfreq.dev_opp_table = NULL; + dev_err(dev, + "Failed to init devfreq opp table: %d\n", ret); + return ret; + } + } + ret = dev_pm_opp_of_add_table(dev); if (ret == -ENODEV) /* Optional, continue without devfreq */ return 0; @@ -119,6 +134,8 @@ void panfrost_devfreq_fini(struct panfrost_device *pfdev) if (pfdev->devfreq.cooling) devfreq_cooling_unregister(pfdev->devfreq.cooling); dev_pm_opp_of_remove_table(&pfdev->pdev->dev); + if (pfdev->devfreq.dev_opp_table) + dev_pm_opp_put_regulators(pfdev->devfreq.dev_opp_table); }
void panfrost_devfreq_resume(struct panfrost_device *pfdev) diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/panfrost/panfrost_device.h index c30c719a805940a..5009a8b7c853ea1 100644 --- a/drivers/gpu/drm/panfrost/panfrost_device.h +++ b/drivers/gpu/drm/panfrost/panfrost_device.h @@ -110,6 +110,7 @@ struct panfrost_device { struct { struct devfreq *devfreq; struct thermal_cooling_device *cooling; + struct opp_table *dev_opp_table; ktime_t busy_time; ktime_t idle_time; ktime_t time_last_update;
Series has my r-b :)
On Fri, Mar 06, 2020 at 12:13:41PM +0800, Nicolas Boichat wrote:
Hi!
Follow-up on the v4: https://patchwork.kernel.org/cover/11369777/, some of the core patches got merged already (thanks Rob!).
The main purpose of this series is to upstream the dts change and the binding document, but I wanted to see how far I could probe the GPU, to check that the binding is indeed correct. The rest of the patches are RFC/work-in-progress.
So this is tested on MT8183 with a chromeos-4.19 kernel, and a ton of backports to get the latest panfrost driver (I should probably try on linux-next at some point but this was the path of least resistance).
I tested it as a module as it's more challenging (originally probing would work built-in, on boot, but not as a module, as I didn't have the power domain changes, and all power domains are on by default during boot).
Probing logs looks like this, currently. They look sane. [ 501.319728] panfrost 13040000.gpu: clock rate = 511999970 [ 501.320041] panfrost 13040000.gpu: Linked as a consumer to regulator.14 [ 501.320102] panfrost 13040000.gpu: Linked as a consumer to regulator.31 [ 501.320651] panfrost 13040000.gpu: Linked as a consumer to genpd:0:13040000.gpu [ 501.320954] panfrost 13040000.gpu: Linked as a consumer to genpd:1:13040000.gpu [ 501.321062] panfrost 13040000.gpu: Linked as a consumer to genpd:2:13040000.gpu [ 501.321734] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0 [ 501.321741] panfrost 13040000.gpu: features: 00000000,13de77ff, issues: 00000000,00000400 [ 501.321747] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7 [ 501.321752] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1 [ 501.324951] [drm] Initialized panfrost 1.1.0 20180908 for 13040000.gpu on minor 2
Some more changes are still required to get devfreq working, and of course I do not have a userspace driver to test this with.
I believe at least patches 1 & 2 can be merged (2 depends on another patch series, so maybe we could start with 1 only for now...).
Thanks!
Nicolas Boichat (4): dt-bindings: gpu: mali-bifrost: Add Mediatek MT8183 arm64: dts: mt8183: Add node for the Mali GPU RFC: drm/panfrost: Add mt8183-mali compatible string RFC: drm/panfrost: devfreq: Add support for 2 regulators
.../bindings/gpu/arm,mali-bifrost.yaml | 25 +++++ arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 7 ++ arch/arm64/boot/dts/mediatek/mt8183.dtsi | 105 ++++++++++++++++++ drivers/gpu/drm/panfrost/panfrost_devfreq.c | 17 +++ drivers/gpu/drm/panfrost/panfrost_device.h | 1 + drivers/gpu/drm/panfrost/panfrost_drv.c | 11 ++ 6 files changed, 166 insertions(+)
-- 2.25.1.481.gfbce0eb801-goog
dri-devel@lists.freedesktop.org
-
Alyssa Rosenzweig -
kbuild test robot -
Nicolas Boichat