This series adds couple improvements to the TC358768 DSI bridge driver, enabling Panasonic VVX10F004B00 DSI panel support. This panel is used by ASUS Transformer TF700T tablet, which is ready for upstream kernel and display panel support is the biggest missing part.
Dmitry Osipenko (5): drm/bridge: tc358768: Enable reference clock drm/bridge: tc358768: Support pulse mode drm/bridge: tc358768: Calculate video start delay drm/bridge: tc358768: Disable non-continuous clock mode drm/bridge: tc358768: Correct BTACNTRL1 programming
drivers/gpu/drm/bridge/tc358768.c | 94 +++++++++++++++++++++++-------- 1 file changed, 71 insertions(+), 23 deletions(-)
The driver assumes that reference clock is always-enabled, but this is hardware-dependent and not true for ASUS Transformer TF700T. Make driver enable / disable the reference clock.
Tested-by: Andreas Westman Dorcsak hedmoo@yahoo.com # Asus TF700T Tested-by: Maxim Schwalm maxim.schwalm@gmail.com #TF700T Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/gpu/drm/bridge/tc358768.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c index a3db532bbdd1..18ae6605a803 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -237,6 +237,10 @@ static void tc358768_hw_enable(struct tc358768_priv *priv) if (priv->enabled) return;
+ ret = clk_prepare_enable(priv->refclk); + if (ret < 0) + dev_err(priv->dev, "error enabling refclk (%d)\n", ret); + ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies); if (ret < 0) dev_err(priv->dev, "error enabling regulators (%d)\n", ret); @@ -274,6 +278,8 @@ static void tc358768_hw_disable(struct tc358768_priv *priv) if (ret < 0) dev_err(priv->dev, "error disabling regulators (%d)\n", ret);
+ clk_disable_unprepare(priv->refclk); + priv->enabled = false; }
Hey Dmitry,
Thanks for submitting this series.
On Sun, 3 Oct 2021 at 01:35, Dmitry Osipenko digetx@gmail.com wrote:
The driver assumes that reference clock is always-enabled, but this is hardware-dependent and not true for ASUS Transformer TF700T. Make driver enable / disable the reference clock.
Tested-by: Andreas Westman Dorcsak hedmoo@yahoo.com # Asus TF700T Tested-by: Maxim Schwalm maxim.schwalm@gmail.com #TF700T Signed-off-by: Dmitry Osipenko digetx@gmail.com
drivers/gpu/drm/bridge/tc358768.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c index a3db532bbdd1..18ae6605a803 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -237,6 +237,10 @@ static void tc358768_hw_enable(struct tc358768_priv *priv) if (priv->enabled) return;
ret = clk_prepare_enable(priv->refclk);if (ret < 0)dev_err(priv->dev, "error enabling refclk (%d)\n", ret);ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies); if (ret < 0) dev_err(priv->dev, "error enabling regulators (%d)\n", ret);@@ -274,6 +278,8 @@ static void tc358768_hw_disable(struct tc358768_priv *priv) if (ret < 0) dev_err(priv->dev, "error disabling regulators (%d)\n", ret);
clk_disable_unprepare(priv->refclk);priv->enabled = false;}
Reviewed-by: Robert Foss robert.foss@linaro.org
Support pulse-mode synchronization which is supported and used by simple DSI panels like Panasonic VVX10F004B00.
Tested-by: Andreas Westman Dorcsak hedmoo@yahoo.com # Asus TF700T Tested-by: Maxim Schwalm maxim.schwalm@gmail.com #TF700T Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/gpu/drm/bridge/tc358768.c | 66 ++++++++++++++++++++++--------- 1 file changed, 48 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c index 18ae6605a803..10ebd0621ad3 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -785,24 +785,54 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) /* START[0] */ tc358768_write(priv, TC358768_STARTCNTRL, 1);
- /* Set event mode */ - tc358768_write(priv, TC358768_DSI_EVENT, 1); - - /* vsw (+ vbp) */ - tc358768_write(priv, TC358768_DSI_VSW, - mode->vtotal - mode->vsync_start); - /* vbp (not used in event mode) */ - tc358768_write(priv, TC358768_DSI_VBPR, 0); - /* vact */ - tc358768_write(priv, TC358768_DSI_VACT, mode->vdisplay); - - /* (hsw + hbp) * byteclk * ndl / pclk */ - val = (u32)div_u64((mode->htotal - mode->hsync_start) * - ((u64)priv->dsiclk / 4) * priv->dsi_lanes, - mode->clock * 1000); - tc358768_write(priv, TC358768_DSI_HSW, val); - /* hbp (not used in event mode) */ - tc358768_write(priv, TC358768_DSI_HBPR, 0); + if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { + /* Set pulse mode */ + tc358768_write(priv, TC358768_DSI_EVENT, 0); + + /* vact */ + tc358768_write(priv, TC358768_DSI_VACT, mode->vdisplay); + + /* vsw */ + tc358768_write(priv, TC358768_DSI_VSW, + mode->vsync_end - mode->vsync_start); + /* vbp */ + tc358768_write(priv, TC358768_DSI_VBPR, + mode->vtotal - mode->vsync_end); + + /* hsw * byteclk * ndl / pclk */ + val = (u32)div_u64((mode->hsync_end - mode->hsync_start) * + ((u64)priv->dsiclk / 4) * priv->dsi_lanes, + mode->clock * 1000); + tc358768_write(priv, TC358768_DSI_HSW, val); + + /* hbp * byteclk * ndl / pclk */ + val = (u32)div_u64((mode->htotal - mode->hsync_end) * + ((u64)priv->dsiclk / 4) * priv->dsi_lanes, + mode->clock * 1000); + tc358768_write(priv, TC358768_DSI_HBPR, val); + } else { + /* Set event mode */ + tc358768_write(priv, TC358768_DSI_EVENT, 1); + + /* vact */ + tc358768_write(priv, TC358768_DSI_VACT, mode->vdisplay); + + /* vsw (+ vbp) */ + tc358768_write(priv, TC358768_DSI_VSW, + mode->vtotal - mode->vsync_start); + /* vbp (not used in event mode) */ + tc358768_write(priv, TC358768_DSI_VBPR, 0); + + /* (hsw + hbp) * byteclk * ndl / pclk */ + val = (u32)div_u64((mode->htotal - mode->hsync_start) * + ((u64)priv->dsiclk / 4) * priv->dsi_lanes, + mode->clock * 1000); + tc358768_write(priv, TC358768_DSI_HSW, val); + + /* hbp (not used in event mode) */ + tc358768_write(priv, TC358768_DSI_HBPR, 0); + } + /* hact (bytes) */ tc358768_write(priv, TC358768_DSI_HACT, hact);
On Sun, 3 Oct 2021 at 01:35, Dmitry Osipenko digetx@gmail.com wrote:
Support pulse-mode synchronization which is supported and used by simple DSI panels like Panasonic VVX10F004B00.
Tested-by: Andreas Westman Dorcsak hedmoo@yahoo.com # Asus TF700T Tested-by: Maxim Schwalm maxim.schwalm@gmail.com #TF700T Signed-off-by: Dmitry Osipenko digetx@gmail.com
drivers/gpu/drm/bridge/tc358768.c | 66 ++++++++++++++++++++++--------- 1 file changed, 48 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c index 18ae6605a803..10ebd0621ad3 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -785,24 +785,54 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) /* START[0] */ tc358768_write(priv, TC358768_STARTCNTRL, 1);
/* Set event mode */tc358768_write(priv, TC358768_DSI_EVENT, 1);/* vsw (+ vbp) */tc358768_write(priv, TC358768_DSI_VSW,mode->vtotal - mode->vsync_start);/* vbp (not used in event mode) */tc358768_write(priv, TC358768_DSI_VBPR, 0);/* vact */tc358768_write(priv, TC358768_DSI_VACT, mode->vdisplay);/* (hsw + hbp) * byteclk * ndl / pclk */val = (u32)div_u64((mode->htotal - mode->hsync_start) *((u64)priv->dsiclk / 4) * priv->dsi_lanes,mode->clock * 1000);tc358768_write(priv, TC358768_DSI_HSW, val);/* hbp (not used in event mode) */tc358768_write(priv, TC358768_DSI_HBPR, 0);
if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {/* Set pulse mode */tc358768_write(priv, TC358768_DSI_EVENT, 0);/* vact */tc358768_write(priv, TC358768_DSI_VACT, mode->vdisplay);/* vsw */tc358768_write(priv, TC358768_DSI_VSW,mode->vsync_end - mode->vsync_start);/* vbp */tc358768_write(priv, TC358768_DSI_VBPR,mode->vtotal - mode->vsync_end);/* hsw * byteclk * ndl / pclk */val = (u32)div_u64((mode->hsync_end - mode->hsync_start) *((u64)priv->dsiclk / 4) * priv->dsi_lanes,mode->clock * 1000);tc358768_write(priv, TC358768_DSI_HSW, val);/* hbp * byteclk * ndl / pclk */val = (u32)div_u64((mode->htotal - mode->hsync_end) *((u64)priv->dsiclk / 4) * priv->dsi_lanes,mode->clock * 1000);tc358768_write(priv, TC358768_DSI_HBPR, val);} else {/* Set event mode */tc358768_write(priv, TC358768_DSI_EVENT, 1);/* vact */tc358768_write(priv, TC358768_DSI_VACT, mode->vdisplay);/* vsw (+ vbp) */tc358768_write(priv, TC358768_DSI_VSW,mode->vtotal - mode->vsync_start);/* vbp (not used in event mode) */tc358768_write(priv, TC358768_DSI_VBPR, 0);/* (hsw + hbp) * byteclk * ndl / pclk */val = (u32)div_u64((mode->htotal - mode->hsync_start) *((u64)priv->dsiclk / 4) * priv->dsi_lanes,mode->clock * 1000);tc358768_write(priv, TC358768_DSI_HSW, val);/* hbp (not used in event mode) */tc358768_write(priv, TC358768_DSI_HBPR, 0);}/* hact (bytes) */ tc358768_write(priv, TC358768_DSI_HACT, hact);
Reviewed-by: Robert Foss robert.foss@linaro.org
Calculate video start delay based on the display timing instead of hardcoding it to a default value. This fixes "trembling" display output on Asus Transformer TF700T which uses Panasonic VVX10F004B00 display panel.
Tested-by: Andreas Westman Dorcsak hedmoo@yahoo.com # Asus TF700T Tested-by: Maxim Schwalm maxim.schwalm@gmail.com #TF700T Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/gpu/drm/bridge/tc358768.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c index 10ebd0621ad3..5b3f8723bd3d 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -634,7 +634,8 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) u32 val, val2, lptxcnt, hact, data_type; const struct drm_display_mode *mode; u32 dsibclk_nsk, dsiclk_nsk, ui_nsk, phy_delay_nsk; - u32 dsiclk, dsibclk; + u32 dsiclk, dsibclk, video_start; + const u32 internal_delay = 40; int ret, i;
tc358768_hw_enable(priv); @@ -663,23 +664,27 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) case MIPI_DSI_FMT_RGB888: val |= (0x3 << 4); hact = mode->hdisplay * 3; + video_start = (mode->htotal - mode->hsync_start) * 3; data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24; break; case MIPI_DSI_FMT_RGB666: val |= (0x4 << 4); hact = mode->hdisplay * 3; + video_start = (mode->htotal - mode->hsync_start) * 3; data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18; break;
case MIPI_DSI_FMT_RGB666_PACKED: val |= (0x4 << 4) | BIT(3); hact = mode->hdisplay * 18 / 8; + video_start = (mode->htotal - mode->hsync_start) * 18 / 8; data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18; break;
case MIPI_DSI_FMT_RGB565: val |= (0x5 << 4); hact = mode->hdisplay * 2; + video_start = (mode->htotal - mode->hsync_start) * 2; data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16; break; default: @@ -690,7 +695,8 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) }
/* VSDly[9:0] */ - tc358768_write(priv, TC358768_VSDLY, 1); + video_start = max(video_start, internal_delay + 1) - internal_delay; + tc358768_write(priv, TC358768_VSDLY, video_start);
tc358768_write(priv, TC358768_DATAFMT, val); tc358768_write(priv, TC358768_DSITX_DT, data_type);
On Sun, 3 Oct 2021 at 01:35, Dmitry Osipenko digetx@gmail.com wrote:
Calculate video start delay based on the display timing instead of hardcoding it to a default value. This fixes "trembling" display output on Asus Transformer TF700T which uses Panasonic VVX10F004B00 display panel.
Tested-by: Andreas Westman Dorcsak hedmoo@yahoo.com # Asus TF700T Tested-by: Maxim Schwalm maxim.schwalm@gmail.com #TF700T Signed-off-by: Dmitry Osipenko digetx@gmail.com
drivers/gpu/drm/bridge/tc358768.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c index 10ebd0621ad3..5b3f8723bd3d 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -634,7 +634,8 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) u32 val, val2, lptxcnt, hact, data_type; const struct drm_display_mode *mode; u32 dsibclk_nsk, dsiclk_nsk, ui_nsk, phy_delay_nsk;
u32 dsiclk, dsibclk;
u32 dsiclk, dsibclk, video_start;const u32 internal_delay = 40; int ret, i; tc358768_hw_enable(priv);@@ -663,23 +664,27 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) case MIPI_DSI_FMT_RGB888: val |= (0x3 << 4); hact = mode->hdisplay * 3;
video_start = (mode->htotal - mode->hsync_start) * 3; data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24; break; case MIPI_DSI_FMT_RGB666: val |= (0x4 << 4); hact = mode->hdisplay * 3;video_start = (mode->htotal - mode->hsync_start) * 3; data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18; break; case MIPI_DSI_FMT_RGB666_PACKED: val |= (0x4 << 4) | BIT(3); hact = mode->hdisplay * 18 / 8;video_start = (mode->htotal - mode->hsync_start) * 18 / 8; data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18; break; case MIPI_DSI_FMT_RGB565: val |= (0x5 << 4); hact = mode->hdisplay * 2;video_start = (mode->htotal - mode->hsync_start) * 2; data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16; break; default:@@ -690,7 +695,8 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) }
/* VSDly[9:0] */
tc358768_write(priv, TC358768_VSDLY, 1);
video_start = max(video_start, internal_delay + 1) - internal_delay;tc358768_write(priv, TC358768_VSDLY, video_start); tc358768_write(priv, TC358768_DATAFMT, val); tc358768_write(priv, TC358768_DSITX_DT, data_type);-- 2.32.0
Reviewed-by: Robert Foss robert.foss@linaro.org
Non-continuous clock mode doesn't work because driver doesn't support it properly. The bridge driver programs wrong bitfields that are required by the non-continuous mode (BTACNTRL1 register bitfields are swapped in the code), but fixing them doesn't help.
Display panel of ASUS Transformer TF700T tablet supports non-continuous mode and display doesn't work at all using that mode. There are no device-trees that are actively using this DSI bridge in upstream yet, so clearly the broken mode wasn't ever tested properly. It's a bit too difficult to get LP mode working, hence let's disable the offending mode for now and fall back to continuous mode.
Tested-by: Andreas Westman Dorcsak hedmoo@yahoo.com # Asus TF700T Tested-by: Maxim Schwalm maxim.schwalm@gmail.com #TF700T Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/gpu/drm/bridge/tc358768.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c index 5b3f8723bd3d..cfceba5ef3b8 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -631,6 +631,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) { struct tc358768_priv *priv = bridge_to_tc358768(bridge); struct mipi_dsi_device *dsi_dev = priv->output.dev; + unsigned long mode_flags = dsi_dev->mode_flags; u32 val, val2, lptxcnt, hact, data_type; const struct drm_display_mode *mode; u32 dsibclk_nsk, dsiclk_nsk, ui_nsk, phy_delay_nsk; @@ -638,6 +639,11 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) const u32 internal_delay = 40; int ret, i;
+ if (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { + dev_warn_once(priv->dev, "Non-continuous mode unimplemented, falling back to continuous\n"); + mode_flags &= ~MIPI_DSI_CLOCK_NON_CONTINUOUS; + } + tc358768_hw_enable(priv);
ret = tc358768_sw_reset(priv); @@ -776,7 +782,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) val |= BIT(i + 1); tc358768_write(priv, TC358768_HSTXVREGEN, val);
- if (!(dsi_dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) + if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) tc358768_write(priv, TC358768_TXOPTIONCNTRL, 0x1);
/* TXTAGOCNT[26:16] RXTASURECNT[10:0] */ @@ -864,7 +870,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) if (!(dsi_dev->mode_flags & MIPI_DSI_MODE_LPM)) val |= TC358768_DSI_CONTROL_TXMD;
- if (!(dsi_dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) + if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) val |= TC358768_DSI_CONTROL_HSCKMD;
if (dsi_dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)
On Sun, 3 Oct 2021 at 01:35, Dmitry Osipenko digetx@gmail.com wrote:
Non-continuous clock mode doesn't work because driver doesn't support it properly. The bridge driver programs wrong bitfields that are required by the non-continuous mode (BTACNTRL1 register bitfields are swapped in the code), but fixing them doesn't help.
Display panel of ASUS Transformer TF700T tablet supports non-continuous mode and display doesn't work at all using that mode. There are no device-trees that are actively using this DSI bridge in upstream yet, so clearly the broken mode wasn't ever tested properly. It's a bit too difficult to get LP mode working, hence let's disable the offending mode for now and fall back to continuous mode.
Tested-by: Andreas Westman Dorcsak hedmoo@yahoo.com # Asus TF700T Tested-by: Maxim Schwalm maxim.schwalm@gmail.com #TF700T Signed-off-by: Dmitry Osipenko digetx@gmail.com
drivers/gpu/drm/bridge/tc358768.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c index 5b3f8723bd3d..cfceba5ef3b8 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -631,6 +631,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) { struct tc358768_priv *priv = bridge_to_tc358768(bridge); struct mipi_dsi_device *dsi_dev = priv->output.dev;
unsigned long mode_flags = dsi_dev->mode_flags; u32 val, val2, lptxcnt, hact, data_type; const struct drm_display_mode *mode; u32 dsibclk_nsk, dsiclk_nsk, ui_nsk, phy_delay_nsk;@@ -638,6 +639,11 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) const u32 internal_delay = 40; int ret, i;
if (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {dev_warn_once(priv->dev, "Non-continuous mode unimplemented, falling back to continuous\n");mode_flags &= ~MIPI_DSI_CLOCK_NON_CONTINUOUS;}tc358768_hw_enable(priv); ret = tc358768_sw_reset(priv);@@ -776,7 +782,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) val |= BIT(i + 1); tc358768_write(priv, TC358768_HSTXVREGEN, val);
if (!(dsi_dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) tc358768_write(priv, TC358768_TXOPTIONCNTRL, 0x1); /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */@@ -864,7 +870,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) if (!(dsi_dev->mode_flags & MIPI_DSI_MODE_LPM)) val |= TC358768_DSI_CONTROL_TXMD;
if (!(dsi_dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) val |= TC358768_DSI_CONTROL_HSCKMD; if (dsi_dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)--
Reviewed-by: Robert Foss robert.foss@linaro.org
TXTAGOCNT and RXTASURECNT bitfields of BTACNTRL1 register are swapped in the code, correct them. Driver doesn't implement low power mode for now, so this change doesn't make a practical difference yet.
Tested-by: Andreas Westman Dorcsak hedmoo@yahoo.com # Asus TF700T Tested-by: Maxim Schwalm maxim.schwalm@gmail.com #TF700T Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/gpu/drm/bridge/tc358768.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c index cfceba5ef3b8..fd585bf925fe 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -790,7 +790,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 1; val2 = tc358768_ns_to_cnt(tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk), dsibclk_nsk) - 2; - val |= val2 << 16; + val = val << 16 | val2; dev_dbg(priv->dev, "BTACNTRL1: 0x%x\n", val); tc358768_write(priv, TC358768_BTACNTRL1, val);
On Sun, 3 Oct 2021 at 01:35, Dmitry Osipenko digetx@gmail.com wrote:
TXTAGOCNT and RXTASURECNT bitfields of BTACNTRL1 register are swapped in the code, correct them. Driver doesn't implement low power mode for now, so this change doesn't make a practical difference yet.
Tested-by: Andreas Westman Dorcsak hedmoo@yahoo.com # Asus TF700T Tested-by: Maxim Schwalm maxim.schwalm@gmail.com #TF700T Signed-off-by: Dmitry Osipenko digetx@gmail.com
drivers/gpu/drm/bridge/tc358768.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c index cfceba5ef3b8..fd585bf925fe 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -790,7 +790,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 1; val2 = tc358768_ns_to_cnt(tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk), dsibclk_nsk) - 2;
val |= val2 << 16;
val = val << 16 | val2; dev_dbg(priv->dev, "BTACNTRL1: 0x%x\n", val); tc358768_write(priv, TC358768_BTACNTRL1, val);
Reviewed-by: Robert Foss robert.foss@linaro.org
Applied to drm-misc-next
On Sun, 3 Oct 2021 at 01:35, Dmitry Osipenko digetx@gmail.com wrote:
This series adds couple improvements to the TC358768 DSI bridge driver, enabling Panasonic VVX10F004B00 DSI panel support. This panel is used by ASUS Transformer TF700T tablet, which is ready for upstream kernel and display panel support is the biggest missing part.
Dmitry Osipenko (5): drm/bridge: tc358768: Enable reference clock drm/bridge: tc358768: Support pulse mode drm/bridge: tc358768: Calculate video start delay drm/bridge: tc358768: Disable non-continuous clock mode drm/bridge: tc358768: Correct BTACNTRL1 programming
drivers/gpu/drm/bridge/tc358768.c | 94 +++++++++++++++++++++++-------- 1 file changed, 71 insertions(+), 23 deletions(-)
-- 2.32.0
19.10.2021 12:47, Robert Foss пишет:
Applied to drm-misc-next
On Sun, 3 Oct 2021 at 01:35, Dmitry Osipenko digetx@gmail.com wrote:
This series adds couple improvements to the TC358768 DSI bridge driver, enabling Panasonic VVX10F004B00 DSI panel support. This panel is used by ASUS Transformer TF700T tablet, which is ready for upstream kernel and display panel support is the biggest missing part.
Dmitry Osipenko (5): drm/bridge: tc358768: Enable reference clock drm/bridge: tc358768: Support pulse mode drm/bridge: tc358768: Calculate video start delay drm/bridge: tc358768: Disable non-continuous clock mode drm/bridge: tc358768: Correct BTACNTRL1 programming
drivers/gpu/drm/bridge/tc358768.c | 94 +++++++++++++++++++++++-------- 1 file changed, 71 insertions(+), 23 deletions(-)
-- 2.32.0
Robert, thank you for taking care of these patches! Now nothing is holding us from upstreaming the device-tree of the Transformer tablet.
19.10.2021 23:37, Dmitry Osipenko пишет:
19.10.2021 12:47, Robert Foss пишет:
Applied to drm-misc-next
On Sun, 3 Oct 2021 at 01:35, Dmitry Osipenko digetx@gmail.com wrote:
This series adds couple improvements to the TC358768 DSI bridge driver, enabling Panasonic VVX10F004B00 DSI panel support. This panel is used by ASUS Transformer TF700T tablet, which is ready for upstream kernel and display panel support is the biggest missing part.
Dmitry Osipenko (5): drm/bridge: tc358768: Enable reference clock drm/bridge: tc358768: Support pulse mode drm/bridge: tc358768: Calculate video start delay drm/bridge: tc358768: Disable non-continuous clock mode drm/bridge: tc358768: Correct BTACNTRL1 programming
drivers/gpu/drm/bridge/tc358768.c | 94 +++++++++++++++++++++++-------- 1 file changed, 71 insertions(+), 23 deletions(-)
-- 2.32.0
Robert, thank you for taking care of these patches! Now nothing is holding us from upstreaming the device-tree of the Transformer tablet.
Hello Robert,
These patches spent 2 months in drm-misc-next, will they graduate into v5.17 or something special needs to be done for that?
Hey Dmitry,
On Sun, 19 Dec 2021 at 17:02, Dmitry Osipenko digetx@gmail.com wrote:
19.10.2021 23:37, Dmitry Osipenko пишет:
19.10.2021 12:47, Robert Foss пишет:
Applied to drm-misc-next
On Sun, 3 Oct 2021 at 01:35, Dmitry Osipenko digetx@gmail.com wrote:
This series adds couple improvements to the TC358768 DSI bridge driver, enabling Panasonic VVX10F004B00 DSI panel support. This panel is used by ASUS Transformer TF700T tablet, which is ready for upstream kernel and display panel support is the biggest missing part.
Dmitry Osipenko (5): drm/bridge: tc358768: Enable reference clock drm/bridge: tc358768: Support pulse mode drm/bridge: tc358768: Calculate video start delay drm/bridge: tc358768: Disable non-continuous clock mode drm/bridge: tc358768: Correct BTACNTRL1 programming
drivers/gpu/drm/bridge/tc358768.c | 94 +++++++++++++++++++++++-------- 1 file changed, 71 insertions(+), 23 deletions(-)
-- 2.32.0
Robert, thank you for taking care of these patches! Now nothing is holding us from upstreaming the device-tree of the Transformer tablet.
Hello Robert,
These patches spent 2 months in drm-misc-next, will they graduate into v5.17 or something special needs to be done for that?
They series has landed in linux-next, and will be in v5.17 if nothing catastrophic happens.
Rob.
21.12.2021 21:10, Robert Foss пишет:
Hey Dmitry,
On Sun, 19 Dec 2021 at 17:02, Dmitry Osipenko digetx@gmail.com wrote:
19.10.2021 23:37, Dmitry Osipenko пишет:
19.10.2021 12:47, Robert Foss пишет:
Applied to drm-misc-next
On Sun, 3 Oct 2021 at 01:35, Dmitry Osipenko digetx@gmail.com wrote:
This series adds couple improvements to the TC358768 DSI bridge driver, enabling Panasonic VVX10F004B00 DSI panel support. This panel is used by ASUS Transformer TF700T tablet, which is ready for upstream kernel and display panel support is the biggest missing part.
Dmitry Osipenko (5): drm/bridge: tc358768: Enable reference clock drm/bridge: tc358768: Support pulse mode drm/bridge: tc358768: Calculate video start delay drm/bridge: tc358768: Disable non-continuous clock mode drm/bridge: tc358768: Correct BTACNTRL1 programming
drivers/gpu/drm/bridge/tc358768.c | 94 +++++++++++++++++++++++-------- 1 file changed, 71 insertions(+), 23 deletions(-)
-- 2.32.0
Robert, thank you for taking care of these patches! Now nothing is holding us from upstreaming the device-tree of the Transformer tablet.
Hello Robert,
These patches spent 2 months in drm-misc-next, will they graduate into v5.17 or something special needs to be done for that?
They series has landed in linux-next, and will be in v5.17 if nothing catastrophic happens.
Very good to know, thank you!
dri-devel@lists.freedesktop.org
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Dmitry Osipenko -
Robert Foss