The header contains only declaration of one function, the rest of exynos plane declaration is in exynos_drm_drv.h. Let's merge it together.

Signed-off-by: Andrzej Hajda a.hajda@samsung.com --- drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 1 - drivers/gpu/drm/exynos/exynos7_drm_decon.c | 1 - drivers/gpu/drm/exynos/exynos_drm_crtc.c | 1 - drivers/gpu/drm/exynos/exynos_drm_drv.c | 1 - drivers/gpu/drm/exynos/exynos_drm_drv.h | 4 ++++ drivers/gpu/drm/exynos/exynos_drm_fimd.c | 1 - drivers/gpu/drm/exynos/exynos_drm_plane.c | 1 - drivers/gpu/drm/exynos/exynos_drm_plane.h | 14 -------------- drivers/gpu/drm/exynos/exynos_drm_vidi.c | 1 - drivers/gpu/drm/exynos/exynos_mixer.c | 1 - 10 files changed, 4 insertions(+), 22 deletions(-) delete mode 100644 drivers/gpu/drm/exynos/exynos_drm_plane.h

diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c index bdfec5f977e9..24df0b307b2f 100644 --- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c @@ -24,7 +24,6 @@ #include "exynos_drm_drv.h" #include "exynos_drm_crtc.h" #include "exynos_drm_fb.h" -#include "exynos_drm_plane.h" #include "regs-decon5433.h"

#define DSD_CFG_MUX 0x1004 diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c b/drivers/gpu/drm/exynos/exynos7_drm_decon.c index 381aa3d60e37..812941b84287 100644 --- a/drivers/gpu/drm/exynos/exynos7_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos7_drm_decon.c @@ -27,7 +27,6 @@ #include <video/of_videomode.h>

#include "exynos_drm_crtc.h" -#include "exynos_drm_plane.h" #include "exynos_drm_drv.h" #include "exynos_drm_fb.h" #include "regs-decon7.h" diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c b/drivers/gpu/drm/exynos/exynos_drm_crtc.c index 96ee83a798c4..1eebfa3fa8da 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c @@ -20,7 +20,6 @@

#include "exynos_drm_crtc.h" #include "exynos_drm_drv.h" -#include "exynos_drm_plane.h"

static void exynos_drm_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c b/drivers/gpu/drm/exynos/exynos_drm_drv.c index e1ef9dc9ebf3..2155586646dc 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.c +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c @@ -26,7 +26,6 @@ #include "exynos_drm_fbdev.h" #include "exynos_drm_fb.h" #include "exynos_drm_gem.h" -#include "exynos_drm_plane.h" #include "exynos_drm_ipp.h" #include "exynos_drm_vidi.h" #include "exynos_drm_g2d.h" diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h index 71eb240bc1f4..6e38d0dc4457 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.h +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h @@ -113,6 +113,10 @@ struct exynos_drm_plane_config { unsigned int capabilities; };

+int exynos_plane_init(struct drm_device *dev, + struct exynos_drm_plane *exynos_plane, unsigned int index, + const struct exynos_drm_plane_config *config); + /* * Exynos drm crtc ops * diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index 46588a14f0c3..b1a9502a4140 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -31,7 +31,6 @@ #include "exynos_drm_drv.h" #include "exynos_drm_fb.h" #include "exynos_drm_crtc.h" -#include "exynos_drm_plane.h"

/* * FIMD stands for Fully Interactive Mobile Display and diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c index df0508e0e49e..8af0eba3f362 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_plane.c +++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c @@ -19,7 +19,6 @@ #include "exynos_drm_crtc.h" #include "exynos_drm_fb.h" #include "exynos_drm_gem.h" -#include "exynos_drm_plane.h"

/* * This function is to get X or Y size shown via screen. This needs length and diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.h b/drivers/gpu/drm/exynos/exynos_drm_plane.h deleted file mode 100644 index 497047b19614..000000000000 --- a/drivers/gpu/drm/exynos/exynos_drm_plane.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (C) 2011 Samsung Electronics Co.Ltd - * Authors: Joonyoung Shim jy0922.shim@samsung.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -int exynos_plane_init(struct drm_device *dev, - struct exynos_drm_plane *exynos_plane, unsigned int index, - const struct exynos_drm_plane_config *config); diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.c b/drivers/gpu/drm/exynos/exynos_drm_vidi.c index 29f4c1932aed..ec30d5aca9aa 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_vidi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_vidi.c @@ -26,7 +26,6 @@ #include "exynos_drm_drv.h" #include "exynos_drm_crtc.h" #include "exynos_drm_fb.h" -#include "exynos_drm_plane.h" #include "exynos_drm_vidi.h"

/* VIDI uses fixed refresh rate of 50Hz */ diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index f35e4ab55b27..ef50943cc9eb 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c @@ -40,7 +40,6 @@ #include "exynos_drm_drv.h" #include "exynos_drm_crtc.h" #include "exynos_drm_fb.h" -#include "exynos_drm_plane.h"

#define MIXER_WIN_NR 3 #define VP_DEFAULT_WIN 2

exynos_drm_plane_config must be present for every plane, and most fields are redundant with exynos_drm_plane: - pixel_formats, num_pixel_formats are stored in plane.base.format_*, - type is stored in plane.base.type, - zpos is always equal to plane.index. The only non-redundant field capabilities can be moved to exynos_drm_plane. As consequence of removing the structure some code should be refactored. The patch should not have functional changes.

Signed-off-by: Andrzej Hajda a.hajda@samsung.com --- drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 18 +++--- drivers/gpu/drm/exynos/exynos7_drm_decon.c | 11 +--- drivers/gpu/drm/exynos/exynos_drm_drv.h | 39 ++++--------- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 17 ++---- drivers/gpu/drm/exynos/exynos_drm_plane.c | 56 +++++++++--------- drivers/gpu/drm/exynos/exynos_drm_vidi.c | 11 +--- drivers/gpu/drm/exynos/exynos_mixer.c | 58 +++++++------------ 7 files changed, 76 insertions(+), 134 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c index 24df0b307b2f..ae0f475eb633 100644 --- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c @@ -56,7 +56,6 @@ struct decon_context { struct drm_device *drm_dev; struct exynos_drm_crtc *crtc; struct exynos_drm_plane planes[WINDOWS_NR]; - struct exynos_drm_plane_config configs[WINDOWS_NR]; void __iomem *addr; struct regmap *sysreg; struct clk *clks[ARRAY_SIZE(decon_clks_name)]; @@ -608,22 +607,19 @@ static int decon_bind(struct device *dev, struct device *master, void *data) struct drm_device *drm_dev = data; struct exynos_drm_plane *exynos_plane; enum exynos_drm_output_type out_type; - unsigned int win; + unsigned int i; int ret;

ctx->drm_dev = drm_dev;

- for (win = ctx->first_win; win < WINDOWS_NR; win++) { - ctx->configs[win].pixel_formats = decon_formats; - ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats); - ctx->configs[win].zpos = win - ctx->first_win; - ctx->configs[win].type = decon_win_types[win]; - ctx->configs[win].capabilities = EXYNOS_DRM_PLANE_CAP_ZPOS + for (i = ctx->first_win; i < WINDOWS_NR; i++) { + ctx->planes[i].index = i - ctx->first_win; + ctx->planes[i].capabilities = EXYNOS_DRM_PLANE_CAP_ZPOS | EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND; - - ret = exynos_plane_init(drm_dev, &ctx->planes[win], win, - &ctx->configs[win]); + ret = exynos_plane_init(drm_dev, &ctx->planes[i], + decon_formats, ARRAY_SIZE(decon_formats), + decon_win_types[i]); if (ret) return ret; } diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c b/drivers/gpu/drm/exynos/exynos7_drm_decon.c index 812941b84287..6d462f057531 100644 --- a/drivers/gpu/drm/exynos/exynos7_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos7_drm_decon.c @@ -44,7 +44,6 @@ struct decon_context { struct drm_device *drm_dev; struct exynos_drm_crtc *crtc; struct exynos_drm_plane planes[WINDOWS_NR]; - struct exynos_drm_plane_config configs[WINDOWS_NR]; struct clk *pclk; struct clk *aclk; struct clk *eclk; @@ -626,13 +625,9 @@ static int decon_bind(struct device *dev, struct device *master, void *data) }

for (i = 0; i < WINDOWS_NR; i++) { - ctx->configs[i].pixel_formats = decon_formats; - ctx->configs[i].num_pixel_formats = ARRAY_SIZE(decon_formats); - ctx->configs[i].zpos = i; - ctx->configs[i].type = decon_win_types[i]; - - ret = exynos_plane_init(drm_dev, &ctx->planes[i], i, - &ctx->configs[i]); + ctx->planes[i].index = i; + ret = exynos_plane_init(drm_dev, &ctx->planes[i], decon_formats, + ARRAY_SIZE(decon_formats), decon_win_types[i]); if (ret) return ret; } diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h index 1f6bb5516170..1d4ef0245958 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.h +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h @@ -71,11 +71,19 @@ to_exynos_plane_state(struct drm_plane_state *state) return container_of(state, struct exynos_drm_plane_state, base); }

+#define EXYNOS_DRM_PLANE_CAP_DOUBLE (1 << 0) +#define EXYNOS_DRM_PLANE_CAP_SCALE (1 << 1) +#define EXYNOS_DRM_PLANE_CAP_ZPOS (1 << 2) +#define EXYNOS_DRM_PLANE_CAP_TILE (1 << 3) +#define EXYNOS_DRM_PLANE_CAP_PIX_BLEND (1 << 4) +#define EXYNOS_DRM_PLANE_CAP_WIN_BLEND (1 << 5) + /* * Exynos drm common overlay structure. * * @base: plane object * @index: hardware index of the overlay layer + * @capabilities: supported features (see EXYNOS_DRM_PLANE_CAP_*) * * this structure is common to exynos SoC and its contents would be copied * to hardware specific overlay info. @@ -83,38 +91,13 @@ to_exynos_plane_state(struct drm_plane_state *state)

struct exynos_drm_plane { struct drm_plane base; - const struct exynos_drm_plane_config *config; unsigned int index; -}; - -#define EXYNOS_DRM_PLANE_CAP_DOUBLE (1 << 0) -#define EXYNOS_DRM_PLANE_CAP_SCALE (1 << 1) -#define EXYNOS_DRM_PLANE_CAP_ZPOS (1 << 2) -#define EXYNOS_DRM_PLANE_CAP_TILE (1 << 3) -#define EXYNOS_DRM_PLANE_CAP_PIX_BLEND (1 << 4) -#define EXYNOS_DRM_PLANE_CAP_WIN_BLEND (1 << 5) - -/* - * Exynos DRM plane configuration structure. - * - * @zpos: initial z-position of the plane. - * @type: type of the plane (primary, cursor or overlay). - * @pixel_formats: supported pixel formats. - * @num_pixel_formats: number of elements in 'pixel_formats'. - * @capabilities: supported features (see EXYNOS_DRM_PLANE_CAP_*) - */ - -struct exynos_drm_plane_config { - unsigned int zpos; - enum drm_plane_type type; - const uint32_t *pixel_formats; - unsigned int num_pixel_formats; unsigned int capabilities; };

-int exynos_plane_init(struct drm_device *dev, - struct exynos_drm_plane *exynos_plane, unsigned int index, - const struct exynos_drm_plane_config *config); +int exynos_plane_init(struct drm_device *dev, struct exynos_drm_plane *plane, + const uint32_t *pixel_formats, int num_pixel_formats, + enum drm_plane_type type);

/* * Exynos drm crtc ops diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index b1a9502a4140..2d34ca375ee1 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -171,7 +171,6 @@ struct fimd_context { struct drm_device *drm_dev; struct exynos_drm_crtc *crtc; struct exynos_drm_plane planes[WINDOWS_NR]; - struct exynos_drm_plane_config configs[WINDOWS_NR]; struct clk *bus_clk; struct clk *lcd_clk; void __iomem *regs; @@ -1044,16 +1043,12 @@ static int fimd_bind(struct device *dev, struct device *master, void *data) ctx->drm_dev = drm_dev;

for (i = 0; i < WINDOWS_NR; i++) { - ctx->configs[i].pixel_formats = fimd_formats; - ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats); - ctx->configs[i].zpos = i; - ctx->configs[i].type = fimd_win_types[i]; - ctx->configs[i].capabilities = EXYNOS_DRM_PLANE_CAP_ZPOS - | EXYNOS_DRM_PLANE_CAP_WIN_BLEND - | EXYNOS_DRM_PLANE_CAP_PIX_BLEND; - - ret = exynos_plane_init(drm_dev, &ctx->planes[i], i, - &ctx->configs[i]); + ctx->planes[i].index = i; + ctx->planes[i].capabilities = EXYNOS_DRM_PLANE_CAP_ZPOS + | EXYNOS_DRM_PLANE_CAP_WIN_BLEND + | EXYNOS_DRM_PLANE_CAP_PIX_BLEND; + ret = exynos_plane_init(drm_dev, &ctx->planes[i], fimd_formats, + ARRAY_SIZE(fimd_formats), fimd_win_types[i]); if (ret) return ret; } diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c index 8af0eba3f362..e1aa504539fa 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_plane.c +++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c @@ -138,7 +138,7 @@ static void exynos_drm_plane_reset(struct drm_plane *plane) exynos_state = kzalloc(sizeof(*exynos_state), GFP_KERNEL); if (exynos_state) { __drm_atomic_helper_plane_reset(plane, &exynos_state->base); - plane->state->zpos = exynos_plane->config->zpos; + plane->state->zpos = exynos_plane->index; } }

@@ -176,14 +176,14 @@ static struct drm_plane_funcs exynos_plane_funcs = { };

static int -exynos_drm_plane_check_format(const struct exynos_drm_plane_config *config, - struct exynos_drm_plane_state *state) +exynos_drm_plane_check_format(struct exynos_drm_plane_state *state) { + struct exynos_drm_plane *plane = to_exynos_plane(state->base.plane); struct drm_framebuffer *fb = state->base.fb;

switch (fb->modifier) { case DRM_FORMAT_MOD_SAMSUNG_64_32_TILE: - if (!(config->capabilities & EXYNOS_DRM_PLANE_CAP_TILE)) + if (!(plane->capabilities & EXYNOS_DRM_PLANE_CAP_TILE)) return -ENOTSUPP; break;

@@ -199,12 +199,12 @@ exynos_drm_plane_check_format(const struct exynos_drm_plane_config *config, }

static int -exynos_drm_plane_check_size(const struct exynos_drm_plane_config *config, - struct exynos_drm_plane_state *state) +exynos_drm_plane_check_size(struct exynos_drm_plane_state *state) { + struct exynos_drm_plane *plane = to_exynos_plane(state->base.plane); bool width_ok = false, height_ok = false;

- if (config->capabilities & EXYNOS_DRM_PLANE_CAP_SCALE) + if (plane->capabilities & EXYNOS_DRM_PLANE_CAP_SCALE) return 0;

if (state->src.w == state->crtc.w) @@ -213,11 +213,11 @@ exynos_drm_plane_check_size(const struct exynos_drm_plane_config *config, if (state->src.h == state->crtc.h) height_ok = true;

- if ((config->capabilities & EXYNOS_DRM_PLANE_CAP_DOUBLE) && + if ((plane->capabilities & EXYNOS_DRM_PLANE_CAP_DOUBLE) && state->h_ratio == (1 << 15)) width_ok = true;

- if ((config->capabilities & EXYNOS_DRM_PLANE_CAP_DOUBLE) && + if ((plane->capabilities & EXYNOS_DRM_PLANE_CAP_DOUBLE) && state->v_ratio == (1 << 15)) height_ok = true;

@@ -231,7 +231,6 @@ exynos_drm_plane_check_size(const struct exynos_drm_plane_config *config, static int exynos_plane_atomic_check(struct drm_plane *plane, struct drm_plane_state *state) { - struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane); struct exynos_drm_plane_state *exynos_state = to_exynos_plane_state(state); int ret = 0; @@ -242,11 +241,11 @@ static int exynos_plane_atomic_check(struct drm_plane *plane, /* translate state into exynos_state */ exynos_plane_mode_set(exynos_state);

- ret = exynos_drm_plane_check_format(exynos_plane->config, exynos_state); + ret = exynos_drm_plane_check_format(exynos_state); if (ret) return ret;

- ret = exynos_drm_plane_check_size(exynos_plane->config, exynos_state); + ret = exynos_drm_plane_check_size(exynos_state); return ret; }

@@ -292,40 +291,37 @@ static void exynos_plane_attach_zpos_property(struct drm_plane *plane, drm_plane_create_zpos_property(plane, zpos, 0, MAX_PLANE - 1); }

-int exynos_plane_init(struct drm_device *dev, - struct exynos_drm_plane *exynos_plane, unsigned int index, - const struct exynos_drm_plane_config *config) +int exynos_plane_init(struct drm_device *dev, struct exynos_drm_plane *plane, + const uint32_t *pixel_formats, int num_pixel_formats, + enum drm_plane_type type) { int err; unsigned int supported_modes = BIT(DRM_MODE_BLEND_PIXEL_NONE) | BIT(DRM_MODE_BLEND_PREMULTI) | BIT(DRM_MODE_BLEND_COVERAGE); - struct drm_plane *plane = &exynos_plane->base; + struct drm_plane *bplane = &plane->base;

- err = drm_universal_plane_init(dev, &exynos_plane->base, + err = drm_universal_plane_init(dev, bplane, 1 << dev->mode_config.num_crtc, &exynos_plane_funcs, - config->pixel_formats, - config->num_pixel_formats, - NULL, config->type, NULL); + pixel_formats, + num_pixel_formats, + NULL, type, NULL); if (err) { DRM_ERROR("failed to initialize plane\n"); return err; }

- drm_plane_helper_add(&exynos_plane->base, &plane_helper_funcs); - - exynos_plane->index = index; - exynos_plane->config = config; + drm_plane_helper_add(bplane, &plane_helper_funcs);

- exynos_plane_attach_zpos_property(&exynos_plane->base, config->zpos, - !(config->capabilities & EXYNOS_DRM_PLANE_CAP_ZPOS)); + exynos_plane_attach_zpos_property(bplane, plane->index, + !(plane->capabilities & EXYNOS_DRM_PLANE_CAP_ZPOS));

- if (config->capabilities & EXYNOS_DRM_PLANE_CAP_PIX_BLEND) - drm_plane_create_blend_mode_property(plane, supported_modes); + if (plane->capabilities & EXYNOS_DRM_PLANE_CAP_PIX_BLEND) + drm_plane_create_blend_mode_property(bplane, supported_modes);

- if (config->capabilities & EXYNOS_DRM_PLANE_CAP_WIN_BLEND) - drm_plane_create_alpha_property(plane); + if (plane->capabilities & EXYNOS_DRM_PLANE_CAP_WIN_BLEND) + drm_plane_create_alpha_property(bplane);

return 0; } diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.c b/drivers/gpu/drm/exynos/exynos_drm_vidi.c index ec30d5aca9aa..b61ae3415b8c 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_vidi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_vidi.c @@ -378,21 +378,14 @@ static int vidi_bind(struct device *dev, struct device *master, void *data) struct drm_device *drm_dev = data; struct drm_encoder *encoder = &ctx->encoder; struct exynos_drm_plane *exynos_plane; - struct exynos_drm_plane_config plane_config = { 0 }; unsigned int i; int ret;

ctx->drm_dev = drm_dev;

- plane_config.pixel_formats = formats; - plane_config.num_pixel_formats = ARRAY_SIZE(formats); - for (i = 0; i < WINDOWS_NR; i++) { - plane_config.zpos = i; - plane_config.type = vidi_win_types[i]; - - ret = exynos_plane_init(drm_dev, &ctx->planes[i], i, - &plane_config); + ret = exynos_plane_init(drm_dev, &ctx->planes[i], formats, + ARRAY_SIZE(formats), vidi_win_types[i]); if (ret) return ret; } diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index ef50943cc9eb..1c82265acf0a 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c @@ -123,37 +123,6 @@ struct mixer_drv_data { bool has_sclk; };

-static const struct exynos_drm_plane_config plane_configs[MIXER_WIN_NR] = { - { - .zpos = 0, - .type = DRM_PLANE_TYPE_PRIMARY, - .pixel_formats = mixer_formats, - .num_pixel_formats = ARRAY_SIZE(mixer_formats), - .capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE | - EXYNOS_DRM_PLANE_CAP_ZPOS | - EXYNOS_DRM_PLANE_CAP_PIX_BLEND | - EXYNOS_DRM_PLANE_CAP_WIN_BLEND, - }, { - .zpos = 1, - .type = DRM_PLANE_TYPE_CURSOR, - .pixel_formats = mixer_formats, - .num_pixel_formats = ARRAY_SIZE(mixer_formats), - .capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE | - EXYNOS_DRM_PLANE_CAP_ZPOS | - EXYNOS_DRM_PLANE_CAP_PIX_BLEND | - EXYNOS_DRM_PLANE_CAP_WIN_BLEND, - }, { - .zpos = 2, - .type = DRM_PLANE_TYPE_OVERLAY, - .pixel_formats = vp_formats, - .num_pixel_formats = ARRAY_SIZE(vp_formats), - .capabilities = EXYNOS_DRM_PLANE_CAP_SCALE | - EXYNOS_DRM_PLANE_CAP_ZPOS | - EXYNOS_DRM_PLANE_CAP_TILE | - EXYNOS_DRM_PLANE_CAP_WIN_BLEND, - }, -}; - static const u8 filter_y_horiz_tap8[] = { 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, 0, 0, @@ -1173,18 +1142,33 @@ static int mixer_bind(struct device *dev, struct device *manager, void *data) struct exynos_drm_plane *exynos_plane; unsigned int i; int ret; + static enum drm_plane_type types[] = { DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_CURSOR, DRM_PLANE_TYPE_OVERLAY };

ret = mixer_initialize(ctx, drm_dev); if (ret) return ret;

- for (i = 0; i < MIXER_WIN_NR; i++) { - if (i == VP_DEFAULT_WIN && !test_bit(MXR_BIT_VP_ENABLED, - &ctx->flags)) - continue; + for (i = 0; i < VP_DEFAULT_WIN; i++) { + ctx->planes[i].index = i; + ctx->planes[i].capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE | + EXYNOS_DRM_PLANE_CAP_ZPOS | + EXYNOS_DRM_PLANE_CAP_PIX_BLEND | + EXYNOS_DRM_PLANE_CAP_WIN_BLEND; + ret = exynos_plane_init(drm_dev, &ctx->planes[i], mixer_formats, + ARRAY_SIZE(mixer_formats), types[i]); + if (ret) + return ret; + }

- ret = exynos_plane_init(drm_dev, &ctx->planes[i], i, - &plane_configs[i]); + if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) { + ctx->planes[i].index = i; + ctx->planes[i].capabilities = EXYNOS_DRM_PLANE_CAP_SCALE | + EXYNOS_DRM_PLANE_CAP_ZPOS | + EXYNOS_DRM_PLANE_CAP_TILE | + EXYNOS_DRM_PLANE_CAP_WIN_BLEND; + ret = exynos_plane_init(drm_dev, &ctx->planes[i], vp_formats, + ARRAY_SIZE(vp_formats), types[i]); if (ret) return ret; }

Since crtc maps 1:1 to the device there is no point in allocating it separately, another benefit is possibility of direct initialisation of its fields which is more readable and allows further expansion.

Signed-off-by: Andrzej Hajda a.hajda@samsung.com --- drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 52 +++++++++---------- 1 file changed, 26 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c index ae0f475eb633..0d409f453923 100644 --- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c @@ -54,7 +54,7 @@ static const char * const decon_clks_name[] = { struct decon_context { struct device *dev; struct drm_device *drm_dev; - struct exynos_drm_crtc *crtc; + struct exynos_drm_crtc crtc; struct exynos_drm_plane planes[WINDOWS_NR]; void __iomem *addr; struct regmap *sysreg; @@ -69,6 +69,8 @@ struct decon_context { u32 frame_id; };

+#define to_decon(ptr) container_of(ptr, struct decon_context, ptr) + static const uint32_t decon_formats[] = { DRM_FORMAT_XRGB1555, DRM_FORMAT_RGB565, @@ -90,7 +92,7 @@ static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,

static int decon_enable_vblank(struct exynos_drm_crtc *crtc) { - struct decon_context *ctx = crtc->ctx; + struct decon_context *ctx = to_decon(crtc); u32 val;

val = VIDINTCON0_INTEN; @@ -110,7 +112,7 @@ static int decon_enable_vblank(struct exynos_drm_crtc *crtc)

static void decon_disable_vblank(struct exynos_drm_crtc *crtc) { - struct decon_context *ctx = crtc->ctx; + struct decon_context *ctx = to_decon(crtc);

if (!(ctx->out_type & I80_HW_TRG)) disable_irq_nosync(ctx->te_irq); @@ -143,7 +145,7 @@ static u32 decon_get_frame_count(struct decon_context *ctx, bool end)

switch (status & (VIDCON1_VSTATUS_MASK | VIDCON1_I80_ACTIVE)) { case VIDCON1_VSTATUS_VS: - if (!(ctx->crtc->i80_mode)) + if (!(ctx->crtc.i80_mode)) --frm; break; case VIDCON1_VSTATUS_BP: @@ -163,7 +165,7 @@ static u32 decon_get_frame_count(struct decon_context *ctx, bool end)

static void decon_setup_trigger(struct decon_context *ctx) { - if (!ctx->crtc->i80_mode && !(ctx->out_type & I80_HW_TRG)) + if (!ctx->crtc.i80_mode && !(ctx->out_type & I80_HW_TRG)) return;

if (!(ctx->out_type & I80_HW_TRG)) { @@ -183,7 +185,7 @@ static void decon_setup_trigger(struct decon_context *ctx)

static void decon_commit(struct exynos_drm_crtc *crtc) { - struct decon_context *ctx = crtc->ctx; + struct decon_context *ctx = to_decon(crtc); struct drm_display_mode *m = &crtc->base.mode; bool interlaced = false; u32 val; @@ -377,7 +379,7 @@ static void decon_shadow_protect(struct decon_context *ctx, bool protect)

static void decon_atomic_begin(struct exynos_drm_crtc *crtc) { - struct decon_context *ctx = crtc->ctx; + struct decon_context *ctx = to_decon(crtc);

decon_shadow_protect(ctx, true); } @@ -391,7 +393,7 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc, { struct exynos_drm_plane_state *state = to_exynos_plane_state(plane->base.state); - struct decon_context *ctx = crtc->ctx; + struct decon_context *ctx = to_decon(crtc); struct drm_framebuffer *fb = state->base.fb; unsigned int win = state->base.normalized_zpos + ctx->first_win; unsigned int cpp = fb->format->cpp[0]; @@ -445,7 +447,7 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc,

static void decon_atomic_flush(struct exynos_drm_crtc *crtc) { - struct decon_context *ctx = crtc->ctx; + struct decon_context *ctx = to_decon(crtc); unsigned long flags; int win = hweight32(crtc->base.state->plane_mask) + ctx->first_win;

@@ -502,7 +504,7 @@ static void decon_swreset(struct decon_context *ctx)

static void decon_enable(struct exynos_drm_crtc *crtc) { - struct decon_context *ctx = crtc->ctx; + struct decon_context *ctx = to_decon(crtc);

pm_runtime_get_sync(ctx->dev);

@@ -510,12 +512,12 @@ static void decon_enable(struct exynos_drm_crtc *crtc)

decon_swreset(ctx);

- decon_commit(ctx->crtc); + decon_commit(&ctx->crtc); }

static void decon_disable(struct exynos_drm_crtc *crtc) { - struct decon_context *ctx = crtc->ctx; + struct decon_context *ctx = to_decon(crtc); int i;

if (!(ctx->out_type & I80_HW_TRG)) @@ -548,7 +550,7 @@ static irqreturn_t decon_te_irq_handler(int irq, void *dev_id)

static void decon_clear_channels(struct exynos_drm_crtc *crtc) { - struct decon_context *ctx = crtc->ctx; + struct decon_context *ctx = to_decon(crtc); int win, i, ret;

DRM_DEBUG_KMS("%s\n", __FILE__); @@ -577,7 +579,7 @@ static void decon_clear_channels(struct exynos_drm_crtc *crtc) static enum drm_mode_status decon_mode_valid(struct exynos_drm_crtc *crtc, const struct drm_display_mode *mode) { - struct decon_context *ctx = crtc->ctx; + struct decon_context *ctx = to_decon(crtc);

ctx->irq = crtc->i80_mode ? ctx->irq_lcd_sys : ctx->irq_vsync;

@@ -605,8 +607,6 @@ static int decon_bind(struct device *dev, struct device *master, void *data) { struct decon_context *ctx = dev_get_drvdata(dev); struct drm_device *drm_dev = data; - struct exynos_drm_plane *exynos_plane; - enum exynos_drm_output_type out_type; unsigned int i; int ret;

@@ -624,15 +624,15 @@ static int decon_bind(struct device *dev, struct device *master, void *data) return ret; }

- exynos_plane = &ctx->planes[PRIMARY_WIN]; - out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI - : EXYNOS_DISPLAY_TYPE_LCD; - ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, - out_type, &decon_crtc_ops, ctx); - if (IS_ERR(ctx->crtc)) - return PTR_ERR(ctx->crtc); + ctx->crtc.type = (ctx->out_type & IFTYPE_HDMI) + ? EXYNOS_DISPLAY_TYPE_HDMI : EXYNOS_DISPLAY_TYPE_LCD; + ctx->crtc.ops = &decon_crtc_ops; + ret = exynos_drm_crtc_init(&ctx->crtc, drm_dev); + if (ret) + return ret; + ctx->crtc.base.primary = &ctx->planes[PRIMARY_WIN].base;

- decon_clear_channels(ctx->crtc); + decon_clear_channels(&ctx->crtc);

return exynos_drm_register_dma(drm_dev, dev); } @@ -641,7 +641,7 @@ static void decon_unbind(struct device *dev, struct device *master, void *data) { struct decon_context *ctx = dev_get_drvdata(dev);

- decon_disable(ctx->crtc); + decon_disable(&ctx->crtc);

/* detach this sub driver from iommu mapping if supported. */ exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev); @@ -663,7 +663,7 @@ static void decon_handle_vblank(struct decon_context *ctx) if (frm != ctx->frame_id) { /* handle only if incremented, take care of wrap-around */ if ((s32)(frm - ctx->frame_id) > 0) - drm_crtc_handle_vblank(&ctx->crtc->base); + drm_crtc_handle_vblank(&ctx->crtc.base); ctx->frame_id = frm; }

Since crtc maps 1:1 to the device there is no point in allocating it separately, another benefit is possibility of direct initialisation of its fields which is more readable and allows further expansion.

Signed-off-by: Andrzej Hajda a.hajda@samsung.com --- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 60 ++++++++++++------------ 1 file changed, 31 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index 2d34ca375ee1..8ea1cfd51736 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -169,7 +169,7 @@ static struct fimd_driver_data exynos5420_fimd_driver_data = { struct fimd_context { struct device *dev; struct drm_device *drm_dev; - struct exynos_drm_crtc *crtc; + struct exynos_drm_crtc crtc; struct exynos_drm_plane planes[WINDOWS_NR]; struct clk *bus_clk; struct clk *lcd_clk; @@ -193,6 +193,8 @@ struct fimd_context { struct exynos_drm_clk dp_clk; };

+#define to_fimd(ptr) container_of(ptr, struct fimd_context, ptr) + static const struct of_device_id fimd_driver_dt_match[] = { { .compatible = "samsung,s3c6400-fimd", .data = &s3c64xx_fimd_driver_data }, @@ -235,7 +237,7 @@ static inline void fimd_set_bits(struct fimd_context *ctx, u32 reg, u32 mask,

static int fimd_enable_vblank(struct exynos_drm_crtc *crtc) { - struct fimd_context *ctx = crtc->ctx; + struct fimd_context *ctx = to_fimd(crtc); u32 val;

if (ctx->suspended) @@ -267,7 +269,7 @@ static int fimd_enable_vblank(struct exynos_drm_crtc *crtc)

static void fimd_disable_vblank(struct exynos_drm_crtc *crtc) { - struct fimd_context *ctx = crtc->ctx; + struct fimd_context *ctx = to_fimd(crtc); u32 val;

if (ctx->suspended) @@ -291,7 +293,7 @@ static void fimd_disable_vblank(struct exynos_drm_crtc *crtc)

static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc) { - struct fimd_context *ctx = crtc->ctx; + struct fimd_context *ctx = to_fimd(crtc);

if (ctx->suspended) return; @@ -345,7 +347,7 @@ static void fimd_disable_win(struct fimd_context *ctx, int win)

static void fimd_clear_channels(struct exynos_drm_crtc *crtc) { - struct fimd_context *ctx = crtc->ctx; + struct fimd_context *ctx = to_fimd(crtc); unsigned int win, ch_enabled = 0;

DRM_DEBUG_KMS("%s\n", __FILE__); @@ -370,9 +372,9 @@ static void fimd_clear_channels(struct exynos_drm_crtc *crtc) if (ch_enabled) { ctx->suspended = false;

- fimd_enable_vblank(ctx->crtc); - fimd_wait_for_vblank(ctx->crtc); - fimd_disable_vblank(ctx->crtc); + fimd_enable_vblank(&ctx->crtc); + fimd_wait_for_vblank(&ctx->crtc); + fimd_disable_vblank(&ctx->crtc);

ctx->suspended = true; } @@ -388,7 +390,7 @@ static int fimd_atomic_check(struct exynos_drm_crtc *crtc, struct drm_crtc_state *state) { struct drm_display_mode *mode = &state->adjusted_mode; - struct fimd_context *ctx = crtc->ctx; + struct fimd_context *ctx = to_fimd(crtc); unsigned long ideal_clk, lcd_rate; u32 clkdiv;

@@ -448,7 +450,7 @@ static void fimd_setup_trigger(struct fimd_context *ctx)

static void fimd_commit(struct exynos_drm_crtc *crtc) { - struct fimd_context *ctx = crtc->ctx; + struct fimd_context *ctx = to_fimd(crtc); struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; const struct fimd_driver_data *driver_data = ctx->driver_data; void *timing_base = ctx->regs + driver_data->timing_base; @@ -754,7 +756,7 @@ static void fimd_shadow_protect_win(struct fimd_context *ctx,

static void fimd_atomic_begin(struct exynos_drm_crtc *crtc) { - struct fimd_context *ctx = crtc->ctx; + struct fimd_context *ctx = to_fimd(crtc); int i;

if (ctx->suspended) @@ -766,7 +768,7 @@ static void fimd_atomic_begin(struct exynos_drm_crtc *crtc)

static void fimd_atomic_flush(struct exynos_drm_crtc *crtc) { - struct fimd_context *ctx = crtc->ctx; + struct fimd_context *ctx = to_fimd(crtc); int i;

if (ctx->suspended) @@ -789,7 +791,7 @@ static void fimd_update_plane(struct exynos_drm_crtc *crtc, { struct exynos_drm_plane_state *state = to_exynos_plane_state(plane->base.state); - struct fimd_context *ctx = crtc->ctx; + struct fimd_context *ctx = to_fimd(crtc); struct drm_framebuffer *fb = state->base.fb; dma_addr_t dma_addr; unsigned long val, size, offset; @@ -878,7 +880,7 @@ static void fimd_update_plane(struct exynos_drm_crtc *crtc,

static void fimd_enable(struct exynos_drm_crtc *crtc) { - struct fimd_context *ctx = crtc->ctx; + struct fimd_context *ctx = to_fimd(crtc);

if (!ctx->suspended) return; @@ -889,14 +891,14 @@ static void fimd_enable(struct exynos_drm_crtc *crtc)

/* if vblank was enabled status, enable it again. */ if (test_and_clear_bit(0, &ctx->irq_flags)) - fimd_enable_vblank(ctx->crtc); + fimd_enable_vblank(&ctx->crtc);

- fimd_commit(ctx->crtc); + fimd_commit(&ctx->crtc); }

static void fimd_disable(struct exynos_drm_crtc *crtc) { - struct fimd_context *ctx = crtc->ctx; + struct fimd_context *ctx = to_fimd(crtc); int i;

if (ctx->suspended) @@ -951,7 +953,7 @@ static void fimd_trigger(struct device *dev)

static void fimd_te_handler(struct exynos_drm_crtc *crtc) { - struct fimd_context *ctx = crtc->ctx; + struct fimd_context *ctx = to_fimd(crtc); u32 trg_type = ctx->driver_data->trg_type;

/* Checks the crtc is detached already from encoder */ @@ -976,7 +978,7 @@ static void fimd_te_handler(struct exynos_drm_crtc *crtc) }

if (test_bit(0, &ctx->irq_flags)) - drm_crtc_handle_vblank(&ctx->crtc->base); + drm_crtc_handle_vblank(&ctx->crtc.base); }

static void fimd_dp_clock_enable(struct exynos_drm_clk *clk, bool enable) @@ -1015,7 +1017,7 @@ static irqreturn_t fimd_irq_handler(int irq, void *dev_id) goto out;

if (!ctx->i80_if) - drm_crtc_handle_vblank(&ctx->crtc->base); + drm_crtc_handle_vblank(&ctx->crtc.base);

if (ctx->i80_if) { /* Exits triggering mode */ @@ -1036,7 +1038,6 @@ static int fimd_bind(struct device *dev, struct device *master, void *data) { struct fimd_context *ctx = dev_get_drvdata(dev); struct drm_device *drm_dev = data; - struct exynos_drm_plane *exynos_plane; unsigned int i; int ret;

@@ -1053,22 +1054,23 @@ static int fimd_bind(struct device *dev, struct device *master, void *data) return ret; }

- exynos_plane = &ctx->planes[DEFAULT_WIN]; - ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, - EXYNOS_DISPLAY_TYPE_LCD, &fimd_crtc_ops, ctx); - if (IS_ERR(ctx->crtc)) - return PTR_ERR(ctx->crtc); + ctx->crtc.type = EXYNOS_DISPLAY_TYPE_LCD; + ctx->crtc.ops = &fimd_crtc_ops; + ret = exynos_drm_crtc_init(&ctx->crtc, drm_dev); + if (ret) + return ret; + ctx->crtc.base.primary = &ctx->planes[DEFAULT_WIN].base;

if (ctx->driver_data->has_dp_clk) { ctx->dp_clk.enable = fimd_dp_clock_enable; - ctx->crtc->pipe_clk = &ctx->dp_clk; + ctx->crtc.pipe_clk = &ctx->dp_clk; }

if (ctx->encoder) exynos_dpi_bind(drm_dev, ctx->encoder);

if (is_drm_iommu_supported(drm_dev)) - fimd_clear_channels(ctx->crtc); + fimd_clear_channels(&ctx->crtc);

return exynos_drm_register_dma(drm_dev, dev); } @@ -1078,7 +1080,7 @@ static void fimd_unbind(struct device *dev, struct device *master, { struct fimd_context *ctx = dev_get_drvdata(dev);

- fimd_disable(ctx->crtc); + fimd_disable(&ctx->crtc);

exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev);

Since crtc maps 1:1 to the device there is no point in allocating it separately, another benefit is possibility of direct initialisation of its fields which is more readable and allows further expansion.

Signed-off-by: Andrzej Hajda a.hajda@samsung.com --- drivers/gpu/drm/exynos/exynos_drm_vidi.c | 26 +++++++++++++----------- 1 file changed, 14 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.c b/drivers/gpu/drm/exynos/exynos_drm_vidi.c index b61ae3415b8c..377aae5f7631 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_vidi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_vidi.c @@ -41,7 +41,7 @@ struct vidi_context { struct drm_encoder encoder; struct platform_device *pdev; struct drm_device *drm_dev; - struct exynos_drm_crtc *crtc; + struct exynos_drm_crtc crtc; struct drm_connector connector; struct exynos_drm_plane planes[WINDOWS_NR]; struct edid *raw_edid; @@ -57,6 +57,8 @@ static inline struct vidi_context *encoder_to_vidi(struct drm_encoder *e) return container_of(e, struct vidi_context, encoder); }

+#define to_vidi(ptr) container_of(ptr, struct vidi_context, ptr) + static const char fake_edid_info[] = { 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x4c, 0x2d, 0x05, 0x05, 0x00, 0x00, 0x00, 0x00, 0x30, 0x12, 0x01, 0x03, 0x80, 0x10, 0x09, 0x78, @@ -96,7 +98,7 @@ static const enum drm_plane_type vidi_win_types[WINDOWS_NR] = {

static int vidi_enable_vblank(struct exynos_drm_crtc *crtc) { - struct vidi_context *ctx = crtc->ctx; + struct vidi_context *ctx = to_vidi(crtc);

if (ctx->suspended) return -EPERM; @@ -115,7 +117,7 @@ static void vidi_update_plane(struct exynos_drm_crtc *crtc, struct exynos_drm_plane *plane) { struct drm_plane_state *state = plane->base.state; - struct vidi_context *ctx = crtc->ctx; + struct vidi_context *ctx = to_vidi(crtc); dma_addr_t addr;

if (ctx->suspended) @@ -127,7 +129,7 @@ static void vidi_update_plane(struct exynos_drm_crtc *crtc,

static void vidi_enable(struct exynos_drm_crtc *crtc) { - struct vidi_context *ctx = crtc->ctx; + struct vidi_context *ctx = to_vidi(crtc);

mutex_lock(&ctx->lock);

@@ -140,7 +142,7 @@ static void vidi_enable(struct exynos_drm_crtc *crtc)

static void vidi_disable(struct exynos_drm_crtc *crtc) { - struct vidi_context *ctx = crtc->ctx; + struct vidi_context *ctx = to_vidi(crtc);

drm_crtc_vblank_off(&crtc->base);

@@ -164,7 +166,7 @@ static void vidi_fake_vblank_timer(struct timer_list *t) { struct vidi_context *ctx = from_timer(ctx, t, timer);

- if (drm_crtc_handle_vblank(&ctx->crtc->base)) + if (drm_crtc_handle_vblank(&ctx->crtc.base)) mod_timer(&ctx->timer, jiffies + msecs_to_jiffies(VIDI_REFRESH_TIME) - 1); } @@ -377,7 +379,6 @@ static int vidi_bind(struct device *dev, struct device *master, void *data) struct vidi_context *ctx = dev_get_drvdata(dev); struct drm_device *drm_dev = data; struct drm_encoder *encoder = &ctx->encoder; - struct exynos_drm_plane *exynos_plane; unsigned int i; int ret;

@@ -390,13 +391,14 @@ static int vidi_bind(struct device *dev, struct device *master, void *data) return ret; }

- exynos_plane = &ctx->planes[DEFAULT_WIN]; - ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, - EXYNOS_DISPLAY_TYPE_VIDI, &vidi_crtc_ops, ctx); - if (IS_ERR(ctx->crtc)) { + ctx->crtc.type = EXYNOS_DISPLAY_TYPE_VIDI; + ctx->crtc.ops = &vidi_crtc_ops; + ret = exynos_drm_crtc_init(&ctx->crtc, drm_dev); + if (ret) { DRM_ERROR("failed to create crtc.\n"); - return PTR_ERR(ctx->crtc); + return ret; } + ctx->crtc.base.primary = &ctx->planes[DEFAULT_WIN].base;

drm_encoder_init(drm_dev, encoder, &exynos_vidi_encoder_funcs, DRM_MODE_ENCODER_TMDS, NULL);

It can be replaced by recently introduced to_vidi helper.

Signed-off-by: Andrzej Hajda a.hajda@samsung.com --- drivers/gpu/drm/exynos/exynos_drm_vidi.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.c b/drivers/gpu/drm/exynos/exynos_drm_vidi.c index 377aae5f7631..2579462aec70 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_vidi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_vidi.c @@ -52,11 +52,6 @@ struct vidi_context { struct mutex lock; };

-static inline struct vidi_context *encoder_to_vidi(struct drm_encoder *e) -{ - return container_of(e, struct vidi_context, encoder); -} - #define to_vidi(ptr) container_of(ptr, struct vidi_context, ptr)

static const char fake_edid_info[] = { @@ -331,7 +326,7 @@ static const struct drm_connector_helper_funcs vidi_connector_helper_funcs = {

static int vidi_create_connector(struct drm_encoder *encoder) { - struct vidi_context *ctx = encoder_to_vidi(encoder); + struct vidi_context *ctx = to_vidi(encoder); struct drm_connector *connector = &ctx->connector; int ret;

exynos_drm_crtc_init has all information necessary to discover primary plane. Let's move logic for setting primary plane into this function.

Signed-off-by: Andrzej Hajda a.hajda@samsung.com --- drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 3 --- drivers/gpu/drm/exynos/exynos7_drm_decon.c | 1 - drivers/gpu/drm/exynos/exynos_drm_crtc.c | 10 +++++++++- drivers/gpu/drm/exynos/exynos_drm_drv.h | 2 -- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 1 - drivers/gpu/drm/exynos/exynos_drm_vidi.c | 1 - drivers/gpu/drm/exynos/exynos_mixer.c | 1 - 7 files changed, 9 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c index 663446ca2d09..958972e3ee1e 100644 --- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c @@ -30,8 +30,6 @@ #define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13)

#define WINDOWS_NR 5 -#define PRIMARY_WIN 2 -#define CURSON_WIN 4

#define MIN_FB_WIDTH_FOR_16WORD_BURST 128

@@ -625,7 +623,6 @@ static int decon_bind(struct device *dev, struct device *master, void *data) ret = exynos_drm_crtc_init(&ctx->crtc, drm_dev); if (ret) return ret; - ctx->crtc.base.primary = &ctx->planes[PRIMARY_WIN].base;

decon_clear_channels(&ctx->crtc);

diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c b/drivers/gpu/drm/exynos/exynos7_drm_decon.c index b6ad2faed159..3d8c96f0b02a 100644 --- a/drivers/gpu/drm/exynos/exynos7_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos7_drm_decon.c @@ -635,7 +635,6 @@ static int decon_bind(struct device *dev, struct device *master, void *data) decon_ctx_remove(ctx); return ret; } - ctx->crtc.base.primary = &ctx->planes[DEFAULT_WIN].base;

if (ctx->encoder) exynos_dpi_bind(drm_dev, ctx->encoder); diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c b/drivers/gpu/drm/exynos/exynos_drm_crtc.c index 72e224e80565..ec1319781b8b 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c @@ -176,9 +176,17 @@ int exynos_drm_crtc_init(struct exynos_drm_crtc *exynos_crtc, struct drm_device *drm_dev) { struct drm_crtc *crtc = &exynos_crtc->base; + struct drm_plane *primary = NULL, *plane; + + drm_for_each_plane(plane, drm_dev) { + if (plane->possible_crtcs != BIT(drm_dev->mode_config.num_crtc)) + continue; + if (!primary && plane->type == DRM_PLANE_TYPE_PRIMARY) + primary = plane; + }

drm_crtc_helper_add(crtc, &exynos_crtc_helper_funcs); - return drm_crtc_init_with_planes(drm_dev, crtc, NULL, NULL, + return drm_crtc_init_with_planes(drm_dev, crtc, primary, NULL, &exynos_crtc_funcs, NULL); }

diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h index 23b27b82de6e..6643db865500 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.h +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h @@ -21,8 +21,6 @@ #define MAX_PLANE 5 #define MAX_FB_BUFFER 4

-#define DEFAULT_WIN 0 - #define to_exynos_crtc(x) container_of(x, struct exynos_drm_crtc, base) #define to_exynos_plane(x) container_of(x, struct exynos_drm_plane, base)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index b3c11bca5aed..14e70971547a 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -1051,7 +1051,6 @@ static int fimd_bind(struct device *dev, struct device *master, void *data) ret = exynos_drm_crtc_init(&ctx->crtc, drm_dev); if (ret) return ret; - ctx->crtc.base.primary = &ctx->planes[DEFAULT_WIN].base;

if (ctx->driver_data->has_dp_clk) { ctx->dp_clk.enable = fimd_dp_clock_enable; diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.c b/drivers/gpu/drm/exynos/exynos_drm_vidi.c index eb1fd3a2cdf3..19cd7275b20f 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_vidi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_vidi.c @@ -387,7 +387,6 @@ static int vidi_bind(struct device *dev, struct device *master, void *data) DRM_ERROR("failed to create crtc.\n"); return ret; } - ctx->crtc.base.primary = &ctx->planes[DEFAULT_WIN].base;

drm_encoder_init(drm_dev, encoder, &exynos_vidi_encoder_funcs, DRM_MODE_ENCODER_TMDS, NULL); diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index a61fb2069e32..efc7d7a2d5b1 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c @@ -1179,7 +1179,6 @@ static int mixer_bind(struct device *dev, struct device *manager, void *data) mixer_ctx_remove(ctx); goto free_ctx; } - ctx->crtc.base.primary = &ctx->planes[DEFAULT_WIN].base;

return 0;

Display controllers in Exynos beside native planes/windows can use external planes provided by other IPs - GSCALER, FIMD, VPP. To add support to them we will need plane specific callbacks.

Signed-off-by: Andrzej Hajda a.hajda@samsung.com --- drivers/gpu/drm/exynos/exynos_drm_drv.h | 7 +++++++ 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h index 6643db865500..5d06e796dc80 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.h +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h @@ -76,6 +76,12 @@ to_exynos_plane_state(struct drm_plane_state *state) #define EXYNOS_DRM_PLANE_CAP_PIX_BLEND (1 << 4) #define EXYNOS_DRM_PLANE_CAP_WIN_BLEND (1 << 5)

+struct exynos_drm_plane; +struct exynos_drm_plane_ops { + void (*update_plane)(struct exynos_drm_plane *plane); + void (*disable_plane)(struct exynos_drm_plane *plane); +}; + /* * Exynos drm common overlay structure. * @@ -89,6 +95,7 @@ to_exynos_plane_state(struct drm_plane_state *state)

struct exynos_drm_plane { struct drm_plane base; + const struct exynos_drm_plane_ops *ops; unsigned int index; unsigned int capabilities; };

Id should be assigned based on OF alias.

Signed-off-by: Andrzej Hajda a.hajda@samsung.com --- drivers/gpu/drm/exynos/exynos_drm_gsc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_gsc.c b/drivers/gpu/drm/exynos/exynos_drm_gsc.c index f048d97fe9e2..8d5aa70c8ab8 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_gsc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_gsc.c @@ -1287,7 +1287,7 @@ static int gsc_probe(struct platform_device *pdev) }

/* context initailization */ - ctx->id = pdev->id; + ctx->id = of_alias_get_id(dev->of_node, "gsc");

platform_set_drvdata(pdev, ctx);

GSCALERs in Exynos5433 have local path to DECON and DECON_TV. They can be used as extra planes with support for non-RGB formats and scaling. To enable it on DECON update_plane and disable_plane callback should be modified. Moreover DSD mux should be set accordingly, and finally atomic_check callback should be used to limit the number of active planes.

Signed-off-by: Andrzej Hajda a.hajda@samsung.com --- drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 80 +++++++++++++++---- drivers/gpu/drm/exynos/regs-decon5433.h | 6 ++ 2 files changed, 72 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c index 958972e3ee1e..b0332763594e 100644 --- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c @@ -26,6 +26,10 @@ #include "exynos_drm_fb.h" #include "regs-decon5433.h"

+#define DSD_CFG 0x1000 +#define DSD_CFG_GSCL_MODE(gsc, decon, wb) (((wb) << 1) | decon) << (3 + ((gsc) << 1)) +#define DSD_CFG_GSCL_MODE_MASK(gsc) DSD_CFG_GSCL_MODE(gsc, 1, 1) + #define DSD_CFG_MUX 0x1004 #define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13)

@@ -47,6 +51,7 @@ static const char * const decon_clks_name[] = { "pclk_smmu_decon1x", "sclk_decon_vclk", "sclk_decon_eclk", + "dsd" };

struct decon_context { @@ -370,11 +375,40 @@ static void decon_shadow_protect(struct decon_context *ctx, bool protect) protect ? ~0 : 0); }

+static int decon_atomic_check(struct exynos_drm_crtc *crtc, + struct drm_crtc_state *state) +{ + struct decon_context *ctx = to_decon(crtc); + + if (hweight32(state->plane_mask) > WINDOWS_NR - ctx->first_win) + return -EINVAL; + return 0; +} + +static void decon_set_gscl_mode(struct decon_context *ctx) +{ + u32 plane_mask = ctx->crtc.base.state->plane_mask; + struct drm_plane *bplane; + u32 mask = 0, val = 0; + bool decon_id = ctx->out_type & IFTYPE_HDMI; + + drm_for_each_plane_mask(bplane, ctx->drm_dev, plane_mask) { + struct exynos_drm_plane *plane = to_exynos_plane(bplane); + + if (!(plane->capabilities & EXYNOS_DRM_PLANE_CAP_GSCALER)) + continue; + mask |= DSD_CFG_GSCL_MODE_MASK(plane->index); + val |= DSD_CFG_GSCL_MODE(plane->index, decon_id, 0); + } + regmap_update_bits(ctx->sysreg, DSD_CFG, mask, val); +} + static void decon_atomic_begin(struct exynos_drm_crtc *crtc) { struct decon_context *ctx = to_decon(crtc);

decon_shadow_protect(ctx, true); + decon_set_gscl_mode(ctx); }

#define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s)) @@ -394,6 +428,9 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc, dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0); u32 val;

+ if (plane->ops && plane->ops->update_plane) + plane->ops->update_plane(plane); + if (crtc->base.mode.flags & DRM_MODE_FLAG_INTERLACE) { val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y / 2); @@ -419,25 +456,38 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc, VIDOSD_Wx_ALPHA_B_F(0x0); writel(val, ctx->addr + DECON_VIDOSDxD(win));

- writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win)); - - val = dma_addr + pitch * state->src.h; - writel(val, ctx->addr + DECON_VIDW0xADD1B0(win)); - - if (!(ctx->out_type & IFTYPE_HDMI)) - val = BIT_VAL(pitch - state->crtc.w * cpp, 27, 14) - | BIT_VAL(state->crtc.w * cpp, 13, 0); - else - val = BIT_VAL(pitch - state->crtc.w * cpp, 29, 15) - | BIT_VAL(state->crtc.w * cpp, 14, 0); - writel(val, ctx->addr + DECON_VIDW0xADD2(win)); - decon_win_set_pixfmt(ctx, plane);

+ if (plane->capabilities & EXYNOS_DRM_PLANE_CAP_GSCALER) { + writel(UPDATE_SCHEME_OTF_PER_FRAME, + ctx->addr + DECON_UPDATE_SCHEME); + decon_set_bits(ctx, DECON_WINCONx(win), + WINCONx_ENLOCAL_F | WINCONx_LOCALSEL_MASK, + WINCONx_ENLOCAL_F | WINCONx_LOCALSEL_F(plane->index)); + } else { + writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win)); + val = dma_addr + pitch * state->src.h; + writel(val, ctx->addr + DECON_VIDW0xADD1B0(win)); + if (!(ctx->out_type & IFTYPE_HDMI)) + val = BIT_VAL(pitch - state->crtc.w * cpp, 27, 14) + | BIT_VAL(state->crtc.w * cpp, 13, 0); + else + val = BIT_VAL(pitch - state->crtc.w * cpp, 29, 15) + | BIT_VAL(state->crtc.w * cpp, 14, 0); + writel(val, ctx->addr + DECON_VIDW0xADD2(win)); + } + /* window enable */ decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0); }

+static void decon_disable_plane(struct exynos_drm_crtc *crtc, + struct exynos_drm_plane *plane) +{ + if (plane->ops && plane->ops->disable_plane) + plane->ops->disable_plane(plane); +} + static void decon_atomic_flush(struct exynos_drm_crtc *crtc) { struct decon_context *ctx = to_decon(crtc); @@ -448,7 +498,7 @@ static void decon_atomic_flush(struct exynos_drm_crtc *crtc) for (; win < WINDOWS_NR; ++win) { if (!readl(ctx->addr + DECON_WINCONx(win)) & WINCONx_ENWIN_F) break; - decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0); + writel(0, ctx->addr + DECON_WINCONx(win)); }

spin_lock_irqsave(&ctx->vblank_lock, flags); @@ -590,8 +640,10 @@ static const struct exynos_drm_crtc_ops decon_crtc_ops = { .disable = decon_disable, .enable_vblank = decon_enable_vblank, .disable_vblank = decon_disable_vblank, + .atomic_check = decon_atomic_check, .atomic_begin = decon_atomic_begin, .update_plane = decon_update_plane, + .disable_plane = decon_disable_plane, .mode_valid = decon_mode_valid, .atomic_flush = decon_atomic_flush, }; diff --git a/drivers/gpu/drm/exynos/regs-decon5433.h b/drivers/gpu/drm/exynos/regs-decon5433.h index 63db6974bf14..21a1c0bdd10a 100644 --- a/drivers/gpu/drm/exynos/regs-decon5433.h +++ b/drivers/gpu/drm/exynos/regs-decon5433.h @@ -98,6 +98,9 @@ #define VIDOUT_COMMAND_IF (0x2 << 20)

/* WINCONx */ +#define WINCONx_LOCALSEL_F(n) ((n) << 21) +#define WINCONx_LOCALSEL_MASK (0x3 << 21) +#define WINCONx_ENLOCAL_F (0x1 << 20) #define WINCONx_HAWSWP_F (1 << 16) #define WINCONx_WSWP_F (1 << 15) #define WINCONx_BURSTLEN_MASK (0x3 << 10) @@ -184,6 +187,9 @@ #define VIDTCON2_LINEVAL(x) (((x) & 0xfff) << 16) #define VIDTCON2_HOZVAL(x) ((x) & 0xfff)

+/* DECON_UPDATE_SCHEME */ +#define UPDATE_SCHEME_OTF_PER_FRAME (1 << 31) + /* TRIGCON */ #define TRIGCON_TRIGEN_PER_F (1 << 31) #define TRIGCON_TRIGEN_F (1 << 30)

DECON should wait for previous update before starting new one. Otherwise internal registers can be updated in non-atomic, error prone way. This patch fixes occasional occurrences of vblank timeouts on tm2 platform: [ 3167.968742] [CRTC:55:crtc-0] vblank wait timed out [ 3167.987440] WARNING: CPU: 1 PID: 194 at ../drivers/gpu/drm/drm_atomic_helper.c:1423 drm_atomic_helper_wait_for_vblanks.part.9+0x2c0/0x2c8 [ 3168.029990] Modules linked in: [ 3168.047240] CPU: 1 PID: 194 Comm: modetest Tainted: G W 5.0.0-rc1+ #694 [ 3168.069539] Hardware name: Samsung TM2 board (DT) ... [ 3168.453566] Call trace: [ 3168.469705] drm_atomic_helper_wait_for_vblanks.part.9+0x2c0/0x2c8 [ 3168.489983] drm_atomic_helper_commit_tail_rpm+0x60/0x78 [ 3168.509463] commit_tail+0x44/0x78 [ 3168.527053] drm_atomic_helper_commit+0xe8/0x160 [ 3168.546010] drm_atomic_commit+0x48/0x58 [ 3168.564304] drm_atomic_helper_update_plane+0x11c/0x140 [ 3168.584080] __setplane_atomic+0x130/0x150 [ 3168.602799] setplane_internal+0xb0/0x1a8 [ 3168.621493] drm_mode_setplane+0xc4/0x1b8 [ 3168.640219] drm_ioctl_kernel+0x94/0x110 [ 3168.658920] drm_ioctl+0x1c8/0x428 ...

Signed-off-by: Andrzej Hajda a.hajda@samsung.com --- drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 5 +++++ 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c index b0332763594e..09f035f52444 100644 --- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c @@ -406,6 +406,11 @@ static void decon_set_gscl_mode(struct decon_context *ctx) static void decon_atomic_begin(struct exynos_drm_crtc *crtc) { struct decon_context *ctx = to_decon(crtc); + u32 val; + + /* wait for finish previous updates */ + if (readl_poll_timeout(ctx->addr + DECON_UPDATE, val, !val, 1000, 20000) < 0) + dev_err(ctx->dev, "DECON_UPDATE timeout\n");

decon_shadow_protect(ctx, true); decon_set_gscl_mode(ctx);

YVU420 requires swapping addresses of U and V planes.

Signed-off-by: Andrzej Hajda a.hajda@samsung.com --- drivers/gpu/drm/exynos/exynos_drm_gsc.c | 52 ++++++++++++++++++------- 1 file changed, 37 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_gsc.c b/drivers/gpu/drm/exynos/exynos_drm_gsc.c index c7a97d053ab1..f75739e8bc55 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_gsc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_gsc.c @@ -535,10 +535,8 @@ static void gsc_src_set_fmt(struct gsc_context *ctx, u32 fmt, bool tiled) cfg |= GSC_IN_YUV422_3P; break; case DRM_FORMAT_YUV420: - cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV420_3P); - break; case DRM_FORMAT_YVU420: - cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV420_3P); + cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV420_3P); break; case DRM_FORMAT_NV12: cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV420_2P); @@ -658,13 +656,32 @@ static void gsc_src_set_buf_seq(struct gsc_context *ctx, u32 buf_id, gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK); }

+/* returns HW plane index based on pixel format */ +static int gsc_hw_plane_index(int index, u32 format) +{ + switch (format) { + case DRM_FORMAT_YVU420: + switch (index) { + case 0: return 0; + case 1: return 2; + case 2: return 1; + } + default: + return index; + } +} + static void gsc_src_set_addr(struct gsc_context *ctx, u32 buf_id, struct exynos_drm_ipp_buffer *buf) { + int idx; + /* address register set */ gsc_write(buf->dma_addr[0], GSC_IN_BASE_ADDR_Y(buf_id)); - gsc_write(buf->dma_addr[1], GSC_IN_BASE_ADDR_CB(buf_id)); - gsc_write(buf->dma_addr[2], GSC_IN_BASE_ADDR_CR(buf_id)); + idx = gsc_hw_plane_index(1, buf->format->format); + gsc_write(buf->dma_addr[idx], GSC_IN_BASE_ADDR_CB(buf_id)); + idx = gsc_hw_plane_index(2, buf->format->format); + gsc_write(buf->dma_addr[idx], GSC_IN_BASE_ADDR_CR(buf_id));

gsc_src_set_buf_seq(ctx, buf_id, true); } @@ -722,10 +739,8 @@ static void gsc_dst_set_fmt(struct gsc_context *ctx, u32 fmt, bool tiled) cfg |= GSC_OUT_YUV422_3P; break; case DRM_FORMAT_YUV420: - cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV420_3P); - break; case DRM_FORMAT_YVU420: - cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_3P); + cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV420_3P); break; case DRM_FORMAT_NV12: cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV420_2P); @@ -985,10 +1000,13 @@ static void gsc_dst_set_buf_seq(struct gsc_context *ctx, u32 buf_id, static void gsc_dst_set_addr(struct gsc_context *ctx, u32 buf_id, struct exynos_drm_ipp_buffer *buf) { - /* address register set */ + int i; + gsc_write(buf->dma_addr[0], GSC_OUT_BASE_ADDR_Y(buf_id)); - gsc_write(buf->dma_addr[1], GSC_OUT_BASE_ADDR_CB(buf_id)); - gsc_write(buf->dma_addr[2], GSC_OUT_BASE_ADDR_CR(buf_id)); + i = gsc_hw_plane_index(1, buf->format->format); + gsc_write(buf->dma_addr[i], GSC_OUT_BASE_ADDR_CB(buf_id)); + i = gsc_hw_plane_index(2, buf->format->format); + gsc_write(buf->dma_addr[i], GSC_OUT_BASE_ADDR_CR(buf_id));

gsc_dst_set_buf_seq(ctx, buf_id, true); } @@ -1238,10 +1256,14 @@ static void gsc_update_plane(struct exynos_drm_plane *plane) gsc_write(BIT(16) * cropped_w / scaled_w, GSC_MAIN_H_RATIO); gsc_write(BIT(16) * cropped_h / scaled_h, GSC_MAIN_V_RATIO); gsc_write(exynos_drm_fb_dma_addr(fb, 0), GSC_IN_BASE_ADDR_Y(0)); - if (fb->format->num_planes > 1) - gsc_write(exynos_drm_fb_dma_addr(fb, 1), GSC_IN_BASE_ADDR_CB(0)); - if (fb->format->num_planes > 2) - gsc_write(exynos_drm_fb_dma_addr(fb, 2), GSC_IN_BASE_ADDR_CR(0)); + if (fb->format->num_planes > 1) { + i = gsc_hw_plane_index(1, fb->format->format); + gsc_write(exynos_drm_fb_dma_addr(fb, i), GSC_IN_BASE_ADDR_CB(0)); + } + if (fb->format->num_planes > 2) { + i = gsc_hw_plane_index(2, fb->format->format); + gsc_write(exynos_drm_fb_dma_addr(fb, i), GSC_IN_BASE_ADDR_CR(0)); + } gsc_src_set_fmt(ctx, fb->format->format, fb->modifier); gsc_write(scaled_w * scaled_h, GSC_SMART_IF_PIXEL_NUM); gsc_write(GSC_ENABLE_SFR_UPDATE | GSC_ENABLE_ON, GSC_ENABLE);