This patchset adds HDMI support for the Tegra114 Dalmore board. Tested with 1080p DVI and HDMI monitors.
Mikko Perttunen (5): host1x: hdmi: Add Tegra114 support host1x: hdmi: Detect whether display is connected with HDMI or DVI clk: tegra114: Initialize clocks needed for HDMI ARM: tegra: Add host1x, dc and hdmi to Tegra114 device tree ARM: tegra: Add hdmi to Tegra114 Dalmore device tree
arch/arm/boot/dts/tegra114-dalmore.dts | 17 ++++ arch/arm/boot/dts/tegra114.dtsi | 43 ++++++++++ drivers/clk/tegra/clk-tegra114.c | 3 + drivers/gpu/host1x/drm/drm.c | 1 + drivers/gpu/host1x/drm/hdmi.c | 110 +++++++++++++++++++++++- drivers/gpu/host1x/drm/hdmi.h | 152 +++++++++++++++++++++++++++++++++ 6 files changed, 323 insertions(+), 3 deletions(-)
Add Tegra114 TMDS configuration, add new peak_current field and use new place for drive current override bit on Tegra114 platform.
Signed-off-by: Mikko Perttunen mperttunen@nvidia.com --- drivers/gpu/host1x/drm/drm.c | 1 + drivers/gpu/host1x/drm/hdmi.c | 102 +++++++++++++++++++++++++++- drivers/gpu/host1x/drm/hdmi.h | 152 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 252 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/host1x/drm/drm.c b/drivers/gpu/host1x/drm/drm.c index 8c61cee..37f5166 100644 --- a/drivers/gpu/host1x/drm/drm.c +++ b/drivers/gpu/host1x/drm/drm.c @@ -88,6 +88,7 @@ static int host1x_parse_dt(struct host1x_drm *host1x) "nvidia,tegra30-dc", "nvidia,tegra30-hdmi", "nvidia,tegra30-gr2d", + "nvidia,tegra114-hdmi", }; unsigned int i; int err; diff --git a/drivers/gpu/host1x/drm/hdmi.c b/drivers/gpu/host1x/drm/hdmi.c index 01097da..d81fac8 100644 --- a/drivers/gpu/host1x/drm/hdmi.c +++ b/drivers/gpu/host1x/drm/hdmi.c @@ -149,6 +149,7 @@ struct tmds_config { u32 pll1; u32 pe_current; u32 drive_current; + u32 peak_current; };
static const struct tmds_config tegra2_tmds_config[] = { @@ -230,6 +231,85 @@ static const struct tmds_config tegra3_tmds_config[] = { }, };
+const struct tmds_config tegra114_tmds_config[] = { + { /* 480p/576p / 25.2MHz/27MHz modes */ + .pclk = 27000000, + .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | + SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL, + .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0), + .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) | + PE_CURRENT1(PE_CURRENT_0_mA_T114) | + PE_CURRENT2(PE_CURRENT_0_mA_T114) | + PE_CURRENT3(PE_CURRENT_0_mA_T114), + .drive_current = + DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) | + DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) | + DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) | + DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114), + .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | + PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | + PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | + PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), + }, { /* 720p / 74.25MHz modes */ + .pclk = 74250000, + .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | + SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL, + .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | + SOR_PLL_TMDS_TERMADJ(0), + .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) | + PE_CURRENT1(PE_CURRENT_15_mA_T114) | + PE_CURRENT2(PE_CURRENT_15_mA_T114) | + PE_CURRENT3(PE_CURRENT_15_mA_T114), + .drive_current = + DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) | + DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) | + DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) | + DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114), + .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | + PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | + PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | + PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), + }, { /* 1080p / 148.5MHz modes */ + .pclk = 148500000, + .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | + SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL, + .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | + SOR_PLL_TMDS_TERMADJ(0), + .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) | + PE_CURRENT1(PE_CURRENT_10_mA_T114) | + PE_CURRENT2(PE_CURRENT_10_mA_T114) | + PE_CURRENT3(PE_CURRENT_10_mA_T114), + .drive_current = + DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) | + DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) | + DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) | + DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114), + .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | + PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | + PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | + PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), + }, { /* 225/297MHz modes */ + .pclk = UINT_MAX, + .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | + SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL, + .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7) + | SOR_PLL_TMDS_TERM_ENABLE, + .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) | + PE_CURRENT1(PE_CURRENT_0_mA_T114) | + PE_CURRENT2(PE_CURRENT_0_mA_T114) | + PE_CURRENT3(PE_CURRENT_0_mA_T114), + .drive_current = + DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) | + DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) | + DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) | + DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114), + .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) | + PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) | + PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) | + PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA), + }, +}; + static const struct tegra_hdmi_audio_config * tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pclk) { @@ -593,8 +673,20 @@ static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi, tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1); tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
- value = tmds->drive_current | DRIVE_CURRENT_FUSE_OVERRIDE; - tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT); + if (of_device_is_compatible(hdmi->dev->of_node, + "nvidia,tegra114-hdmi")) { + tegra_hdmi_writel(hdmi, tmds->drive_current, + HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT); + value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PAD_CTLS0); + value |= DRIVE_CURRENT_FUSE_OVERRIDE_T114; + tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PAD_CTLS0); + tegra_hdmi_writel(hdmi, tmds->peak_current, + HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT); + } else { + value = tmds->drive_current | DRIVE_CURRENT_FUSE_OVERRIDE; + tegra_hdmi_writel(hdmi, value, + HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT); + } }
static int tegra_output_hdmi_enable(struct tegra_output *output) @@ -726,7 +818,10 @@ static int tegra_output_hdmi_enable(struct tegra_output *output) tegra_hdmi_setup_stereo_infoframe(hdmi);
/* TMDS CONFIG */ - if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) { + if (of_device_is_compatible(node, "nvidia,tegra114-hdmi")) { + num_tmds = ARRAY_SIZE(tegra114_tmds_config); + tmds = tegra114_tmds_config; + } else if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) { num_tmds = ARRAY_SIZE(tegra3_tmds_config); tmds = tegra3_tmds_config; } else { @@ -1299,6 +1394,7 @@ static int tegra_hdmi_remove(struct platform_device *pdev) static struct of_device_id tegra_hdmi_of_match[] = { { .compatible = "nvidia,tegra30-hdmi", }, { .compatible = "nvidia,tegra20-hdmi", }, + { .compatible = "nvidia,tegra114-hdmi", }, { }, };
diff --git a/drivers/gpu/host1x/drm/hdmi.h b/drivers/gpu/host1x/drm/hdmi.h index 52ac36e..37925c2 100644 --- a/drivers/gpu/host1x/drm/hdmi.h +++ b/drivers/gpu/host1x/drm/hdmi.h @@ -233,6 +233,10 @@ #define DRIVE_CURRENT_LANE1(x) (((x) & 0x3f) << 8) #define DRIVE_CURRENT_LANE2(x) (((x) & 0x3f) << 16) #define DRIVE_CURRENT_LANE3(x) (((x) & 0x3f) << 24) +#define DRIVE_CURRENT_LANE0_T114(x) (((x) & 0x7f) << 0) +#define DRIVE_CURRENT_LANE1_T114(x) (((x) & 0x7f) << 8) +#define DRIVE_CURRENT_LANE2_T114(x) (((x) & 0x7f) << 16) +#define DRIVE_CURRENT_LANE3_T114(x) (((x) & 0x7f) << 24) #define DRIVE_CURRENT_FUSE_OVERRIDE (1 << 31)
#define DRIVE_CURRENT_1_500_mA 0x00 @@ -299,6 +303,79 @@ #define DRIVE_CURRENT_24_375_mA 0x3d #define DRIVE_CURRENT_24_750_mA 0x3e
+#define DRIVE_CURRENT_0_000_mA_T114 0x00 +#define DRIVE_CURRENT_0_400_mA_T114 0x01 +#define DRIVE_CURRENT_0_800_mA_T114 0x02 +#define DRIVE_CURRENT_1_200_mA_T114 0x03 +#define DRIVE_CURRENT_1_600_mA_T114 0x04 +#define DRIVE_CURRENT_2_000_mA_T114 0x05 +#define DRIVE_CURRENT_2_400_mA_T114 0x06 +#define DRIVE_CURRENT_2_800_mA_T114 0x07 +#define DRIVE_CURRENT_3_200_mA_T114 0x08 +#define DRIVE_CURRENT_3_600_mA_T114 0x09 +#define DRIVE_CURRENT_4_000_mA_T114 0x0a +#define DRIVE_CURRENT_4_400_mA_T114 0x0b +#define DRIVE_CURRENT_4_800_mA_T114 0x0c +#define DRIVE_CURRENT_5_200_mA_T114 0x0d +#define DRIVE_CURRENT_5_600_mA_T114 0x0e +#define DRIVE_CURRENT_6_000_mA_T114 0x0f +#define DRIVE_CURRENT_6_400_mA_T114 0x10 +#define DRIVE_CURRENT_6_800_mA_T114 0x11 +#define DRIVE_CURRENT_7_200_mA_T114 0x12 +#define DRIVE_CURRENT_7_600_mA_T114 0x13 +#define DRIVE_CURRENT_8_000_mA_T114 0x14 +#define DRIVE_CURRENT_8_400_mA_T114 0x15 +#define DRIVE_CURRENT_8_800_mA_T114 0x16 +#define DRIVE_CURRENT_9_200_mA_T114 0x17 +#define DRIVE_CURRENT_9_600_mA_T114 0x18 +#define DRIVE_CURRENT_10_000_mA_T114 0x19 +#define DRIVE_CURRENT_10_400_mA_T114 0x1a +#define DRIVE_CURRENT_10_800_mA_T114 0x1b +#define DRIVE_CURRENT_11_200_mA_T114 0x1c +#define DRIVE_CURRENT_11_600_mA_T114 0x1d +#define DRIVE_CURRENT_12_000_mA_T114 0x1e +#define DRIVE_CURRENT_12_400_mA_T114 0x1f +#define DRIVE_CURRENT_12_800_mA_T114 0x20 +#define DRIVE_CURRENT_13_200_mA_T114 0x21 +#define DRIVE_CURRENT_13_600_mA_T114 0x22 +#define DRIVE_CURRENT_14_000_mA_T114 0x23 +#define DRIVE_CURRENT_14_400_mA_T114 0x24 +#define DRIVE_CURRENT_14_800_mA_T114 0x25 +#define DRIVE_CURRENT_15_200_mA_T114 0x26 +#define DRIVE_CURRENT_15_600_mA_T114 0x27 +#define DRIVE_CURRENT_16_000_mA_T114 0x28 +#define DRIVE_CURRENT_16_400_mA_T114 0x29 +#define DRIVE_CURRENT_16_800_mA_T114 0x2a +#define DRIVE_CURRENT_17_200_mA_T114 0x2b +#define DRIVE_CURRENT_17_600_mA_T114 0x2c +#define DRIVE_CURRENT_18_000_mA_T114 0x2d +#define DRIVE_CURRENT_18_400_mA_T114 0x2e +#define DRIVE_CURRENT_18_800_mA_T114 0x2f +#define DRIVE_CURRENT_19_200_mA_T114 0x30 +#define DRIVE_CURRENT_19_600_mA_T114 0x31 +#define DRIVE_CURRENT_20_000_mA_T114 0x32 +#define DRIVE_CURRENT_20_400_mA_T114 0x33 +#define DRIVE_CURRENT_20_800_mA_T114 0x34 +#define DRIVE_CURRENT_21_200_mA_T114 0x35 +#define DRIVE_CURRENT_21_600_mA_T114 0x36 +#define DRIVE_CURRENT_22_000_mA_T114 0x37 +#define DRIVE_CURRENT_22_400_mA_T114 0x38 +#define DRIVE_CURRENT_22_800_mA_T114 0x39 +#define DRIVE_CURRENT_23_200_mA_T114 0x3a +#define DRIVE_CURRENT_23_600_mA_T114 0x3b +#define DRIVE_CURRENT_24_000_mA_T114 0x3c +#define DRIVE_CURRENT_24_400_mA_T114 0x3d +#define DRIVE_CURRENT_24_800_mA_T114 0x3e +#define DRIVE_CURRENT_25_200_mA_T114 0x3f +#define DRIVE_CURRENT_25_400_mA_T114 0x40 +#define DRIVE_CURRENT_25_800_mA_T114 0x41 +#define DRIVE_CURRENT_26_200_mA_T114 0x42 +#define DRIVE_CURRENT_26_600_mA_T114 0x43 +#define DRIVE_CURRENT_27_000_mA_T114 0x44 +#define DRIVE_CURRENT_27_400_mA_T114 0x45 +#define DRIVE_CURRENT_27_800_mA_T114 0x46 +#define DRIVE_CURRENT_28_200_mA_T114 0x47 + #define HDMI_NV_PDISP_AUDIO_DEBUG0 0x7f #define HDMI_NV_PDISP_AUDIO_DEBUG1 0x80 #define HDMI_NV_PDISP_AUDIO_DEBUG2 0x81 @@ -358,6 +435,23 @@ #define PE_CURRENT_7_0_mA 0xe #define PE_CURRENT_7_5_mA 0xf
+#define PE_CURRENT_0_mA_T114 0x0 +#define PE_CURRENT_1_mA_T114 0x1 +#define PE_CURRENT_2_mA_T114 0x2 +#define PE_CURRENT_3_mA_T114 0x3 +#define PE_CURRENT_4_mA_T114 0x4 +#define PE_CURRENT_5_mA_T114 0x5 +#define PE_CURRENT_6_mA_T114 0x6 +#define PE_CURRENT_7_mA_T114 0x7 +#define PE_CURRENT_8_mA_T114 0x8 +#define PE_CURRENT_9_mA_T114 0x9 +#define PE_CURRENT_10_mA_T114 0xa +#define PE_CURRENT_11_mA_T114 0xb +#define PE_CURRENT_12_mA_T114 0xc +#define PE_CURRENT_13_mA_T114 0xd +#define PE_CURRENT_14_mA_T114 0xe +#define PE_CURRENT_15_mA_T114 0xf + #define HDMI_NV_PDISP_KEY_CTRL 0x9a #define HDMI_NV_PDISP_KEY_DEBUG0 0x9b #define HDMI_NV_PDISP_KEY_DEBUG1 0x9c @@ -383,4 +477,62 @@ #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 0xc5 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT 0xc5
+#define HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT 0xd1 +#define PEAK_CURRENT_LANE0(x) (((x) & 0x7f) << 0) +#define PEAK_CURRENT_LANE1(x) (((x) & 0x7f) << 8) +#define PEAK_CURRENT_LANE2(x) (((x) & 0x7f) << 16) +#define PEAK_CURRENT_LANE3(x) (((x) & 0x7f) << 24) + +#define PEAK_CURRENT_0_000_mA 0x00 +#define PEAK_CURRENT_0_200_mA 0x01 +#define PEAK_CURRENT_0_400_mA 0x02 +#define PEAK_CURRENT_0_600_mA 0x03 +#define PEAK_CURRENT_0_800_mA 0x04 +#define PEAK_CURRENT_1_000_mA 0x05 +#define PEAK_CURRENT_1_200_mA 0x06 +#define PEAK_CURRENT_1_400_mA 0x07 +#define PEAK_CURRENT_1_600_mA 0x08 +#define PEAK_CURRENT_1_800_mA 0x09 +#define PEAK_CURRENT_2_000_mA 0x0a +#define PEAK_CURRENT_2_200_mA 0x0b +#define PEAK_CURRENT_2_400_mA 0x0c +#define PEAK_CURRENT_2_600_mA 0x0d +#define PEAK_CURRENT_2_800_mA 0x0e +#define PEAK_CURRENT_3_000_mA 0x0f +#define PEAK_CURRENT_3_200_mA 0x10 +#define PEAK_CURRENT_3_400_mA 0x11 +#define PEAK_CURRENT_3_600_mA 0x12 +#define PEAK_CURRENT_3_800_mA 0x13 +#define PEAK_CURRENT_4_000_mA 0x14 +#define PEAK_CURRENT_4_200_mA 0x15 +#define PEAK_CURRENT_4_400_mA 0x16 +#define PEAK_CURRENT_4_600_mA 0x17 +#define PEAK_CURRENT_4_800_mA 0x18 +#define PEAK_CURRENT_5_000_mA 0x19 +#define PEAK_CURRENT_5_200_mA 0x1a +#define PEAK_CURRENT_5_400_mA 0x1b +#define PEAK_CURRENT_5_600_mA 0x1c +#define PEAK_CURRENT_5_800_mA 0x1d +#define PEAK_CURRENT_6_000_mA 0x1e +#define PEAK_CURRENT_6_200_mA 0x1f +#define PEAK_CURRENT_6_400_mA 0x20 +#define PEAK_CURRENT_6_600_mA 0x21 +#define PEAK_CURRENT_6_800_mA 0x22 +#define PEAK_CURRENT_7_000_mA 0x23 +#define PEAK_CURRENT_7_200_mA 0x24 +#define PEAK_CURRENT_7_400_mA 0x25 +#define PEAK_CURRENT_7_600_mA 0x26 +#define PEAK_CURRENT_7_800_mA 0x27 +#define PEAK_CURRENT_8_000_mA 0x28 +#define PEAK_CURRENT_8_200_mA 0x29 +#define PEAK_CURRENT_8_400_mA 0x2a +#define PEAK_CURRENT_8_600_mA 0x2b +#define PEAK_CURRENT_8_800_mA 0x2c +#define PEAK_CURRENT_9_000_mA 0x2d +#define PEAK_CURRENT_9_200_mA 0x2e +#define PEAK_CURRENT_9_400_mA 0x2f + +#define HDMI_NV_PDISP_SOR_PAD_CTLS0 0xd2 +#define DRIVE_CURRENT_FUSE_OVERRIDE_T114 (1 << 31) + #endif /* TEGRA_HDMI_H */
Use EDID data to determine whether the display supports HDMI or just DVI. This used to be hardcoded to be HDMI, which broke support for DVI displays that couldn't understand the interspersed audio/other data.
If the EDID data isn't available, default to DVI, which should be a safer choice.
Signed-off-by: Mikko Perttunen mperttunen@nvidia.com --- drivers/gpu/host1x/drm/hdmi.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/host1x/drm/hdmi.c b/drivers/gpu/host1x/drm/hdmi.c index d81fac8..140339b 100644 --- a/drivers/gpu/host1x/drm/hdmi.c +++ b/drivers/gpu/host1x/drm/hdmi.c @@ -702,6 +702,14 @@ static int tegra_output_hdmi_enable(struct tegra_output *output) unsigned long value; int retries = 1000; int err; + struct drm_property_blob *edid_blob = output->connector.edid_blob_ptr; + + if (edid_blob && edid_blob->data && + drm_detect_hdmi_monitor((struct edid *)edid_blob->data)) { + hdmi->dvi = false; + } else { + hdmi->dvi = true; + }
pclk = mode->clock * 1000; h_sync_width = mode->hsync_end - mode->hsync_start;
On Wed, Aug 28, 2013 at 01:40:56PM +0300, Mikko Perttunen wrote:
Use EDID data to determine whether the display supports HDMI or just DVI. This used to be hardcoded to be HDMI, which broke support for DVI displays that couldn't understand the interspersed audio/other data.
If the EDID data isn't available, default to DVI, which should be a safer choice.
Signed-off-by: Mikko Perttunen mperttunen@nvidia.com
drivers/gpu/host1x/drm/hdmi.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/host1x/drm/hdmi.c b/drivers/gpu/host1x/drm/hdmi.c index d81fac8..140339b 100644 --- a/drivers/gpu/host1x/drm/hdmi.c +++ b/drivers/gpu/host1x/drm/hdmi.c @@ -702,6 +702,14 @@ static int tegra_output_hdmi_enable(struct tegra_output *output) unsigned long value; int retries = 1000; int err;
struct drm_property_blob *edid_blob = output->connector.edid_blob_ptr;
if (edid_blob && edid_blob->data &&
drm_detect_hdmi_monitor((struct edid *)edid_blob->data)) {hdmi->dvi = false;} else {
hdmi->dvi = true;}
pclk = mode->clock * 1000; h_sync_width = mode->hsync_end - mode->hsync_start;
Odd, now that I see that code I remember that there was a similar patch a few months back, but it was never applied for some reason:
http://lists.freedesktop.org/archives/dri-devel/2013-January/033509.html
That was already reviewed by me and Jon Mayo, so I'll go ahead and apply that one instead.
Thierry
On 08/28/2013 03:07 PM, Thierry Reding wrote:
- PGP Signed by an unknown key
On Wed, Aug 28, 2013 at 01:40:56PM +0300, Mikko Perttunen wrote:
Use EDID data to determine whether the display supports HDMI or just DVI. This used to be hardcoded to be HDMI, which broke support for DVI displays that couldn't understand the interspersed audio/other data.
If the EDID data isn't available, default to DVI, which should be a safer choice.
Signed-off-by: Mikko Perttunen mperttunen@nvidia.com
drivers/gpu/host1x/drm/hdmi.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/host1x/drm/hdmi.c b/drivers/gpu/host1x/drm/hdmi.c index d81fac8..140339b 100644 --- a/drivers/gpu/host1x/drm/hdmi.c +++ b/drivers/gpu/host1x/drm/hdmi.c @@ -702,6 +702,14 @@ static int tegra_output_hdmi_enable(struct tegra_output *output) unsigned long value; int retries = 1000; int err;
struct drm_property_blob *edid_blob = output->connector.edid_blob_ptr;
if (edid_blob && edid_blob->data &&
drm_detect_hdmi_monitor((struct edid *)edid_blob->data)) {hdmi->dvi = false;} else {
hdmi->dvi = true;}
pclk = mode->clock * 1000; h_sync_width = mode->hsync_end - mode->hsync_start;
Odd, now that I see that code I remember that there was a similar patch a few months back, but it was never applied for some reason:
http://lists.freedesktop.org/archives/dri-devel/2013-January/033509.html
That was already reviewed by me and Jon Mayo, so I'll go ahead and apply that one instead.
Thierry
- Unknown Key
- 0x7F3EB3A1
That patch seems to cause a warning for me: drivers/gpu/host1x/drm/hdmi.c: In function ‘tegra_output_hdmi_enable’: drivers/gpu/host1x/drm/hdmi.c:706:2: warning: passing argument 1 of ‘drm_detect_hdmi_monitor’ discards ‘const’ qualifier from pointer target type [enabled by default] include/drm/drm_crtc.h:1037:13: note: expected ‘struct edid *’ but argument is of type ‘const struct edid *’
Looks much nicer though.
On Wed, Aug 28, 2013 at 03:34:53PM +0300, Mikko Perttunen wrote:
On 08/28/2013 03:07 PM, Thierry Reding wrote:
- PGP Signed by an unknown key
On Wed, Aug 28, 2013 at 01:40:56PM +0300, Mikko Perttunen wrote:
Use EDID data to determine whether the display supports HDMI or just DVI. This used to be hardcoded to be HDMI, which broke support for DVI displays that couldn't understand the interspersed audio/other data.
If the EDID data isn't available, default to DVI, which should be a safer choice.
Signed-off-by: Mikko Perttunen mperttunen@nvidia.com
drivers/gpu/host1x/drm/hdmi.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/host1x/drm/hdmi.c b/drivers/gpu/host1x/drm/hdmi.c index d81fac8..140339b 100644 --- a/drivers/gpu/host1x/drm/hdmi.c +++ b/drivers/gpu/host1x/drm/hdmi.c @@ -702,6 +702,14 @@ static int tegra_output_hdmi_enable(struct tegra_output *output) unsigned long value; int retries = 1000; int err;
struct drm_property_blob *edid_blob = output->connector.edid_blob_ptr;
if (edid_blob && edid_blob->data &&
drm_detect_hdmi_monitor((struct edid *)edid_blob->data)) {hdmi->dvi = false;} else {
hdmi->dvi = true;}
pclk = mode->clock * 1000; h_sync_width = mode->hsync_end - mode->hsync_start;
Odd, now that I see that code I remember that there was a similar patch a few months back, but it was never applied for some reason:
http://lists.freedesktop.org/archives/dri-devel/2013-January/033509.html
That was already reviewed by me and Jon Mayo, so I'll go ahead and apply that one instead.
Thierry
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That patch seems to cause a warning for me: drivers/gpu/host1x/drm/hdmi.c: In function ‘tegra_output_hdmi_enable’: drivers/gpu/host1x/drm/hdmi.c:706:2: warning: passing argument 1 of ‘drm_detect_hdmi_monitor’ discards ‘const’ qualifier from pointer target type [enabled by default] include/drm/drm_crtc.h:1037:13: note: expected ‘struct edid *’ but argument is of type ‘const struct edid *’
Given the discussion about this back in January, I think the best way, at least for now, is to keep a copy of the EDID data so that it can actually be modified.
But looking at the problem more closely, I don't think the patch from January is quite correct. The problem is that it uses the EDID stored within the struct tegra_output. That's problematic because that field is not updated when EDID is probed via DDC. That would make the patch that you proposed more correct.
Thierry
Add host1x, disp1 and disp2 clocks to the clock initialization table. These clocks are required for HDMI support.
Signed-off-by: Mikko Perttunen mperttunen@nvidia.com --- drivers/clk/tegra/clk-tegra114.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index cd94b0c..a491dea 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -2211,6 +2211,9 @@ static struct tegra_clk_init_table init_table[] __initdata = { {i2s4, pll_a_out0, 11289600, 0}, {dfll_soc, pll_p, 51000000, 1}, {dfll_ref, pll_p, 51000000, 1}, + {host1x, pll_c, 150000000, 0}, + {disp1, pll_p, 600000000, 0}, + {disp2, pll_p, 600000000, 0}, {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */ };
Add host1x, dc (display controller) and hdmi devices to Tegra114 device tree.
Signed-off-by: Mikko Perttunen mperttunen@nvidia.com --- arch/arm/boot/dts/tegra114.dtsi | 43 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+)
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 2905145..ce5a95c 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -27,6 +27,49 @@ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; };
+ host1x { + compatible = "nvidia,tegra114-host1x", "nvidia,tegra30-host1x", + "simple-bus"; + reg = <0x50000000 0x00028000>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA114_CLK_HOST1X>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x54000000 0x54000000 0x04000000>; + + dc@54200000 { + compatible = "nvidia,tegra114-dc", "nvidia,tegra30-dc"; + reg = <0x54200000 0x00040000>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA114_CLK_DISP1>, + <&tegra_car TEGRA114_CLK_PLL_P>; + clock-names = "disp1", "parent"; + }; + + dc@54240000 { + compatible = "nvidia,tegra114-dc", "nvidia,tegra30-dc"; + reg = <0x54240000 0x00040000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA114_CLK_DISP2>, + <&tegra_car TEGRA114_CLK_PLL_P>; + clock-names = "disp2", "parent"; + }; + + hdmi { + compatible = "nvidia,tegra114-hdmi"; + reg = <0x54280000 0x00040000>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA114_CLK_HDMI>, + <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; + clock-names = "hdmi", "parent"; + + status = "disabled"; + }; + }; + timer@60005000 { compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer"; reg = <0x60005000 0x400>;
On Wed, Aug 28, 2013 at 01:40:58PM +0300, Mikko Perttunen wrote:
Add host1x, dc (display controller) and hdmi devices to Tegra114 device tree.
"DC" and "HDMI".
Signed-off-by: Mikko Perttunen mperttunen@nvidia.com
arch/arm/boot/dts/tegra114.dtsi | 43 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+)
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 2905145..ce5a95c 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -27,6 +27,49 @@ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; };
- host1x {
compatible = "nvidia,tegra114-host1x", "nvidia,tegra30-host1x",
I don't think that's correct. The Tegra114 host1x is not backwards compatible with the Tegra30 host1x.
That said, I have a local patch that is a bit more complete in that it adds other host1x devices as listed in the TRM as well. But I'll leave it up to Stephen how he prefers to handle that. It should be fine to defer adding nodes for additional hardware blocks when the supporting drivers are merged. We've done it for other devices as well.
"simple-bus";reg = <0x50000000 0x00028000>;interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
I think this should be indented with the previous line. Also other SoC .dtsi files use a single entry, as in:
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
hdmi {compatible = "nvidia,tegra114-hdmi";reg = <0x54280000 0x00040000>;interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;clocks = <&tegra_car TEGRA114_CLK_HDMI>,<&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
Any reason why we can't use pll_d2_out0 here, like we do on Tegra30?
Thierry
On 08/28/2013 03:25 PM, Thierry Reding wrote:
- PGP Signed by an unknown key
On Wed, Aug 28, 2013 at 01:40:58PM +0300, Mikko Perttunen wrote:
Add host1x, dc (display controller) and hdmi devices to Tegra114 device tree.
"DC" and "HDMI".
Will fix.
Signed-off-by: Mikko Perttunen mperttunen@nvidia.com
arch/arm/boot/dts/tegra114.dtsi | 43 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+)
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 2905145..ce5a95c 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -27,6 +27,49 @@ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; };
- host1x {
compatible = "nvidia,tegra114-host1x", "nvidia,tegra30-host1x",I don't think that's correct. The Tegra114 host1x is not backwards compatible with the Tegra30 host1x.
That said, I have a local patch that is a bit more complete in that it adds other host1x devices as listed in the TRM as well. But I'll leave it up to Stephen how he prefers to handle that. It should be fine to defer adding nodes for additional hardware blocks when the supporting drivers are merged. We've done it for other devices as well.
Ok. Will need to add tegra114-host1x to the host1x driver compat strings, then, but I guess that's better than having it wrong in the DT.
"simple-bus";reg = <0x50000000 0x00028000>;interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;I think this should be indented with the previous line. Also other SoC .dtsi files use a single entry, as in:
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
Will fix.
hdmi {compatible = "nvidia,tegra114-hdmi";reg = <0x54280000 0x00040000>;interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;clocks = <&tegra_car TEGRA114_CLK_HDMI>,<&tegra_car TEGRA114_CLK_PLL_D_OUT0>;Any reason why we can't use pll_d2_out0 here, like we do on Tegra30?
I have this set to PLL_D because I don't have panel support so disp1 will be the HDMI DC. However, it doesn't seem to matter which one is specified here. I have also tested HDMI with disp2 and that works too.
Thierry
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On Wed, Aug 28, 2013 at 03:41:35PM +0300, Mikko Perttunen wrote:
On 08/28/2013 03:25 PM, Thierry Reding wrote:
[...]
Signed-off-by: Mikko Perttunen mperttunen@nvidia.com
arch/arm/boot/dts/tegra114.dtsi | 43 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+)
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 2905145..ce5a95c 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -27,6 +27,49 @@ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; };
- host1x {
compatible = "nvidia,tegra114-host1x", "nvidia,tegra30-host1x",I don't think that's correct. The Tegra114 host1x is not backwards compatible with the Tegra30 host1x.
That said, I have a local patch that is a bit more complete in that it adds other host1x devices as listed in the TRM as well. But I'll leave it up to Stephen how he prefers to handle that. It should be fine to defer adding nodes for additional hardware blocks when the supporting drivers are merged. We've done it for other devices as well.
Ok. Will need to add tegra114-host1x to the host1x driver compat strings, then, but I guess that's better than having it wrong in the DT.
I think that's not all. I have local patches that also introduce a v2 of host1x, because the number of syncpoints is different. There may also be other differences, but Terje might be more qualified to answer that.
hdmi {compatible = "nvidia,tegra114-hdmi";reg = <0x54280000 0x00040000>;interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;clocks = <&tegra_car TEGRA114_CLK_HDMI>,<&tegra_car TEGRA114_CLK_PLL_D_OUT0>;Any reason why we can't use pll_d2_out0 here, like we do on Tegra30?
I have this set to PLL_D because I don't have panel support so disp1 will be the HDMI DC. However, it doesn't seem to matter which one is specified here. I have also tested HDMI with disp2 and that works too.
Well eventually we'll add panel support and I think it'd be good to stay consistent as to what clocks are used for the internal and external displays.
Thierry
On 28.08.2013 16:18, Thierry Reding wrote:
I think that's not all. I have local patches that also introduce a v2 of host1x, because the number of syncpoints is different. There may also be other differences, but Terje might be more qualified to answer that.
Tegra4 host1x has an extra channel(totals 9), which caused bitfields in a couple of registers to shift. The registers are mainly used in the debug code to dump the channel FIFO. Same number of sync points as Tegra3, but 12 wait bases.
Other changes are minor and driver already deals with them, for example 32-bit versus 16-bit sync point value comparison.
Terje
Add hdmi node to Dalmore device tree to supply Dalmore-specific data: VDD and PLL regulators for HDMI port, DDC bus and HDMI cable hotplug GPIO.
Signed-off-by: Mikko Perttunen mperttunen@nvidia.com --- arch/arm/boot/dts/tegra114-dalmore.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 6023028..50e6fb4 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -713,6 +713,17 @@ }; };
+ host1x { + hdmi { + status = "okay"; + + vdd-supply = <&vdd_hdmi_reg>; + pll-supply = <&palmas_smps3_reg>; + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + }; + }; + serial@70006300 { status = "okay"; }; @@ -740,6 +751,10 @@ }; };
+ hdmi_ddc: i2c@7000c700 { + status = "okay"; + }; + i2c@7000d000 { status = "okay"; clock-frequency = <400000>; @@ -1169,6 +1184,8 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; + regulator-always-on; + regulator-boot-on; gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; vin-supply = <&tps65090_dcdc1_reg>; };
On Wed, Aug 28, 2013 at 01:40:59PM +0300, Mikko Perttunen wrote:
Add hdmi node to Dalmore device tree to supply Dalmore-specific
s/hdmi/HDMI/
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
[...]
- host1x {
hdmi {status = "okay";vdd-supply = <&vdd_hdmi_reg>;pll-supply = <&palmas_smps3_reg>;nvidia,ddc-i2c-bus = <&hdmi_ddc>;
I prefer to use a blank line to separate "standard" from "vendor-specific" properties.
nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
Other .dts files split this so it doesn't exceed 80 characters. I'm not sure how useful that is as a general rule for DT source files, though.
i2c@7000d000 { status = "okay"; clock-frequency = <400000>; @@ -1169,6 +1184,8 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high;
regulator-always-on;regulator-boot-on;
This warrants at least a mention in the commit message.
Thierry
On 08/28/2013 03:30 PM, Thierry Reding wrote:
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On Wed, Aug 28, 2013 at 01:40:59PM +0300, Mikko Perttunen wrote:
Add hdmi node to Dalmore device tree to supply Dalmore-specific
s/hdmi/HDMI/
Will fix.
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
[...]
- host1x {
hdmi {status = "okay";vdd-supply = <&vdd_hdmi_reg>;pll-supply = <&palmas_smps3_reg>;nvidia,ddc-i2c-bus = <&hdmi_ddc>;I prefer to use a blank line to separate "standard" from "vendor-specific" properties.
Will fix.
nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;Other .dts files split this so it doesn't exceed 80 characters. I'm not sure how useful that is as a general rule for DT source files, though.
Will fix. I guess check_patch.pl doesn't check for line length in *.dts.
i2c@7000d000 { status = "okay"; clock-frequency = <400000>; @@ -1169,6 +1184,8 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high;
regulator-always-on;regulator-boot-on;This warrants at least a mention in the commit message.
Hmm, yeah. Looks like the HDMI driver only enables the Vdd in tegra_output_hdmi_enable, which is too late at least for DDC. I guess a better patch would be to enable it earlier. In _probe?
Thierry
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On Wed, Aug 28, 2013 at 03:49:45PM +0300, Mikko Perttunen wrote:
On 08/28/2013 03:30 PM, Thierry Reding wrote:
On Wed, Aug 28, 2013 at 01:40:59PM +0300, Mikko Perttunen wrote:
[...]
regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high;
regulator-always-on;regulator-boot-on;This warrants at least a mention in the commit message.
Hmm, yeah. Looks like the HDMI driver only enables the Vdd in tegra_output_hdmi_enable, which is too late at least for DDC. I guess a better patch would be to enable it earlier. In _probe?
I don't think that would be much better. That way the supply will still always be on, independent of whether we're actually using HDMI or not. I'm thinking that perhaps we need to allow HDMI to override get_modes() by something custom. That should also help with the EDID problem in the earlier patch.
Thierry
dri-devel@lists.freedesktop.org
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Mikko Perttunen -
Terje Bergström -
Thierry Reding