Hi,
This series adds some DRM bridge drivers support for i.MX8qm/qxp SoCs.
The bridges may chain one by one to form display pipes to support LVDS displays. The relevant display controller is DPU embedded in i.MX8qm/qxp SoCs.
The DPU KMS driver can be found at: https://www.spinics.net/lists/arm-kernel/msg862106.html
This series supports the following display pipes: 1) i.MX8qxp: prefetch eng -> DPU -> pixel combiner -> pixel link -> pixel link to DPI(PXL2DPI) -> LVDS display bridge(LDB)
2) i.MX8qm: prefetch eng -> DPU -> pixel combiner -> pixel link -> LVDS display bridge(LDB)
Patch 1/14 adds LVDS PHY configuration options, which has already been sent with the following series to add Mixel combo PHY found in i.MX8qxp: https://www.spinics.net/lists/arm-kernel/msg862560.html
Patch 2/14 and 3/14 add bus formats used by PXL2DPI.
Patch 4/14 ~ 13/14 add drm bridge drivers and dt-bindings support for the bridges.
Patch 14/14 updates MAINTAINERS.
I've tested this series with a koe,tx26d202vm0bwa dual link LVDS panel and a LVDS to HDMI bridge(with a downstream drm bridge driver).
Welcome comments, thanks.
Liu Ying (14): phy: Add LVDS configuration options media: uapi: Add some RGB bus formats for i.MX8qm/qxp pixel combiner media: docs: Add some RGB bus formats for i.MX8qm/qxp pixel combiner dt-bindings: display: bridge: Add i.MX8qm/qxp pixel combiner binding drm/bridge: imx: Add i.MX8qm/qxp pixel combiner support dt-bindings: display: bridge: Add i.MX8qm/qxp display pixel link binding drm/bridge: imx: Add i.MX8qm/qxp display pixel link support dt-bindings: display: bridge: Add i.MX8qxp pixel link to DPI binding drm/bridge: imx: Add i.MX8qxp pixel link to DPI support drm/bridge: imx: Add LDB driver helper support dt-bindings: display: bridge: Add i.MX8qm/qxp LVDS display bridge binding drm/bridge: imx: Add LDB support for i.MX8qxp drm/bridge: imx: Add LDB support for i.MX8qm MAINTAINERS: add maintainer for DRM bridge drivers for i.MX SoCs
.../bindings/display/bridge/fsl,imx8qxp-ldb.yaml | 185 +++++ .../display/bridge/fsl,imx8qxp-pixel-combiner.yaml | 160 +++++ .../display/bridge/fsl,imx8qxp-pixel-link.yaml | 128 ++++ .../display/bridge/fsl,imx8qxp-pxl2dpi.yaml | 134 ++++ .../userspace-api/media/v4l/subdev-formats.rst | 156 +++++ MAINTAINERS | 10 + drivers/gpu/drm/bridge/Kconfig | 2 + drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/imx/Kconfig | 52 ++ drivers/gpu/drm/bridge/imx/Makefile | 6 + drivers/gpu/drm/bridge/imx/imx-ldb-helper.c | 248 +++++++ drivers/gpu/drm/bridge/imx/imx8qm-ldb.c | 589 ++++++++++++++++ drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c | 762 +++++++++++++++++++++ .../gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c | 452 ++++++++++++ drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c | 411 +++++++++++ drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c | 494 +++++++++++++ include/drm/bridge/imx_ldb_helper.h | 98 +++ include/linux/phy/phy-lvds.h | 48 ++ include/linux/phy/phy.h | 4 + include/uapi/linux/media-bus-format.h | 6 +- 20 files changed, 3945 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml create mode 100644 drivers/gpu/drm/bridge/imx/Kconfig create mode 100644 drivers/gpu/drm/bridge/imx/Makefile create mode 100644 drivers/gpu/drm/bridge/imx/imx-ldb-helper.c create mode 100644 drivers/gpu/drm/bridge/imx/imx8qm-ldb.c create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c create mode 100644 include/drm/bridge/imx_ldb_helper.h create mode 100644 include/linux/phy/phy-lvds.h
This patch allows LVDS PHYs to be configured through the generic functions and through a custom structure added to the generic union.
The parameters added here are based on common LVDS PHY implementation practices. The set of parameters should cover all potential users.
Cc: Kishon Vijay Abraham I kishon@ti.com Cc: Vinod Koul vkoul@kernel.org Cc: NXP Linux Team linux-imx@nxp.com Signed-off-by: Liu Ying victor.liu@nxp.com --- include/linux/phy/phy-lvds.h | 48 ++++++++++++++++++++++++++++++++++++++++++++ include/linux/phy/phy.h | 4 ++++ 2 files changed, 52 insertions(+) create mode 100644 include/linux/phy/phy-lvds.h
diff --git a/include/linux/phy/phy-lvds.h b/include/linux/phy/phy-lvds.h new file mode 100644 index 00000000..1b5b9d6 --- /dev/null +++ b/include/linux/phy/phy-lvds.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2020 NXP + */ + +#ifndef __PHY_LVDS_H_ +#define __PHY_LVDS_H_ + +/** + * struct phy_configure_opts_lvds - LVDS configuration set + * + * This structure is used to represent the configuration state of a + * LVDS phy. + */ +struct phy_configure_opts_lvds { + /** + * @bits_per_lane_and_dclk_cycle: + * + * Number of bits per data lane and differential clock cycle. + */ + unsigned int bits_per_lane_and_dclk_cycle; + + /** + * @differential_clk_rate: + * + * Clock rate, in Hertz, of the LVDS differential clock. + */ + unsigned long differential_clk_rate; + + /** + * @lanes: + * + * Number of active, consecutive, data lanes, starting from + * lane 0, used for the transmissions. + */ + unsigned int lanes; + + /** + * @is_slave: + * + * Boolean, true if the phy is a slave which works together + * with a master phy to support dual link transmission, + * otherwise a regular phy or a master phy. + */ + bool is_slave; +}; + +#endif /* __PHY_LVDS_H_ */ diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h index e435bdb..d450b44 100644 --- a/include/linux/phy/phy.h +++ b/include/linux/phy/phy.h @@ -17,6 +17,7 @@ #include <linux/regulator/consumer.h>
#include <linux/phy/phy-dp.h> +#include <linux/phy/phy-lvds.h> #include <linux/phy/phy-mipi-dphy.h>
struct phy; @@ -51,10 +52,13 @@ enum phy_mode { * the MIPI_DPHY phy mode. * @dp: Configuration set applicable for phys supporting * the DisplayPort protocol. + * @lvds: Configuration set applicable for phys supporting + * the LVDS phy mode. */ union phy_configure_opts { struct phy_configure_opts_mipi_dphy mipi_dphy; struct phy_configure_opts_dp dp; + struct phy_configure_opts_lvds lvds; };
/**
This patch adds RGB666_1X30_CPADLO, RGB888_1X30_CPADLO, RGB666_1X36_CPADLO and RGB888_1X36_CPADLO bus formats used by i.MX8qm/qxp pixel combiner. The RGB pixels with padding low per component are transmitted on a 30-bit input bus(10-bit per component) from a display controller or a 36-bit output bus(12-bit per component) to a pixel link.
Signed-off-by: Liu Ying victor.liu@nxp.com --- include/uapi/linux/media-bus-format.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/include/uapi/linux/media-bus-format.h b/include/uapi/linux/media-bus-format.h index 5d905ad..b218282 100644 --- a/include/uapi/linux/media-bus-format.h +++ b/include/uapi/linux/media-bus-format.h @@ -34,7 +34,7 @@
#define MEDIA_BUS_FMT_FIXED 0x0001
-/* RGB - next is 0x101e */ +/* RGB - next is 0x1022 */ #define MEDIA_BUS_FMT_RGB444_1X12 0x1016 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002 @@ -59,9 +59,13 @@ #define MEDIA_BUS_FMT_RGB888_3X8_DELTA 0x101d #define MEDIA_BUS_FMT_RGB888_1X7X4_SPWG 0x1011 #define MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA 0x1012 +#define MEDIA_BUS_FMT_RGB666_1X30_CPADLO 0x101e +#define MEDIA_BUS_FMT_RGB888_1X30_CPADLO 0x101f #define MEDIA_BUS_FMT_ARGB8888_1X32 0x100d #define MEDIA_BUS_FMT_RGB888_1X32_PADHI 0x100f #define MEDIA_BUS_FMT_RGB101010_1X30 0x1018 +#define MEDIA_BUS_FMT_RGB666_1X36_CPADLO 0x1020 +#define MEDIA_BUS_FMT_RGB888_1X36_CPADLO 0x1021 #define MEDIA_BUS_FMT_RGB121212_1X36 0x1019 #define MEDIA_BUS_FMT_RGB161616_1X48 0x101a
This patch adds documentations for RGB666_1X30_CPADLO, RGB888_1X30_CPADLO, RGB666_1X36_CPADLO and RGB888_1X36_CPADLO bus formats used by i.MX8qm/qxp pixel combiner. The RGB pixels with padding low per component are transmitted on a 30-bit input bus(10-bit per component) from a display controller or a 36-bit output bus(12-bit per component) to a pixel link.
Signed-off-by: Liu Ying victor.liu@nxp.com --- .../userspace-api/media/v4l/subdev-formats.rst | 156 +++++++++++++++++++++ 1 file changed, 156 insertions(+)
diff --git a/Documentation/userspace-api/media/v4l/subdev-formats.rst b/Documentation/userspace-api/media/v4l/subdev-formats.rst index c9b7bb3..e02b92b 100644 --- a/Documentation/userspace-api/media/v4l/subdev-formats.rst +++ b/Documentation/userspace-api/media/v4l/subdev-formats.rst @@ -1488,6 +1488,80 @@ The following tables list existing packed RGB formats. - b\ :sub:`2` - b\ :sub:`1` - b\ :sub:`0` + * .. _MEDIA-BUS-FMT-RGB666-1X30-CPADLO: + + - MEDIA_BUS_FMT_RGB666_1X30-CPADLO + - 0x101e + - + - 0 + - 0 + - r\ :sub:`5` + - r\ :sub:`4` + - r\ :sub:`3` + - r\ :sub:`2` + - r\ :sub:`1` + - r\ :sub:`0` + - 0 + - 0 + - 0 + - 0 + - g\ :sub:`5` + - g\ :sub:`4` + - g\ :sub:`3` + - g\ :sub:`2` + - g\ :sub:`1` + - g\ :sub:`0` + - 0 + - 0 + - 0 + - 0 + - b\ :sub:`5` + - b\ :sub:`4` + - b\ :sub:`3` + - b\ :sub:`2` + - b\ :sub:`1` + - b\ :sub:`0` + - 0 + - 0 + - 0 + - 0 + * .. _MEDIA-BUS-FMT-RGB888-1X30-CPADLO: + + - MEDIA_BUS_FMT_RGB888_1X30-CPADLO + - 0x101f + - + - 0 + - 0 + - r\ :sub:`7` + - r\ :sub:`6` + - r\ :sub:`5` + - r\ :sub:`4` + - r\ :sub:`3` + - r\ :sub:`2` + - r\ :sub:`1` + - r\ :sub:`0` + - 0 + - 0 + - g\ :sub:`7` + - g\ :sub:`6` + - g\ :sub:`5` + - g\ :sub:`4` + - g\ :sub:`3` + - g\ :sub:`2` + - g\ :sub:`1` + - g\ :sub:`0` + - 0 + - 0 + - b\ :sub:`7` + - b\ :sub:`6` + - b\ :sub:`5` + - b\ :sub:`4` + - b\ :sub:`3` + - b\ :sub:`2` + - b\ :sub:`1` + - b\ :sub:`0` + - 0 + - 0 * .. _MEDIA-BUS-FMT-ARGB888-1X32:
- MEDIA_BUS_FMT_ARGB888_1X32 @@ -1665,6 +1739,88 @@ The following table list existing packed 36bit wide RGB formats. - 2 - 1 - 0 + * .. _MEDIA-BUS-FMT-RGB666-1X36-CPADLO: + + - MEDIA_BUS_FMT_RGB666_1X36_CPADLO + - 0x1020 + - + - r\ :sub:`5` + - r\ :sub:`4` + - r\ :sub:`3` + - r\ :sub:`2` + - r\ :sub:`1` + - r\ :sub:`0` + - 0 + - 0 + - 0 + - 0 + - 0 + - 0 + - g\ :sub:`5` + - g\ :sub:`4` + - g\ :sub:`3` + - g\ :sub:`2` + - g\ :sub:`1` + - g\ :sub:`0` + - 0 + - 0 + - 0 + - 0 + - 0 + - 0 + - b\ :sub:`5` + - b\ :sub:`4` + - b\ :sub:`3` + - b\ :sub:`2` + - b\ :sub:`1` + - b\ :sub:`0` + - 0 + - 0 + - 0 + - 0 + - 0 + - 0 + * .. _MEDIA-BUS-FMT-RGB888-1X36-CPADLO: + + - MEDIA_BUS_FMT_RGB888_1X36_CPADLO + - 0x1021 + - + - r\ :sub:`7` + - r\ :sub:`6` + - r\ :sub:`5` + - r\ :sub:`4` + - r\ :sub:`3` + - r\ :sub:`2` + - r\ :sub:`1` + - r\ :sub:`0` + - 0 + - 0 + - 0 + - 0 + - g\ :sub:`7` + - g\ :sub:`6` + - g\ :sub:`5` + - g\ :sub:`4` + - g\ :sub:`3` + - g\ :sub:`2` + - g\ :sub:`1` + - g\ :sub:`0` + - 0 + - 0 + - 0 + - 0 + - b\ :sub:`7` + - b\ :sub:`6` + - b\ :sub:`5` + - b\ :sub:`4` + - b\ :sub:`3` + - b\ :sub:`2` + - b\ :sub:`1` + - b\ :sub:`0` + - 0 + - 0 + - 0 + - 0 * .. _MEDIA-BUS-FMT-RGB121212-1X36:
- MEDIA_BUS_FMT_RGB121212_1X36
This patch adds bindings for i.MX8qm/qxp pixel combiner.
Signed-off-by: Liu Ying victor.liu@nxp.com --- .../display/bridge/fsl,imx8qxp-pixel-combiner.yaml | 160 +++++++++++++++++++++ 1 file changed, 160 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml new file mode 100644 index 00000000..bacacd8 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml @@ -0,0 +1,160 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-combiner.yaml... +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8qm/qxp Pixel Combiner + +maintainers: + - Liu Ying victor.liu@nxp.com + +description: | + The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a + single display controller and manipulates the two streams to support a number + of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured as + either one screen, two screens, or virtual screens. The pixel combiner is + also responsible for generating some of the control signals for the pixel link + output channel. + +properties: + compatible: + enum: + - fsl,imx8qm-pixel-combiner + - fsl,imx8qxp-pixel-combiner + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: apb + + power-domains: + maxItems: 1 + +patternProperties: + "^channel@[0-1]$": + type: object + description: Represents a display stream of pixel combiner. + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reg: + description: The display stream index. + oneOf: + - const: 0 + - const: 1 + + port@0: + type: object + description: Input endpoint of the display stream. + + properties: + reg: + const: 0 + + required: + - reg + + port@1: + type: object + description: Output endpoint of the display stream. + + properties: + reg: + const: 1 + + required: + - reg + + required: + - "#address-cells" + - "#size-cells" + - reg + - port@0 + - port@1 + + additionalProperties: false + +required: + - compatible + - "#address-cells" + - "#size-cells" + - reg + - clocks + - clock-names + - power-domains + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx8-lpcg.h> + #include <dt-bindings/firmware/imx/rsrc.h> + pixel-combiner@56020000 { + compatible = "fsl,imx8qxp-pixel-combiner"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x56020000 0x10000>; + clocks = <&dc0_pixel_combiner_lpcg IMX_LPCG_CLK_4>; + clock-names = "apb"; + power-domains = <&pd IMX_SC_R_DC_0>; + + channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + port@0 { + reg = <0>; + + dc0_pixel_combiner_ch0_dc0_dpu_disp0: endpoint { + remote-endpoint = <&dc0_dpu_disp0_dc0_pixel_combiner_ch0>; + }; + }; + + port@1 { + reg = <1>; + + dc0_pixel_combiner_ch0_dc0_pixel_link0: endpoint { + remote-endpoint = <&dc0_pixel_link0_dc0_pixel_combiner_ch0>; + }; + }; + }; + + channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + port@0 { + reg = <0>; + + dc0_pixel_combiner_ch1_dc0_dpu_disp1: endpoint { + remote-endpoint = <&dc0_dpu_disp1_dc0_pixel_combiner_ch1>; + }; + }; + + port@1 { + reg = <1>; + + dc0_pixel_combiner_ch1_dc0_pixel_link1: endpoint { + remote-endpoint = <&dc0_pixel_link1_dc0_pixel_combiner_ch1>; + }; + }; + }; + };
On Thu, 17 Dec 2020 17:59:23 +0800, Liu Ying wrote:
This patch adds bindings for i.MX8qm/qxp pixel combiner.
Signed-off-by: Liu Ying victor.liu@nxp.com
.../display/bridge/fsl,imx8qxp-pixel-combiner.yaml | 160 +++++++++++++++++++++ 1 file changed, 160 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.example.dts:19:18: fatal error: dt-bindings/clock/imx8-lpcg.h: No such file or directory 19 | #include <dt-bindings/clock/imx8-lpcg.h> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. make[1]: *** [scripts/Makefile.lib:342: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.example.dt.yaml] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [Makefile:1364: dt_binding_check] Error 2
See https://patchwork.ozlabs.org/patch/1417599
This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
pip3 install dtschema --upgrade
Please check and re-submit.
Hi,
On Thu, 2020-12-17 at 12:50 -0600, Rob Herring wrote:
On Thu, 17 Dec 2020 17:59:23 +0800, Liu Ying wrote:
This patch adds bindings for i.MX8qm/qxp pixel combiner.
Signed-off-by: Liu Ying victor.liu@nxp.com
.../display/bridge/fsl,imx8qxp-pixel-combiner.yaml | 160 +++++++++++++++++++++ 1 file changed, 160 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.example.dts:19:18: fatal error: dt-bindings/clock/imx8-lpcg.h: No such file or directory 19 | #include <dt-bindings/clock/imx8-lpcg.h> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. make[1]: *** [scripts/Makefile.lib:342: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.example.dt.yaml] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [Makefile:1364: dt_binding_check] Error 2
See https://patchwork.ozlabs.org/patch/1417599
This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1.
This series can be applied to linux-next/master branch. The header file 'imx8-lpcg.h' was added with the below commit on that branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/i...
With that header file, this patch may pass 'make dt_binding_check'.
Regards, Liu Ying
If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
pip3 install dtschema --upgrade
Please check and re-submit.
On Thu, Dec 17, 2020 at 7:48 PM Liu Ying victor.liu@nxp.com wrote:
Hi,
On Thu, 2020-12-17 at 12:50 -0600, Rob Herring wrote:
On Thu, 17 Dec 2020 17:59:23 +0800, Liu Ying wrote:
This patch adds bindings for i.MX8qm/qxp pixel combiner.
Signed-off-by: Liu Ying victor.liu@nxp.com
.../display/bridge/fsl,imx8qxp-pixel-combiner.yaml | 160 +++++++++++++++++++++ 1 file changed, 160 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.example.dts:19:18: fatal error: dt-bindings/clock/imx8-lpcg.h: No such file or directory 19 | #include <dt-bindings/clock/imx8-lpcg.h> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. make[1]: *** [scripts/Makefile.lib:342: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.example.dt.yaml] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [Makefile:1364: dt_binding_check] Error 2
See https://patchwork.ozlabs.org/patch/1417599
This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1.
This series can be applied to linux-next/master branch.
I can't know that to apply and run checks automatically. I guessed that reviewing this before sending, but I want it abundantly clear what the result of applying this might be and it wasn't mentioned in this patch.
Plus linux-next is a base no one can apply patches to, so should you be sending patches based on it? It's also the merge window, so maybe wait until rc1 when your dependency is in and the patch can actually be applied. Also, the drm-misc folks will still need to know they need to merge rc1 in before this is applied.
Rob
Hi,
On Fri, 2020-12-18 at 16:42 -0600, Rob Herring wrote:
On Thu, Dec 17, 2020 at 7:48 PM Liu Ying victor.liu@nxp.com wrote:
Hi,
On Thu, 2020-12-17 at 12:50 -0600, Rob Herring wrote:
On Thu, 17 Dec 2020 17:59:23 +0800, Liu Ying wrote:
This patch adds bindings for i.MX8qm/qxp pixel combiner.
Signed-off-by: Liu Ying victor.liu@nxp.com
.../display/bridge/fsl,imx8qxp-pixel-combiner.yaml | 160 +++++++++++++++++++++ 1 file changed, 160 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp- pixel-combiner.yaml
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp- pixel-combiner.example.dts:19:18: fatal error: dt- bindings/clock/imx8-lpcg.h: No such file or directory 19 | #include <dt-bindings/clock/imx8-lpcg.h> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. make[1]: *** [scripts/Makefile.lib:342: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp- pixel-combiner.example.dt.yaml] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [Makefile:1364: dt_binding_check] Error 2
See https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork....
This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1.
This series can be applied to linux-next/master branch.
I can't know that to apply and run checks automatically. I guessed that reviewing this before sending, but I want it abundantly clear what the result of applying this might be and it wasn't mentioned in this patch.
Plus linux-next is a base no one can apply patches to, so should you be sending patches based on it? It's also the merge window, so maybe
I sent this series based on drm-misc-next. This series is applicable to linux-next/master, and may pass 'make dt_binding_check' there.
I'll mention dependencies in the future where similar situations appear. Thanks.
BTW, does it make sense for the bot to additionaly try linux-next if needed? Maybe, that'll be helpful?
Regards, Liu Ying
wait until rc1 when your dependency is in and the patch can actually be applied. Also, the drm-misc folks will still need to know they need to merge rc1 in before this is applied.
Rob
On Fri, Dec 18, 2020 at 9:15 PM Liu Ying victor.liu@nxp.com wrote:
Hi,
On Fri, 2020-12-18 at 16:42 -0600, Rob Herring wrote:
On Thu, Dec 17, 2020 at 7:48 PM Liu Ying victor.liu@nxp.com wrote:
Hi,
On Thu, 2020-12-17 at 12:50 -0600, Rob Herring wrote:
On Thu, 17 Dec 2020 17:59:23 +0800, Liu Ying wrote:
This patch adds bindings for i.MX8qm/qxp pixel combiner.
Signed-off-by: Liu Ying victor.liu@nxp.com
.../display/bridge/fsl,imx8qxp-pixel-combiner.yaml | 160 +++++++++++++++++++++ 1 file changed, 160 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp- pixel-combiner.yaml
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp- pixel-combiner.example.dts:19:18: fatal error: dt- bindings/clock/imx8-lpcg.h: No such file or directory 19 | #include <dt-bindings/clock/imx8-lpcg.h> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. make[1]: *** [scripts/Makefile.lib:342: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp- pixel-combiner.example.dt.yaml] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [Makefile:1364: dt_binding_check] Error 2
See https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork....
This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1.
This series can be applied to linux-next/master branch.
I can't know that to apply and run checks automatically. I guessed that reviewing this before sending, but I want it abundantly clear what the result of applying this might be and it wasn't mentioned in this patch.
Plus linux-next is a base no one can apply patches to, so should you be sending patches based on it? It's also the merge window, so maybe
I sent this series based on drm-misc-next. This series is applicable to linux-next/master, and may pass 'make dt_binding_check' there.
But to be clear, 'make dt_binding_check' would fail on drm-misc-next until 5.11-rc1 is merged in. The drm-misc maintainers need to know that.
I'll mention dependencies in the future where similar situations appear. Thanks.
BTW, does it make sense for the bot to additionaly try linux-next if needed? Maybe, that'll be helpful?
Sure, and when I've got nothing else to do maybe I'll do that. Though maintainers still need to know what the dependencies are. The real solution here is to make 'base-commit' tags more common or required so that neither scripts/bots nor humans have to guess what the base is.
Rob
On Mon, 2020-12-21 at 10:02 -0700, Rob Herring wrote:
On Fri, Dec 18, 2020 at 9:15 PM Liu Ying victor.liu@nxp.com wrote:
Hi,
On Fri, 2020-12-18 at 16:42 -0600, Rob Herring wrote:
On Thu, Dec 17, 2020 at 7:48 PM Liu Ying victor.liu@nxp.com wrote:
Hi,
On Thu, 2020-12-17 at 12:50 -0600, Rob Herring wrote:
On Thu, 17 Dec 2020 17:59:23 +0800, Liu Ying wrote:
This patch adds bindings for i.MX8qm/qxp pixel combiner.
Signed-off-by: Liu Ying victor.liu@nxp.com
.../display/bridge/fsl,imx8qxp-pixel-combiner.yaml | 160 +++++++++++++++++++++ 1 file changed, 160 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp- pixel-combiner.yaml
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp- pixel-combiner.example.dts:19:18: fatal error: dt- bindings/clock/imx8-lpcg.h: No such file or directory 19 | #include <dt-bindings/clock/imx8-lpcg.h> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. make[1]: *** [scripts/Makefile.lib:342: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp- pixel-combiner.example.dt.yaml] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [Makefile:1364: dt_binding_check] Error 2
See https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork....
This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1.
This series can be applied to linux-next/master branch.
I can't know that to apply and run checks automatically. I guessed that reviewing this before sending, but I want it abundantly clear what the result of applying this might be and it wasn't mentioned in this patch.
Plus linux-next is a base no one can apply patches to, so should you be sending patches based on it? It's also the merge window, so maybe
I sent this series based on drm-misc-next. This series is applicable to linux-next/master, and may pass 'make dt_binding_check' there.
But to be clear, 'make dt_binding_check' would fail on drm-misc-next until 5.11-rc1 is merged in. The drm-misc maintainers need to know that.
Ok, will mention the dependency. Thanks.
I'll mention dependencies in the future where similar situations appear. Thanks.
BTW, does it make sense for the bot to additionaly try linux-next if needed? Maybe, that'll be helpful?
Sure, and when I've got nothing else to do maybe I'll do that. Though maintainers still need to know what the dependencies are. The real solution here is to make 'base-commit' tags more common or required so that neither scripts/bots nor humans have to guess what the base is.
Yeah, 'base-commit' is good, but a base commit should be 'well-known' as doc[1] indicates, otherwise, it is likely unfound. So, it seems that linux-next is worthy of a try.
[1] https://git-scm.com/docs/git-format-patch
Regards, Liu Ying
Rob
On Thu, Dec 17, 2020 at 05:59:23PM +0800, Liu Ying wrote:
This patch adds bindings for i.MX8qm/qxp pixel combiner.
Signed-off-by: Liu Ying victor.liu@nxp.com
.../display/bridge/fsl,imx8qxp-pixel-combiner.yaml | 160 +++++++++++++++++++++ 1 file changed, 160 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml new file mode 100644 index 00000000..bacacd8 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml @@ -0,0 +1,160 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-combiner.yaml... +$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: Freescale i.MX8qm/qxp Pixel Combiner
+maintainers:
- Liu Ying victor.liu@nxp.com
+description: |
- The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a
- single display controller and manipulates the two streams to support a number
- of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured as
- either one screen, two screens, or virtual screens. The pixel combiner is
- also responsible for generating some of the control signals for the pixel link
- output channel.
+properties:
- compatible:
- enum:
- fsl,imx8qm-pixel-combiner- fsl,imx8qxp-pixel-combiner- "#address-cells":
- const: 1
- "#size-cells":
- const: 0
- reg:
- maxItems: 1
- clocks:
- maxItems: 1
- clock-names:
- const: apb
- power-domains:
- maxItems: 1
+patternProperties:
- "^channel@[0-1]$":
- type: object
- description: Represents a display stream of pixel combiner.
- properties:
"#address-cells":const: 1"#size-cells":const: 0reg:description: The display stream index.oneOf:- const: 0- const: 1
enum: [ 0, 1 ]
port@0:type: objectdescription: Input endpoint of the display stream.properties:reg:const: 0required:- reg
You can drop 'reg' parts. That's going to get covered by the graph schema.
port@1:type: objectdescription: Output endpoint of the display stream.properties:reg:const: 1required:- reg- required:
- "#address-cells"- "#size-cells"- reg- port@0- port@1- additionalProperties: false
+required:
- compatible
- "#address-cells"
- "#size-cells"
- reg
- clocks
- clock-names
- power-domains
+additionalProperties: false
+examples:
- |
- #include <dt-bindings/clock/imx8-lpcg.h>
- #include <dt-bindings/firmware/imx/rsrc.h>
- pixel-combiner@56020000 {
compatible = "fsl,imx8qxp-pixel-combiner";#address-cells = <1>;#size-cells = <0>;reg = <0x56020000 0x10000>;clocks = <&dc0_pixel_combiner_lpcg IMX_LPCG_CLK_4>;clock-names = "apb";power-domains = <&pd IMX_SC_R_DC_0>;channel@0 {#address-cells = <1>;#size-cells = <0>;reg = <0>;port@0 {reg = <0>;dc0_pixel_combiner_ch0_dc0_dpu_disp0: endpoint {remote-endpoint = <&dc0_dpu_disp0_dc0_pixel_combiner_ch0>;};};port@1 {reg = <1>;dc0_pixel_combiner_ch0_dc0_pixel_link0: endpoint {remote-endpoint = <&dc0_pixel_link0_dc0_pixel_combiner_ch0>;};};};channel@1 {#address-cells = <1>;#size-cells = <0>;reg = <1>;port@0 {reg = <0>;dc0_pixel_combiner_ch1_dc0_dpu_disp1: endpoint {remote-endpoint = <&dc0_dpu_disp1_dc0_pixel_combiner_ch1>;};};port@1 {reg = <1>;dc0_pixel_combiner_ch1_dc0_pixel_link1: endpoint {remote-endpoint = <&dc0_pixel_link1_dc0_pixel_combiner_ch1>;};};};- };
-- 2.7.4
On Mon, 2020-12-21 at 15:07 -0700, Rob Herring wrote:
On Thu, Dec 17, 2020 at 05:59:23PM +0800, Liu Ying wrote:
This patch adds bindings for i.MX8qm/qxp pixel combiner.
Signed-off-by: Liu Ying victor.liu@nxp.com
.../display/bridge/fsl,imx8qxp-pixel-combiner.yaml | 160 +++++++++++++++++++++ 1 file changed, 160 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml new file mode 100644 index 00000000..bacacd8 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml @@ -0,0 +1,160 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.... +$schema: https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree....
+title: Freescale i.MX8qm/qxp Pixel Combiner
+maintainers:
- Liu Ying victor.liu@nxp.com
+description: |
- The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a
- single display controller and manipulates the two streams to support a number
- of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured as
- either one screen, two screens, or virtual screens. The pixel combiner is
- also responsible for generating some of the control signals for the pixel link
- output channel.
+properties:
- compatible:
- enum:
- fsl,imx8qm-pixel-combiner- fsl,imx8qxp-pixel-combiner- "#address-cells":
- const: 1
- "#size-cells":
- const: 0
- reg:
- maxItems: 1
- clocks:
- maxItems: 1
- clock-names:
- const: apb
- power-domains:
- maxItems: 1
+patternProperties:
- "^channel@[0-1]$":
- type: object
- description: Represents a display stream of pixel combiner.
- properties:
"#address-cells":const: 1"#size-cells":const: 0reg:description: The display stream index.oneOf:- const: 0- const: 1enum: [ 0, 1 ]
I forgot to modify this oneOf + const to enum. Will do. Thanks.
port@0:type: objectdescription: Input endpoint of the display stream.properties:reg:const: 0required:- regYou can drop 'reg' parts. That's going to get covered by the graph schema.
I'm assuming the 'const' numbers for 'reg' parts are still needed, so I'll keep the 'const' parts.
I'll drop 'required' parts for 'reg'.
Liu Ying
port@1:type: objectdescription: Output endpoint of the display stream.properties:reg:const: 1required:- reg- required:
- "#address-cells"- "#size-cells"- reg- port@0- port@1- additionalProperties: false
+required:
- compatible
- "#address-cells"
- "#size-cells"
- reg
- clocks
- clock-names
- power-domains
+additionalProperties: false
+examples:
- |
- #include <dt-bindings/clock/imx8-lpcg.h>
- #include <dt-bindings/firmware/imx/rsrc.h>
- pixel-combiner@56020000 {
compatible = "fsl,imx8qxp-pixel-combiner";#address-cells = <1>;#size-cells = <0>;reg = <0x56020000 0x10000>;clocks = <&dc0_pixel_combiner_lpcg IMX_LPCG_CLK_4>;clock-names = "apb";power-domains = <&pd IMX_SC_R_DC_0>;channel@0 {#address-cells = <1>;#size-cells = <0>;reg = <0>;port@0 {reg = <0>;dc0_pixel_combiner_ch0_dc0_dpu_disp0: endpoint {remote-endpoint = <&dc0_dpu_disp0_dc0_pixel_combiner_ch0>;};};port@1 {reg = <1>;dc0_pixel_combiner_ch0_dc0_pixel_link0: endpoint {remote-endpoint = <&dc0_pixel_link0_dc0_pixel_combiner_ch0>;};};};channel@1 {#address-cells = <1>;#size-cells = <0>;reg = <1>;port@0 {reg = <0>;dc0_pixel_combiner_ch1_dc0_dpu_disp1: endpoint {remote-endpoint = <&dc0_dpu_disp1_dc0_pixel_combiner_ch1>;};};port@1 {reg = <1>;dc0_pixel_combiner_ch1_dc0_pixel_link1: endpoint {remote-endpoint = <&dc0_pixel_link1_dc0_pixel_combiner_ch1>;};};};- };
-- 2.7.4
This patch adds a drm bridge driver for i.MX8qm/qxp pixel combiner. The pixel combiner takes two output streams from a single display controller and manipulates the two streams to support a number of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured as either one screen, two screens, or virtual screens. The pixel combiner is also responsible for generating some of the control signals for the pixel link output channel. For now, the driver only supports the bypass mode.
Signed-off-by: Liu Ying victor.liu@nxp.com --- drivers/gpu/drm/bridge/Kconfig | 2 + drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/imx/Kconfig | 8 + drivers/gpu/drm/bridge/imx/Makefile | 1 + .../gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c | 452 +++++++++++++++++++++ 5 files changed, 464 insertions(+) create mode 100644 drivers/gpu/drm/bridge/imx/Kconfig create mode 100644 drivers/gpu/drm/bridge/imx/Makefile create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index e4110d6c..84944e0 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -256,6 +256,8 @@ source "drivers/gpu/drm/bridge/adv7511/Kconfig"
source "drivers/gpu/drm/bridge/cadence/Kconfig"
+source "drivers/gpu/drm/bridge/imx/Kconfig" + source "drivers/gpu/drm/bridge/synopsys/Kconfig"
endmenu diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index 86e7acc..bc80cae 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -27,4 +27,5 @@ obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-dsi.o
obj-y += analogix/ obj-y += cadence/ +obj-y += imx/ obj-y += synopsys/ diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig new file mode 100644 index 00000000..f1c91b6 --- /dev/null +++ b/drivers/gpu/drm/bridge/imx/Kconfig @@ -0,0 +1,8 @@ +config DRM_IMX8QXP_PIXEL_COMBINER + tristate "Freescale i.MX8QM/QXP pixel combiner" + depends on OF + depends on COMMON_CLK + select DRM_KMS_HELPER + help + Choose this to enable pixel combiner found in + Freescale i.MX8qm/qxp processors. diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile new file mode 100644 index 00000000..7d7c8d6 --- /dev/null +++ b/drivers/gpu/drm/bridge/imx/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c new file mode 100644 index 00000000..cd5b1be --- /dev/null +++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c @@ -0,0 +1,452 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include <linux/bitfield.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_graph.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> + +#include <drm/drm_atomic_state_helper.h> +#include <drm/drm_bridge.h> +#include <drm/drm_print.h> + +#define PC_CTRL_REG 0x0 +#define PC_COMBINE_ENABLE BIT(0) +#define PC_DISP_BYPASS(n) BIT(1 + 21 * (n)) +#define PC_DISP_HSYNC_POLARITY(n) BIT(2 + 11 * (n)) +#define PC_DISP_HSYNC_POLARITY_POS(n) DISP_HSYNC_POLARITY(n) +#define PC_DISP_VSYNC_POLARITY(n) BIT(3 + 11 * (n)) +#define PC_DISP_VSYNC_POLARITY_POS(n) DISP_VSYNC_POLARITY(n) +#define PC_DISP_DVALID_POLARITY(n) BIT(4 + 11 * (n)) +#define PC_DISP_DVALID_POLARITY_POS(n) DISP_DVALID_POLARITY(n) +#define PC_VSYNC_MASK_ENABLE BIT(5) +#define PC_SKIP_MODE BIT(6) +#define PC_SKIP_NUMBER_MASK GENMASK(12, 7) +#define PC_SKIP_NUMBER(n) FIELD_PREP(PC_SKIP_NUMBER_MASK, (n)) +#define PC_DISP0_PIX_DATA_FORMAT_MASK GENMASK(18, 16) +#define PC_DISP0_PIX_DATA_FORMAT(fmt) \ + FIELD_PREP(PC_DISP0_PIX_DATA_FORMAT_MASK, (fmt)) +#define PC_DISP1_PIX_DATA_FORMAT_MASK GENMASK(21, 19) +#define PC_DISP1_PIX_DATA_FORMAT(fmt) \ + FIELD_PREP(PC_DISP1_PIX_DATA_FORMAT_MASK, (fmt)) + +#define PC_BUF_PARA_REG 0x10 +#define PC_BUF_ACTIVE_DEPTH_MASK GENMASK(10, 0) +#define PC_BUF_ACTIVE_DEPTH(n) FIELD_PREP(PC_BUF_ACTIVE_DEPTH_MASK, (n)) + +#define PC_SW_RESET_REG 0x20 +#define PC_SW_RESET_N BIT(0) +#define PC_DISP_SW_RESET_N(n) BIT(1 + (n)) +#define PC_FULL_RESET_N (PC_SW_RESET_N | \ + PC_DISP_SW_RESET_N(0) | \ + PC_DISP_SW_RESET_N(1)) + +#define PC_REG_SET 0x4 +#define PC_REG_CLR 0x8 + +#define DRIVER_NAME "imx8qxp-pixel-combiner" + +enum imx8qxp_pc_pix_data_format { + RGB, + YUV444, + YUV422, + SPLIT_RGB, +}; + +struct imx8qxp_pc_channel { + struct drm_bridge bridge; + struct drm_bridge *next_bridge; + struct imx8qxp_pc *pc; + unsigned int stream_id; + bool is_available; +}; + +struct imx8qxp_pc { + struct device *dev; + struct imx8qxp_pc_channel ch[2]; + struct clk *clk_apb; + void __iomem *base; +}; + +static inline u32 imx8qxp_pc_read(struct imx8qxp_pc *pc, unsigned int offset) +{ + return readl(pc->base + offset); +} + +static inline void +imx8qxp_pc_write(struct imx8qxp_pc *pc, unsigned int offset, u32 value) +{ + writel(value, pc->base + offset); +} + +static inline void +imx8qxp_pc_write_set(struct imx8qxp_pc *pc, unsigned int offset, u32 value) +{ + imx8qxp_pc_write(pc, offset + PC_REG_SET, value); +} + +static inline void +imx8qxp_pc_write_clr(struct imx8qxp_pc *pc, unsigned int offset, u32 value) +{ + imx8qxp_pc_write(pc, offset + PC_REG_CLR, value); +} + +static enum drm_mode_status +imx8qxp_pc_bridge_mode_valid(struct drm_bridge *bridge, + const struct drm_display_info *info, + const struct drm_display_mode *mode) +{ + if (mode->hdisplay > 2560) + return MODE_BAD_HVALUE; + + return MODE_OK; +} + +static int imx8qxp_pc_bridge_attach(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags) +{ + struct imx8qxp_pc_channel *ch = bridge->driver_private; + struct imx8qxp_pc *pc = ch->pc; + + if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) { + DRM_DEV_ERROR(pc->dev, + "do not support creating a drm_connector\n"); + return -EINVAL; + } + + if (!bridge->encoder) { + DRM_DEV_ERROR(pc->dev, "missing encoder\n"); + return -ENODEV; + } + + return drm_bridge_attach(bridge->encoder, + ch->next_bridge, bridge, + DRM_BRIDGE_ATTACH_NO_CONNECTOR); +} + +static void +imx8qxp_pc_bridge_mode_set(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + const struct drm_display_mode *adjusted_mode) +{ + struct imx8qxp_pc_channel *ch = bridge->driver_private; + struct imx8qxp_pc *pc = ch->pc; + u32 val; + int ret; + + ret = pm_runtime_get_sync(pc->dev); + if (ret < 0) + DRM_DEV_ERROR(pc->dev, + "failed to get runtime PM sync: %d\n", ret); + + ret = clk_prepare_enable(pc->clk_apb); + if (ret) + DRM_DEV_ERROR(pc->dev, "%s: failed to enable apb clock: %d\n", + __func__, ret); + + /* HSYNC to pixel link is active low. */ + imx8qxp_pc_write_clr(pc, PC_CTRL_REG, + PC_DISP_HSYNC_POLARITY(ch->stream_id)); + + /* VSYNC to pixel link is active low. */ + imx8qxp_pc_write_clr(pc, PC_CTRL_REG, + PC_DISP_VSYNC_POLARITY(ch->stream_id)); + + /* Data enable to pixel link is active high. */ + imx8qxp_pc_write_set(pc, PC_CTRL_REG, + PC_DISP_DVALID_POLARITY(ch->stream_id)); + + /* Mask the first frame output which may be incomplete. */ + imx8qxp_pc_write_set(pc, PC_CTRL_REG, PC_VSYNC_MASK_ENABLE); + + /* Only support RGB currently. */ + val = imx8qxp_pc_read(pc, PC_CTRL_REG); + if (ch->stream_id == 0) { + val &= ~PC_DISP0_PIX_DATA_FORMAT_MASK; + val |= PC_DISP0_PIX_DATA_FORMAT(RGB); + } else { + val &= ~PC_DISP1_PIX_DATA_FORMAT_MASK; + val |= PC_DISP1_PIX_DATA_FORMAT(RGB); + } + imx8qxp_pc_write(pc, PC_CTRL_REG, val); + + /* Only support bypass mode currently. */ + imx8qxp_pc_write_set(pc, PC_CTRL_REG, PC_DISP_BYPASS(ch->stream_id)); + + clk_disable_unprepare(pc->clk_apb); +} + +static void imx8qxp_pc_bridge_atomic_disable(struct drm_bridge *bridge, + struct drm_bridge_state *old_bridge_state) +{ + struct imx8qxp_pc_channel *ch = bridge->driver_private; + struct imx8qxp_pc *pc = ch->pc; + int ret; + + ret = pm_runtime_put(pc->dev); + if (ret < 0) + DRM_DEV_ERROR(pc->dev, "failed to put runtime PM: %d\n", ret); +} + +static const u32 imx8qxp_pc_bus_output_fmts[] = { + MEDIA_BUS_FMT_RGB888_1X36_CPADLO, + MEDIA_BUS_FMT_RGB666_1X36_CPADLO, +}; + +static bool imx8qxp_pc_bus_output_fmt_supported(u32 fmt) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(imx8qxp_pc_bus_output_fmts); i++) { + if (imx8qxp_pc_bus_output_fmts[i] == fmt) + return true; + } + + return false; +} + +static u32 * +imx8qxp_pc_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + u32 output_fmt, + unsigned int *num_input_fmts) +{ + u32 *input_fmts; + + if (!imx8qxp_pc_bus_output_fmt_supported(output_fmt)) + return NULL; + + *num_input_fmts = 1; + + input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL); + if (!input_fmts) + return NULL; + + switch (output_fmt) { + case MEDIA_BUS_FMT_RGB888_1X36_CPADLO: + input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X30_CPADLO; + break; + case MEDIA_BUS_FMT_RGB666_1X36_CPADLO: + input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X30_CPADLO; + break; + default: + kfree(input_fmts); + input_fmts = NULL; + break; + } + + return input_fmts; +} + +static u32 * +imx8qxp_pc_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + unsigned int *num_output_fmts) +{ + *num_output_fmts = ARRAY_SIZE(imx8qxp_pc_bus_output_fmts); + return kmemdup(imx8qxp_pc_bus_output_fmts, + sizeof(imx8qxp_pc_bus_output_fmts), GFP_KERNEL); +} + +static const struct drm_bridge_funcs imx8qxp_pc_bridge_funcs = { + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, + .atomic_reset = drm_atomic_helper_bridge_reset, + .mode_valid = imx8qxp_pc_bridge_mode_valid, + .attach = imx8qxp_pc_bridge_attach, + .mode_set = imx8qxp_pc_bridge_mode_set, + .atomic_disable = imx8qxp_pc_bridge_atomic_disable, + .atomic_get_input_bus_fmts = + imx8qxp_pc_bridge_atomic_get_input_bus_fmts, + .atomic_get_output_bus_fmts = + imx8qxp_pc_bridge_atomic_get_output_bus_fmts, +}; + +static int imx8qxp_pc_bridge_probe(struct platform_device *pdev) +{ + struct imx8qxp_pc *pc; + struct imx8qxp_pc_channel *ch; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct device_node *child, *remote; + u32 i; + int ret; + + pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL); + if (!pc) + return -ENOMEM; + + pc->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pc->base)) + return PTR_ERR(pc->base); + + pc->dev = dev; + + pc->clk_apb = devm_clk_get(dev, "apb"); + if (IS_ERR(pc->clk_apb)) { + ret = PTR_ERR(pc->clk_apb); + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(dev, "failed to get apb clock: %d\n", + ret); + return ret; + } + + platform_set_drvdata(pdev, pc); + pm_runtime_enable(dev); + + for_each_available_child_of_node(np, child) { + ret = of_property_read_u32(child, "reg", &i); + if (ret || i > 1) { + ret = -EINVAL; + DRM_DEV_ERROR(dev, + "invalid channel(%u) node address\n", i); + goto free_child; + } + + ch = &pc->ch[i]; + ch->pc = pc; + ch->stream_id = i; + + remote = of_graph_get_remote_node(child, 1, 0); + if (!remote) { + ret = -ENODEV; + DRM_DEV_ERROR(dev, + "channel%u failed to get port1's remote node: %d\n", + i, ret); + goto free_child; + } + + ch->next_bridge = of_drm_find_bridge(remote); + if (!ch->next_bridge) { + of_node_put(remote); + ret = -EPROBE_DEFER; + DRM_DEV_DEBUG_DRIVER(dev, + "channel%u failed to find next bridge: %d\n", + i, ret); + goto free_child; + } + + of_node_put(remote); + + ch->bridge.driver_private = ch; + ch->bridge.funcs = &imx8qxp_pc_bridge_funcs; + ch->bridge.of_node = child; + ch->is_available = true; + + drm_bridge_add(&ch->bridge); + } + + return 0; + +free_child: + of_node_put(child); + + if (i == 1 && pc->ch[0].next_bridge) + drm_bridge_remove(&pc->ch[0].bridge); + + pm_runtime_disable(dev); + return ret; +} + +static int imx8qxp_pc_bridge_remove(struct platform_device *pdev) +{ + struct imx8qxp_pc *pc = platform_get_drvdata(pdev); + struct imx8qxp_pc_channel *ch; + int i; + + for (i = 0; i < 2; i++) { + ch = &pc->ch[i]; + + if (!ch->is_available) + continue; + + drm_bridge_remove(&ch->bridge); + ch->is_available = false; + } + + pm_runtime_disable(&pdev->dev); + + return 0; +} + +static int __maybe_unused imx8qxp_pc_runtime_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct imx8qxp_pc *pc = platform_get_drvdata(pdev); + int ret; + + ret = clk_prepare_enable(pc->clk_apb); + if (ret) + DRM_DEV_ERROR(pc->dev, "%s: failed to enable apb clock: %d\n", + __func__, ret); + + /* Disable pixel combiner by full reset. */ + imx8qxp_pc_write_clr(pc, PC_SW_RESET_REG, PC_FULL_RESET_N); + + clk_disable_unprepare(pc->clk_apb); + + /* Ensure the reset takes effect. */ + usleep_range(10, 20); + + return ret; +} + +static int __maybe_unused imx8qxp_pc_runtime_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct imx8qxp_pc *pc = platform_get_drvdata(pdev); + int ret; + + ret = clk_prepare_enable(pc->clk_apb); + if (ret) { + DRM_DEV_ERROR(pc->dev, "%s: failed to enable apb clock: %d\n", + __func__, ret); + return ret; + } + + /* out of reset */ + imx8qxp_pc_write_set(pc, PC_SW_RESET_REG, PC_FULL_RESET_N); + + clk_disable_unprepare(pc->clk_apb); + + return ret; +} + +static const struct dev_pm_ops imx8qxp_pc_pm_ops = { + SET_RUNTIME_PM_OPS(imx8qxp_pc_runtime_suspend, + imx8qxp_pc_runtime_resume, NULL) +}; + +static const struct of_device_id imx8qxp_pc_dt_ids[] = { + { .compatible = "fsl,imx8qm-pixel-combiner", }, + { .compatible = "fsl,imx8qxp-pixel-combiner", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx8qxp_pc_dt_ids); + +static struct platform_driver imx8qxp_pc_bridge_driver = { + .probe = imx8qxp_pc_bridge_probe, + .remove = imx8qxp_pc_bridge_remove, + .driver = { + .pm = &imx8qxp_pc_pm_ops, + .name = DRIVER_NAME, + .of_match_table = imx8qxp_pc_dt_ids, + }, +}; +module_platform_driver(imx8qxp_pc_bridge_driver); + +MODULE_DESCRIPTION("i.MX8QM/QXP pixel combiner bridge driver"); +MODULE_AUTHOR("Liu Ying victor.liu@nxp.com"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRIVER_NAME);
This patch adds bindings for i.MX8qm/qxp display pixel link.
Signed-off-by: Liu Ying victor.liu@nxp.com --- .../display/bridge/fsl,imx8qxp-pixel-link.yaml | 128 +++++++++++++++++++++ 1 file changed, 128 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml new file mode 100644 index 00000000..fd24a0e --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8qm/qxp Display Pixel Link + +maintainers: + - Liu Ying victor.liu@nxp.com + +description: | + The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard + asynchronous linkage between pixel sources(display controller or + camera module) and pixel consumers(imaging or displays). + It consists of two distinct functions, a pixel transfer function and a + control interface. Multiple pixel channels can exist per one control channel. + This binding documentation is only for pixel links whose pixel sources are + display controllers. + +properties: + compatible: + enum: + - fsl,imx8qm-dc-pixel-link + - fsl,imx8qxp-dc-pixel-link + + ports: + type: object + description: | + A node containing pixel link input & output port nodes with endpoint + definitions as documented in + Documentation/devicetree/bindings/media/video-interfaces.txt + Documentation/devicetree/bindings/graph.txt + + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + port@0: + type: object + description: The pixel link input port node from upstream video source. + + properties: + reg: + const: 0 + + required: + - reg + + patternProperties: + "^port@[1-4]$": + type: object + description: The pixel link output port node to downstream bridge. + + properties: + reg: + enum: [ 1, 2, 3, 4 ] + + required: + - reg + + required: + - "#address-cells" + - "#size-cells" + - port@0 + + anyOf: + - required: + - port@1 + - required: + - port@2 + - required: + - port@3 + - required: + - port@4 + + additionalProperties: false + +required: + - compatible + - ports + +additionalProperties: false + +examples: + - | + dc0-pixel-link0 { + compatible = "fsl,imx8qxp-dc-pixel-link"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* from dc0 pixel combiner channel0 */ + port@0 { + reg = <0>; + + dc0_pixel_link0_dc0_pixel_combiner_ch0: endpoint { + remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_pixel_link0>; + }; + }; + + /* to PXL2DPIs in MIPI/LVDS combo subsystems */ + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + dc0_pixel_link0_mipi_lvds_0_pxl2dpi: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link0>; + }; + + dc0_pixel_link0_mipi_lvds_1_pxl2dpi: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link0>; + }; + }; + + /* to imaging subsystem */ + port@4 { + reg = <4>; + }; + }; + };
On Thu, Dec 17, 2020 at 05:59:25PM +0800, Liu Ying wrote:
This patch adds bindings for i.MX8qm/qxp display pixel link.
Signed-off-by: Liu Ying victor.liu@nxp.com
.../display/bridge/fsl,imx8qxp-pixel-link.yaml | 128 +++++++++++++++++++++ 1 file changed, 128 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml new file mode 100644 index 00000000..fd24a0e --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: Freescale i.MX8qm/qxp Display Pixel Link
+maintainers:
- Liu Ying victor.liu@nxp.com
+description: |
- The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
- asynchronous linkage between pixel sources(display controller or
- camera module) and pixel consumers(imaging or displays).
- It consists of two distinct functions, a pixel transfer function and a
- control interface. Multiple pixel channels can exist per one control channel.
- This binding documentation is only for pixel links whose pixel sources are
- display controllers.
Perhaps some information about how this 'device' is accessed because you have no control interface.
+properties:
- compatible:
- enum:
- fsl,imx8qm-dc-pixel-link- fsl,imx8qxp-dc-pixel-link- ports:
- type: object
- description: |
A node containing pixel link input & output port nodes with endpointdefinitions as documented inDocumentation/devicetree/bindings/media/video-interfaces.txtDocumentation/devicetree/bindings/graph.txt- properties:
'#address-cells':const: 1'#size-cells':const: 0port@0:type: objectdescription: The pixel link input port node from upstream video source.properties:reg:const: 0required:- reg
You can drop 'reg' parts.
- patternProperties:
"^port@[1-4]$":type: objectdescription: The pixel link output port node to downstream bridge.properties:reg:enum: [ 1, 2, 3, 4 ]required:- reg- required:
- "#address-cells"- "#size-cells"- port@0- anyOf:
- required:- port@1- required:- port@2- required:- port@3- required:- port@4- additionalProperties: false
+required:
- compatible
- ports
+additionalProperties: false
+examples:
- |
- dc0-pixel-link0 {
compatible = "fsl,imx8qxp-dc-pixel-link";ports {#address-cells = <1>;#size-cells = <0>;/* from dc0 pixel combiner channel0 */port@0 {reg = <0>;dc0_pixel_link0_dc0_pixel_combiner_ch0: endpoint {remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_pixel_link0>;};};/* to PXL2DPIs in MIPI/LVDS combo subsystems */port@1 {#address-cells = <1>;#size-cells = <0>;reg = <1>;dc0_pixel_link0_mipi_lvds_0_pxl2dpi: endpoint@0 {reg = <0>;remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link0>;};dc0_pixel_link0_mipi_lvds_1_pxl2dpi: endpoint@1 {reg = <1>;remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link0>;};};/* to imaging subsystem */port@4 {reg = <4>;};};- };
-- 2.7.4
On Mon, 2020-12-21 at 15:31 -0700, Rob Herring wrote:
On Thu, Dec 17, 2020 at 05:59:25PM +0800, Liu Ying wrote:
This patch adds bindings for i.MX8qm/qxp display pixel link.
Signed-off-by: Liu Ying victor.liu@nxp.com
.../display/bridge/fsl,imx8qxp-pixel-link.yaml | 128 +++++++++++++++++++++ 1 file changed, 128 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml new file mode 100644 index 00000000..fd24a0e --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.... +$schema: https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree....
+title: Freescale i.MX8qm/qxp Display Pixel Link
+maintainers:
- Liu Ying victor.liu@nxp.com
+description: |
- The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
- asynchronous linkage between pixel sources(display controller or
- camera module) and pixel consumers(imaging or displays).
- It consists of two distinct functions, a pixel transfer function and a
- control interface. Multiple pixel channels can exist per one control channel.
- This binding documentation is only for pixel links whose pixel sources are
- display controllers.
Perhaps some information about how this 'device' is accessed because you have no control interface.
The i.MX8qm/qxp Display Pixel Link is controlled by SCU firmare. Will add the information.
+properties:
- compatible:
- enum:
- fsl,imx8qm-dc-pixel-link- fsl,imx8qxp-dc-pixel-link- ports:
- type: object
- description: |
A node containing pixel link input & output port nodes with endpointdefinitions as documented inDocumentation/devicetree/bindings/media/video-interfaces.txtDocumentation/devicetree/bindings/graph.txt- properties:
'#address-cells':const: 1'#size-cells':const: 0port@0:type: objectdescription: The pixel link input port node from upstream video source.properties:reg:const: 0required:- regYou can drop 'reg' parts.
Will drop the 'required' parts for 'reg'. Also, will drop the '#address-cells' and '#size-cells' parts if no objections.
Thanks, Liu Ying
- patternProperties:
"^port@[1-4]$":type: objectdescription: The pixel link output port node to downstream bridge.properties:reg:enum: [ 1, 2, 3, 4 ]required:- reg- required:
- "#address-cells"- "#size-cells"- port@0- anyOf:
- required:- port@1- required:- port@2- required:- port@3- required:- port@4- additionalProperties: false
+required:
- compatible
- ports
+additionalProperties: false
+examples:
- |
- dc0-pixel-link0 {
compatible = "fsl,imx8qxp-dc-pixel-link";ports {#address-cells = <1>;#size-cells = <0>;/* from dc0 pixel combiner channel0 */port@0 {reg = <0>;dc0_pixel_link0_dc0_pixel_combiner_ch0: endpoint {remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_pixel_link0>;};};/* to PXL2DPIs in MIPI/LVDS combo subsystems */port@1 {#address-cells = <1>;#size-cells = <0>;reg = <1>;dc0_pixel_link0_mipi_lvds_0_pxl2dpi: endpoint@0 {reg = <0>;remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link0>;};dc0_pixel_link0_mipi_lvds_1_pxl2dpi: endpoint@1 {reg = <1>;remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link0>;};};/* to imaging subsystem */port@4 {reg = <4>;};};- };
-- 2.7.4
Hi Liu,
Thank you for the patch.
On Thu, Dec 17, 2020 at 05:59:25PM +0800, Liu Ying wrote:
This patch adds bindings for i.MX8qm/qxp display pixel link.
Signed-off-by: Liu Ying victor.liu@nxp.com
.../display/bridge/fsl,imx8qxp-pixel-link.yaml | 128 +++++++++++++++++++++ 1 file changed, 128 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml new file mode 100644 index 00000000..fd24a0e --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: Freescale i.MX8qm/qxp Display Pixel Link
+maintainers:
- Liu Ying victor.liu@nxp.com
+description: |
- The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
- asynchronous linkage between pixel sources(display controller or
- camera module) and pixel consumers(imaging or displays).
- It consists of two distinct functions, a pixel transfer function and a
- control interface. Multiple pixel channels can exist per one control channel.
- This binding documentation is only for pixel links whose pixel sources are
- display controllers.
+properties:
- compatible:
- enum:
- fsl,imx8qm-dc-pixel-link- fsl,imx8qxp-dc-pixel-link- ports:
- type: object
- description: |
A node containing pixel link input & output port nodes with endpointdefinitions as documented inDocumentation/devicetree/bindings/media/video-interfaces.txtDocumentation/devicetree/bindings/graph.txt
With Rob's patch that convert both of these to YAML, I think you can drop the references to these documents, and use
$ref: /schemas/graph.yaml#/properties/ports
in the ports node, and
$ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false
in the port nodes, dropping the type property. You will also be able to drop
additionalProperties: false
for the ports node.
- properties:
'#address-cells':const: 1'#size-cells':const: 0port@0:type: objectdescription: The pixel link input port node from upstream video source.properties:reg:const: 0required:- reg- patternProperties:
"^port@[1-4]$":type: objectdescription: The pixel link output port node to downstream bridge.properties:reg:enum: [ 1, 2, 3, 4 ]required:- reg- required:
- "#address-cells"- "#size-cells"- port@0- anyOf:
- required:- port@1- required:- port@2- required:- port@3- required:- port@4
Do all DPL instances have four output ports ? If so I would make all of them mandatory, as they describe the hardware. They can be left without any endpoing if they're not connected to anything.
- additionalProperties: false
+required:
- compatible
- ports
+additionalProperties: false
+examples:
- |
- dc0-pixel-link0 {
compatible = "fsl,imx8qxp-dc-pixel-link";ports {#address-cells = <1>;#size-cells = <0>;/* from dc0 pixel combiner channel0 */port@0 {reg = <0>;dc0_pixel_link0_dc0_pixel_combiner_ch0: endpoint {remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_pixel_link0>;};};/* to PXL2DPIs in MIPI/LVDS combo subsystems */port@1 {#address-cells = <1>;#size-cells = <0>;reg = <1>;dc0_pixel_link0_mipi_lvds_0_pxl2dpi: endpoint@0 {reg = <0>;remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link0>;};dc0_pixel_link0_mipi_lvds_1_pxl2dpi: endpoint@1 {reg = <1>;remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link0>;};};/* to imaging subsystem */port@4 {reg = <4>;};};- };
Hi,
On Tue, 2020-12-22 at 09:09 +0200, Laurent Pinchart wrote:
Hi Liu,
Thank you for the patch.
On Thu, Dec 17, 2020 at 05:59:25PM +0800, Liu Ying wrote:
This patch adds bindings for i.MX8qm/qxp display pixel link.
Signed-off-by: Liu Ying victor.liu@nxp.com
.../display/bridge/fsl,imx8qxp-pixel-link.yaml | 128 +++++++++++++++++++++ 1 file changed, 128 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml new file mode 100644 index 00000000..fd24a0e --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.... +$schema: https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree....
+title: Freescale i.MX8qm/qxp Display Pixel Link
+maintainers:
- Liu Ying victor.liu@nxp.com
+description: |
- The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
- asynchronous linkage between pixel sources(display controller or
- camera module) and pixel consumers(imaging or displays).
- It consists of two distinct functions, a pixel transfer function and a
- control interface. Multiple pixel channels can exist per one control channel.
- This binding documentation is only for pixel links whose pixel sources are
- display controllers.
+properties:
- compatible:
- enum:
- fsl,imx8qm-dc-pixel-link- fsl,imx8qxp-dc-pixel-link- ports:
- type: object
- description: |
A node containing pixel link input & output port nodes with endpointdefinitions as documented inDocumentation/devicetree/bindings/media/video-interfaces.txtDocumentation/devicetree/bindings/graph.txtWith Rob's patch that convert both of these to YAML, I think you can drop the references to these documents, and use
$ref: /schemas/graph.yaml#/properties/ports
in the ports node, and
$ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false
in the port nodes, dropping the type property. You will also be able to drop
additionalProperties: false
for the ports node.
Thanks for the suggestion.
Rob looked this binding and provided some comments without requiring to reference the new graph.yaml.
Rob, do you think it is needed for now?
- properties:
'#address-cells':const: 1'#size-cells':const: 0port@0:type: objectdescription: The pixel link input port node from upstream video source.properties:reg:const: 0required:- reg- patternProperties:
"^port@[1-4]$":type: objectdescription: The pixel link output port node to downstream bridge.properties:reg:enum: [ 1, 2, 3, 4 ]required:- reg- required:
- "#address-cells"- "#size-cells"- port@0- anyOf:
- required:- port@1- required:- port@2- required:- port@3- required:- port@4Do all DPL instances have four output ports ? If so I would make all of them mandatory, as they describe the hardware. They can be left without any endpoing if they're not connected to anything.
Yes, I think all DPL instances have 4 output ports and some don't connect to anything. I'll require all of them in the next version.
Thanks, Liu Ying
- additionalProperties: false
+required:
- compatible
- ports
+additionalProperties: false
+examples:
- |
- dc0-pixel-link0 {
compatible = "fsl,imx8qxp-dc-pixel-link";ports {#address-cells = <1>;#size-cells = <0>;/* from dc0 pixel combiner channel0 */port@0 {reg = <0>;dc0_pixel_link0_dc0_pixel_combiner_ch0: endpoint {remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_pixel_link0>;};};/* to PXL2DPIs in MIPI/LVDS combo subsystems */port@1 {#address-cells = <1>;#size-cells = <0>;reg = <1>;dc0_pixel_link0_mipi_lvds_0_pxl2dpi: endpoint@0 {reg = <0>;remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link0>;};dc0_pixel_link0_mipi_lvds_1_pxl2dpi: endpoint@1 {reg = <1>;remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link0>;};};/* to imaging subsystem */port@4 {reg = <4>;};};- };
This patch adds a drm bridge driver for i.MX8qm/qxp display pixel link. The pixel link forms a standard asynchronous linkage between pixel sources(display controller or camera module) and pixel consumers(imaging or displays). It consists of two distinct functions, a pixel transfer function and a control interface.
Signed-off-by: Liu Ying victor.liu@nxp.com --- drivers/gpu/drm/bridge/imx/Kconfig | 8 + drivers/gpu/drm/bridge/imx/Makefile | 1 + drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c | 411 ++++++++++++++++++++++++ 3 files changed, 420 insertions(+) create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig index f1c91b6..4d1f027 100644 --- a/drivers/gpu/drm/bridge/imx/Kconfig +++ b/drivers/gpu/drm/bridge/imx/Kconfig @@ -6,3 +6,11 @@ config DRM_IMX8QXP_PIXEL_COMBINER help Choose this to enable pixel combiner found in Freescale i.MX8qm/qxp processors. + +config DRM_IMX8QXP_PIXEL_LINK + tristate "Freescale i.MX8QM/QXP display pixel link" + depends on OF + select DRM_KMS_HELPER + help + Choose this to enable display pixel link found in + Freescale i.MX8qm/qxp processors. diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile index 7d7c8d6..c15469f 100644 --- a/drivers/gpu/drm/bridge/imx/Makefile +++ b/drivers/gpu/drm/bridge/imx/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o +obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c new file mode 100644 index 00000000..1af7467 --- /dev/null +++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c @@ -0,0 +1,411 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include <linux/firmware/imx/svc/misc.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_graph.h> +#include <linux/platform_device.h> + +#include <drm/drm_atomic_state_helper.h> +#include <drm/drm_bridge.h> +#include <drm/drm_print.h> + +#include <dt-bindings/firmware/imx/rsrc.h> + +#define DRIVER_NAME "imx8qxp-display-pixel-link" +#define PL_MAX_MST_ADDR 3 + +struct imx8qxp_pixel_link { + struct drm_bridge bridge; + struct drm_bridge *next_bridge; + struct device *dev; + struct imx_sc_ipc *ipc_handle; + int id; + int stream_id; + int dc_id; + u32 sink_rsc; + u32 mst_addr; + u8 mst_addr_ctrl; + u8 mst_en_ctrl; + u8 mst_vld_ctrl; + u8 sync_ctrl; +}; + +#define DEFINE_IMX8QXP_PIXEL_LINK_ENABLE_CTRL(name) \ +static void \ +imx8qxp_pixel_link_enable_##name(struct imx8qxp_pixel_link *pl) \ +{ \ + int ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc, \ + pl->name##_ctrl, true); \ + if (ret) \ + DRM_DEV_ERROR(pl->dev, \ + "failed to enable DC%d stream%d pixel link " \ + #name ": %d\n", pl->dc_id, pl->stream_id, ret); \ +} + +DEFINE_IMX8QXP_PIXEL_LINK_ENABLE_CTRL(mst_en) +DEFINE_IMX8QXP_PIXEL_LINK_ENABLE_CTRL(mst_vld) +DEFINE_IMX8QXP_PIXEL_LINK_ENABLE_CTRL(sync) + +#define DEFINE_IMX8QXP_PIXEL_LINK_DISABLE_CTRL(name) \ +static int \ +imx8qxp_pixel_link_disable_##name(struct imx8qxp_pixel_link *pl) \ +{ \ + int ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc, \ + pl->name##_ctrl, false); \ + if (ret) \ + DRM_DEV_ERROR(pl->dev, \ + "failed to disable DC%d stream%d pixel link " \ + #name ": %d\n", pl->dc_id, pl->stream_id, ret); \ + \ + return ret; \ +} + +DEFINE_IMX8QXP_PIXEL_LINK_DISABLE_CTRL(mst_en) +DEFINE_IMX8QXP_PIXEL_LINK_DISABLE_CTRL(mst_vld) +DEFINE_IMX8QXP_PIXEL_LINK_DISABLE_CTRL(sync) + +static void imx8qxp_pixel_link_set_mst_addr(struct imx8qxp_pixel_link *pl) +{ + int ret; + + ret = imx_sc_misc_set_control(pl->ipc_handle, + pl->sink_rsc, pl->mst_addr_ctrl, + pl->mst_addr); + if (ret) + DRM_DEV_ERROR(pl->dev, + "failed to set DC%d stream%d pixel link mst addr(%u): %d\n", + pl->dc_id, pl->stream_id, pl->mst_addr, ret); +} + +static int imx8qxp_pixel_link_bridge_attach(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags) +{ + struct imx8qxp_pixel_link *pl = bridge->driver_private; + + if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) { + DRM_DEV_ERROR(pl->dev, + "do not support creating a drm_connector\n"); + return -EINVAL; + } + + if (!bridge->encoder) { + DRM_DEV_ERROR(pl->dev, "missing encoder\n"); + return -ENODEV; + } + + return drm_bridge_attach(bridge->encoder, + pl->next_bridge, bridge, + DRM_BRIDGE_ATTACH_NO_CONNECTOR); +} + +static void +imx8qxp_pixel_link_bridge_mode_set(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + const struct drm_display_mode *adjusted_mode) +{ + struct imx8qxp_pixel_link *pl = bridge->driver_private; + + imx8qxp_pixel_link_set_mst_addr(pl); +} + +static void imx8qxp_pixel_link_bridge_atomic_enable(struct drm_bridge *bridge, + struct drm_bridge_state *old_bridge_state) +{ + struct imx8qxp_pixel_link *pl = bridge->driver_private; + + imx8qxp_pixel_link_enable_mst_en(pl); + imx8qxp_pixel_link_enable_mst_vld(pl); + imx8qxp_pixel_link_enable_sync(pl); +} + +static void imx8qxp_pixel_link_bridge_atomic_disable(struct drm_bridge *bridge, + struct drm_bridge_state *old_bridge_state) +{ + struct imx8qxp_pixel_link *pl = bridge->driver_private; + + imx8qxp_pixel_link_disable_mst_en(pl); + imx8qxp_pixel_link_disable_mst_vld(pl); + imx8qxp_pixel_link_disable_sync(pl); +} + +static const u32 imx8qxp_pixel_link_bus_output_fmts[] = { + MEDIA_BUS_FMT_RGB888_1X36_CPADLO, + MEDIA_BUS_FMT_RGB666_1X36_CPADLO, +}; + +static bool imx8qxp_pixel_link_bus_output_fmt_supported(u32 fmt) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(imx8qxp_pixel_link_bus_output_fmts); i++) { + if (imx8qxp_pixel_link_bus_output_fmts[i] == fmt) + return true; + } + + return false; +} + +static u32 * +imx8qxp_pixel_link_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + u32 output_fmt, + unsigned int *num_input_fmts) +{ + u32 *input_fmts; + + if (!imx8qxp_pixel_link_bus_output_fmt_supported(output_fmt)) + return NULL; + + *num_input_fmts = 1; + + input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL); + if (!input_fmts) + return NULL; + + input_fmts[0] = output_fmt; + + return input_fmts; +} + +static u32 * +imx8qxp_pixel_link_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + unsigned int *num_output_fmts) +{ + *num_output_fmts = ARRAY_SIZE(imx8qxp_pixel_link_bus_output_fmts); + return kmemdup(imx8qxp_pixel_link_bus_output_fmts, + sizeof(imx8qxp_pixel_link_bus_output_fmts), GFP_KERNEL); +} + +static const struct drm_bridge_funcs imx8qxp_pixel_link_bridge_funcs = { + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, + .atomic_reset = drm_atomic_helper_bridge_reset, + .attach = imx8qxp_pixel_link_bridge_attach, + .mode_set = imx8qxp_pixel_link_bridge_mode_set, + .atomic_enable = imx8qxp_pixel_link_bridge_atomic_enable, + .atomic_disable = imx8qxp_pixel_link_bridge_atomic_disable, + .atomic_get_input_bus_fmts = + imx8qxp_pixel_link_bridge_atomic_get_input_bus_fmts, + .atomic_get_output_bus_fmts = + imx8qxp_pixel_link_bridge_atomic_get_output_bus_fmts, +}; + +static struct drm_bridge * +imx8qxp_pixel_link_find_next_bridge(struct imx8qxp_pixel_link *pl) +{ + struct device_node *np = pl->dev->of_node; + struct device_node *port, *ep, *remote; + struct of_endpoint endpoint; + struct drm_bridge *next_bridge[2], *err_bridge; + u32 port_id, vld_port_id; + int port_cnt = 0, ep_cnt = 0; + int bridge_sel = 0; /* select the first next bridge by default */ + int ret; + + for (port_id = 1; port_id <= PL_MAX_MST_ADDR + 1; port_id++) { + port = of_graph_get_port_by_id(np, port_id); + if (!port) + continue; + + if (of_device_is_available(port)) { + port_cnt++; + vld_port_id = port_id; + } + + of_node_put(port); + } + + /* check the number of available output ports */ + if (port_cnt == 0) { + DRM_DEV_ERROR(pl->dev, "no available output port\n"); + return ERR_PTR(-ENODEV); + } else if (port_cnt > 1) { + DRM_DEV_ERROR(pl->dev, "invalid available output ports: %d\n", + port_cnt); + return ERR_PTR(-ENOTSUPP); + } + + port = of_graph_get_port_by_id(np, vld_port_id); + if (!port) { + DRM_DEV_ERROR(pl->dev, "failed to get output port\n"); + return ERR_PTR(-ENODEV); + } + + for_each_available_child_of_node(port, ep) { + /* 2 available endpoints at most */ + if (++ep_cnt > 2) { + DRM_DEV_ERROR(pl->dev, + "invalid available endpoints: %d\n", + ep_cnt); + err_bridge = ERR_PTR(-ENOTSUPP); + of_node_put(ep); + goto err; + } + + ret = of_graph_parse_endpoint(ep, &endpoint); + if (ret) { + DRM_DEV_ERROR(pl->dev, "failed to parse endpoint: %d\n", + ret); + err_bridge = ERR_PTR(ret); + of_node_put(ep); + goto err; + } + + remote = of_graph_get_remote_port_parent(ep); + if (!remote || !of_device_is_available(remote)) { + DRM_DEV_ERROR(pl->dev, + "endpoint%u has no available remote\n", + endpoint.id); + of_node_put(remote); + of_node_put(ep); + err_bridge = ERR_PTR(-ENODEV); + goto err; + } else if (!of_device_is_available(remote->parent)) { + DRM_DEV_ERROR(pl->dev, + "endpoint%u remote parent is not available\n", + endpoint.id); + of_node_put(remote); + of_node_put(ep); + err_bridge = ERR_PTR(-ENODEV); + goto err; + } + + next_bridge[ep_cnt - 1] = of_drm_find_bridge(remote); + if (!next_bridge[ep_cnt - 1]) { + of_node_put(remote); + of_node_put(ep); + err_bridge = ERR_PTR(-EPROBE_DEFER); + goto err; + } + + /* specially select the next bridge with companion PXL2DPI */ + if (of_find_property(remote, "fsl,companion-pxl2dpi", NULL)) + bridge_sel = ep_cnt - 1; + + of_node_put(remote); + } + + pl->mst_addr = vld_port_id - 1; + + of_node_put(port); + + return next_bridge[bridge_sel]; +err: + of_node_put(port); + + return err_bridge; +} + +static int imx8qxp_pixel_link_bridge_probe(struct platform_device *pdev) +{ + struct imx8qxp_pixel_link *pl; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + int ret; + + pl = devm_kzalloc(dev, sizeof(*pl), GFP_KERNEL); + if (!pl) + return -ENOMEM; + + ret = imx_scu_get_handle(&pl->ipc_handle); + if (ret) { + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(dev, "failed to get SCU ipc handle: %d\n", + ret); + return ret; + } + + pl->id = of_alias_get_id(np, "dc_pl"); + if (pl->id < 0) { + DRM_DEV_ERROR(dev, + "failed to get pixel link node alias id: %d\n", + pl->id); + return pl->id; + } + + pl->dev = dev; + + pl->dc_id = pl->id / 2; + pl->stream_id = pl->id % 2; + + pl->sink_rsc = pl->dc_id ? IMX_SC_R_DC_1 : IMX_SC_R_DC_0; + + if (pl->stream_id == 0) { + pl->mst_addr_ctrl = IMX_SC_C_PXL_LINK_MST1_ADDR; + pl->mst_en_ctrl = IMX_SC_C_PXL_LINK_MST1_ENB; + pl->mst_vld_ctrl = IMX_SC_C_PXL_LINK_MST1_VLD; + pl->sync_ctrl = IMX_SC_C_SYNC_CTRL0; + } else { + pl->mst_addr_ctrl = IMX_SC_C_PXL_LINK_MST2_ADDR; + pl->mst_en_ctrl = IMX_SC_C_PXL_LINK_MST2_ENB; + pl->mst_vld_ctrl = IMX_SC_C_PXL_LINK_MST2_VLD; + pl->sync_ctrl = IMX_SC_C_SYNC_CTRL1; + } + + /* disable all controls to POR default */ + ret = imx8qxp_pixel_link_disable_mst_en(pl); + ret |= imx8qxp_pixel_link_disable_mst_vld(pl); + ret |= imx8qxp_pixel_link_disable_sync(pl); + if (ret) + return ret; + + pl->next_bridge = imx8qxp_pixel_link_find_next_bridge(pl); + if (IS_ERR(pl->next_bridge)) { + ret = PTR_ERR(pl->next_bridge); + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(dev, "failed to find next bridge: %d\n", + ret); + return ret; + } + + platform_set_drvdata(pdev, pl); + + pl->bridge.driver_private = pl; + pl->bridge.funcs = &imx8qxp_pixel_link_bridge_funcs; + pl->bridge.of_node = np; + + drm_bridge_add(&pl->bridge); + + return ret; +} + +static int imx8qxp_pixel_link_bridge_remove(struct platform_device *pdev) +{ + struct imx8qxp_pixel_link *pl = platform_get_drvdata(pdev); + + drm_bridge_remove(&pl->bridge); + + return 0; +} + +static const struct of_device_id imx8qxp_pixel_link_dt_ids[] = { + { .compatible = "fsl,imx8qm-dc-pixel-link", }, + { .compatible = "fsl,imx8qxp-dc-pixel-link", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx8qxp_pixel_link_dt_ids); + +static struct platform_driver imx8qxp_pixel_link_bridge_driver = { + .probe = imx8qxp_pixel_link_bridge_probe, + .remove = imx8qxp_pixel_link_bridge_remove, + .driver = { + .of_match_table = imx8qxp_pixel_link_dt_ids, + .name = DRIVER_NAME, + }, +}; +module_platform_driver(imx8qxp_pixel_link_bridge_driver); + +MODULE_DESCRIPTION("i.MX8QXP/QM display pixel link bridge driver"); +MODULE_AUTHOR("Liu Ying victor.liu@nxp.com"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRIVER_NAME);
On Thu, Dec 17, 2020 at 05:59:26PM +0800, Liu Ying wrote:
This patch adds a drm bridge driver for i.MX8qm/qxp display pixel link. The pixel link forms a standard asynchronous linkage between pixel sources(display controller or camera module) and pixel consumers(imaging or displays). It consists of two distinct functions, a pixel transfer function and a control interface.
Signed-off-by: Liu Ying victor.liu@nxp.com
drivers/gpu/drm/bridge/imx/Kconfig | 8 + drivers/gpu/drm/bridge/imx/Makefile | 1 + drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c | 411 ++++++++++++++++++++++++ 3 files changed, 420 insertions(+) create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig index f1c91b6..4d1f027 100644 --- a/drivers/gpu/drm/bridge/imx/Kconfig +++ b/drivers/gpu/drm/bridge/imx/Kconfig @@ -6,3 +6,11 @@ config DRM_IMX8QXP_PIXEL_COMBINER help Choose this to enable pixel combiner found in Freescale i.MX8qm/qxp processors.
+config DRM_IMX8QXP_PIXEL_LINK
- tristate "Freescale i.MX8QM/QXP display pixel link"
- depends on OF
- select DRM_KMS_HELPER
- help
Choose this to enable display pixel link found inFreescale i.MX8qm/qxp processors.diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile index 7d7c8d6..c15469f 100644 --- a/drivers/gpu/drm/bridge/imx/Makefile +++ b/drivers/gpu/drm/bridge/imx/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o +obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c new file mode 100644 index 00000000..1af7467 --- /dev/null +++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c @@ -0,0 +1,411 @@ +// SPDX-License-Identifier: GPL-2.0+
+/*
- Copyright 2020 NXP
- */
+#include <linux/firmware/imx/svc/misc.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_graph.h> +#include <linux/platform_device.h>
+#include <drm/drm_atomic_state_helper.h> +#include <drm/drm_bridge.h> +#include <drm/drm_print.h>
+#include <dt-bindings/firmware/imx/rsrc.h>
+#define DRIVER_NAME "imx8qxp-display-pixel-link" +#define PL_MAX_MST_ADDR 3
+struct imx8qxp_pixel_link {
- struct drm_bridge bridge;
- struct drm_bridge *next_bridge;
- struct device *dev;
- struct imx_sc_ipc *ipc_handle;
- int id;
- int stream_id;
- int dc_id;
- u32 sink_rsc;
- u32 mst_addr;
- u8 mst_addr_ctrl;
- u8 mst_en_ctrl;
- u8 mst_vld_ctrl;
- u8 sync_ctrl;
+};
+#define DEFINE_IMX8QXP_PIXEL_LINK_ENABLE_CTRL(name) \ +static void \ +imx8qxp_pixel_link_enable_##name(struct imx8qxp_pixel_link *pl) \ +{ \
- int ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc, \
pl->name##_ctrl, true); \- if (ret) \
DRM_DEV_ERROR(pl->dev, \"failed to enable DC%d stream%d pixel link " \#name ": %d\n", pl->dc_id, pl->stream_id, ret); \+}
+DEFINE_IMX8QXP_PIXEL_LINK_ENABLE_CTRL(mst_en) +DEFINE_IMX8QXP_PIXEL_LINK_ENABLE_CTRL(mst_vld) +DEFINE_IMX8QXP_PIXEL_LINK_ENABLE_CTRL(sync)
+#define DEFINE_IMX8QXP_PIXEL_LINK_DISABLE_CTRL(name) \ +static int \ +imx8qxp_pixel_link_disable_##name(struct imx8qxp_pixel_link *pl) \ +{ \
- int ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc, \
pl->name##_ctrl, false); \- if (ret) \
DRM_DEV_ERROR(pl->dev, \"failed to disable DC%d stream%d pixel link " \#name ": %d\n", pl->dc_id, pl->stream_id, ret); \\- return ret; \
+}
+DEFINE_IMX8QXP_PIXEL_LINK_DISABLE_CTRL(mst_en) +DEFINE_IMX8QXP_PIXEL_LINK_DISABLE_CTRL(mst_vld) +DEFINE_IMX8QXP_PIXEL_LINK_DISABLE_CTRL(sync)
+static void imx8qxp_pixel_link_set_mst_addr(struct imx8qxp_pixel_link *pl) +{
- int ret;
- ret = imx_sc_misc_set_control(pl->ipc_handle,
pl->sink_rsc, pl->mst_addr_ctrl,pl->mst_addr);- if (ret)
DRM_DEV_ERROR(pl->dev,"failed to set DC%d stream%d pixel link mst addr(%u): %d\n",pl->dc_id, pl->stream_id, pl->mst_addr, ret);+}
+static int imx8qxp_pixel_link_bridge_attach(struct drm_bridge *bridge,
enum drm_bridge_attach_flags flags)+{
- struct imx8qxp_pixel_link *pl = bridge->driver_private;
- if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
DRM_DEV_ERROR(pl->dev,"do not support creating a drm_connector\n");return -EINVAL;- }
- if (!bridge->encoder) {
DRM_DEV_ERROR(pl->dev, "missing encoder\n");return -ENODEV;- }
- return drm_bridge_attach(bridge->encoder,
pl->next_bridge, bridge,DRM_BRIDGE_ATTACH_NO_CONNECTOR);+}
+static void +imx8qxp_pixel_link_bridge_mode_set(struct drm_bridge *bridge,
const struct drm_display_mode *mode,const struct drm_display_mode *adjusted_mode)+{
- struct imx8qxp_pixel_link *pl = bridge->driver_private;
- imx8qxp_pixel_link_set_mst_addr(pl);
+}
+static void imx8qxp_pixel_link_bridge_atomic_enable(struct drm_bridge *bridge,
struct drm_bridge_state *old_bridge_state)+{
- struct imx8qxp_pixel_link *pl = bridge->driver_private;
- imx8qxp_pixel_link_enable_mst_en(pl);
- imx8qxp_pixel_link_enable_mst_vld(pl);
- imx8qxp_pixel_link_enable_sync(pl);
+}
+static void imx8qxp_pixel_link_bridge_atomic_disable(struct drm_bridge *bridge,
struct drm_bridge_state *old_bridge_state)+{
- struct imx8qxp_pixel_link *pl = bridge->driver_private;
- imx8qxp_pixel_link_disable_mst_en(pl);
- imx8qxp_pixel_link_disable_mst_vld(pl);
- imx8qxp_pixel_link_disable_sync(pl);
+}
+static const u32 imx8qxp_pixel_link_bus_output_fmts[] = {
- MEDIA_BUS_FMT_RGB888_1X36_CPADLO,
- MEDIA_BUS_FMT_RGB666_1X36_CPADLO,
+};
+static bool imx8qxp_pixel_link_bus_output_fmt_supported(u32 fmt) +{
- int i;
- for (i = 0; i < ARRAY_SIZE(imx8qxp_pixel_link_bus_output_fmts); i++) {
if (imx8qxp_pixel_link_bus_output_fmts[i] == fmt)return true;- }
- return false;
+}
+static u32 * +imx8qxp_pixel_link_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
struct drm_bridge_state *bridge_state,struct drm_crtc_state *crtc_state,struct drm_connector_state *conn_state,u32 output_fmt,unsigned int *num_input_fmts)+{
- u32 *input_fmts;
- if (!imx8qxp_pixel_link_bus_output_fmt_supported(output_fmt))
return NULL;- *num_input_fmts = 1;
- input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
- if (!input_fmts)
return NULL;- input_fmts[0] = output_fmt;
- return input_fmts;
+}
+static u32 * +imx8qxp_pixel_link_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
struct drm_bridge_state *bridge_state,struct drm_crtc_state *crtc_state,struct drm_connector_state *conn_state,unsigned int *num_output_fmts)+{
- *num_output_fmts = ARRAY_SIZE(imx8qxp_pixel_link_bus_output_fmts);
- return kmemdup(imx8qxp_pixel_link_bus_output_fmts,
sizeof(imx8qxp_pixel_link_bus_output_fmts), GFP_KERNEL);+}
+static const struct drm_bridge_funcs imx8qxp_pixel_link_bridge_funcs = {
- .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
- .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
- .atomic_reset = drm_atomic_helper_bridge_reset,
- .attach = imx8qxp_pixel_link_bridge_attach,
- .mode_set = imx8qxp_pixel_link_bridge_mode_set,
- .atomic_enable = imx8qxp_pixel_link_bridge_atomic_enable,
- .atomic_disable = imx8qxp_pixel_link_bridge_atomic_disable,
- .atomic_get_input_bus_fmts =
imx8qxp_pixel_link_bridge_atomic_get_input_bus_fmts,- .atomic_get_output_bus_fmts =
imx8qxp_pixel_link_bridge_atomic_get_output_bus_fmts,+};
+static struct drm_bridge * +imx8qxp_pixel_link_find_next_bridge(struct imx8qxp_pixel_link *pl) +{
- struct device_node *np = pl->dev->of_node;
- struct device_node *port, *ep, *remote;
- struct of_endpoint endpoint;
- struct drm_bridge *next_bridge[2], *err_bridge;
- u32 port_id, vld_port_id;
- int port_cnt = 0, ep_cnt = 0;
- int bridge_sel = 0; /* select the first next bridge by default */
- int ret;
- for (port_id = 1; port_id <= PL_MAX_MST_ADDR + 1; port_id++) {
port = of_graph_get_port_by_id(np, port_id);if (!port)continue;if (of_device_is_available(port)) {port_cnt++;vld_port_id = port_id;}of_node_put(port);- }
- /* check the number of available output ports */
- if (port_cnt == 0) {
DRM_DEV_ERROR(pl->dev, "no available output port\n");return ERR_PTR(-ENODEV);- } else if (port_cnt > 1) {
DRM_DEV_ERROR(pl->dev, "invalid available output ports: %d\n",port_cnt);return ERR_PTR(-ENOTSUPP);- }
- port = of_graph_get_port_by_id(np, vld_port_id);
- if (!port) {
DRM_DEV_ERROR(pl->dev, "failed to get output port\n");return ERR_PTR(-ENODEV);- }
- for_each_available_child_of_node(port, ep) {
for_each_endpoint_of_node
/* 2 available endpoints at most */if (++ep_cnt > 2) {DRM_DEV_ERROR(pl->dev,"invalid available endpoints: %d\n",ep_cnt);
Not really the kernel's job to validate the DT. Just get endpoints 0 and 1 if those are the 2 you want.
err_bridge = ERR_PTR(-ENOTSUPP);of_node_put(ep);goto err;}ret = of_graph_parse_endpoint(ep, &endpoint);if (ret) {DRM_DEV_ERROR(pl->dev, "failed to parse endpoint: %d\n",ret);err_bridge = ERR_PTR(ret);of_node_put(ep);goto err;}remote = of_graph_get_remote_port_parent(ep);if (!remote || !of_device_is_available(remote)) {DRM_DEV_ERROR(pl->dev,"endpoint%u has no available remote\n",endpoint.id);of_node_put(remote);of_node_put(ep);err_bridge = ERR_PTR(-ENODEV);goto err;} else if (!of_device_is_available(remote->parent)) {DRM_DEV_ERROR(pl->dev,"endpoint%u remote parent is not available\n",endpoint.id);of_node_put(remote);of_node_put(ep);err_bridge = ERR_PTR(-ENODEV);goto err;}
Rewrite all this in terms of of_graph_get_remote_node(). It takes care of of_device_is_available checking for you.
next_bridge[ep_cnt - 1] = of_drm_find_bridge(remote);if (!next_bridge[ep_cnt - 1]) {of_node_put(remote);of_node_put(ep);err_bridge = ERR_PTR(-EPROBE_DEFER);goto err;}/* specially select the next bridge with companion PXL2DPI */if (of_find_property(remote, "fsl,companion-pxl2dpi", NULL))bridge_sel = ep_cnt - 1;of_node_put(remote);- }
- pl->mst_addr = vld_port_id - 1;
- of_node_put(port);
- return next_bridge[bridge_sel];
+err:
- of_node_put(port);
- return err_bridge;
+}
+static int imx8qxp_pixel_link_bridge_probe(struct platform_device *pdev) +{
- struct imx8qxp_pixel_link *pl;
- struct device *dev = &pdev->dev;
- struct device_node *np = dev->of_node;
- int ret;
- pl = devm_kzalloc(dev, sizeof(*pl), GFP_KERNEL);
- if (!pl)
return -ENOMEM;- ret = imx_scu_get_handle(&pl->ipc_handle);
- if (ret) {
if (ret != -EPROBE_DEFER)DRM_DEV_ERROR(dev, "failed to get SCU ipc handle: %d\n",ret);return ret;- }
- pl->id = of_alias_get_id(np, "dc_pl");
What's this needed for? I doubt aliases is the right thing to use here.
Rob
On Mon, 2020-12-21 at 15:29 -0700, Rob Herring wrote:
On Thu, Dec 17, 2020 at 05:59:26PM +0800, Liu Ying wrote:
This patch adds a drm bridge driver for i.MX8qm/qxp display pixel link. The pixel link forms a standard asynchronous linkage between pixel sources(display controller or camera module) and pixel consumers(imaging or displays). It consists of two distinct functions, a pixel transfer function and a control interface.
Signed-off-by: Liu Ying victor.liu@nxp.com
drivers/gpu/drm/bridge/imx/Kconfig | 8 + drivers/gpu/drm/bridge/imx/Makefile | 1 + drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c | 411 ++++++++++++++++++++++++ 3 files changed, 420 insertions(+) create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig index f1c91b6..4d1f027 100644 --- a/drivers/gpu/drm/bridge/imx/Kconfig +++ b/drivers/gpu/drm/bridge/imx/Kconfig @@ -6,3 +6,11 @@ config DRM_IMX8QXP_PIXEL_COMBINER help Choose this to enable pixel combiner found in Freescale i.MX8qm/qxp processors.
+config DRM_IMX8QXP_PIXEL_LINK
- tristate "Freescale i.MX8QM/QXP display pixel link"
- depends on OF
- select DRM_KMS_HELPER
- help
Choose this to enable display pixel link found inFreescale i.MX8qm/qxp processors.diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile index 7d7c8d6..c15469f 100644 --- a/drivers/gpu/drm/bridge/imx/Makefile +++ b/drivers/gpu/drm/bridge/imx/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o +obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c new file mode 100644 index 00000000..1af7467 --- /dev/null +++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c @@ -0,0 +1,411 @@ +// SPDX-License-Identifier: GPL-2.0+
+/*
- Copyright 2020 NXP
- */
+#include <linux/firmware/imx/svc/misc.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_graph.h> +#include <linux/platform_device.h>
+#include <drm/drm_atomic_state_helper.h> +#include <drm/drm_bridge.h> +#include <drm/drm_print.h>
+#include <dt-bindings/firmware/imx/rsrc.h>
+#define DRIVER_NAME "imx8qxp-display-pixel-link" +#define PL_MAX_MST_ADDR 3
+struct imx8qxp_pixel_link {
- struct drm_bridge bridge;
- struct drm_bridge *next_bridge;
- struct device *dev;
- struct imx_sc_ipc *ipc_handle;
- int id;
- int stream_id;
- int dc_id;
- u32 sink_rsc;
- u32 mst_addr;
- u8 mst_addr_ctrl;
- u8 mst_en_ctrl;
- u8 mst_vld_ctrl;
- u8 sync_ctrl;
+};
+#define DEFINE_IMX8QXP_PIXEL_LINK_ENABLE_CTRL(name) \ +static void \ +imx8qxp_pixel_link_enable_##name(struct imx8qxp_pixel_link *pl) \ +{ \
- int ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc, \
pl->name##_ctrl, true); \- if (ret) \
DRM_DEV_ERROR(pl->dev, \"failed to enable DC%d stream%d pixel link " \#name ": %d\n", pl->dc_id, pl->stream_id, ret); \+}
+DEFINE_IMX8QXP_PIXEL_LINK_ENABLE_CTRL(mst_en) +DEFINE_IMX8QXP_PIXEL_LINK_ENABLE_CTRL(mst_vld) +DEFINE_IMX8QXP_PIXEL_LINK_ENABLE_CTRL(sync)
+#define DEFINE_IMX8QXP_PIXEL_LINK_DISABLE_CTRL(name) \ +static int \ +imx8qxp_pixel_link_disable_##name(struct imx8qxp_pixel_link *pl) \ +{ \
- int ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc, \
pl->name##_ctrl, false); \- if (ret) \
DRM_DEV_ERROR(pl->dev, \"failed to disable DC%d stream%d pixel link " \#name ": %d\n", pl->dc_id, pl->stream_id, ret); \\- return ret; \
+}
+DEFINE_IMX8QXP_PIXEL_LINK_DISABLE_CTRL(mst_en) +DEFINE_IMX8QXP_PIXEL_LINK_DISABLE_CTRL(mst_vld) +DEFINE_IMX8QXP_PIXEL_LINK_DISABLE_CTRL(sync)
+static void imx8qxp_pixel_link_set_mst_addr(struct imx8qxp_pixel_link *pl) +{
- int ret;
- ret = imx_sc_misc_set_control(pl->ipc_handle,
pl->sink_rsc, pl->mst_addr_ctrl,pl->mst_addr);- if (ret)
DRM_DEV_ERROR(pl->dev,"failed to set DC%d stream%d pixel link mst addr(%u): %d\n",pl->dc_id, pl->stream_id, pl->mst_addr, ret);+}
+static int imx8qxp_pixel_link_bridge_attach(struct drm_bridge *bridge,
enum drm_bridge_attach_flags flags)+{
- struct imx8qxp_pixel_link *pl = bridge->driver_private;
- if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
DRM_DEV_ERROR(pl->dev,"do not support creating a drm_connector\n");return -EINVAL;- }
- if (!bridge->encoder) {
DRM_DEV_ERROR(pl->dev, "missing encoder\n");return -ENODEV;- }
- return drm_bridge_attach(bridge->encoder,
pl->next_bridge, bridge,DRM_BRIDGE_ATTACH_NO_CONNECTOR);+}
+static void +imx8qxp_pixel_link_bridge_mode_set(struct drm_bridge *bridge,
const struct drm_display_mode *mode,const struct drm_display_mode *adjusted_mode)+{
- struct imx8qxp_pixel_link *pl = bridge->driver_private;
- imx8qxp_pixel_link_set_mst_addr(pl);
+}
+static void imx8qxp_pixel_link_bridge_atomic_enable(struct drm_bridge *bridge,
struct drm_bridge_state *old_bridge_state)+{
- struct imx8qxp_pixel_link *pl = bridge->driver_private;
- imx8qxp_pixel_link_enable_mst_en(pl);
- imx8qxp_pixel_link_enable_mst_vld(pl);
- imx8qxp_pixel_link_enable_sync(pl);
+}
+static void imx8qxp_pixel_link_bridge_atomic_disable(struct drm_bridge *bridge,
struct drm_bridge_state *old_bridge_state)+{
- struct imx8qxp_pixel_link *pl = bridge->driver_private;
- imx8qxp_pixel_link_disable_mst_en(pl);
- imx8qxp_pixel_link_disable_mst_vld(pl);
- imx8qxp_pixel_link_disable_sync(pl);
+}
+static const u32 imx8qxp_pixel_link_bus_output_fmts[] = {
- MEDIA_BUS_FMT_RGB888_1X36_CPADLO,
- MEDIA_BUS_FMT_RGB666_1X36_CPADLO,
+};
+static bool imx8qxp_pixel_link_bus_output_fmt_supported(u32 fmt) +{
- int i;
- for (i = 0; i < ARRAY_SIZE(imx8qxp_pixel_link_bus_output_fmts); i++) {
if (imx8qxp_pixel_link_bus_output_fmts[i] == fmt)return true;- }
- return false;
+}
+static u32 * +imx8qxp_pixel_link_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
struct drm_bridge_state *bridge_state,struct drm_crtc_state *crtc_state,struct drm_connector_state *conn_state,u32 output_fmt,unsigned int *num_input_fmts)+{
- u32 *input_fmts;
- if (!imx8qxp_pixel_link_bus_output_fmt_supported(output_fmt))
return NULL;- *num_input_fmts = 1;
- input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
- if (!input_fmts)
return NULL;- input_fmts[0] = output_fmt;
- return input_fmts;
+}
+static u32 * +imx8qxp_pixel_link_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
struct drm_bridge_state *bridge_state,struct drm_crtc_state *crtc_state,struct drm_connector_state *conn_state,unsigned int *num_output_fmts)+{
- *num_output_fmts = ARRAY_SIZE(imx8qxp_pixel_link_bus_output_fmts);
- return kmemdup(imx8qxp_pixel_link_bus_output_fmts,
sizeof(imx8qxp_pixel_link_bus_output_fmts), GFP_KERNEL);+}
+static const struct drm_bridge_funcs imx8qxp_pixel_link_bridge_funcs = {
- .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
- .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
- .atomic_reset = drm_atomic_helper_bridge_reset,
- .attach = imx8qxp_pixel_link_bridge_attach,
- .mode_set = imx8qxp_pixel_link_bridge_mode_set,
- .atomic_enable = imx8qxp_pixel_link_bridge_atomic_enable,
- .atomic_disable = imx8qxp_pixel_link_bridge_atomic_disable,
- .atomic_get_input_bus_fmts =
imx8qxp_pixel_link_bridge_atomic_get_input_bus_fmts,- .atomic_get_output_bus_fmts =
imx8qxp_pixel_link_bridge_atomic_get_output_bus_fmts,+};
+static struct drm_bridge * +imx8qxp_pixel_link_find_next_bridge(struct imx8qxp_pixel_link *pl) +{
- struct device_node *np = pl->dev->of_node;
- struct device_node *port, *ep, *remote;
- struct of_endpoint endpoint;
- struct drm_bridge *next_bridge[2], *err_bridge;
- u32 port_id, vld_port_id;
- int port_cnt = 0, ep_cnt = 0;
- int bridge_sel = 0; /* select the first next bridge by default */
- int ret;
- for (port_id = 1; port_id <= PL_MAX_MST_ADDR + 1; port_id++) {
port = of_graph_get_port_by_id(np, port_id);if (!port)continue;if (of_device_is_available(port)) {port_cnt++;vld_port_id = port_id;}of_node_put(port);- }
- /* check the number of available output ports */
- if (port_cnt == 0) {
DRM_DEV_ERROR(pl->dev, "no available output port\n");return ERR_PTR(-ENODEV);- } else if (port_cnt > 1) {
DRM_DEV_ERROR(pl->dev, "invalid available output ports: %d\n",port_cnt);return ERR_PTR(-ENOTSUPP);- }
- port = of_graph_get_port_by_id(np, vld_port_id);
- if (!port) {
DRM_DEV_ERROR(pl->dev, "failed to get output port\n");return ERR_PTR(-ENODEV);- }
- for_each_available_child_of_node(port, ep) {
for_each_endpoint_of_node
I've rewritten this entire function locally to get the endpoints 0&1 directly by using of_graph_get_remote_node(). It does look better and concise.
But the new function doesn't use for_each_endpoint_of_node(). It gets an available output port first(port0 is input, so still use something like the above snippet without port number check) and then get remotes for the two endpoints of the port.
Please let me know if it can still be improved or just review the next version.
/* 2 available endpoints at most */if (++ep_cnt > 2) {DRM_DEV_ERROR(pl->dev,"invalid available endpoints: %d\n",ep_cnt);Not really the kernel's job to validate the DT. Just get endpoints 0 and 1 if those are the 2 you want.
Will drop the DT validation.
err_bridge = ERR_PTR(-ENOTSUPP);of_node_put(ep);goto err;}ret = of_graph_parse_endpoint(ep, &endpoint);if (ret) {DRM_DEV_ERROR(pl->dev, "failed to parse endpoint: %d\n",ret);err_bridge = ERR_PTR(ret);of_node_put(ep);goto err;}remote = of_graph_get_remote_port_parent(ep);if (!remote || !of_device_is_available(remote)) {DRM_DEV_ERROR(pl->dev,"endpoint%u has no available remote\n",endpoint.id);of_node_put(remote);of_node_put(ep);err_bridge = ERR_PTR(-ENODEV);goto err;} else if (!of_device_is_available(remote->parent)) {DRM_DEV_ERROR(pl->dev,"endpoint%u remote parent is not available\n",endpoint.id);of_node_put(remote);of_node_put(ep);err_bridge = ERR_PTR(-ENODEV);goto err;}Rewrite all this in terms of of_graph_get_remote_node(). It takes care of of_device_is_available checking for you.
Will do.
next_bridge[ep_cnt - 1] = of_drm_find_bridge(remote);if (!next_bridge[ep_cnt - 1]) {of_node_put(remote);of_node_put(ep);err_bridge = ERR_PTR(-EPROBE_DEFER);goto err;}/* specially select the next bridge with companion PXL2DPI */if (of_find_property(remote, "fsl,companion-pxl2dpi", NULL))bridge_sel = ep_cnt - 1;of_node_put(remote);- }
- pl->mst_addr = vld_port_id - 1;
- of_node_put(port);
- return next_bridge[bridge_sel];
+err:
- of_node_put(port);
- return err_bridge;
+}
+static int imx8qxp_pixel_link_bridge_probe(struct platform_device *pdev) +{
- struct imx8qxp_pixel_link *pl;
- struct device *dev = &pdev->dev;
- struct device_node *np = dev->of_node;
- int ret;
- pl = devm_kzalloc(dev, sizeof(*pl), GFP_KERNEL);
- if (!pl)
return -ENOMEM;- ret = imx_scu_get_handle(&pl->ipc_handle);
- if (ret) {
if (ret != -EPROBE_DEFER)DRM_DEV_ERROR(dev, "failed to get SCU ipc handle: %d\n",ret);return ret;- }
- pl->id = of_alias_get_id(np, "dc_pl");
What's this needed for? I doubt aliases is the right thing to use here.
pl->dc_id and pl->stream_id are calculated out based on pl->id. And then, pl->mst_addr_ctrl/mst_en_ctrl/mst_vld_ctrl/sync_ctrl controls can be set based on pl->stream_id. pl->dc_id determines the SCU firmware resource to apply the controls.
Each display controller(DC) has two display streams and i.MX8qxp has one DC while i.MX8qm has two. Pixel combiner stands bewteen the display pixel link and display controller. It looks painful to go through the graph up to the display controller to get pl->dc_id and pl->stream_id.
Suggestions?
Thanks, Liu Ying
Rob
This patch adds bindings for i.MX8qxp pixel link to DPI(PXL2DPI).
Signed-off-by: Liu Ying victor.liu@nxp.com --- .../display/bridge/fsl,imx8qxp-pxl2dpi.yaml | 134 +++++++++++++++++++++ 1 file changed, 134 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml new file mode 100644 index 00000000..1649622 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pxl2dpi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8qxp Pixel Link to Display Pixel Interface + +maintainers: + - Liu Ying victor.liu@nxp.com + +description: | + The Freescale i.MX8qxp Pixel Link to Display Pixel Interface(PXL2DPI) + interfaces the pixel link 36-bit data output and the DSI controller’s + MIPI-DPI 24-bit data input, and inputs of LVDS Display Bridge(LDB) module + used in LVDS mode, to remap the pixel color codings between those modules. + This module is purely combinatorial. + +properties: + compatible: + const: fsl,imx8qxp-pxl2dpi + + power-domains: + maxItems: 1 + + fsl,syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + A phandle which points to Control and Status Registers(CSR) module. + + fsl,companion-pxl2dpi: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + A phandle which points to companion PXL2DPI which is used by downstream + LVDS Display Bridge(LDB) in split mode. + + ports: + type: object + description: | + A node containing PXL2DPI input & output port nodes with endpoint + definitions as documented in + Documentation/devicetree/bindings/media/video-interfaces.txt + Documentation/devicetree/bindings/graph.txt + + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + port@0: + type: object + description: The PXL2DPI input port node from pixel link. + + properties: + reg: + const: 0 + + required: + - reg + + port@1: + type: object + description: The PXL2DPI output port node to downstream bridge. + + properties: + reg: + const: 1 + + required: + - reg + + required: + - "#address-cells" + - "#size-cells" + - port@0 + - port@1 + + additionalProperties: false + +required: + - compatible + - power-domains + - fsl,syscon + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/firmware/imx/rsrc.h> + pxl2dpi { + compatible = "fsl,imx8qxp-pxl2dpi"; + power-domains = <&pd IMX_SC_R_MIPI_0>; + fsl,syscon = <&mipi_lvds_0_csr>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + mipi_lvds_0_pxl2dpi_dc_pixel_link0: endpoint@0 { + reg = <0>; + remote-endpoint = <&dc_pixel_link0_mipi_lvds_0_pxl2dpi>; + }; + + mipi_lvds_0_pxl2dpi_dc_pixel_link1: endpoint@1 { + reg = <1>; + remote-endpoint = <&dc_pixel_link1_mipi_lvds_0_pxl2dpi>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>; + }; + + mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>; + }; + }; + }; + };
This patch adds a drm bridge driver for i.MX8qxp pixel link to display pixel interface(PXL2DPI). The PXL2DPI interfaces the pixel link 36-bit data output and the DSI controller’s MIPI-DPI 24-bit data input, and inputs of LVDS Display Bridge(LDB) module used in LVDS mode, to remap the pixel color codings between those modules. The PXL2DPI is purely combinatorial.
Signed-off-by: Liu Ying victor.liu@nxp.com --- drivers/gpu/drm/bridge/imx/Kconfig | 8 + drivers/gpu/drm/bridge/imx/Makefile | 1 + drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c | 494 +++++++++++++++++++++++++++ 3 files changed, 503 insertions(+) create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c
diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig index 4d1f027..1ea1ce7 100644 --- a/drivers/gpu/drm/bridge/imx/Kconfig +++ b/drivers/gpu/drm/bridge/imx/Kconfig @@ -14,3 +14,11 @@ config DRM_IMX8QXP_PIXEL_LINK help Choose this to enable display pixel link found in Freescale i.MX8qm/qxp processors. + +config DRM_IMX8QXP_PIXEL_LINK_TO_DPI + tristate "Freescale i.MX8QXP pixel link to display pixel interface" + depends on OF + select DRM_KMS_HELPER + help + Choose this to enable pixel link to display pixel interface(PXL2DPI) + found in Freescale i.MX8qxp processor. diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile index c15469f..e74dd64 100644 --- a/drivers/gpu/drm/bridge/imx/Makefile +++ b/drivers/gpu/drm/bridge/imx/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o +obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI) += imx8qxp-pxl2dpi.o diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c b/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c new file mode 100644 index 00000000..95ed89e --- /dev/null +++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c @@ -0,0 +1,494 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include <linux/firmware/imx/svc/misc.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/of_graph.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h> + +#include <drm/drm_atomic_state_helper.h> +#include <drm/drm_bridge.h> +#include <drm/drm_of.h> +#include <drm/drm_print.h> + +#include <dt-bindings/firmware/imx/rsrc.h> + +#define PXL2DPI_CTRL 0x40 +#define CFG1_16BIT 0x0 +#define CFG2_16BIT 0x1 +#define CFG3_16BIT 0x2 +#define CFG1_18BIT 0x3 +#define CFG2_18BIT 0x4 +#define CFG_24BIT 0x5 + +#define DRIVER_NAME "imx8qxp-pxl2dpi" + +struct imx8qxp_pxl2dpi { + struct regmap *regmap; + struct drm_bridge bridge; + struct drm_bridge *next_bridge; + struct drm_bridge *companion; + struct device *dev; + struct imx_sc_ipc *ipc_handle; + u32 rsc; + u32 in_bus_format; + u32 out_bus_format; + u32 pl_sel; + int id; +}; + +#define bridge_to_p2d(b) container_of(b, struct imx8qxp_pxl2dpi, bridge) + +static int imx8qxp_pxl2dpi_bridge_attach(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags) +{ + struct imx8qxp_pxl2dpi *p2d = bridge->driver_private; + + if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) { + DRM_DEV_ERROR(p2d->dev, + "do not support creating a drm_connector\n"); + return -EINVAL; + } + + if (!bridge->encoder) { + DRM_DEV_ERROR(p2d->dev, "missing encoder\n"); + return -ENODEV; + } + + return drm_bridge_attach(bridge->encoder, + p2d->next_bridge, bridge, + DRM_BRIDGE_ATTACH_NO_CONNECTOR); +} + +static int +imx8qxp_pxl2dpi_bridge_atomic_check(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct imx8qxp_pxl2dpi *p2d = bridge->driver_private; + + p2d->in_bus_format = bridge_state->input_bus_cfg.format; + p2d->out_bus_format = bridge_state->output_bus_cfg.format; + + return 0; +} + +static void +imx8qxp_pxl2dpi_bridge_mode_set(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + const struct drm_display_mode *adjusted_mode) +{ + struct imx8qxp_pxl2dpi *p2d = bridge->driver_private; + struct imx8qxp_pxl2dpi *companion_p2d; + int ret; + + ret = pm_runtime_get_sync(p2d->dev); + if (ret < 0) + DRM_DEV_ERROR(p2d->dev, + "failed to get runtime PM sync: %d\n", ret); + + ret = imx_sc_misc_set_control(p2d->ipc_handle, p2d->rsc, + IMX_SC_C_PXL_LINK_SEL, p2d->pl_sel); + if (ret) + DRM_DEV_ERROR(p2d->dev, + "failed to set pixel link selection(%u): %d\n", + p2d->pl_sel, ret); + + switch (p2d->out_bus_format) { + case MEDIA_BUS_FMT_RGB888_1X24: + regmap_write(p2d->regmap, PXL2DPI_CTRL, CFG_24BIT); + break; + case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: + regmap_write(p2d->regmap, PXL2DPI_CTRL, CFG2_18BIT); + break; + default: + DRM_DEV_ERROR(p2d->dev, + "unsupported output bus format 0x%08x\n", + p2d->out_bus_format); + } + + if (p2d->companion) { + companion_p2d = bridge_to_p2d(p2d->companion); + + companion_p2d->in_bus_format = p2d->in_bus_format; + companion_p2d->out_bus_format = p2d->out_bus_format; + + p2d->companion->funcs->mode_set(p2d->companion, mode, + adjusted_mode); + } +} + +static void +imx8qxp_pxl2dpi_bridge_atomic_disable(struct drm_bridge *bridge, + struct drm_bridge_state *old_bridge_state) +{ + struct imx8qxp_pxl2dpi *p2d = bridge->driver_private; + int ret; + + ret = pm_runtime_put(p2d->dev); + if (ret < 0) + DRM_DEV_ERROR(p2d->dev, "failed to put runtime PM: %d\n", ret); + + if (p2d->companion) + p2d->companion->funcs->atomic_disable(p2d->companion, + old_bridge_state); +} + +static const u32 imx8qxp_pxl2dpi_bus_output_fmts[] = { + MEDIA_BUS_FMT_RGB888_1X24, + MEDIA_BUS_FMT_RGB666_1X24_CPADHI, +}; + +static bool imx8qxp_pxl2dpi_bus_output_fmt_supported(u32 fmt) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(imx8qxp_pxl2dpi_bus_output_fmts); i++) { + if (imx8qxp_pxl2dpi_bus_output_fmts[i] == fmt) + return true; + } + + return false; +} + +static u32 * +imx8qxp_pxl2dpi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + u32 output_fmt, + unsigned int *num_input_fmts) +{ + u32 *input_fmts; + + if (!imx8qxp_pxl2dpi_bus_output_fmt_supported(output_fmt)) + return NULL; + + *num_input_fmts = 1; + + input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL); + if (!input_fmts) + return NULL; + + switch (output_fmt) { + case MEDIA_BUS_FMT_RGB888_1X24: + input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X36_CPADLO; + break; + case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: + input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X36_CPADLO; + break; + default: + kfree(input_fmts); + input_fmts = NULL; + break; + } + + return input_fmts; +} + +static u32 * +imx8qxp_pxl2dpi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + unsigned int *num_output_fmts) +{ + *num_output_fmts = ARRAY_SIZE(imx8qxp_pxl2dpi_bus_output_fmts); + return kmemdup(imx8qxp_pxl2dpi_bus_output_fmts, + sizeof(imx8qxp_pxl2dpi_bus_output_fmts), GFP_KERNEL); +} + +static const struct drm_bridge_funcs imx8qxp_pxl2dpi_bridge_funcs = { + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, + .atomic_reset = drm_atomic_helper_bridge_reset, + .attach = imx8qxp_pxl2dpi_bridge_attach, + .atomic_check = imx8qxp_pxl2dpi_bridge_atomic_check, + .mode_set = imx8qxp_pxl2dpi_bridge_mode_set, + .atomic_disable = imx8qxp_pxl2dpi_bridge_atomic_disable, + .atomic_get_input_bus_fmts = + imx8qxp_pxl2dpi_bridge_atomic_get_input_bus_fmts, + .atomic_get_output_bus_fmts = + imx8qxp_pxl2dpi_bridge_atomic_get_output_bus_fmts, +}; + +static struct device_node * +imx8qxp_pxl2dpi_get_available_ep_from_port(struct imx8qxp_pxl2dpi *p2d, + u32 port_id) +{ + struct device_node *port, *ep; + int ep_cnt; + + port = of_graph_get_port_by_id(p2d->dev->of_node, port_id); + if (!port) { + DRM_DEV_ERROR(p2d->dev, "failed to get port@%u\n", port_id); + return ERR_PTR(-ENODEV); + } + + if (!of_device_is_available(port)) { + DRM_DEV_ERROR(p2d->dev, "port@%u is disabled\n", port_id); + ep = ERR_PTR(-ENODEV); + goto out; + } + + ep_cnt = of_get_available_child_count(port); + if (ep_cnt == 0) { + DRM_DEV_ERROR(p2d->dev, "no available endpoints of port@%u\n", + port_id); + ep = ERR_PTR(-ENODEV); + goto out; + } else if (ep_cnt > 1) { + DRM_DEV_ERROR(p2d->dev, + "invalid available endpoints of port@%u\n", port_id); + ep = ERR_PTR(-ENOTSUPP); + goto out; + } + + ep = of_get_next_available_child(port, NULL); + if (!ep) { + DRM_DEV_ERROR(p2d->dev, + "failed to get available endpoint of port@%u\n", + port_id); + ep = ERR_PTR(-ENODEV); + goto out; + } +out: + of_node_put(port); + return ep; +} + +static struct drm_bridge * +imx8qxp_pxl2dpi_find_next_bridge(struct imx8qxp_pxl2dpi *p2d) +{ + struct device_node *ep, *remote; + struct drm_bridge *next_bridge; + int ret; + + ep = imx8qxp_pxl2dpi_get_available_ep_from_port(p2d, 1); + if (IS_ERR(ep)) { + ret = PTR_ERR(ep); + return ERR_PTR(ret); + } + + remote = of_graph_get_remote_port_parent(ep); + if (!remote || !of_device_is_available(remote)) { + DRM_DEV_ERROR(p2d->dev, "no available remote\n"); + next_bridge = ERR_PTR(-ENODEV); + goto out; + } else if (!of_device_is_available(remote->parent)) { + DRM_DEV_ERROR(p2d->dev, "remote parent is not available\n"); + next_bridge = ERR_PTR(-ENODEV); + goto out; + } + + next_bridge = of_drm_find_bridge(remote); + if (!next_bridge) { + next_bridge = ERR_PTR(-EPROBE_DEFER); + goto out; + } +out: + of_node_put(remote); + of_node_put(ep); + + return next_bridge; +} + +static int imx8qxp_pxl2dpi_set_pixel_link_sel(struct imx8qxp_pxl2dpi *p2d) +{ + struct device_node *ep; + struct of_endpoint endpoint; + int ret; + + ep = imx8qxp_pxl2dpi_get_available_ep_from_port(p2d, 0); + if (IS_ERR(ep)) + return PTR_ERR(ep); + + ret = of_graph_parse_endpoint(ep, &endpoint); + if (ret) { + DRM_DEV_ERROR(p2d->dev, + "failed to parse endpoint of port@0: %d\n", ret); + goto out; + } + + p2d->pl_sel = endpoint.id; +out: + of_node_put(ep); + + return ret; +} + +static int imx8qxp_pxl2dpi_parse_dt_companion(struct imx8qxp_pxl2dpi *p2d) +{ + struct imx8qxp_pxl2dpi *companion_p2d; + struct device *dev = p2d->dev; + struct device_node *companion; + struct device_node *port1, *port2; + const struct of_device_id *match; + int dual_link; + int ret = 0; + + /* Locate the companion PXL2DPI for dual-link operation, if any. */ + companion = of_parse_phandle(dev->of_node, "fsl,companion-pxl2dpi", 0); + if (!companion) + return 0; + + if (!of_device_is_available(companion)) { + DRM_DEV_ERROR(dev, "companion PXL2DPI is not available\n"); + ret = -ENODEV; + goto out; + } + + /* + * Sanity check: the companion bridge must have the same compatible + * string. + */ + match = of_match_device(dev->driver->of_match_table, dev); + if (!of_device_is_compatible(companion, match->compatible)) { + DRM_DEV_ERROR(dev, "companion PXL2DPI is incompatible\n"); + ret = -ENXIO; + goto out; + } + + p2d->companion = of_drm_find_bridge(companion); + if (!p2d->companion) { + ret = -EPROBE_DEFER; + DRM_DEV_DEBUG_DRIVER(p2d->dev, + "failed to find companion bridge: %d\n", ret); + goto out; + } + + companion_p2d = bridge_to_p2d(p2d->companion); + + /* + * We need to work out if the sink is expecting us to function in + * dual-link mode. We do this by looking at the DT port nodes that + * the next bridges are connected to. If they are marked as expecting + * even pixels and odd pixels than we need to use the companion PXL2DPI. + */ + port1 = of_graph_get_port_by_id(p2d->next_bridge->of_node, 1); + port2 = of_graph_get_port_by_id(companion_p2d->next_bridge->of_node, 1); + dual_link = drm_of_lvds_get_dual_link_pixel_order(port1, port2); + of_node_put(port1); + of_node_put(port2); + + if (dual_link < 0) { + ret = dual_link; + DRM_DEV_ERROR(dev, "failed to get dual link pixel order: %d\n", + ret); + goto out; + } + + DRM_DEV_DEBUG_DRIVER(dev, + "dual-link configuration detected (companion bridge %pOF)\n", + companion); +out: + of_node_put(companion); + return ret; +} + +static int imx8qxp_pxl2dpi_bridge_probe(struct platform_device *pdev) +{ + struct imx8qxp_pxl2dpi *p2d; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + int ret; + + p2d = devm_kzalloc(dev, sizeof(*p2d), GFP_KERNEL); + if (!p2d) + return -ENOMEM; + + p2d->regmap = syscon_regmap_lookup_by_phandle(np, "fsl,syscon"); + if (IS_ERR(p2d->regmap)) { + ret = PTR_ERR(p2d->regmap); + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(dev, "failed to get regmap: %d\n", ret); + return ret; + } + + p2d->id = of_alias_get_id(np, "pxl2dpi"); + if (p2d->id < 0) { + DRM_DEV_ERROR(dev, "failed to get PXL2DPI node alias id: %d\n", + p2d->id); + return p2d->id; + } + + ret = imx_scu_get_handle(&p2d->ipc_handle); + if (ret) { + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(dev, "failed to get SCU ipc handle: %d\n", + ret); + return ret; + } + + p2d->dev = dev; + p2d->rsc = p2d->id ? IMX_SC_R_MIPI_1 : IMX_SC_R_MIPI_0; + + p2d->next_bridge = imx8qxp_pxl2dpi_find_next_bridge(p2d); + if (IS_ERR(p2d->next_bridge)) { + ret = PTR_ERR(p2d->next_bridge); + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(dev, "failed to find next bridge: %d\n", + ret); + return ret; + } + + ret = imx8qxp_pxl2dpi_set_pixel_link_sel(p2d); + if (ret) + return ret; + + ret = imx8qxp_pxl2dpi_parse_dt_companion(p2d); + if (ret) + return ret; + + platform_set_drvdata(pdev, p2d); + pm_runtime_enable(dev); + + p2d->bridge.driver_private = p2d; + p2d->bridge.funcs = &imx8qxp_pxl2dpi_bridge_funcs; + p2d->bridge.of_node = np; + + drm_bridge_add(&p2d->bridge); + + return ret; +} + +static int imx8qxp_pxl2dpi_bridge_remove(struct platform_device *pdev) +{ + struct imx8qxp_pxl2dpi *p2d = platform_get_drvdata(pdev); + + drm_bridge_remove(&p2d->bridge); + + pm_runtime_disable(&pdev->dev); + + return 0; +} + +static const struct of_device_id imx8qxp_pxl2dpi_dt_ids[] = { + { .compatible = "fsl,imx8qxp-pxl2dpi", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx8qxp_pxl2dpi_dt_ids); + +static struct platform_driver imx8qxp_pxl2dpi_bridge_driver = { + .probe = imx8qxp_pxl2dpi_bridge_probe, + .remove = imx8qxp_pxl2dpi_bridge_remove, + .driver = { + .of_match_table = imx8qxp_pxl2dpi_dt_ids, + .name = DRIVER_NAME, + }, +}; +module_platform_driver(imx8qxp_pxl2dpi_bridge_driver); + +MODULE_DESCRIPTION("i.MX8QXP pixel link to DPI bridge driver"); +MODULE_AUTHOR("Liu Ying victor.liu@nxp.com"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRIVER_NAME);
This patch adds a helper to support LDB drm bridge drivers for i.MX SoCs. Helper functions exported from this driver should implement common logics for all LDB modules embedded in i.MX SoCs.
Signed-off-by: Liu Ying victor.liu@nxp.com --- drivers/gpu/drm/bridge/imx/Kconfig | 8 + drivers/gpu/drm/bridge/imx/Makefile | 1 + drivers/gpu/drm/bridge/imx/imx-ldb-helper.c | 248 ++++++++++++++++++++++++++++ include/drm/bridge/imx_ldb_helper.h | 98 +++++++++++ 4 files changed, 355 insertions(+) create mode 100644 drivers/gpu/drm/bridge/imx/imx-ldb-helper.c create mode 100644 include/drm/bridge/imx_ldb_helper.h
diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig index 1ea1ce7..23e24fd 100644 --- a/drivers/gpu/drm/bridge/imx/Kconfig +++ b/drivers/gpu/drm/bridge/imx/Kconfig @@ -1,3 +1,11 @@ +config DRM_IMX_LVDS_BRIDGE_HELPER + tristate "Freescale i.MX LVDS display bridge helper" + depends on OF + select DRM_PANEL_BRIDGE + help + Helper to support Freescale i.MX LVDS Display Bridge(LDB). + This bridge is embedded in a SoC. + config DRM_IMX8QXP_PIXEL_COMBINER tristate "Freescale i.MX8QM/QXP pixel combiner" depends on OF diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile index e74dd64..902b703 100644 --- a/drivers/gpu/drm/bridge/imx/Makefile +++ b/drivers/gpu/drm/bridge/imx/Makefile @@ -1,3 +1,4 @@ +obj-$(CONFIG_DRM_IMX_LVDS_BRIDGE_HELPER) += imx-ldb-helper.o obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI) += imx8qxp-pxl2dpi.o diff --git a/drivers/gpu/drm/bridge/imx/imx-ldb-helper.c b/drivers/gpu/drm/bridge/imx/imx-ldb-helper.c new file mode 100644 index 00000000..ccf06a7 --- /dev/null +++ b/drivers/gpu/drm/bridge/imx/imx-ldb-helper.c @@ -0,0 +1,248 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2012 Sascha Hauer, Pengutronix + * Copyright 2019,2020 NXP + */ + +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/regmap.h> + +#include <drm/bridge/imx_ldb_helper.h> +#include <drm/drm_of.h> +#include <drm/drm_panel.h> +#include <drm/drm_print.h> + +bool ldb_channel_is_single_link(struct ldb_channel *ldb_ch) +{ + return ldb_ch->link_type == LDB_CH_SINGLE_LINK; +} +EXPORT_SYMBOL_GPL(ldb_channel_is_single_link); + +bool ldb_channel_is_split_link(struct ldb_channel *ldb_ch) +{ + return ldb_ch->link_type == LDB_CH_DUAL_LINK_EVEN_ODD_PIXELS || + ldb_ch->link_type == LDB_CH_DUAL_LINK_ODD_EVEN_PIXELS; +} +EXPORT_SYMBOL_GPL(ldb_channel_is_split_link); + +int ldb_bridge_atomic_check_helper(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + + ldb_ch->in_bus_format = bridge_state->input_bus_cfg.format; + ldb_ch->out_bus_format = bridge_state->output_bus_cfg.format; + + return 0; +} +EXPORT_SYMBOL_GPL(ldb_bridge_atomic_check_helper); + +void ldb_bridge_mode_set_helper(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + const struct drm_display_mode *adjusted_mode) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + struct ldb *ldb = ldb_ch->ldb; + bool is_split = ldb_channel_is_split_link(ldb_ch); + + if (is_split) + ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN; + + switch (ldb_ch->out_bus_format) { + case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: + break; + case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: + if (ldb_ch->chno == 0 || is_split) + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24; + if (ldb_ch->chno == 1 || is_split) + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24; + break; + case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: + if (ldb_ch->chno == 0 || is_split) + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 | + LDB_BIT_MAP_CH0_JEIDA; + if (ldb_ch->chno == 1 || is_split) + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 | + LDB_BIT_MAP_CH1_JEIDA; + break; + } +} +EXPORT_SYMBOL_GPL(ldb_bridge_mode_set_helper); + +void ldb_bridge_enable_helper(struct drm_bridge *bridge) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + struct ldb *ldb = ldb_ch->ldb; + + /* + * Platform specific bridge drivers should set ldb_ctrl properly + * for the enablement, so just write the ctrl_reg here. + */ + regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl); +} +EXPORT_SYMBOL_GPL(ldb_bridge_enable_helper); + +void ldb_bridge_disable_helper(struct drm_bridge *bridge) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + struct ldb *ldb = ldb_ch->ldb; + bool is_split = ldb_channel_is_split_link(ldb_ch); + + if (ldb_ch->chno == 0 || is_split) + ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK; + if (ldb_ch->chno == 1 || is_split) + ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK; + + regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl); +} +EXPORT_SYMBOL_GPL(ldb_bridge_disable_helper); + +int ldb_bridge_attach_helper(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + struct ldb *ldb = ldb_ch->ldb; + + if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) { + DRM_DEV_ERROR(ldb->dev, + "do not support creating a drm_connector\n"); + return -EINVAL; + } + + if (!bridge->encoder) { + DRM_DEV_ERROR(ldb->dev, "missing encoder\n"); + return -ENODEV; + } + + return drm_bridge_attach(bridge->encoder, + ldb_ch->next_bridge, bridge, + DRM_BRIDGE_ATTACH_NO_CONNECTOR); +} +EXPORT_SYMBOL_GPL(ldb_bridge_attach_helper); + +int ldb_init_helper(struct ldb *ldb) +{ + struct device *dev = ldb->dev; + struct device_node *np = dev->of_node; + struct device_node *child; + int ret; + u32 i; + + ldb->regmap = syscon_regmap_lookup_by_phandle(np, "fsl,syscon"); + if (IS_ERR(ldb->regmap)) { + ret = PTR_ERR(ldb->regmap); + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(dev, "failed to get regmap: %d\n", ret); + return ret; + } + + for_each_available_child_of_node(np, child) { + struct ldb_channel *ldb_ch; + + ret = of_property_read_u32(child, "reg", &i); + if (ret || i > MAX_LDB_CHAN_NUM - 1) { + ret = -EINVAL; + DRM_DEV_ERROR(dev, + "invalid channel node address: %u\n", i); + of_node_put(child); + return ret; + } + + ldb_ch = ldb->channel[i]; + ldb_ch->ldb = ldb; + ldb_ch->chno = i; + ldb_ch->is_available = true; + ldb_ch->np = child; + + ldb->available_ch_cnt++; + } + + return 0; +} +EXPORT_SYMBOL_GPL(ldb_init_helper); + +int ldb_find_next_bridge_helper(struct ldb *ldb) +{ + struct device *dev = ldb->dev; + struct ldb_channel *ldb_ch; + int ret, i; + + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) { + ldb_ch = ldb->channel[i]; + + if (!ldb_ch->is_available) + continue; + + ret = drm_of_find_panel_or_bridge(ldb_ch->np, 1, 0, + &ldb_ch->panel, + &ldb_ch->next_bridge); + if (ret) { + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(dev, + "failed to find panel or bridge: %d\n", + ret); + return ret; + } + + if (ldb_ch->panel) { + ldb_ch->next_bridge = devm_drm_panel_bridge_add(dev, + ldb_ch->panel); + if (IS_ERR(ldb_ch->next_bridge)) { + ret = PTR_ERR(ldb_ch->next_bridge); + DRM_DEV_ERROR(dev, + "failed to add panel bridge: %d\n", + ret); + return ret; + } + } + } + + return 0; +} +EXPORT_SYMBOL_GPL(ldb_find_next_bridge_helper); + +void ldb_add_bridge_helper(struct ldb *ldb, + const struct drm_bridge_funcs *bridge_funcs) +{ + struct ldb_channel *ldb_ch; + int i; + + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) { + ldb_ch = ldb->channel[i]; + + if (!ldb_ch->is_available) + continue; + + ldb_ch->bridge.driver_private = ldb_ch; + ldb_ch->bridge.funcs = bridge_funcs; + ldb_ch->bridge.of_node = ldb_ch->np; + + drm_bridge_add(&ldb_ch->bridge); + } +} +EXPORT_SYMBOL_GPL(ldb_add_bridge_helper); + +void ldb_remove_bridge_helper(struct ldb *ldb) +{ + struct ldb_channel *ldb_ch; + int i; + + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) { + ldb_ch = ldb->channel[i]; + + if (!ldb_ch->is_available) + continue; + + drm_bridge_remove(&ldb_ch->bridge); + } +} +EXPORT_SYMBOL_GPL(ldb_remove_bridge_helper); + +MODULE_DESCRIPTION("Freescale i.MX LVDS Display Bridge driver helper"); +MODULE_AUTHOR("Liu Ying victor.liu@nxp.com"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:imx-ldb-helper"); diff --git a/include/drm/bridge/imx_ldb_helper.h b/include/drm/bridge/imx_ldb_helper.h new file mode 100644 index 00000000..2a7ba97 --- /dev/null +++ b/include/drm/bridge/imx_ldb_helper.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +/* + * Copyright 2019,2020 NXP + */ + +#ifndef __FSL_IMX_LDB__ +#define __FSL_IMX_LDB__ + +#include <linux/device.h> +#include <linux/kernel.h> +#include <linux/of.h> +#include <linux/regmap.h> + +#include <drm/drm_atomic.h> +#include <drm/drm_bridge.h> +#include <drm/drm_device.h> +#include <drm/drm_encoder.h> +#include <drm/drm_modeset_helper_vtables.h> +#include <drm/drm_panel.h> + +#define LDB_CH0_MODE_EN_TO_DI0 (1 << 0) +#define LDB_CH0_MODE_EN_TO_DI1 (3 << 0) +#define LDB_CH0_MODE_EN_MASK (3 << 0) +#define LDB_CH1_MODE_EN_TO_DI0 (1 << 2) +#define LDB_CH1_MODE_EN_TO_DI1 (3 << 2) +#define LDB_CH1_MODE_EN_MASK (3 << 2) +#define LDB_SPLIT_MODE_EN (1 << 4) +#define LDB_DATA_WIDTH_CH0_24 (1 << 5) +#define LDB_BIT_MAP_CH0_JEIDA (1 << 6) +#define LDB_DATA_WIDTH_CH1_24 (1 << 7) +#define LDB_BIT_MAP_CH1_JEIDA (1 << 8) +#define LDB_DI0_VS_POL_ACT_LOW (1 << 9) +#define LDB_DI1_VS_POL_ACT_LOW (1 << 10) + +#define MAX_LDB_CHAN_NUM 2 + +enum ldb_channel_link_type { + LDB_CH_SINGLE_LINK, + LDB_CH_DUAL_LINK_EVEN_ODD_PIXELS, + LDB_CH_DUAL_LINK_ODD_EVEN_PIXELS, +}; + +struct ldb; + +struct ldb_channel { + struct ldb *ldb; + struct drm_bridge bridge; + struct drm_panel *panel; + struct drm_bridge *next_bridge; + struct device_node *np; + u32 chno; + bool is_available; + u32 in_bus_format; + u32 out_bus_format; + enum ldb_channel_link_type link_type; +}; + +struct ldb { + struct regmap *regmap; + struct device *dev; + struct ldb_channel *channel[MAX_LDB_CHAN_NUM]; + unsigned int ctrl_reg; + u32 ldb_ctrl; + unsigned int available_ch_cnt; +}; + +#define bridge_to_ldb_ch(b) container_of(b, struct ldb_channel, bridge) + +bool ldb_channel_is_single_link(struct ldb_channel *ldb_ch); +bool ldb_channel_is_split_link(struct ldb_channel *ldb_ch); + +int ldb_bridge_atomic_check_helper(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state); + +void ldb_bridge_mode_set_helper(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + const struct drm_display_mode *adjusted_mode); + +void ldb_bridge_enable_helper(struct drm_bridge *bridge); + +void ldb_bridge_disable_helper(struct drm_bridge *bridge); + +int ldb_bridge_attach_helper(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags); + +int ldb_init_helper(struct ldb *ldb); + +int ldb_find_next_bridge_helper(struct ldb *ldb); + +void ldb_add_bridge_helper(struct ldb *ldb, + const struct drm_bridge_funcs *bridge_funcs); + +void ldb_remove_bridge_helper(struct ldb *ldb); + +#endif /* __FSL_IMX_LDB__ */
This patch adds bindings for i.MX8qm/qxp LVDS display bridge(LDB).
Signed-off-by: Liu Ying victor.liu@nxp.com --- .../bindings/display/bridge/fsl,imx8qxp-ldb.yaml | 185 +++++++++++++++++++++ 1 file changed, 185 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml new file mode 100644 index 00000000..4e5ff6f --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml @@ -0,0 +1,185 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8qm/qxp LVDS Display Bridge + +maintainers: + - Liu Ying victor.liu@nxp.com + +description: | + The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels. + + For i.MX8qxp LDB, each channel supports up to 24bpp parallel input color + format and can map the input to VESA or JEIDA standards. The two channels + cannot be used simultaneously, that is to say, the user should pick one of + them to use. Two LDB channels from two LDB instances can work together in + LDB split mode to support a dual link LVDS display. The channel indexes + have to be different. Channel0 outputs odd pixels and channel1 outputs + even pixels. + + For i.MX8qm LDB, each channel additionally supports up to 30bpp parallel + input color format. The two channels can be used simultaneously, either + in dual mode or split mode. In dual mode, the two channels output identical + data. In split mode, channel0 outputs odd pixels and channel1 outputs even + pixels. + +properties: + compatible: + enum: + - fsl,imx8qm-ldb + - fsl,imx8qxp-ldb + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + clocks: + items: + - description: pixel clock + - description: bypass clock + + clock-names: + items: + - const: pixel + - const: bypass + + power-domains: + maxItems: 1 + + fsl,syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + A phandle which points to Control and Status Registers(CSR) module. + + fsl,companion-ldb: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + A phandle which points to companion LDB which is used in LDB split mode. + +patternProperties: + "^channel@[0-1]$": + type: object + description: Represents a channel of LDB. + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reg: + description: The channel index. + enum: [ 0, 1 ] + + phys: + description: A phandle to the phy module representing the LVDS PHY. + maxItems: 1 + + phy-names: + const: lvds_phy + + port@0: + type: object + description: Input port of the channel. + + properties: + reg: + const: 0 + + required: + - reg + + port@1: + type: object + description: Output port of the channel. + + properties: + reg: + const: 1 + + required: + - reg + + required: + - "#address-cells" + - "#size-cells" + - reg + - phys + - phy-names + + additionalProperties: false + +required: + - compatible + - "#address-cells" + - "#size-cells" + - clocks + - clock-names + - power-domains + - fsl,syscon + - channel@0 + - channel@1 + +allOf: + - if: + properties: + compatible: + contains: + const: fsl,imx8qm-ldb + then: + properties: + fsl,companion-ldb: false + +additionalProperties: false + +examples: + - | + #include <dt-bindings/firmware/imx/rsrc.h> + ldb { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-ldb"; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; + clock-names = "pixel", "bypass"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + fsl,syscon = <&mipi_lvds_0_csr>; + + channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&mipi_lvds_0_phy>; + phy-names = "lvds_phy"; + + port@0 { + reg = <0>; + + mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint { + remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>; + }; + }; + }; + + channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&mipi_lvds_0_phy>; + phy-names = "lvds_phy"; + + port@0 { + reg = <0>; + + mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint { + remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>; + }; + }; + }; + };
On Thu, Dec 17, 2020 at 05:59:30PM +0800, Liu Ying wrote:
This patch adds bindings for i.MX8qm/qxp LVDS display bridge(LDB).
Signed-off-by: Liu Ying victor.liu@nxp.com
.../bindings/display/bridge/fsl,imx8qxp-ldb.yaml | 185 +++++++++++++++++++++ 1 file changed, 185 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml new file mode 100644 index 00000000..4e5ff6f --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml @@ -0,0 +1,185 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: Freescale i.MX8qm/qxp LVDS Display Bridge
+maintainers:
- Liu Ying victor.liu@nxp.com
+description: |
- The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.
- For i.MX8qxp LDB, each channel supports up to 24bpp parallel input color
- format and can map the input to VESA or JEIDA standards. The two channels
- cannot be used simultaneously, that is to say, the user should pick one of
- them to use. Two LDB channels from two LDB instances can work together in
- LDB split mode to support a dual link LVDS display. The channel indexes
- have to be different. Channel0 outputs odd pixels and channel1 outputs
- even pixels.
- For i.MX8qm LDB, each channel additionally supports up to 30bpp parallel
- input color format. The two channels can be used simultaneously, either
- in dual mode or split mode. In dual mode, the two channels output identical
- data. In split mode, channel0 outputs odd pixels and channel1 outputs even
- pixels.
This LDB doesn't share anything with prior ones?
+properties:
- compatible:
- enum:
- fsl,imx8qm-ldb- fsl,imx8qxp-ldb- "#address-cells":
- const: 1
- "#size-cells":
- const: 0
- clocks:
- items:
- description: pixel clock- description: bypass clock- clock-names:
- items:
- const: pixel- const: bypass- power-domains:
- maxItems: 1
- fsl,syscon:
- $ref: /schemas/types.yaml#/definitions/phandle
- description: |
A phandle which points to Control and Status Registers(CSR) module.- fsl,companion-ldb:
- $ref: /schemas/types.yaml#/definitions/phandle
- description: |
A phandle which points to companion LDB which is used in LDB split mode.+patternProperties:
- "^channel@[0-1]$":
- type: object
- description: Represents a channel of LDB.
- properties:
"#address-cells":const: 1"#size-cells":const: 0reg:description: The channel index.enum: [ 0, 1 ]phys:description: A phandle to the phy module representing the LVDS PHY.maxItems: 1phy-names:const: lvds_phyport@0:type: objectdescription: Input port of the channel.properties:reg:const: 0required:- regport@1:type: objectdescription: Output port of the channel.properties:reg:const: 1required:- reg- required:
- "#address-cells"- "#size-cells"- reg- phys- phy-names- additionalProperties: false
+required:
- compatible
- "#address-cells"
- "#size-cells"
- clocks
- clock-names
- power-domains
- fsl,syscon
- channel@0
- channel@1
+allOf:
- if:
properties:compatible:contains:const: fsl,imx8qm-ldb- then:
properties:fsl,companion-ldb: false+additionalProperties: false
+examples:
- |
- #include <dt-bindings/firmware/imx/rsrc.h>
- ldb {
#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8qxp-ldb";clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,<&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;clock-names = "pixel", "bypass";power-domains = <&pd IMX_SC_R_LVDS_0>;fsl,syscon = <&mipi_lvds_0_csr>;channel@0 {#address-cells = <1>;#size-cells = <0>;reg = <0>;phys = <&mipi_lvds_0_phy>;phy-names = "lvds_phy";port@0 {reg = <0>;mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;};};};channel@1 {#address-cells = <1>;#size-cells = <0>;reg = <1>;phys = <&mipi_lvds_0_phy>;phy-names = "lvds_phy";port@0 {reg = <0>;mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;};};};- };
-- 2.7.4
On Mon, 2020-12-21 at 15:33 -0700, Rob Herring wrote:
On Thu, Dec 17, 2020 at 05:59:30PM +0800, Liu Ying wrote:
This patch adds bindings for i.MX8qm/qxp LVDS display bridge(LDB).
Signed-off-by: Liu Ying victor.liu@nxp.com
.../bindings/display/bridge/fsl,imx8qxp-ldb.yaml | 185 +++++++++++++++++++++ 1 file changed, 185 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml new file mode 100644 index 00000000..4e5ff6f --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml @@ -0,0 +1,185 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.... +$schema: https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree....
+title: Freescale i.MX8qm/qxp LVDS Display Bridge
+maintainers:
- Liu Ying victor.liu@nxp.com
+description: |
- The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.
- For i.MX8qxp LDB, each channel supports up to 24bpp parallel input color
- format and can map the input to VESA or JEIDA standards. The two channels
- cannot be used simultaneously, that is to say, the user should pick one of
- them to use. Two LDB channels from two LDB instances can work together in
- LDB split mode to support a dual link LVDS display. The channel indexes
- have to be different. Channel0 outputs odd pixels and channel1 outputs
- even pixels.
- For i.MX8qm LDB, each channel additionally supports up to 30bpp parallel
- input color format. The two channels can be used simultaneously, either
- in dual mode or split mode. In dual mode, the two channels output identical
- data. In split mode, channel0 outputs odd pixels and channel1 outputs even
- pixels.
This LDB doesn't share anything with prior ones?
i.MX53/6qdl/6sx/8mp/8qm/8qxp SoCs embed LDB. Bridge drivers for them should be able to use the 'imx-ldb-helper' added by patch 10/14, so they do share those logics.
i.MX53/6qdl LDB encoder driver is at drivers/gpu/drm/imx/imx-ldb.c. It's essentially a drm encoder driver. Efforts are needed to convert it to be a pure drm bridge driver, just like the patch 12/14 and 13/14 for i.MX8qm/qxp LDB which live in drivers/gpu/drm/bridge. 'imx-drm' is also needed to create drm encoders and connectors. So, a fair amount of work. With that done, the binding Documentation/devicetree/bindings/display/imx/ldb.txt for i.MX53/6dql LDBs can be dropped and we can probably cover them by this binding, though I see quite a few new/inconsitent propeties.
i.MX6sx and i.MX8mp LDBs have no drivers yet. They can be potentially covered by this binding.
Liu Ying
+properties:
- compatible:
- enum:
- fsl,imx8qm-ldb- fsl,imx8qxp-ldb- "#address-cells":
- const: 1
- "#size-cells":
- const: 0
- clocks:
- items:
- description: pixel clock- description: bypass clock- clock-names:
- items:
- const: pixel- const: bypass- power-domains:
- maxItems: 1
- fsl,syscon:
- $ref: /schemas/types.yaml#/definitions/phandle
- description: |
A phandle which points to Control and Status Registers(CSR) module.- fsl,companion-ldb:
- $ref: /schemas/types.yaml#/definitions/phandle
- description: |
A phandle which points to companion LDB which is used in LDB split mode.+patternProperties:
- "^channel@[0-1]$":
- type: object
- description: Represents a channel of LDB.
- properties:
"#address-cells":const: 1"#size-cells":const: 0reg:description: The channel index.enum: [ 0, 1 ]phys:description: A phandle to the phy module representing the LVDS PHY.maxItems: 1phy-names:const: lvds_phyport@0:type: objectdescription: Input port of the channel.properties:reg:const: 0required:- regport@1:type: objectdescription: Output port of the channel.properties:reg:const: 1required:- reg- required:
- "#address-cells"- "#size-cells"- reg- phys- phy-names- additionalProperties: false
+required:
- compatible
- "#address-cells"
- "#size-cells"
- clocks
- clock-names
- power-domains
- fsl,syscon
- channel@0
- channel@1
+allOf:
- if:
properties:compatible:contains:const: fsl,imx8qm-ldb- then:
properties:fsl,companion-ldb: false+additionalProperties: false
+examples:
- |
- #include <dt-bindings/firmware/imx/rsrc.h>
- ldb {
#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8qxp-ldb";clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,<&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;clock-names = "pixel", "bypass";power-domains = <&pd IMX_SC_R_LVDS_0>;fsl,syscon = <&mipi_lvds_0_csr>;channel@0 {#address-cells = <1>;#size-cells = <0>;reg = <0>;phys = <&mipi_lvds_0_phy>;phy-names = "lvds_phy";port@0 {reg = <0>;mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;};};};channel@1 {#address-cells = <1>;#size-cells = <0>;reg = <1>;phys = <&mipi_lvds_0_phy>;phy-names = "lvds_phy";port@0 {reg = <0>;mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;};};};- };
-- 2.7.4
Hi Liu,
Thank you for the patch.
On Thu, Dec 17, 2020 at 05:59:30PM +0800, Liu Ying wrote:
This patch adds bindings for i.MX8qm/qxp LVDS display bridge(LDB).
Signed-off-by: Liu Ying victor.liu@nxp.com
.../bindings/display/bridge/fsl,imx8qxp-ldb.yaml | 185 +++++++++++++++++++++ 1 file changed, 185 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml new file mode 100644 index 00000000..4e5ff6f --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml @@ -0,0 +1,185 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: Freescale i.MX8qm/qxp LVDS Display Bridge
+maintainers:
- Liu Ying victor.liu@nxp.com
+description: |
- The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.
- For i.MX8qxp LDB, each channel supports up to 24bpp parallel input color
- format and can map the input to VESA or JEIDA standards. The two channels
- cannot be used simultaneously, that is to say, the user should pick one of
- them to use. Two LDB channels from two LDB instances can work together in
- LDB split mode to support a dual link LVDS display. The channel indexes
- have to be different. Channel0 outputs odd pixels and channel1 outputs
- even pixels.
In this case, does the display controller output odd pixels and even pixels separately to the two LVDS channels, with each channel effectively be a separate LVDS encoder ? Could you give an example of DT integration for dual-link LVDS support, with the display controller, two LDB instances, and a dual-link LVDS panel ?
- For i.MX8qm LDB, each channel additionally supports up to 30bpp parallel
- input color format. The two channels can be used simultaneously, either
- in dual mode or split mode. In dual mode, the two channels output identical
- data. In split mode, channel0 outputs odd pixels and channel1 outputs even
- pixels.
+properties:
- compatible:
- enum:
- fsl,imx8qm-ldb- fsl,imx8qxp-ldb- "#address-cells":
- const: 1
- "#size-cells":
- const: 0
- clocks:
- items:
- description: pixel clock- description: bypass clock- clock-names:
- items:
- const: pixel- const: bypass- power-domains:
- maxItems: 1
- fsl,syscon:
- $ref: /schemas/types.yaml#/definitions/phandle
- description: |
A phandle which points to Control and Status Registers(CSR) module.- fsl,companion-ldb:
- $ref: /schemas/types.yaml#/definitions/phandle
- description: |
A phandle which points to companion LDB which is used in LDB split mode.+patternProperties:
- "^channel@[0-1]$":
- type: object
- description: Represents a channel of LDB.
- properties:
"#address-cells":const: 1"#size-cells":const: 0reg:description: The channel index.enum: [ 0, 1 ]phys:description: A phandle to the phy module representing the LVDS PHY.maxItems: 1phy-names:const: lvds_phyport@0:type: objectdescription: Input port of the channel.properties:reg:const: 0required:- regport@1:type: objectdescription: Output port of the channel.properties:reg:const: 1required:- reg- required:
- "#address-cells"- "#size-cells"- reg- phys- phy-names- additionalProperties: false
+required:
- compatible
- "#address-cells"
- "#size-cells"
- clocks
- clock-names
- power-domains
- fsl,syscon
- channel@0
- channel@1
+allOf:
- if:
properties:compatible:contains:const: fsl,imx8qm-ldb- then:
properties:fsl,companion-ldb: false+additionalProperties: false
+examples:
- |
- #include <dt-bindings/firmware/imx/rsrc.h>
- ldb {
#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8qxp-ldb";clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,<&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;clock-names = "pixel", "bypass";power-domains = <&pd IMX_SC_R_LVDS_0>;fsl,syscon = <&mipi_lvds_0_csr>;channel@0 {#address-cells = <1>;#size-cells = <0>;reg = <0>;phys = <&mipi_lvds_0_phy>;phy-names = "lvds_phy";port@0 {reg = <0>;mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;};};};channel@1 {#address-cells = <1>;#size-cells = <0>;reg = <1>;phys = <&mipi_lvds_0_phy>;phy-names = "lvds_phy";port@0 {reg = <0>;mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;};};};- };
Hi Liu,
On Tue, Dec 22, 2020 at 09:36:37AM +0200, Laurent Pinchart wrote:
On Thu, Dec 17, 2020 at 05:59:30PM +0800, Liu Ying wrote:
This patch adds bindings for i.MX8qm/qxp LVDS display bridge(LDB).
Signed-off-by: Liu Ying victor.liu@nxp.com
.../bindings/display/bridge/fsl,imx8qxp-ldb.yaml | 185 +++++++++++++++++++++ 1 file changed, 185 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml new file mode 100644 index 00000000..4e5ff6f --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml @@ -0,0 +1,185 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: Freescale i.MX8qm/qxp LVDS Display Bridge
+maintainers:
- Liu Ying victor.liu@nxp.com
+description: |
- The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.
- For i.MX8qxp LDB, each channel supports up to 24bpp parallel input color
- format and can map the input to VESA or JEIDA standards. The two channels
- cannot be used simultaneously, that is to say, the user should pick one of
- them to use. Two LDB channels from two LDB instances can work together in
- LDB split mode to support a dual link LVDS display. The channel indexes
- have to be different. Channel0 outputs odd pixels and channel1 outputs
- even pixels.
In this case, does the display controller output odd pixels and even pixels separately to the two LVDS channels, with each channel effectively be a separate LVDS encoder ? Could you give an example of DT integration for dual-link LVDS support, with the display controller, two LDB instances, and a dual-link LVDS panel ?
I also can't find any mention of the LDB in IMX8MDQLQRM or IMX8DQXPRM. Am I missing something ?
- For i.MX8qm LDB, each channel additionally supports up to 30bpp parallel
- input color format. The two channels can be used simultaneously, either
- in dual mode or split mode. In dual mode, the two channels output identical
- data. In split mode, channel0 outputs odd pixels and channel1 outputs even
- pixels.
+properties:
- compatible:
- enum:
- fsl,imx8qm-ldb- fsl,imx8qxp-ldb- "#address-cells":
- const: 1
- "#size-cells":
- const: 0
- clocks:
- items:
- description: pixel clock- description: bypass clock- clock-names:
- items:
- const: pixel- const: bypass- power-domains:
- maxItems: 1
- fsl,syscon:
- $ref: /schemas/types.yaml#/definitions/phandle
- description: |
A phandle which points to Control and Status Registers(CSR) module.- fsl,companion-ldb:
- $ref: /schemas/types.yaml#/definitions/phandle
- description: |
A phandle which points to companion LDB which is used in LDB split mode.+patternProperties:
- "^channel@[0-1]$":
- type: object
- description: Represents a channel of LDB.
- properties:
"#address-cells":const: 1"#size-cells":const: 0reg:description: The channel index.enum: [ 0, 1 ]phys:description: A phandle to the phy module representing the LVDS PHY.maxItems: 1phy-names:const: lvds_phyport@0:type: objectdescription: Input port of the channel.properties:reg:const: 0required:- regport@1:type: objectdescription: Output port of the channel.properties:reg:const: 1required:- reg- required:
- "#address-cells"- "#size-cells"- reg- phys- phy-names- additionalProperties: false
+required:
- compatible
- "#address-cells"
- "#size-cells"
- clocks
- clock-names
- power-domains
- fsl,syscon
- channel@0
- channel@1
+allOf:
- if:
properties:compatible:contains:const: fsl,imx8qm-ldb- then:
properties:fsl,companion-ldb: false+additionalProperties: false
+examples:
- |
- #include <dt-bindings/firmware/imx/rsrc.h>
- ldb {
#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8qxp-ldb";clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,<&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;clock-names = "pixel", "bypass";power-domains = <&pd IMX_SC_R_LVDS_0>;fsl,syscon = <&mipi_lvds_0_csr>;channel@0 {#address-cells = <1>;#size-cells = <0>;reg = <0>;phys = <&mipi_lvds_0_phy>;phy-names = "lvds_phy";port@0 {reg = <0>;mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;};};};channel@1 {#address-cells = <1>;#size-cells = <0>;reg = <1>;phys = <&mipi_lvds_0_phy>;phy-names = "lvds_phy";port@0 {reg = <0>;mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;};};};- };
-- Regards,
Laurent Pinchart
Hi Laurent,
On Tue, 2020-12-22 at 09:49 +0200, Laurent Pinchart wrote:
Hi Liu,
On Tue, Dec 22, 2020 at 09:36:37AM +0200, Laurent Pinchart wrote:
On Thu, Dec 17, 2020 at 05:59:30PM +0800, Liu Ying wrote:
This patch adds bindings for i.MX8qm/qxp LVDS display bridge(LDB).
Signed-off-by: Liu Ying victor.liu@nxp.com
.../bindings/display/bridge/fsl,imx8qxp-ldb.yaml | 185 +++++++++++++++++++++ 1 file changed, 185 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml new file mode 100644 index 00000000..4e5ff6f --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml @@ -0,0 +1,185 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.... +$schema: https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree....
+title: Freescale i.MX8qm/qxp LVDS Display Bridge
+maintainers:
- Liu Ying victor.liu@nxp.com
+description: |
- The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.
- For i.MX8qxp LDB, each channel supports up to 24bpp parallel input color
- format and can map the input to VESA or JEIDA standards. The two channels
- cannot be used simultaneously, that is to say, the user should pick one of
- them to use. Two LDB channels from two LDB instances can work together in
- LDB split mode to support a dual link LVDS display. The channel indexes
- have to be different. Channel0 outputs odd pixels and channel1 outputs
- even pixels.
In this case, does the display controller output odd pixels and even pixels separately to the two LVDS channels, with each channel effectively be a separate LVDS encoder ? Could you give an example of DT integration for dual-link LVDS support, with the display controller, two LDB instances, and a dual-link LVDS panel ?
I also can't find any mention of the LDB in IMX8MDQLQRM or IMX8DQXPRM. Am I missing something ?
i.MX8mq doesn't has LDB.
The i.MX8qxp RM calls LDB as pixel mapper.
This binding calls it 'LDB' for below reasons: 1) 'LDB' is a shorter name.
2) Our internal i.MX8qm/qxp documentations do mention that pixel mapper uses LDB logic and is based on i.MX6 LDB.
3) Patch 10/14 creates a 'imx-ldb-helper' which can be potentially used by i.MX6qdl/sx LDBs. So, it will be a consistent name.
Do you think if it will be ok if I mention 'pixel mapper' as a side note in the next version?
Liu Ying
- For i.MX8qm LDB, each channel additionally supports up to 30bpp parallel
- input color format. The two channels can be used simultaneously, either
- in dual mode or split mode. In dual mode, the two channels output identical
- data. In split mode, channel0 outputs odd pixels and channel1 outputs even
- pixels.
+properties:
- compatible:
- enum:
- fsl,imx8qm-ldb- fsl,imx8qxp-ldb- "#address-cells":
- const: 1
- "#size-cells":
- const: 0
- clocks:
- items:
- description: pixel clock- description: bypass clock- clock-names:
- items:
- const: pixel- const: bypass- power-domains:
- maxItems: 1
- fsl,syscon:
- $ref: /schemas/types.yaml#/definitions/phandle
- description: |
A phandle which points to Control and Status Registers(CSR) module.- fsl,companion-ldb:
- $ref: /schemas/types.yaml#/definitions/phandle
- description: |
A phandle which points to companion LDB which is used in LDB split mode.+patternProperties:
- "^channel@[0-1]$":
- type: object
- description: Represents a channel of LDB.
- properties:
"#address-cells":const: 1"#size-cells":const: 0reg:description: The channel index.enum: [ 0, 1 ]phys:description: A phandle to the phy module representing the LVDS PHY.maxItems: 1phy-names:const: lvds_phyport@0:type: objectdescription: Input port of the channel.properties:reg:const: 0required:- regport@1:type: objectdescription: Output port of the channel.properties:reg:const: 1required:- reg- required:
- "#address-cells"- "#size-cells"- reg- phys- phy-names- additionalProperties: false
+required:
- compatible
- "#address-cells"
- "#size-cells"
- clocks
- clock-names
- power-domains
- fsl,syscon
- channel@0
- channel@1
+allOf:
- if:
properties:compatible:contains:const: fsl,imx8qm-ldb- then:
properties:fsl,companion-ldb: false+additionalProperties: false
+examples:
- |
- #include <dt-bindings/firmware/imx/rsrc.h>
- ldb {
#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8qxp-ldb";clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,<&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;clock-names = "pixel", "bypass";power-domains = <&pd IMX_SC_R_LVDS_0>;fsl,syscon = <&mipi_lvds_0_csr>;channel@0 {#address-cells = <1>;#size-cells = <0>;reg = <0>;phys = <&mipi_lvds_0_phy>;phy-names = "lvds_phy";port@0 {reg = <0>;mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;};};};channel@1 {#address-cells = <1>;#size-cells = <0>;reg = <1>;phys = <&mipi_lvds_0_phy>;phy-names = "lvds_phy";port@0 {reg = <0>;mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;};};};- };
-- Regards,
Laurent Pinchart
Hi Laurent,
On Tue, 2020-12-22 at 09:36 +0200, Laurent Pinchart wrote:
Hi Liu,
Thank you for the patch.
On Thu, Dec 17, 2020 at 05:59:30PM +0800, Liu Ying wrote:
This patch adds bindings for i.MX8qm/qxp LVDS display bridge(LDB).
Signed-off-by: Liu Ying victor.liu@nxp.com
.../bindings/display/bridge/fsl,imx8qxp-ldb.yaml | 185 +++++++++++++++++++++ 1 file changed, 185 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml new file mode 100644 index 00000000..4e5ff6f --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml @@ -0,0 +1,185 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.... +$schema: https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree....
+title: Freescale i.MX8qm/qxp LVDS Display Bridge
+maintainers:
- Liu Ying victor.liu@nxp.com
+description: |
- The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.
- For i.MX8qxp LDB, each channel supports up to 24bpp parallel input color
- format and can map the input to VESA or JEIDA standards. The two channels
- cannot be used simultaneously, that is to say, the user should pick one of
- them to use. Two LDB channels from two LDB instances can work together in
- LDB split mode to support a dual link LVDS display. The channel indexes
- have to be different. Channel0 outputs odd pixels and channel1 outputs
- even pixels.
In this case, does the display controller output odd pixels and even pixels separately to the two LVDS channels, with each channel effectively be a separate LVDS encoder ? Could you give an example of DT
The display controller just outputs frames without odd/even pixels concept.
The frames reach two LDBs through pixel combiner, display pixel link and PXL2DPI.
Each LDB would split out odd/even pixels and just use either odd pixels or even pixels.
integration for dual-link LVDS support, with the display controller, two LDB instances, and a dual-link LVDS panel ?
https://pastebin.ubuntu.com/p/HmzxV6PpvH/
Liu Ying
- For i.MX8qm LDB, each channel additionally supports up to 30bpp parallel
- input color format. The two channels can be used simultaneously, either
- in dual mode or split mode. In dual mode, the two channels output identical
- data. In split mode, channel0 outputs odd pixels and channel1 outputs even
- pixels.
+properties:
- compatible:
- enum:
- fsl,imx8qm-ldb- fsl,imx8qxp-ldb- "#address-cells":
- const: 1
- "#size-cells":
- const: 0
- clocks:
- items:
- description: pixel clock- description: bypass clock- clock-names:
- items:
- const: pixel- const: bypass- power-domains:
- maxItems: 1
- fsl,syscon:
- $ref: /schemas/types.yaml#/definitions/phandle
- description: |
A phandle which points to Control and Status Registers(CSR) module.- fsl,companion-ldb:
- $ref: /schemas/types.yaml#/definitions/phandle
- description: |
A phandle which points to companion LDB which is used in LDB split mode.+patternProperties:
- "^channel@[0-1]$":
- type: object
- description: Represents a channel of LDB.
- properties:
"#address-cells":const: 1"#size-cells":const: 0reg:description: The channel index.enum: [ 0, 1 ]phys:description: A phandle to the phy module representing the LVDS PHY.maxItems: 1phy-names:const: lvds_phyport@0:type: objectdescription: Input port of the channel.properties:reg:const: 0required:- regport@1:type: objectdescription: Output port of the channel.properties:reg:const: 1required:- reg- required:
- "#address-cells"- "#size-cells"- reg- phys- phy-names- additionalProperties: false
+required:
- compatible
- "#address-cells"
- "#size-cells"
- clocks
- clock-names
- power-domains
- fsl,syscon
- channel@0
- channel@1
+allOf:
- if:
properties:compatible:contains:const: fsl,imx8qm-ldb- then:
properties:fsl,companion-ldb: false+additionalProperties: false
+examples:
- |
- #include <dt-bindings/firmware/imx/rsrc.h>
- ldb {
#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8qxp-ldb";clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,<&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;clock-names = "pixel", "bypass";power-domains = <&pd IMX_SC_R_LVDS_0>;fsl,syscon = <&mipi_lvds_0_csr>;channel@0 {#address-cells = <1>;#size-cells = <0>;reg = <0>;phys = <&mipi_lvds_0_phy>;phy-names = "lvds_phy";port@0 {reg = <0>;mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;};};};channel@1 {#address-cells = <1>;#size-cells = <0>;reg = <1>;phys = <&mipi_lvds_0_phy>;phy-names = "lvds_phy";port@0 {reg = <0>;mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;};};};- };
This patch adds a drm bridge driver for i.MX8qxp LVDS display bridge(LDB). The LDB has two channels. Each of them supports up to 24bpp parallel input color format and can map the input to VESA or JEIDA standards. The two channels cannot be used simultaneously, that is to say, the user should pick one of them to use. Two LDB channels from two LDB instances can work together in LDB split mode to support a dual link LVDS display. The channel indexes have to be different. Channel0 outputs odd pixels and channel1 outputs even pixels. This patch supports the LDB single mode and split mode.
Signed-off-by: Liu Ying victor.liu@nxp.com --- drivers/gpu/drm/bridge/imx/Kconfig | 10 + drivers/gpu/drm/bridge/imx/Makefile | 1 + drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c | 762 +++++++++++++++++++++++++++++++ 3 files changed, 773 insertions(+) create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c
diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig index 23e24fd..2a32ad3 100644 --- a/drivers/gpu/drm/bridge/imx/Kconfig +++ b/drivers/gpu/drm/bridge/imx/Kconfig @@ -6,6 +6,16 @@ config DRM_IMX_LVDS_BRIDGE_HELPER Helper to support Freescale i.MX LVDS Display Bridge(LDB). This bridge is embedded in a SoC.
+config DRM_IMX8QXP_LDB + tristate "Freescale i.MX8QXP LVDS display bridge" + depends on DRM_IMX_LVDS_BRIDGE_HELPER + depends on OF + depends on COMMON_CLK + select DRM_KMS_HELPER + help + Choose this to enable the internal LVDS Display Bridge(LDB) found in + Freescale i.MX8qxp processor. + config DRM_IMX8QXP_PIXEL_COMBINER tristate "Freescale i.MX8QM/QXP pixel combiner" depends on OF diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile index 902b703..13160f0 100644 --- a/drivers/gpu/drm/bridge/imx/Makefile +++ b/drivers/gpu/drm/bridge/imx/Makefile @@ -1,4 +1,5 @@ obj-$(CONFIG_DRM_IMX_LVDS_BRIDGE_HELPER) += imx-ldb-helper.o +obj-$(CONFIG_DRM_IMX8QXP_LDB) += imx8qxp-ldb.o obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI) += imx8qxp-pxl2dpi.o diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c b/drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c new file mode 100644 index 00000000..318615fb --- /dev/null +++ b/drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c @@ -0,0 +1,762 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include <linux/clk.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/of_graph.h> +#include <linux/phy/phy.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h> + +#include <drm/bridge/imx_ldb_helper.h> +#include <drm/drm_atomic_state_helper.h> +#include <drm/drm_bridge.h> +#include <drm/drm_connector.h> +#include <drm/drm_fourcc.h> +#include <drm/drm_of.h> +#include <drm/drm_print.h> + +#define LDB_CH_SEL (1 << 28) + +#define SS_CTRL 0x20 +#define CH_HSYNC_M(id) BIT(0 + ((id) * 2)) +#define CH_VSYNC_M(id) BIT(1 + ((id) * 2)) +#define CH_PHSYNC(id) BIT(0 + ((id) * 2)) +#define CH_PVSYNC(id) BIT(1 + ((id) * 2)) + +#define DRIVER_NAME "imx8qxp-ldb" + +struct imx8qxp_ldb_channel { + struct ldb_channel base; + struct phy *phy; + unsigned int di_id; +}; + +struct imx8qxp_ldb { + struct ldb base; + struct device *dev; + struct imx8qxp_ldb_channel channel[MAX_LDB_CHAN_NUM]; + struct clk *clk_pixel; + struct clk *clk_bypass; + struct drm_bridge *companion; + int active_chno; +}; + +static inline struct imx8qxp_ldb_channel * +base_to_imx8qxp_ldb_channel(struct ldb_channel *base) +{ + return container_of(base, struct imx8qxp_ldb_channel, base); +} + +static inline struct imx8qxp_ldb *base_to_imx8qxp_ldb(struct ldb *base) +{ + return container_of(base, struct imx8qxp_ldb, base); +} + +static void imx8qxp_ldb_set_phy_cfg(struct imx8qxp_ldb *imx8qxp_ldb, + unsigned long di_clk, bool is_split, + struct phy_configure_opts_lvds *phy_cfg) +{ + phy_cfg->bits_per_lane_and_dclk_cycle = 7; + phy_cfg->lanes = 4; + + if (is_split) { + phy_cfg->differential_clk_rate = di_clk / 2; + phy_cfg->is_slave = !imx8qxp_ldb->companion; + } else { + phy_cfg->differential_clk_rate = di_clk; + phy_cfg->is_slave = false; + } +} + +static int imx8qxp_ldb_bridge_atomic_check(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + struct ldb *ldb = ldb_ch->ldb; + struct imx8qxp_ldb_channel *imx8qxp_ldb_ch = + base_to_imx8qxp_ldb_channel(ldb_ch); + struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb); + struct drm_bridge *companion = imx8qxp_ldb->companion; + struct drm_display_mode *adj = &crtc_state->adjusted_mode; + unsigned long di_clk = adj->clock * 1000; + bool is_split = ldb_channel_is_split_link(ldb_ch); + union phy_configure_opts opts = { }; + struct phy_configure_opts_lvds *phy_cfg = &opts.lvds; + int ret; + + ret = ldb_bridge_atomic_check_helper(bridge, bridge_state, + crtc_state, conn_state); + if (ret) + return ret; + + imx8qxp_ldb_set_phy_cfg(imx8qxp_ldb, di_clk, is_split, phy_cfg); + ret = phy_validate(imx8qxp_ldb_ch->phy, PHY_MODE_LVDS, 0, &opts); + if (ret < 0) { + DRM_DEV_DEBUG_DRIVER(imx8qxp_ldb->dev, + "failed to validate PHY: %d\n", ret); + return ret; + } + + if (is_split && companion) { + ret = companion->funcs->atomic_check(companion, + bridge_state, crtc_state, conn_state); + if (ret) + return ret; + } + + return ret; +} + +static void +imx8qxp_ldb_bridge_mode_set(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + const struct drm_display_mode *adjusted_mode) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + struct ldb_channel *companion_ldb_ch; + struct ldb *ldb = ldb_ch->ldb; + struct imx8qxp_ldb_channel *imx8qxp_ldb_ch = + base_to_imx8qxp_ldb_channel(ldb_ch); + struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb); + struct drm_bridge *companion = imx8qxp_ldb->companion; + struct device *dev = imx8qxp_ldb->dev; + unsigned long di_clk = adjusted_mode->clock * 1000; + bool is_split = ldb_channel_is_split_link(ldb_ch); + union phy_configure_opts opts = { }; + struct phy_configure_opts_lvds *phy_cfg = &opts.lvds; + u32 chno = ldb_ch->chno; + int ret; + + ret = pm_runtime_get_sync(dev); + if (ret < 0) + DRM_DEV_ERROR(dev, "failed to get runtime PM sync: %d\n", ret); + + ret = phy_init(imx8qxp_ldb_ch->phy); + if (ret < 0) + DRM_DEV_ERROR(dev, "failed to initialize PHY: %d\n", ret); + + ret = phy_set_mode(imx8qxp_ldb_ch->phy, PHY_MODE_LVDS); + if (ret < 0) + DRM_DEV_ERROR(dev, "failed to set PHY mode: %d\n", ret); + + if (is_split && companion) { + companion_ldb_ch = bridge_to_ldb_ch(companion); + + companion_ldb_ch->in_bus_format = ldb_ch->in_bus_format; + companion_ldb_ch->out_bus_format = ldb_ch->out_bus_format; + } + + clk_set_rate(imx8qxp_ldb->clk_bypass, di_clk); + clk_set_rate(imx8qxp_ldb->clk_pixel, di_clk); + + imx8qxp_ldb_set_phy_cfg(imx8qxp_ldb, di_clk, is_split, phy_cfg); + ret = phy_configure(imx8qxp_ldb_ch->phy, &opts); + if (ret < 0) + DRM_DEV_ERROR(dev, "failed to configure PHY: %d\n", ret); + + if (chno == 0) + ldb->ldb_ctrl &= ~LDB_CH_SEL; + else + ldb->ldb_ctrl |= LDB_CH_SEL; + + /* input VSYNC signal from pixel link is active low */ + if (imx8qxp_ldb_ch->di_id == 0) + ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW; + else + ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW; + + /* + * For split mode, settle input VSYNC signal polarity and + * channel selection down early. + */ + if (is_split) + regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl); + + ldb_bridge_mode_set_helper(bridge, mode, adjusted_mode); + + if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) + regmap_update_bits(ldb->regmap, SS_CTRL, CH_VSYNC_M(chno), 0); + else if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) + regmap_update_bits(ldb->regmap, SS_CTRL, + CH_VSYNC_M(chno), CH_PVSYNC(chno)); + + if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) + regmap_update_bits(ldb->regmap, SS_CTRL, CH_HSYNC_M(chno), 0); + else if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) + regmap_update_bits(ldb->regmap, SS_CTRL, + CH_HSYNC_M(chno), CH_PHSYNC(chno)); + + if (is_split && companion) + companion->funcs->mode_set(companion, mode, adjusted_mode); +} + +static void +imx8qxp_ldb_bridge_atomic_pre_enable(struct drm_bridge *bridge, + struct drm_bridge_state *old_bridge_state) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + struct ldb *ldb = ldb_ch->ldb; + struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb); + struct drm_bridge *companion = imx8qxp_ldb->companion; + bool is_split = ldb_channel_is_split_link(ldb_ch); + + clk_prepare_enable(imx8qxp_ldb->clk_pixel); + clk_prepare_enable(imx8qxp_ldb->clk_bypass); + + if (is_split && companion) + companion->funcs->atomic_pre_enable(companion, old_bridge_state); +} + +static void +imx8qxp_ldb_bridge_atomic_enable(struct drm_bridge *bridge, + struct drm_bridge_state *old_bridge_state) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + struct ldb *ldb = ldb_ch->ldb; + struct imx8qxp_ldb_channel *imx8qxp_ldb_ch = + base_to_imx8qxp_ldb_channel(ldb_ch); + struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb); + struct drm_bridge *companion = imx8qxp_ldb->companion; + struct device *dev = imx8qxp_ldb->dev; + bool is_split = ldb_channel_is_split_link(ldb_ch); + int ret; + + if (ldb_ch->chno == 0 || is_split) { + ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK; + ldb->ldb_ctrl |= imx8qxp_ldb_ch->di_id == 0 ? + LDB_CH0_MODE_EN_TO_DI0 : LDB_CH0_MODE_EN_TO_DI1; + } + if (ldb_ch->chno == 1 || is_split) { + ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK; + ldb->ldb_ctrl |= imx8qxp_ldb_ch->di_id == 0 ? + LDB_CH1_MODE_EN_TO_DI0 : LDB_CH1_MODE_EN_TO_DI1; + } + + ldb_bridge_enable_helper(bridge); + + ret = phy_power_on(imx8qxp_ldb_ch->phy); + if (ret) + DRM_DEV_ERROR(dev, "failed to power on PHY: %d\n", ret); + + if (is_split && companion) + companion->funcs->atomic_enable(companion, old_bridge_state); +} + +static void +imx8qxp_ldb_bridge_atomic_disable(struct drm_bridge *bridge, + struct drm_bridge_state *old_bridge_state) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + struct ldb *ldb = ldb_ch->ldb; + struct imx8qxp_ldb_channel *imx8qxp_ldb_ch = + base_to_imx8qxp_ldb_channel(ldb_ch); + struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb); + struct drm_bridge *companion = imx8qxp_ldb->companion; + struct device *dev = imx8qxp_ldb->dev; + bool is_split = ldb_channel_is_split_link(ldb_ch); + int ret; + + ret = phy_power_off(imx8qxp_ldb_ch->phy); + if (ret) + DRM_DEV_ERROR(dev, "failed to power off PHY: %d\n", ret); + + ret = phy_exit(imx8qxp_ldb_ch->phy); + if (ret < 0) + DRM_DEV_ERROR(dev, "failed to teardown PHY: %d\n", ret); + + ldb_bridge_disable_helper(bridge); + + clk_disable_unprepare(imx8qxp_ldb->clk_bypass); + clk_disable_unprepare(imx8qxp_ldb->clk_pixel); + + if (is_split && companion) + companion->funcs->atomic_disable(companion, old_bridge_state); + + ret = pm_runtime_put(dev); + if (ret < 0) + DRM_DEV_ERROR(dev, "failed to put runtime PM: %d\n", ret); +} + +static const u32 imx8qxp_ldb_bus_output_fmts[] = { + MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, + MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, + MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, + MEDIA_BUS_FMT_FIXED, +}; + +static bool imx8qxp_ldb_bus_output_fmt_supported(u32 fmt) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(imx8qxp_ldb_bus_output_fmts); i++) { + if (imx8qxp_ldb_bus_output_fmts[i] == fmt) + return true; + } + + return false; +} + +static u32 * +imx8qxp_ldb_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + u32 output_fmt, + unsigned int *num_input_fmts) +{ + struct drm_display_info *di; + const struct drm_format_info *finfo; + u32 *input_fmts; + + if (!imx8qxp_ldb_bus_output_fmt_supported(output_fmt)) + return NULL; + + *num_input_fmts = 1; + + input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL); + if (!input_fmts) + return NULL; + + switch (output_fmt) { + case MEDIA_BUS_FMT_FIXED: + di = &conn_state->connector->display_info; + + /* + * Look at the first bus format to determine input format. + * Default to MEDIA_BUS_FMT_RGB888_1X24, if no match. + */ + if (di->num_bus_formats) { + finfo = drm_format_info(di->bus_formats[0]); + + input_fmts[0] = finfo->depth == 18 ? + MEDIA_BUS_FMT_RGB666_1X24_CPADHI : + MEDIA_BUS_FMT_RGB888_1X24; + } else { + input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; + } + break; + case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: + input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X24_CPADHI; + break; + case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: + case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: + input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; + break; + default: + kfree(input_fmts); + input_fmts = NULL; + break; + } + + return input_fmts; +} + +static u32 * +imx8qxp_ldb_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + unsigned int *num_output_fmts) +{ + *num_output_fmts = ARRAY_SIZE(imx8qxp_ldb_bus_output_fmts); + return kmemdup(imx8qxp_ldb_bus_output_fmts, + sizeof(imx8qxp_ldb_bus_output_fmts), GFP_KERNEL); +} + +static enum drm_mode_status +imx8qxp_ldb_bridge_mode_valid(struct drm_bridge *bridge, + const struct drm_display_info *info, + const struct drm_display_mode *mode) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + bool is_single = ldb_channel_is_single_link(ldb_ch); + + if (mode->clock > 170000) + return MODE_CLOCK_HIGH; + + if (mode->clock > 150000 && is_single) + return MODE_CLOCK_HIGH; + + return MODE_OK; +} + +static const struct drm_bridge_funcs imx8qxp_ldb_bridge_funcs = { + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, + .atomic_reset = drm_atomic_helper_bridge_reset, + .mode_valid = imx8qxp_ldb_bridge_mode_valid, + .attach = ldb_bridge_attach_helper, + .atomic_check = imx8qxp_ldb_bridge_atomic_check, + .mode_set = imx8qxp_ldb_bridge_mode_set, + .atomic_pre_enable = imx8qxp_ldb_bridge_atomic_pre_enable, + .atomic_enable = imx8qxp_ldb_bridge_atomic_enable, + .atomic_disable = imx8qxp_ldb_bridge_atomic_disable, + .atomic_get_input_bus_fmts = + imx8qxp_ldb_bridge_atomic_get_input_bus_fmts, + .atomic_get_output_bus_fmts = + imx8qxp_ldb_bridge_atomic_get_output_bus_fmts, +}; + +static int imx8qxp_ldb_set_di_id(struct imx8qxp_ldb *imx8qxp_ldb) +{ + struct imx8qxp_ldb_channel *imx8qxp_ldb_ch = + &imx8qxp_ldb->channel[imx8qxp_ldb->active_chno]; + struct ldb_channel *ldb_ch = &imx8qxp_ldb_ch->base; + struct device_node *remote, *port, *ep = NULL; + struct device *dev = imx8qxp_ldb->dev; + struct of_endpoint endpoint; + int ep_cnt; + int ret; + + /* remote is PXL2DPI */ + remote = of_graph_get_remote_node(ldb_ch->np, 0, 0); + if (!remote) { + DRM_DEV_ERROR(dev, "failed to get PXL2DPI node\n"); + return -ENODEV; + } + + port = of_graph_get_port_by_id(remote, 0); + if (!port) { + DRM_DEV_ERROR(dev, "failed to get PXL2DPI node's port@0\n"); + ret = -ENODEV; + goto out; + } + + ep_cnt = of_get_available_child_count(port); + if (ep_cnt == 0) { + DRM_DEV_ERROR(dev, + "no available endpoints of PXL2DPI node's port@0\n"); + ret = -ENODEV; + goto out; + } else if (ep_cnt > 1) { + DRM_DEV_ERROR(dev, + "invalid available endpoints of PXL2DPI node's port@0\n"); + ret = -ENOTSUPP; + goto out; + } + + ep = of_get_next_available_child(port, NULL); + if (!ep) { + DRM_DEV_ERROR(dev, + "failed to get available endpoint of PXL2DPI node's port@0\n"); + ret = -ENODEV; + goto out; + } + + ret = of_graph_parse_endpoint(ep, &endpoint); + if (ret) { + DRM_DEV_ERROR(dev, + "failed to parse endpoint of PXL2DPI node's port@0: %d\n", + ret); + goto out; + } + + imx8qxp_ldb_ch->di_id = endpoint.id; +out: + of_node_put(ep); + of_node_put(port); + of_node_put(remote); + + return ret; +} + +static int +imx8qxp_ldb_check_chno_and_dual_link(struct ldb_channel *ldb_ch, int link) +{ + if ((link == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS && ldb_ch->chno != 0) || + (link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS && ldb_ch->chno != 1)) + return -EINVAL; + + return 0; +} + +static int imx8qxp_ldb_parse_dt_companion(struct imx8qxp_ldb *imx8qxp_ldb) +{ + struct imx8qxp_ldb_channel *imx8qxp_ldb_ch = + &imx8qxp_ldb->channel[imx8qxp_ldb->active_chno]; + struct ldb_channel *ldb_ch = &imx8qxp_ldb_ch->base; + struct ldb_channel *companion_ldb_ch; + struct device_node *companion; + struct device_node *child; + struct device_node *companion_port = NULL; + struct device_node *port1, *port2; + struct device *dev = imx8qxp_ldb->dev; + const struct of_device_id *match; + u32 i; + int ch_cnt; + int dual_link; + int ret; + + /* Locate the companion LDB for dual-link operation, if any. */ + companion = of_parse_phandle(dev->of_node, "fsl,companion-ldb", 0); + if (!companion) + return 0; + + if (!of_device_is_available(companion)) { + DRM_DEV_ERROR(dev, "companion LDB is not available\n"); + ret = -ENODEV; + goto out; + } + + /* + * Sanity check: the companion bridge must have the same compatible + * string. + */ + match = of_match_device(dev->driver->of_match_table, dev); + if (!of_device_is_compatible(companion, match->compatible)) { + DRM_DEV_ERROR(dev, "companion LDB is incompatible\n"); + ret = -ENXIO; + goto out; + } + + ch_cnt = of_get_available_child_count(companion); + if (ch_cnt == 0) { + DRM_DEV_ERROR(dev, "no available companion LDB channel\n"); + ret = -ENODEV; + goto out; + } else if (ch_cnt > 1) { + DRM_DEV_ERROR(dev, "invalid available companion LDB channels\n"); + ret = -ENOTSUPP; + goto out; + } + + for_each_available_child_of_node(companion, child) { + ret = of_property_read_u32(child, "reg", &i); + if (ret || i > MAX_LDB_CHAN_NUM - 1) { + DRM_DEV_ERROR(dev, + "invalid channel node address: %u\n", i); + ret = -EINVAL; + of_node_put(child); + goto out; + } + + companion_port = child; + of_node_put(child); + break; + } + + if (companion_port == NULL) { + DRM_DEV_ERROR(dev, + "failed to find companion LDB channel port\n"); + ret = -EINVAL; + goto out; + } + + /* + * Channel numbers have to be different, because channel0 transmits + * odd pixels and channel1 transmits even pixels. + */ + if (i == ldb_ch->chno) { + DRM_DEV_ERROR(dev, "invalid companion LDB channel number\n"); + ret = -EINVAL; + goto out; + } + + /* + * We need to work out if the sink is expecting us to function in + * dual-link mode. We do this by looking at the DT port nodes we are + * connected to. If they are marked as expecting odd pixels and + * even pixels than we need to enable LDB split mode. + */ + port1 = of_graph_get_port_by_id(ldb_ch->np, 1); + port2 = of_graph_get_port_by_id(companion_port, 1); + dual_link = drm_of_lvds_get_dual_link_pixel_order(port1, port2); + of_node_put(port1); + of_node_put(port2); + + switch (dual_link) { + case DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS: + ldb_ch->link_type = LDB_CH_DUAL_LINK_ODD_EVEN_PIXELS; + break; + case DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS: + ldb_ch->link_type = LDB_CH_DUAL_LINK_EVEN_ODD_PIXELS; + break; + default: + ret = dual_link; + DRM_DEV_ERROR(dev, + "failed to get dual link pixel order: %d\n", ret); + goto out; + } + + ret = imx8qxp_ldb_check_chno_and_dual_link(ldb_ch, dual_link); + if (ret < 0) { + DRM_DEV_ERROR(dev, + "unmatched channel number(%u) vs dual link(%d)\n", + ldb_ch->chno, dual_link); + goto out; + } + + imx8qxp_ldb->companion = of_drm_find_bridge(companion_port); + if (!imx8qxp_ldb->companion) { + ret = -EPROBE_DEFER; + DRM_DEV_DEBUG_DRIVER(dev, + "failed to find bridge for companion bridge: %d\n", ret); + goto out; + } + + DRM_DEV_DEBUG_DRIVER(dev, + "dual-link configuration detected (companion bridge %pOF)\n", + companion); + + companion_ldb_ch = bridge_to_ldb_ch(imx8qxp_ldb->companion); + companion_ldb_ch->link_type = ldb_ch->link_type; +out: + of_node_put(companion); + return ret; +} + +static int imx8qxp_ldb_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct imx8qxp_ldb *imx8qxp_ldb; + struct imx8qxp_ldb_channel *imx8qxp_ldb_ch; + struct ldb *ldb; + struct ldb_channel *ldb_ch; + int ret, i; + + imx8qxp_ldb = devm_kzalloc(dev, sizeof(*imx8qxp_ldb), GFP_KERNEL); + if (!imx8qxp_ldb) + return -ENOMEM; + + imx8qxp_ldb->clk_pixel = devm_clk_get(dev, "pixel"); + if (IS_ERR(imx8qxp_ldb->clk_pixel)) { + ret = PTR_ERR(imx8qxp_ldb->clk_pixel); + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(dev, + "failed to get pixel clock: %d\n", ret); + return ret; + } + + imx8qxp_ldb->clk_bypass = devm_clk_get(dev, "bypass"); + if (IS_ERR(imx8qxp_ldb->clk_bypass)) { + ret = PTR_ERR(imx8qxp_ldb->clk_bypass); + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(dev, + "failed to get bypass clock: %d\n", ret); + return ret; + } + + imx8qxp_ldb->dev = dev; + + ldb = &imx8qxp_ldb->base; + ldb->dev = dev; + ldb->ctrl_reg = 0xe0; + + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) + ldb->channel[i] = &imx8qxp_ldb->channel[i].base; + + ret = ldb_init_helper(ldb); + if (ret) + return ret; + + if (ldb->available_ch_cnt == 0) { + DRM_DEV_DEBUG_DRIVER(dev, "no available channel\n"); + return 0; + } else if (ldb->available_ch_cnt > 1) { + DRM_DEV_ERROR(dev, "invalid available channel number(%u)\n", + ldb->available_ch_cnt); + return -ENOTSUPP; + } + + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) { + imx8qxp_ldb_ch = &imx8qxp_ldb->channel[i]; + ldb_ch = &imx8qxp_ldb_ch->base; + + if (ldb_ch->is_available) { + imx8qxp_ldb->active_chno = ldb_ch->chno; + break; + } + } + + imx8qxp_ldb_ch->phy = devm_of_phy_get(dev, ldb_ch->np, "lvds_phy"); + if (IS_ERR(imx8qxp_ldb_ch->phy)) { + ret = PTR_ERR(imx8qxp_ldb_ch->phy); + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(dev, "failed to get channel%d PHY: %d\n", + imx8qxp_ldb->active_chno, ret); + return ret; + } + + ret = ldb_find_next_bridge_helper(ldb); + if (ret) + return ret; + + ret = imx8qxp_ldb_set_di_id(imx8qxp_ldb); + if (ret) + return ret; + + ret = imx8qxp_ldb_parse_dt_companion(imx8qxp_ldb); + if (ret) + return ret; + + platform_set_drvdata(pdev, imx8qxp_ldb); + pm_runtime_enable(dev); + + ldb_add_bridge_helper(ldb, &imx8qxp_ldb_bridge_funcs); + + return ret; +} + +static int imx8qxp_ldb_remove(struct platform_device *pdev) +{ + struct imx8qxp_ldb *imx8qxp_ldb = platform_get_drvdata(pdev); + struct ldb *ldb = &imx8qxp_ldb->base; + + ldb_remove_bridge_helper(ldb); + + pm_runtime_disable(&pdev->dev); + + return 0; +} + +static int __maybe_unused imx8qxp_ldb_runtime_suspend(struct device *dev) +{ + return 0; +} + +static int __maybe_unused imx8qxp_ldb_runtime_resume(struct device *dev) +{ + struct imx8qxp_ldb *imx8qxp_ldb = dev_get_drvdata(dev); + struct ldb *ldb = &imx8qxp_ldb->base; + + /* disable LDB by resetting the control register to POR default */ + regmap_write(ldb->regmap, ldb->ctrl_reg, 0); + + return 0; +} + +static const struct dev_pm_ops imx8qxp_ldb_pm_ops = { + SET_RUNTIME_PM_OPS(imx8qxp_ldb_runtime_suspend, + imx8qxp_ldb_runtime_resume, NULL) +}; + +static const struct of_device_id imx8qxp_ldb_dt_ids[] = { + { .compatible = "fsl,imx8qxp-ldb" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx8qxp_ldb_dt_ids); + +static struct platform_driver imx8qxp_ldb_driver = { + .probe = imx8qxp_ldb_probe, + .remove = imx8qxp_ldb_remove, + .driver = { + .pm = &imx8qxp_ldb_pm_ops, + .name = DRIVER_NAME, + .of_match_table = imx8qxp_ldb_dt_ids, + }, +}; +module_platform_driver(imx8qxp_ldb_driver); + +MODULE_DESCRIPTION("i.MX8QXP LVDS Display Bridge(LDB) bridge driver"); +MODULE_AUTHOR("Liu Ying victor.liu@nxp.com"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRIVER_NAME);
On Thu, 2020-12-17 at 17:59 +0800, Liu Ying wrote:
This patch adds a drm bridge driver for i.MX8qxp LVDS display bridge(LDB). The LDB has two channels. Each of them supports up to 24bpp parallel input color format and can map the input to VESA or JEIDA standards. The two channels cannot be used simultaneously, that is to say, the user should pick one of them to use. Two LDB channels from two LDB instances can work together in LDB split mode to support a dual link LVDS display. The channel indexes have to be different. Channel0 outputs odd pixels and channel1 outputs even pixels. This patch supports the LDB single mode and split mode.
Signed-off-by: Liu Ying victor.liu@nxp.com
drivers/gpu/drm/bridge/imx/Kconfig | 10 + drivers/gpu/drm/bridge/imx/Makefile | 1 + drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c | 762 +++++++++++++++++++++++++++++++ 3 files changed, 773 insertions(+) create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c
diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig index 23e24fd..2a32ad3 100644 --- a/drivers/gpu/drm/bridge/imx/Kconfig +++ b/drivers/gpu/drm/bridge/imx/Kconfig @@ -6,6 +6,16 @@ config DRM_IMX_LVDS_BRIDGE_HELPER Helper to support Freescale i.MX LVDS Display Bridge(LDB). This bridge is embedded in a SoC.
+config DRM_IMX8QXP_LDB
- tristate "Freescale i.MX8QXP LVDS display bridge"
- depends on DRM_IMX_LVDS_BRIDGE_HELPER
- depends on OF
- depends on COMMON_CLK
- select DRM_KMS_HELPER
- help
Choose this to enable the internal LVDS Display Bridge(LDB) found inFreescale i.MX8qxp processor.config DRM_IMX8QXP_PIXEL_COMBINER tristate "Freescale i.MX8QM/QXP pixel combiner" depends on OF diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile index 902b703..13160f0 100644 --- a/drivers/gpu/drm/bridge/imx/Makefile +++ b/drivers/gpu/drm/bridge/imx/Makefile @@ -1,4 +1,5 @@ obj-$(CONFIG_DRM_IMX_LVDS_BRIDGE_HELPER) += imx-ldb-helper.o +obj-$(CONFIG_DRM_IMX8QXP_LDB) += imx8qxp-ldb.o obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI) += imx8qxp-pxl2dpi.o diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c b/drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c new file mode 100644 index 00000000..318615fb --- /dev/null +++ b/drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c @@ -0,0 +1,762 @@ +// SPDX-License-Identifier: GPL-2.0+
+/*
- Copyright 2020 NXP
- */
+#include <linux/clk.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/of_graph.h> +#include <linux/phy/phy.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h>
+#include <drm/bridge/imx_ldb_helper.h> +#include <drm/drm_atomic_state_helper.h> +#include <drm/drm_bridge.h> +#include <drm/drm_connector.h> +#include <drm/drm_fourcc.h> +#include <drm/drm_of.h> +#include <drm/drm_print.h>
+#define LDB_CH_SEL (1 << 28)
+#define SS_CTRL 0x20 +#define CH_HSYNC_M(id) BIT(0 + ((id) * 2)) +#define CH_VSYNC_M(id) BIT(1 + ((id) * 2)) +#define CH_PHSYNC(id) BIT(0 + ((id) * 2)) +#define CH_PVSYNC(id) BIT(1 + ((id) * 2))
+#define DRIVER_NAME "imx8qxp-ldb"
+struct imx8qxp_ldb_channel {
- struct ldb_channel base;
- struct phy *phy;
- unsigned int di_id;
+};
+struct imx8qxp_ldb {
- struct ldb base;
- struct device *dev;
- struct imx8qxp_ldb_channel channel[MAX_LDB_CHAN_NUM];
- struct clk *clk_pixel;
- struct clk *clk_bypass;
- struct drm_bridge *companion;
- int active_chno;
+};
+static inline struct imx8qxp_ldb_channel * +base_to_imx8qxp_ldb_channel(struct ldb_channel *base) +{
- return container_of(base, struct imx8qxp_ldb_channel, base);
+}
+static inline struct imx8qxp_ldb *base_to_imx8qxp_ldb(struct ldb *base) +{
- return container_of(base, struct imx8qxp_ldb, base);
+}
+static void imx8qxp_ldb_set_phy_cfg(struct imx8qxp_ldb *imx8qxp_ldb,
unsigned long di_clk, bool is_split,struct phy_configure_opts_lvds *phy_cfg)+{
- phy_cfg->bits_per_lane_and_dclk_cycle = 7;
- phy_cfg->lanes = 4;
- if (is_split) {
phy_cfg->differential_clk_rate = di_clk / 2;phy_cfg->is_slave = !imx8qxp_ldb->companion;- } else {
phy_cfg->differential_clk_rate = di_clk;phy_cfg->is_slave = false;- }
+}
+static int imx8qxp_ldb_bridge_atomic_check(struct drm_bridge *bridge,
struct drm_bridge_state *bridge_state,struct drm_crtc_state *crtc_state,struct drm_connector_state *conn_state)+{
- struct ldb_channel *ldb_ch = bridge->driver_private;
- struct ldb *ldb = ldb_ch->ldb;
- struct imx8qxp_ldb_channel *imx8qxp_ldb_ch =
base_to_imx8qxp_ldb_channel(ldb_ch);- struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb);
- struct drm_bridge *companion = imx8qxp_ldb->companion;
- struct drm_display_mode *adj = &crtc_state->adjusted_mode;
- unsigned long di_clk = adj->clock * 1000;
- bool is_split = ldb_channel_is_split_link(ldb_ch);
- union phy_configure_opts opts = { };
- struct phy_configure_opts_lvds *phy_cfg = &opts.lvds;
- int ret;
- ret = ldb_bridge_atomic_check_helper(bridge, bridge_state,
crtc_state, conn_state);- if (ret)
return ret;- imx8qxp_ldb_set_phy_cfg(imx8qxp_ldb, di_clk, is_split, phy_cfg);
- ret = phy_validate(imx8qxp_ldb_ch->phy, PHY_MODE_LVDS, 0, &opts);
- if (ret < 0) {
DRM_DEV_DEBUG_DRIVER(imx8qxp_ldb->dev,"failed to validate PHY: %d\n", ret);return ret;- }
- if (is_split && companion) {
ret = companion->funcs->atomic_check(companion,bridge_state, crtc_state, conn_state);if (ret)return ret;- }
- return ret;
+}
+static void +imx8qxp_ldb_bridge_mode_set(struct drm_bridge *bridge,
const struct drm_display_mode *mode,const struct drm_display_mode *adjusted_mode)+{
- struct ldb_channel *ldb_ch = bridge->driver_private;
- struct ldb_channel *companion_ldb_ch;
- struct ldb *ldb = ldb_ch->ldb;
- struct imx8qxp_ldb_channel *imx8qxp_ldb_ch =
base_to_imx8qxp_ldb_channel(ldb_ch);- struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb);
- struct drm_bridge *companion = imx8qxp_ldb->companion;
- struct device *dev = imx8qxp_ldb->dev;
- unsigned long di_clk = adjusted_mode->clock * 1000;
- bool is_split = ldb_channel_is_split_link(ldb_ch);
- union phy_configure_opts opts = { };
- struct phy_configure_opts_lvds *phy_cfg = &opts.lvds;
- u32 chno = ldb_ch->chno;
- int ret;
- ret = pm_runtime_get_sync(dev);
- if (ret < 0)
DRM_DEV_ERROR(dev, "failed to get runtime PM sync: %d\n", ret);- ret = phy_init(imx8qxp_ldb_ch->phy);
- if (ret < 0)
DRM_DEV_ERROR(dev, "failed to initialize PHY: %d\n", ret);- ret = phy_set_mode(imx8qxp_ldb_ch->phy, PHY_MODE_LVDS);
- if (ret < 0)
DRM_DEV_ERROR(dev, "failed to set PHY mode: %d\n", ret);- if (is_split && companion) {
companion_ldb_ch = bridge_to_ldb_ch(companion);companion_ldb_ch->in_bus_format = ldb_ch->in_bus_format;companion_ldb_ch->out_bus_format = ldb_ch->out_bus_format;- }
- clk_set_rate(imx8qxp_ldb->clk_bypass, di_clk);
- clk_set_rate(imx8qxp_ldb->clk_pixel, di_clk);
- imx8qxp_ldb_set_phy_cfg(imx8qxp_ldb, di_clk, is_split, phy_cfg);
- ret = phy_configure(imx8qxp_ldb_ch->phy, &opts);
- if (ret < 0)
DRM_DEV_ERROR(dev, "failed to configure PHY: %d\n", ret);- if (chno == 0)
ldb->ldb_ctrl &= ~LDB_CH_SEL;- else
ldb->ldb_ctrl |= LDB_CH_SEL;- /* input VSYNC signal from pixel link is active low */
- if (imx8qxp_ldb_ch->di_id == 0)
ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW;- else
ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW;- /*
* For split mode, settle input VSYNC signal polarity and* channel selection down early.*/- if (is_split)
regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl);- ldb_bridge_mode_set_helper(bridge, mode, adjusted_mode);
- if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
regmap_update_bits(ldb->regmap, SS_CTRL, CH_VSYNC_M(chno), 0);- else if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
regmap_update_bits(ldb->regmap, SS_CTRL,CH_VSYNC_M(chno), CH_PVSYNC(chno));- if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
regmap_update_bits(ldb->regmap, SS_CTRL, CH_HSYNC_M(chno), 0);- else if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
regmap_update_bits(ldb->regmap, SS_CTRL,CH_HSYNC_M(chno), CH_PHSYNC(chno));- if (is_split && companion)
companion->funcs->mode_set(companion, mode, adjusted_mode);+}
+static void +imx8qxp_ldb_bridge_atomic_pre_enable(struct drm_bridge *bridge,
struct drm_bridge_state *old_bridge_state)+{
- struct ldb_channel *ldb_ch = bridge->driver_private;
- struct ldb *ldb = ldb_ch->ldb;
- struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb);
- struct drm_bridge *companion = imx8qxp_ldb->companion;
- bool is_split = ldb_channel_is_split_link(ldb_ch);
- clk_prepare_enable(imx8qxp_ldb->clk_pixel);
- clk_prepare_enable(imx8qxp_ldb->clk_bypass);
- if (is_split && companion)
companion->funcs->atomic_pre_enable(companion, old_bridge_state);+}
+static void +imx8qxp_ldb_bridge_atomic_enable(struct drm_bridge *bridge,
struct drm_bridge_state *old_bridge_state)+{
- struct ldb_channel *ldb_ch = bridge->driver_private;
- struct ldb *ldb = ldb_ch->ldb;
- struct imx8qxp_ldb_channel *imx8qxp_ldb_ch =
base_to_imx8qxp_ldb_channel(ldb_ch);- struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb);
- struct drm_bridge *companion = imx8qxp_ldb->companion;
- struct device *dev = imx8qxp_ldb->dev;
- bool is_split = ldb_channel_is_split_link(ldb_ch);
- int ret;
- if (ldb_ch->chno == 0 || is_split) {
ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;ldb->ldb_ctrl |= imx8qxp_ldb_ch->di_id == 0 ?LDB_CH0_MODE_EN_TO_DI0 : LDB_CH0_MODE_EN_TO_DI1;- }
- if (ldb_ch->chno == 1 || is_split) {
ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;ldb->ldb_ctrl |= imx8qxp_ldb_ch->di_id == 0 ?LDB_CH1_MODE_EN_TO_DI0 : LDB_CH1_MODE_EN_TO_DI1;- }
- ldb_bridge_enable_helper(bridge);
- ret = phy_power_on(imx8qxp_ldb_ch->phy);
- if (ret)
DRM_DEV_ERROR(dev, "failed to power on PHY: %d\n", ret);- if (is_split && companion)
companion->funcs->atomic_enable(companion, old_bridge_state);+}
+static void +imx8qxp_ldb_bridge_atomic_disable(struct drm_bridge *bridge,
struct drm_bridge_state *old_bridge_state)+{
- struct ldb_channel *ldb_ch = bridge->driver_private;
- struct ldb *ldb = ldb_ch->ldb;
- struct imx8qxp_ldb_channel *imx8qxp_ldb_ch =
base_to_imx8qxp_ldb_channel(ldb_ch);- struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb);
- struct drm_bridge *companion = imx8qxp_ldb->companion;
- struct device *dev = imx8qxp_ldb->dev;
- bool is_split = ldb_channel_is_split_link(ldb_ch);
- int ret;
- ret = phy_power_off(imx8qxp_ldb_ch->phy);
- if (ret)
DRM_DEV_ERROR(dev, "failed to power off PHY: %d\n", ret);- ret = phy_exit(imx8qxp_ldb_ch->phy);
- if (ret < 0)
DRM_DEV_ERROR(dev, "failed to teardown PHY: %d\n", ret);- ldb_bridge_disable_helper(bridge);
- clk_disable_unprepare(imx8qxp_ldb->clk_bypass);
- clk_disable_unprepare(imx8qxp_ldb->clk_pixel);
- if (is_split && companion)
companion->funcs->atomic_disable(companion, old_bridge_state);- ret = pm_runtime_put(dev);
- if (ret < 0)
DRM_DEV_ERROR(dev, "failed to put runtime PM: %d\n", ret);+}
+static const u32 imx8qxp_ldb_bus_output_fmts[] = {
- MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
- MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
- MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
- MEDIA_BUS_FMT_FIXED,
+};
+static bool imx8qxp_ldb_bus_output_fmt_supported(u32 fmt) +{
- int i;
- for (i = 0; i < ARRAY_SIZE(imx8qxp_ldb_bus_output_fmts); i++) {
if (imx8qxp_ldb_bus_output_fmts[i] == fmt)return true;- }
- return false;
+}
+static u32 * +imx8qxp_ldb_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
struct drm_bridge_state *bridge_state,struct drm_crtc_state *crtc_state,struct drm_connector_state *conn_state,u32 output_fmt,unsigned int *num_input_fmts)+{
- struct drm_display_info *di;
- const struct drm_format_info *finfo;
- u32 *input_fmts;
- if (!imx8qxp_ldb_bus_output_fmt_supported(output_fmt))
return NULL;- *num_input_fmts = 1;
- input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
- if (!input_fmts)
return NULL;- switch (output_fmt) {
- case MEDIA_BUS_FMT_FIXED:
di = &conn_state->connector->display_info;/** Look at the first bus format to determine input format.* Default to MEDIA_BUS_FMT_RGB888_1X24, if no match.*/if (di->num_bus_formats) {finfo = drm_format_info(di->bus_formats[0]);input_fmts[0] = finfo->depth == 18 ?MEDIA_BUS_FMT_RGB666_1X24_CPADHI :MEDIA_BUS_FMT_RGB888_1X24;} else {input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;}break;- case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X24_CPADHI;break;- case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
- case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;break;- default:
kfree(input_fmts);input_fmts = NULL;break;- }
- return input_fmts;
+}
+static u32 * +imx8qxp_ldb_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
struct drm_bridge_state *bridge_state,struct drm_crtc_state *crtc_state,struct drm_connector_state *conn_state,unsigned int *num_output_fmts)+{
- *num_output_fmts = ARRAY_SIZE(imx8qxp_ldb_bus_output_fmts);
- return kmemdup(imx8qxp_ldb_bus_output_fmts,
sizeof(imx8qxp_ldb_bus_output_fmts), GFP_KERNEL);+}
+static enum drm_mode_status +imx8qxp_ldb_bridge_mode_valid(struct drm_bridge *bridge,
const struct drm_display_info *info,const struct drm_display_mode *mode)+{
- struct ldb_channel *ldb_ch = bridge->driver_private;
- bool is_single = ldb_channel_is_single_link(ldb_ch);
- if (mode->clock > 170000)
return MODE_CLOCK_HIGH;- if (mode->clock > 150000 && is_single)
return MODE_CLOCK_HIGH;- return MODE_OK;
+}
+static const struct drm_bridge_funcs imx8qxp_ldb_bridge_funcs = {
- .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
- .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
- .atomic_reset = drm_atomic_helper_bridge_reset,
- .mode_valid = imx8qxp_ldb_bridge_mode_valid,
- .attach = ldb_bridge_attach_helper,
- .atomic_check = imx8qxp_ldb_bridge_atomic_check,
- .mode_set = imx8qxp_ldb_bridge_mode_set,
- .atomic_pre_enable = imx8qxp_ldb_bridge_atomic_pre_enable,
- .atomic_enable = imx8qxp_ldb_bridge_atomic_enable,
- .atomic_disable = imx8qxp_ldb_bridge_atomic_disable,
- .atomic_get_input_bus_fmts =
imx8qxp_ldb_bridge_atomic_get_input_bus_fmts,- .atomic_get_output_bus_fmts =
imx8qxp_ldb_bridge_atomic_get_output_bus_fmts,+};
+static int imx8qxp_ldb_set_di_id(struct imx8qxp_ldb *imx8qxp_ldb) +{
- struct imx8qxp_ldb_channel *imx8qxp_ldb_ch =
&imx8qxp_ldb->channel[imx8qxp_ldb->active_chno];- struct ldb_channel *ldb_ch = &imx8qxp_ldb_ch->base;
- struct device_node *remote, *port, *ep = NULL;
- struct device *dev = imx8qxp_ldb->dev;
- struct of_endpoint endpoint;
- int ep_cnt;
- int ret;
- /* remote is PXL2DPI */
- remote = of_graph_get_remote_node(ldb_ch->np, 0, 0);
- if (!remote) {
DRM_DEV_ERROR(dev, "failed to get PXL2DPI node\n");return -ENODEV;- }
- port = of_graph_get_port_by_id(remote, 0);
- if (!port) {
DRM_DEV_ERROR(dev, "failed to get PXL2DPI node's port@0\n");ret = -ENODEV;goto out;- }
- ep_cnt = of_get_available_child_count(port);
- if (ep_cnt == 0) {
DRM_DEV_ERROR(dev,"no available endpoints of PXL2DPI node's port@0\n");ret = -ENODEV;goto out;- } else if (ep_cnt > 1) {
DRM_DEV_ERROR(dev,"invalid available endpoints of PXL2DPI node's port@0\n");ret = -ENOTSUPP;goto out;- }
- ep = of_get_next_available_child(port, NULL);
- if (!ep) {
DRM_DEV_ERROR(dev,"failed to get available endpoint of PXL2DPI node's port@0\n");ret = -ENODEV;goto out;- }
This function is not well written. I'll rewrite it in the next version by using of_graph_get_endpoint_by_regs() and of_graph_get_remote_endpoint() to get the remote endpoint.
Liu Ying
- ret = of_graph_parse_endpoint(ep, &endpoint);
- if (ret) {
DRM_DEV_ERROR(dev,"failed to parse endpoint of PXL2DPI node's port@0: %d\n",ret);goto out;- }
- imx8qxp_ldb_ch->di_id = endpoint.id;
+out:
- of_node_put(ep);
- of_node_put(port);
- of_node_put(remote);
- return ret;
+}
+static int +imx8qxp_ldb_check_chno_and_dual_link(struct ldb_channel *ldb_ch, int link) +{
- if ((link == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS && ldb_ch->chno != 0) ||
(link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS && ldb_ch->chno != 1))return -EINVAL;- return 0;
+}
+static int imx8qxp_ldb_parse_dt_companion(struct imx8qxp_ldb *imx8qxp_ldb) +{
- struct imx8qxp_ldb_channel *imx8qxp_ldb_ch =
&imx8qxp_ldb->channel[imx8qxp_ldb->active_chno];- struct ldb_channel *ldb_ch = &imx8qxp_ldb_ch->base;
- struct ldb_channel *companion_ldb_ch;
- struct device_node *companion;
- struct device_node *child;
- struct device_node *companion_port = NULL;
- struct device_node *port1, *port2;
- struct device *dev = imx8qxp_ldb->dev;
- const struct of_device_id *match;
- u32 i;
- int ch_cnt;
- int dual_link;
- int ret;
- /* Locate the companion LDB for dual-link operation, if any. */
- companion = of_parse_phandle(dev->of_node, "fsl,companion-ldb", 0);
- if (!companion)
return 0;- if (!of_device_is_available(companion)) {
DRM_DEV_ERROR(dev, "companion LDB is not available\n");ret = -ENODEV;goto out;- }
- /*
* Sanity check: the companion bridge must have the same compatible* string.*/- match = of_match_device(dev->driver->of_match_table, dev);
- if (!of_device_is_compatible(companion, match->compatible)) {
DRM_DEV_ERROR(dev, "companion LDB is incompatible\n");ret = -ENXIO;goto out;- }
- ch_cnt = of_get_available_child_count(companion);
- if (ch_cnt == 0) {
DRM_DEV_ERROR(dev, "no available companion LDB channel\n");ret = -ENODEV;goto out;- } else if (ch_cnt > 1) {
DRM_DEV_ERROR(dev, "invalid available companion LDB channels\n");ret = -ENOTSUPP;goto out;- }
- for_each_available_child_of_node(companion, child) {
ret = of_property_read_u32(child, "reg", &i);if (ret || i > MAX_LDB_CHAN_NUM - 1) {DRM_DEV_ERROR(dev,"invalid channel node address: %u\n", i);ret = -EINVAL;of_node_put(child);goto out;}companion_port = child;of_node_put(child);break;- }
- if (companion_port == NULL) {
DRM_DEV_ERROR(dev,"failed to find companion LDB channel port\n");ret = -EINVAL;goto out;- }
- /*
* Channel numbers have to be different, because channel0 transmits* odd pixels and channel1 transmits even pixels.*/- if (i == ldb_ch->chno) {
DRM_DEV_ERROR(dev, "invalid companion LDB channel number\n");ret = -EINVAL;goto out;- }
- /*
* We need to work out if the sink is expecting us to function in* dual-link mode. We do this by looking at the DT port nodes we are* connected to. If they are marked as expecting odd pixels and* even pixels than we need to enable LDB split mode.*/- port1 = of_graph_get_port_by_id(ldb_ch->np, 1);
- port2 = of_graph_get_port_by_id(companion_port, 1);
- dual_link = drm_of_lvds_get_dual_link_pixel_order(port1, port2);
- of_node_put(port1);
- of_node_put(port2);
- switch (dual_link) {
- case DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS:
ldb_ch->link_type = LDB_CH_DUAL_LINK_ODD_EVEN_PIXELS;break;- case DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS:
ldb_ch->link_type = LDB_CH_DUAL_LINK_EVEN_ODD_PIXELS;break;- default:
ret = dual_link;DRM_DEV_ERROR(dev,"failed to get dual link pixel order: %d\n", ret);goto out;- }
- ret = imx8qxp_ldb_check_chno_and_dual_link(ldb_ch, dual_link);
- if (ret < 0) {
DRM_DEV_ERROR(dev,"unmatched channel number(%u) vs dual link(%d)\n",ldb_ch->chno, dual_link);goto out;- }
- imx8qxp_ldb->companion = of_drm_find_bridge(companion_port);
- if (!imx8qxp_ldb->companion) {
ret = -EPROBE_DEFER;DRM_DEV_DEBUG_DRIVER(dev,"failed to find bridge for companion bridge: %d\n", ret);goto out;- }
- DRM_DEV_DEBUG_DRIVER(dev,
"dual-link configuration detected (companion bridge %pOF)\n",companion);- companion_ldb_ch = bridge_to_ldb_ch(imx8qxp_ldb->companion);
- companion_ldb_ch->link_type = ldb_ch->link_type;
+out:
- of_node_put(companion);
- return ret;
+}
+static int imx8qxp_ldb_probe(struct platform_device *pdev) +{
- struct device *dev = &pdev->dev;
- struct imx8qxp_ldb *imx8qxp_ldb;
- struct imx8qxp_ldb_channel *imx8qxp_ldb_ch;
- struct ldb *ldb;
- struct ldb_channel *ldb_ch;
- int ret, i;
- imx8qxp_ldb = devm_kzalloc(dev, sizeof(*imx8qxp_ldb), GFP_KERNEL);
- if (!imx8qxp_ldb)
return -ENOMEM;- imx8qxp_ldb->clk_pixel = devm_clk_get(dev, "pixel");
- if (IS_ERR(imx8qxp_ldb->clk_pixel)) {
ret = PTR_ERR(imx8qxp_ldb->clk_pixel);if (ret != -EPROBE_DEFER)DRM_DEV_ERROR(dev,"failed to get pixel clock: %d\n", ret);return ret;- }
- imx8qxp_ldb->clk_bypass = devm_clk_get(dev, "bypass");
- if (IS_ERR(imx8qxp_ldb->clk_bypass)) {
ret = PTR_ERR(imx8qxp_ldb->clk_bypass);if (ret != -EPROBE_DEFER)DRM_DEV_ERROR(dev,"failed to get bypass clock: %d\n", ret);return ret;- }
- imx8qxp_ldb->dev = dev;
- ldb = &imx8qxp_ldb->base;
- ldb->dev = dev;
- ldb->ctrl_reg = 0xe0;
- for (i = 0; i < MAX_LDB_CHAN_NUM; i++)
ldb->channel[i] = &imx8qxp_ldb->channel[i].base;- ret = ldb_init_helper(ldb);
- if (ret)
return ret;- if (ldb->available_ch_cnt == 0) {
DRM_DEV_DEBUG_DRIVER(dev, "no available channel\n");return 0;- } else if (ldb->available_ch_cnt > 1) {
DRM_DEV_ERROR(dev, "invalid available channel number(%u)\n",ldb->available_ch_cnt);return -ENOTSUPP;- }
- for (i = 0; i < MAX_LDB_CHAN_NUM; i++) {
imx8qxp_ldb_ch = &imx8qxp_ldb->channel[i];ldb_ch = &imx8qxp_ldb_ch->base;if (ldb_ch->is_available) {imx8qxp_ldb->active_chno = ldb_ch->chno;break;}- }
- imx8qxp_ldb_ch->phy = devm_of_phy_get(dev, ldb_ch->np, "lvds_phy");
- if (IS_ERR(imx8qxp_ldb_ch->phy)) {
ret = PTR_ERR(imx8qxp_ldb_ch->phy);if (ret != -EPROBE_DEFER)DRM_DEV_ERROR(dev, "failed to get channel%d PHY: %d\n",imx8qxp_ldb->active_chno, ret);return ret;- }
- ret = ldb_find_next_bridge_helper(ldb);
- if (ret)
return ret;- ret = imx8qxp_ldb_set_di_id(imx8qxp_ldb);
- if (ret)
return ret;- ret = imx8qxp_ldb_parse_dt_companion(imx8qxp_ldb);
- if (ret)
return ret;- platform_set_drvdata(pdev, imx8qxp_ldb);
- pm_runtime_enable(dev);
- ldb_add_bridge_helper(ldb, &imx8qxp_ldb_bridge_funcs);
- return ret;
+}
+static int imx8qxp_ldb_remove(struct platform_device *pdev) +{
- struct imx8qxp_ldb *imx8qxp_ldb = platform_get_drvdata(pdev);
- struct ldb *ldb = &imx8qxp_ldb->base;
- ldb_remove_bridge_helper(ldb);
- pm_runtime_disable(&pdev->dev);
- return 0;
+}
+static int __maybe_unused imx8qxp_ldb_runtime_suspend(struct device *dev) +{
- return 0;
+}
+static int __maybe_unused imx8qxp_ldb_runtime_resume(struct device *dev) +{
- struct imx8qxp_ldb *imx8qxp_ldb = dev_get_drvdata(dev);
- struct ldb *ldb = &imx8qxp_ldb->base;
- /* disable LDB by resetting the control register to POR default */
- regmap_write(ldb->regmap, ldb->ctrl_reg, 0);
- return 0;
+}
+static const struct dev_pm_ops imx8qxp_ldb_pm_ops = {
- SET_RUNTIME_PM_OPS(imx8qxp_ldb_runtime_suspend,
imx8qxp_ldb_runtime_resume, NULL)+};
+static const struct of_device_id imx8qxp_ldb_dt_ids[] = {
- { .compatible = "fsl,imx8qxp-ldb" },
- { /* sentinel */ }
+}; +MODULE_DEVICE_TABLE(of, imx8qxp_ldb_dt_ids);
+static struct platform_driver imx8qxp_ldb_driver = {
- .probe = imx8qxp_ldb_probe,
- .remove = imx8qxp_ldb_remove,
- .driver = {
.pm = &imx8qxp_ldb_pm_ops,.name = DRIVER_NAME,.of_match_table = imx8qxp_ldb_dt_ids,- },
+}; +module_platform_driver(imx8qxp_ldb_driver);
+MODULE_DESCRIPTION("i.MX8QXP LVDS Display Bridge(LDB) bridge driver"); +MODULE_AUTHOR("Liu Ying victor.liu@nxp.com"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRIVER_NAME);
This patch adds a drm bridge driver for i.MX8qm LVDS display bridge(LDB). The LDB has two channels. Each of them supports up to 30bpp parallel input color format and can map the input to VESA or JEIDA standards. The two channels can be used simultaneously, either in dual mode or split mode. In dual mode, the two channels output identical data. In split mode, channel0 outputs odd pixels and channel1 outputs even pixels. This patch supports the LDB single mode and split mode.
Signed-off-by: Liu Ying victor.liu@nxp.com --- drivers/gpu/drm/bridge/imx/Kconfig | 10 + drivers/gpu/drm/bridge/imx/Makefile | 1 + drivers/gpu/drm/bridge/imx/imx8qm-ldb.c | 589 ++++++++++++++++++++++++++++++++ 3 files changed, 600 insertions(+) create mode 100644 drivers/gpu/drm/bridge/imx/imx8qm-ldb.c
diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig index 2a32ad3..46981f3 100644 --- a/drivers/gpu/drm/bridge/imx/Kconfig +++ b/drivers/gpu/drm/bridge/imx/Kconfig @@ -6,6 +6,16 @@ config DRM_IMX_LVDS_BRIDGE_HELPER Helper to support Freescale i.MX LVDS Display Bridge(LDB). This bridge is embedded in a SoC.
+config DRM_IMX8QM_LDB + tristate "Freescale i.MX8QM LVDS display bridge" + depends on DRM_IMX_LVDS_BRIDGE_HELPER + depends on OF + depends on COMMON_CLK + select DRM_KMS_HELPER + help + Choose this to enable the internal LVDS Display Bridge(LDB) found in + Freescale i.MX8qm processor. + config DRM_IMX8QXP_LDB tristate "Freescale i.MX8QXP LVDS display bridge" depends on DRM_IMX_LVDS_BRIDGE_HELPER diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile index 13160f0..a964efc 100644 --- a/drivers/gpu/drm/bridge/imx/Makefile +++ b/drivers/gpu/drm/bridge/imx/Makefile @@ -1,4 +1,5 @@ obj-$(CONFIG_DRM_IMX_LVDS_BRIDGE_HELPER) += imx-ldb-helper.o +obj-$(CONFIG_DRM_IMX8QM_LDB) += imx8qm-ldb.o obj-$(CONFIG_DRM_IMX8QXP_LDB) += imx8qxp-ldb.o obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o diff --git a/drivers/gpu/drm/bridge/imx/imx8qm-ldb.c b/drivers/gpu/drm/bridge/imx/imx8qm-ldb.c new file mode 100644 index 00000000..9860320 --- /dev/null +++ b/drivers/gpu/drm/bridge/imx/imx8qm-ldb.c @@ -0,0 +1,589 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include <linux/clk.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/of_graph.h> +#include <linux/phy/phy.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h> + +#include <drm/bridge/imx_ldb_helper.h> +#include <drm/drm_atomic_state_helper.h> +#include <drm/drm_bridge.h> +#include <drm/drm_connector.h> +#include <drm/drm_fourcc.h> +#include <drm/drm_of.h> +#include <drm/drm_print.h> + +#define LDB_CH0_10BIT_EN (1 << 22) +#define LDB_CH1_10BIT_EN (1 << 23) +#define LDB_CH0_DATA_WIDTH_24BIT (1 << 24) +#define LDB_CH1_DATA_WIDTH_24BIT (1 << 26) +#define LDB_CH0_DATA_WIDTH_30BIT (2 << 24) +#define LDB_CH1_DATA_WIDTH_30BIT (2 << 26) + +#define SS_CTRL 0x20 +#define CH_HSYNC_M(id) BIT(0 + ((id) * 2)) +#define CH_VSYNC_M(id) BIT(1 + ((id) * 2)) +#define CH_PHSYNC(id) BIT(0 + ((id) * 2)) +#define CH_PVSYNC(id) BIT(1 + ((id) * 2)) + +#define DRIVER_NAME "imx8qm-ldb" + +struct imx8qm_ldb_channel { + struct ldb_channel base; + struct phy *phy; +}; + +struct imx8qm_ldb { + struct ldb base; + struct device *dev; + struct imx8qm_ldb_channel channel[MAX_LDB_CHAN_NUM]; + struct clk *clk_pixel; + struct clk *clk_bypass; + int active_chno; +}; + +static inline struct imx8qm_ldb_channel * +base_to_imx8qm_ldb_channel(struct ldb_channel *base) +{ + return container_of(base, struct imx8qm_ldb_channel, base); +} + +static inline struct imx8qm_ldb *base_to_imx8qm_ldb(struct ldb *base) +{ + return container_of(base, struct imx8qm_ldb, base); +} + +static void imx8qm_ldb_set_phy_cfg(struct imx8qm_ldb *imx8qm_ldb, + unsigned long di_clk, + bool is_split, bool is_slave, + struct phy_configure_opts_lvds *phy_cfg) +{ + phy_cfg->bits_per_lane_and_dclk_cycle = 7; + phy_cfg->lanes = 4; + phy_cfg->differential_clk_rate = is_split ? di_clk / 2 : di_clk; + phy_cfg->is_slave = is_slave; +} + +static int imx8qm_ldb_bridge_atomic_check(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + struct ldb *ldb = ldb_ch->ldb; + struct imx8qm_ldb_channel *imx8qm_ldb_ch = + base_to_imx8qm_ldb_channel(ldb_ch); + struct imx8qm_ldb *imx8qm_ldb = base_to_imx8qm_ldb(ldb); + struct drm_display_mode *adj = &crtc_state->adjusted_mode; + unsigned long di_clk = adj->clock * 1000; + bool is_split = ldb_channel_is_split_link(ldb_ch); + union phy_configure_opts opts = { }; + struct phy_configure_opts_lvds *phy_cfg = &opts.lvds; + int ret; + + ret = ldb_bridge_atomic_check_helper(bridge, bridge_state, + crtc_state, conn_state); + if (ret) + return ret; + + imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, false, phy_cfg); + ret = phy_validate(imx8qm_ldb_ch->phy, PHY_MODE_LVDS, 0, &opts); + if (ret < 0) { + DRM_DEV_DEBUG_DRIVER(imx8qm_ldb->dev, + "failed to validate PHY: %d\n", ret); + return ret; + } + + if (is_split) { + imx8qm_ldb_ch = + &imx8qm_ldb->channel[imx8qm_ldb->active_chno ^ 1]; + imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, true, + phy_cfg); + ret = phy_validate(imx8qm_ldb_ch->phy, PHY_MODE_LVDS, 0, &opts); + if (ret < 0) { + DRM_DEV_DEBUG_DRIVER(imx8qm_ldb->dev, + "failed to validate slave PHY: %d\n", ret); + return ret; + } + } + + return ret; +} + +static void +imx8qm_ldb_bridge_mode_set(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + const struct drm_display_mode *adjusted_mode) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + struct ldb *ldb = ldb_ch->ldb; + struct imx8qm_ldb_channel *imx8qm_ldb_ch = + base_to_imx8qm_ldb_channel(ldb_ch); + struct imx8qm_ldb *imx8qm_ldb = base_to_imx8qm_ldb(ldb); + struct device *dev = imx8qm_ldb->dev; + unsigned long di_clk = adjusted_mode->clock * 1000; + bool is_split = ldb_channel_is_split_link(ldb_ch); + union phy_configure_opts opts = { }; + struct phy_configure_opts_lvds *phy_cfg = &opts.lvds; + u32 chno = ldb_ch->chno; + int ret; + + ret = pm_runtime_get_sync(dev); + if (ret < 0) + DRM_DEV_ERROR(dev, "failed to get runtime PM sync: %d\n", ret); + + ret = phy_init(imx8qm_ldb_ch->phy); + if (ret < 0) + DRM_DEV_ERROR(dev, "failed to initialize PHY: %d\n", ret); + + clk_set_rate(imx8qm_ldb->clk_bypass, di_clk); + clk_set_rate(imx8qm_ldb->clk_pixel, di_clk); + + imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, false, phy_cfg); + ret = phy_configure(imx8qm_ldb_ch->phy, &opts); + if (ret < 0) + DRM_DEV_ERROR(dev, "failed to configure PHY: %d\n", ret); + + if (is_split) { + imx8qm_ldb_ch = + &imx8qm_ldb->channel[imx8qm_ldb->active_chno ^ 1]; + imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, true, + phy_cfg); + ret = phy_configure(imx8qm_ldb_ch->phy, &opts); + if (ret < 0) + DRM_DEV_ERROR(dev, "failed to configure slave PHY: %d\n", + ret); + } + + /* input VSYNC signal from pixel link is active low */ + if (ldb_ch->chno == 0 || is_split) + ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW; + if (ldb_ch->chno == 1 || is_split) + ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW; + + switch (ldb_ch->out_bus_format) { + case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: + break; + case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: + case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: + if (ldb_ch->chno == 0 || is_split) + ldb->ldb_ctrl |= LDB_CH0_DATA_WIDTH_24BIT; + if (ldb_ch->chno == 1 || is_split) + ldb->ldb_ctrl |= LDB_CH1_DATA_WIDTH_24BIT; + break; + } + + ldb_bridge_mode_set_helper(bridge, mode, adjusted_mode); + + if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) + regmap_update_bits(ldb->regmap, SS_CTRL, CH_VSYNC_M(chno), 0); + else if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) + regmap_update_bits(ldb->regmap, SS_CTRL, + CH_VSYNC_M(chno), CH_PVSYNC(chno)); + + if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) + regmap_update_bits(ldb->regmap, SS_CTRL, CH_HSYNC_M(chno), 0); + else if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) + regmap_update_bits(ldb->regmap, SS_CTRL, + CH_HSYNC_M(chno), CH_PHSYNC(chno)); +} + +static void +imx8qm_ldb_bridge_atomic_enable(struct drm_bridge *bridge, + struct drm_bridge_state *old_bridge_state) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + struct ldb *ldb = ldb_ch->ldb; + struct imx8qm_ldb_channel *imx8qm_ldb_ch = + base_to_imx8qm_ldb_channel(ldb_ch); + struct imx8qm_ldb *imx8qm_ldb = base_to_imx8qm_ldb(ldb); + struct device *dev = imx8qm_ldb->dev; + bool is_split = ldb_channel_is_split_link(ldb_ch); + int ret; + + clk_prepare_enable(imx8qm_ldb->clk_pixel); + clk_prepare_enable(imx8qm_ldb->clk_bypass); + + /* both DI0 and DI1 connect with pixel link, so ok to use DI0 only */ + if (ldb_ch->chno == 0 || is_split) { + ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK; + ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0; + } + if (ldb_ch->chno == 1 || is_split) { + ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK; + ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0; + } + + if (is_split) { + ret = phy_power_on(imx8qm_ldb->channel[0].phy); + if (ret) + DRM_DEV_ERROR(dev, + "failed to power on channel0 PHY: %d\n", + ret); + + ret = phy_power_on(imx8qm_ldb->channel[1].phy); + if (ret) + DRM_DEV_ERROR(dev, + "failed to power on channel1 PHY: %d\n", + ret); + } else { + ret = phy_power_on(imx8qm_ldb_ch->phy); + if (ret) + DRM_DEV_ERROR(dev, "failed to power on PHY: %d\n", ret); + } + + ldb_bridge_enable_helper(bridge); +} + +static void +imx8qm_ldb_bridge_atomic_disable(struct drm_bridge *bridge, + struct drm_bridge_state *old_bridge_state) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + struct ldb *ldb = ldb_ch->ldb; + struct imx8qm_ldb_channel *imx8qm_ldb_ch = + base_to_imx8qm_ldb_channel(ldb_ch); + struct imx8qm_ldb *imx8qm_ldb = base_to_imx8qm_ldb(ldb); + struct device *dev = imx8qm_ldb->dev; + bool is_split = ldb_channel_is_split_link(ldb_ch); + int ret; + + ldb_bridge_disable_helper(bridge); + + if (is_split) { + ret = phy_power_off(imx8qm_ldb->channel[0].phy); + if (ret) + DRM_DEV_ERROR(dev, + "failed to power off channel0 PHY: %d\n", + ret); + ret = phy_power_off(imx8qm_ldb->channel[1].phy); + if (ret) + DRM_DEV_ERROR(dev, + "failed to power off channel1 PHY: %d\n", + ret); + } else { + ret = phy_power_off(imx8qm_ldb_ch->phy); + if (ret) + DRM_DEV_ERROR(dev, "failed to power off PHY: %d\n", ret); + } + + clk_disable_unprepare(imx8qm_ldb->clk_bypass); + clk_disable_unprepare(imx8qm_ldb->clk_pixel); + + ret = pm_runtime_put(dev); + if (ret < 0) + DRM_DEV_ERROR(dev, "failed to put runtime PM: %d\n", ret); +} + +static const u32 imx8qm_ldb_bus_output_fmts[] = { + MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, + MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, + MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, + MEDIA_BUS_FMT_FIXED, +}; + +static bool imx8qm_ldb_bus_output_fmt_supported(u32 fmt) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(imx8qm_ldb_bus_output_fmts); i++) { + if (imx8qm_ldb_bus_output_fmts[i] == fmt) + return true; + } + + return false; +} + +static u32 * +imx8qm_ldb_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + u32 output_fmt, + unsigned int *num_input_fmts) +{ + struct drm_display_info *di; + const struct drm_format_info *finfo; + u32 *input_fmts; + + if (!imx8qm_ldb_bus_output_fmt_supported(output_fmt)) + return NULL; + + *num_input_fmts = 1; + + input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL); + if (!input_fmts) + return NULL; + + switch (output_fmt) { + case MEDIA_BUS_FMT_FIXED: + di = &conn_state->connector->display_info; + + /* + * Look at the first bus format to determine input format. + * Default to MEDIA_BUS_FMT_RGB888_1X36_CPADLO, if no match. + */ + if (di->num_bus_formats) { + finfo = drm_format_info(di->bus_formats[0]); + + input_fmts[0] = finfo->depth == 18 ? + MEDIA_BUS_FMT_RGB666_1X36_CPADLO : + MEDIA_BUS_FMT_RGB888_1X36_CPADLO; + } else { + input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X36_CPADLO; + } + break; + case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: + input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X36_CPADLO; + break; + case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: + case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: + input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X36_CPADLO; + break; + default: + kfree(input_fmts); + input_fmts = NULL; + break; + } + + return input_fmts; +} + +static u32 * +imx8qm_ldb_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + unsigned int *num_output_fmts) +{ + *num_output_fmts = ARRAY_SIZE(imx8qm_ldb_bus_output_fmts); + return kmemdup(imx8qm_ldb_bus_output_fmts, + sizeof(imx8qm_ldb_bus_output_fmts), GFP_KERNEL); +} + +static enum drm_mode_status +imx8qm_ldb_bridge_mode_valid(struct drm_bridge *bridge, + const struct drm_display_info *info, + const struct drm_display_mode *mode) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + bool is_single = ldb_channel_is_single_link(ldb_ch); + + if (mode->clock > 300000) + return MODE_CLOCK_HIGH; + + if (mode->clock > 150000 && is_single) + return MODE_CLOCK_HIGH; + + return MODE_OK; +} + +static const struct drm_bridge_funcs imx8qm_ldb_bridge_funcs = { + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, + .atomic_reset = drm_atomic_helper_bridge_reset, + .mode_valid = imx8qm_ldb_bridge_mode_valid, + .attach = ldb_bridge_attach_helper, + .atomic_check = imx8qm_ldb_bridge_atomic_check, + .mode_set = imx8qm_ldb_bridge_mode_set, + .atomic_enable = imx8qm_ldb_bridge_atomic_enable, + .atomic_disable = imx8qm_ldb_bridge_atomic_disable, + .atomic_get_input_bus_fmts = + imx8qm_ldb_bridge_atomic_get_input_bus_fmts, + .atomic_get_output_bus_fmts = + imx8qm_ldb_bridge_atomic_get_output_bus_fmts, +}; + +static int imx8qm_ldb_get_phy(struct imx8qm_ldb *imx8qm_ldb) +{ + struct imx8qm_ldb_channel *imx8qm_ldb_ch; + struct ldb_channel *ldb_ch; + struct device *dev = imx8qm_ldb->dev; + int i, ret; + + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) { + imx8qm_ldb_ch = &imx8qm_ldb->channel[i]; + ldb_ch = &imx8qm_ldb_ch->base; + + if (!ldb_ch->is_available) + continue; + + imx8qm_ldb_ch->phy = devm_of_phy_get(dev, ldb_ch->np, + "lvds_phy"); + if (IS_ERR(imx8qm_ldb_ch->phy)) { + ret = PTR_ERR(imx8qm_ldb_ch->phy); + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(dev, + "failed to get channel%d PHY: %d\n", + i, ret); + return ret; + } + } + + return 0; +} + +static int imx8qm_ldb_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct imx8qm_ldb *imx8qm_ldb; + struct imx8qm_ldb_channel *imx8qm_ldb_ch; + struct ldb *ldb; + struct ldb_channel *ldb_ch; + struct device_node *port1, *port2; + int pixel_order; + int ret, i; + + imx8qm_ldb = devm_kzalloc(dev, sizeof(*imx8qm_ldb), GFP_KERNEL); + if (!imx8qm_ldb) + return -ENOMEM; + + imx8qm_ldb->clk_pixel = devm_clk_get(dev, "pixel"); + if (IS_ERR(imx8qm_ldb->clk_pixel)) { + ret = PTR_ERR(imx8qm_ldb->clk_pixel); + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(dev, + "failed to get pixel clock: %d\n", ret); + return ret; + } + + imx8qm_ldb->clk_bypass = devm_clk_get(dev, "bypass"); + if (IS_ERR(imx8qm_ldb->clk_bypass)) { + ret = PTR_ERR(imx8qm_ldb->clk_bypass); + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(dev, + "failed to get bypass clock: %d\n", ret); + return ret; + } + + imx8qm_ldb->dev = dev; + + ldb = &imx8qm_ldb->base; + ldb->dev = dev; + ldb->ctrl_reg = 0xe0; + + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) + ldb->channel[i] = &imx8qm_ldb->channel[i].base; + + ret = ldb_init_helper(ldb); + if (ret) + return ret; + + if (ldb->available_ch_cnt == 0) { + DRM_DEV_DEBUG_DRIVER(dev, "no available channel\n"); + return 0; + } else if (ldb->available_ch_cnt > 2) { + DRM_DEV_ERROR(dev, "invalid available channel number %d\n", + ldb->available_ch_cnt); + return -ENOTSUPP; + } + + if (ldb->available_ch_cnt == 2) { + port1 = of_graph_get_port_by_id(ldb->channel[0]->np, 1); + port2 = of_graph_get_port_by_id(ldb->channel[1]->np, 1); + pixel_order = + drm_of_lvds_get_dual_link_pixel_order(port1, port2); + of_node_put(port1); + of_node_put(port2); + + if (pixel_order != DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS) { + DRM_DEV_ERROR(dev, "invalid dual link pixel order: %d\n", + pixel_order); + return -EINVAL; + } + + imx8qm_ldb->active_chno = 0; + imx8qm_ldb_ch = &imx8qm_ldb->channel[0]; + ldb_ch = &imx8qm_ldb_ch->base; + ldb_ch->link_type = pixel_order; + } else { + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) { + imx8qm_ldb_ch = &imx8qm_ldb->channel[i]; + ldb_ch = &imx8qm_ldb_ch->base; + + if (ldb_ch->is_available) { + imx8qm_ldb->active_chno = ldb_ch->chno; + break; + } + } + } + + ret = imx8qm_ldb_get_phy(imx8qm_ldb); + if (ret) + return ret; + + ret = ldb_find_next_bridge_helper(ldb); + if (ret) + return ret; + + platform_set_drvdata(pdev, imx8qm_ldb); + pm_runtime_enable(dev); + + ldb_add_bridge_helper(ldb, &imx8qm_ldb_bridge_funcs); + + return ret; +} + +static int imx8qm_ldb_remove(struct platform_device *pdev) +{ + struct imx8qm_ldb *imx8qm_ldb = platform_get_drvdata(pdev); + struct ldb *ldb = &imx8qm_ldb->base; + + ldb_remove_bridge_helper(ldb); + + pm_runtime_disable(&pdev->dev); + + return 0; +} + +static int __maybe_unused imx8qm_ldb_runtime_suspend(struct device *dev) +{ + return 0; +} + +static int __maybe_unused imx8qm_ldb_runtime_resume(struct device *dev) +{ + struct imx8qm_ldb *imx8qm_ldb = dev_get_drvdata(dev); + struct ldb *ldb = &imx8qm_ldb->base; + + /* disable LDB by resetting the control register to POR default */ + regmap_write(ldb->regmap, ldb->ctrl_reg, 0); + + return 0; +} + +static const struct dev_pm_ops imx8qm_ldb_pm_ops = { + SET_RUNTIME_PM_OPS(imx8qm_ldb_runtime_suspend, + imx8qm_ldb_runtime_resume, NULL) +}; + +static const struct of_device_id imx8qm_ldb_dt_ids[] = { + { .compatible = "fsl,imx8qm-ldb" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx8qm_ldb_dt_ids); + +static struct platform_driver imx8qm_ldb_driver = { + .probe = imx8qm_ldb_probe, + .remove = imx8qm_ldb_remove, + .driver = { + .pm = &imx8qm_ldb_pm_ops, + .name = DRIVER_NAME, + .of_match_table = imx8qm_ldb_dt_ids, + }, +}; +module_platform_driver(imx8qm_ldb_driver); + +MODULE_DESCRIPTION("i.MX8QM LVDS Display Bridge(LDB) bridge driver"); +MODULE_AUTHOR("Liu Ying victor.liu@nxp.com"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRIVER_NAME);
Add myself as the maintainer of DRM bridge drivers for i.MX SoCs.
Signed-off-by: Liu Ying victor.liu@nxp.com --- MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS index 7b073c4..4b4e40e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5846,6 +5846,16 @@ F: Documentation/devicetree/bindings/display/imx/ F: drivers/gpu/drm/imx/ F: drivers/gpu/ipu-v3/
+DRM DRIVERS FOR FREESCALE IMX BRIDGE +M: Liu Ying victor.liu@nxp.com +L: dri-devel@lists.freedesktop.org +S: Maintained +F: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml +F: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml +F: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml +F: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml +F: drivers/gpu/drm/bridge/imx/ + DRM DRIVERS FOR GMA500 (Poulsbo, Moorestown and derivative chipsets) M: Patrik Jakobsson patrik.r.jakobsson@gmail.com L: dri-devel@lists.freedesktop.org
dri-devel@lists.freedesktop.org
-
Laurent Pinchart -
Liu Ying -
Rob Herring