Drop the assigned clock rate property and vote on the mdp clock to max frequency during bind/probe sequence.
Changes in v2: - Remove assigned-clock-rate property and set mdp clk during resume sequence. - Add fixes tag.
Changes in v3: - Remove extra line after fixes tag.(Stephen Boyd) - Add similar changes for sc7180, sdm845 which uses opp table for voting mdp clk.(Stephen Boyd) - Drop patch: "drm/msm/disp/dpu1: set mdp clk to the maximum frequency in opp table"
Changes in v4: - Add similar change for sm8250.(Dmitry)
Changes in v5: - Add change to set mdp clk to max frequency in opp table during mdp probe/bind.
Changes in v6: - Remove change log in dt patch. - Fix the leak reference for opp by adding dev_pm_opp_put. (Dmitry)
Changes in v7: - Update commit message and fix tag. (Stephen/Doug)
Vinod Polimera (5): drm/msm/disp/dpu1: set mdp clk to the maximum frequency in opp table during probe arm64: dts: qcom: sm7280: remove assigned-clock-rate property for mdp clk arm64: dts: qcom: sm7180: remove assigned-clock-rate property for mdp clk arm64: dts: qcom: sdm845: remove assigned-clock-rate property for mdp clk arm64: dts: qcom: sm8250: remove assigned-clock-rate property for mdp clk
arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 ++------- arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 ++------- arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 ++------- arch/arm64/boot/dts/qcom/sm8250.dtsi | 9 ++------- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8 ++++++++ 5 files changed, 16 insertions(+), 28 deletions(-)
Set mdp clock to max clock rate during probe/bind sequence from the opp table so that rails are not at undetermined state. Since we do not know what will be the rate set in boot loader, it would be ideal to vote at max frequency. There could be a firmware display programmed in bootloader and we want to transition it to kernel without underflowing. The clock will be scaled down later when framework sends an update.
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Signed-off-by: Vinod Polimera quic_vpolimer@quicinc.com Reviewed-by: Dmitry Baryshkov dmitry.baryshkov@linaro.org Reviewed-by: Douglas Anderson dianders@chromium.org --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index e29796c..9c346ce 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1202,7 +1202,9 @@ static int dpu_bind(struct device *dev, struct device *master, void *data) struct platform_device *pdev = to_platform_device(dev); struct drm_device *ddev = priv->dev; struct dpu_kms *dpu_kms; + struct dev_pm_opp *opp; int ret = 0; + unsigned long max_freq = ULONG_MAX;
dpu_kms = devm_kzalloc(&pdev->dev, sizeof(*dpu_kms), GFP_KERNEL); if (!dpu_kms) @@ -1225,6 +1227,12 @@ static int dpu_bind(struct device *dev, struct device *master, void *data) } dpu_kms->num_clocks = ret;
+ opp = dev_pm_opp_find_freq_floor(dev, &max_freq); + if (!IS_ERR(opp)) + dev_pm_opp_put(opp); + + dev_pm_opp_set_rate(dev, max_freq); + platform_set_drvdata(pdev, dpu_kms);
ret = msm_kms_init(&dpu_kms->base, &kms_funcs);
Hi,
On Mon, Mar 21, 2022 at 8:27 PM Vinod Polimera quic_vpolimer@quicinc.com wrote:
Set mdp clock to max clock rate during probe/bind sequence from the opp table so that rails are not at undetermined state. Since we do not know what will be the rate set in boot loader, it would be ideal to vote at max frequency. There could be a firmware display programmed in bootloader and we want to transition it to kernel without underflowing. The clock will be scaled down later when framework sends an update.
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Signed-off-by: Vinod Polimera quic_vpolimer@quicinc.com Reviewed-by: Dmitry Baryshkov dmitry.baryshkov@linaro.org Reviewed-by: Douglas Anderson dianders@chromium.org
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8 ++++++++ 1 file changed, 8 insertions(+)
Just wanted to confirm that this patch will be queued up somewhat soon. I think it's good to go but I don't see it in any trees yet. ;-)
FWIW, I can also say that I've tested this patch and it fixes the underrun issues on sc7280-herobrine-rev1.
Tested-by: Douglas Anderson dianders@chromium.org
-Doug
Drop the assigned clock rate property and vote on the mdp clock as per calculated value during the usecase.
This patch is dependent on the patch ("drm/msm/disp/dpu1: set mdp clk to the maximum frequency in opp table during probe") [1].
[1] https://lore.kernel.org/r/1647269217-14064-2-git-send-email-quic_vpolimer@qu...
Signed-off-by: Vinod Polimera quic_vpolimer@quicinc.com Reviewed-by: Stephen Boyd swboyd@chromium.org Reviewed-by: Douglas Anderson dianders@chromium.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index c07765d..a3c768c 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3086,9 +3086,6 @@ "ahb", "core";
- assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; - assigned-clock-rates = <300000000>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <1>; @@ -3122,11 +3119,9 @@ "lut", "core", "vsync"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>; - assigned-clock-rates = <300000000>, - <19200000>, + assigned-clock-rates = <19200000>, <19200000>; operating-points-v2 = <&mdp_opp_table>; power-domains = <&rpmhpd SC7280_CX>;
Drop the assigned clock rate property and vote on the mdp clock as per calculated value during the usecase.
This patch is dependent on the patch ("drm/msm/disp/dpu1: set mdp clk to the maximum frequency in opp table during probe") [1].
[1] https://lore.kernel.org/r/1647269217-14064-2-git-send-email-quic_vpolimer@qu...
Signed-off-by: Vinod Polimera quic_vpolimer@quicinc.com Reviewed-by: Stephen Boyd swboyd@chromium.org Reviewed-by: Douglas Anderson dianders@chromium.org --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index e1c46b8..eaab746 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2900,9 +2900,6 @@ <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "iface", "ahb", "core";
- assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; - assigned-clock-rates = <300000000>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <1>; @@ -2932,12 +2929,10 @@ <&dispcc DISP_CC_MDSS_VSYNC_CLK>; clock-names = "bus", "iface", "rot", "lut", "core", "vsync"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, <&dispcc DISP_CC_MDSS_ROT_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>; - assigned-clock-rates = <300000000>, - <19200000>, + assigned-clock-rates = <19200000>, <19200000>, <19200000>; operating-points-v2 = <&mdp_opp_table>;
Drop the assigned clock rate property and vote on the mdp clock as per calculated value during the usecase.
This patch is dependent on the patch ("drm/msm/disp/dpu1: set mdp clk to the maximum frequency in opp table during probe") [1].
[1] https://lore.kernel.org/r/1647269217-14064-2-git-send-email-quic_vpolimer@qu...
Signed-off-by: Vinod Polimera quic_vpolimer@quicinc.com Reviewed-by: Stephen Boyd swboyd@chromium.org Reviewed-by: Douglas Anderson dianders@chromium.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 41f4e46..c0771d2 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4240,9 +4240,6 @@ <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "iface", "core";
- assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; - assigned-clock-rates = <300000000>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <1>; @@ -4273,10 +4270,8 @@ <&dispcc DISP_CC_MDSS_VSYNC_CLK>; clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
- assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <300000000>, - <19200000>; + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; power-domains = <&rpmhpd SDM845_CX>;
Drop the assigned clock rate property and vote on the mdp clock as per calculated value during the usecase.
This patch is dependent on the patch ("drm/msm/disp/dpu1: set mdp clk to the maximum frequency in opp table during probe") [1].
[1] https://lore.kernel.org/r/1647269217-14064-2-git-send-email-quic_vpolimer@qu...
Signed-off-by: Vinod Polimera quic_vpolimer@quicinc.com Reviewed-by: Stephen Boyd swboyd@chromium.org Reviewed-by: Douglas Anderson dianders@chromium.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index fdaf303..2105eb7 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3164,9 +3164,6 @@ <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "iface", "bus", "nrt_bus", "core";
- assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; - assigned-clock-rates = <460000000>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <1>; @@ -3191,10 +3188,8 @@ <&dispcc DISP_CC_MDSS_VSYNC_CLK>; clock-names = "iface", "bus", "core", "vsync";
- assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <460000000>, - <19200000>; + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>;
operating-points-v2 = <&mdp_opp_table>; power-domains = <&rpmhpd SM8250_MMCX>;
dri-devel@lists.freedesktop.org
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Doug Anderson -
Vinod Polimera