This series enable CRTC color-mgmt for komeda driver, for current komeda HW which only supports color conversion and forward gamma for CRTC.
This series actually are regrouped from: - drm/komeda: Enable layer/plane color-mgmt: https://patchwork.freedesktop.org/series/60893/
- drm/komeda: Enable CRTC color-mgmt https://patchwork.freedesktop.org/series/61370/
For removing the dependence on: - https://patchwork.freedesktop.org/series/30876/
Lowry Li (Arm Technology China) (1): drm/komeda: Adds gamma and color-transform support for DOU-IPS
james qian wang (Arm Technology China) (3): drm/komeda: Add a new helper drm_color_ctm_s31_32_to_qm_n() drm/komeda: Add drm_lut_to_fgamma_coeffs() drm/komeda: Add drm_ctm_to_coeffs()
v2: Move the fixpoint conversion function s31_32_to_q2_12() to drm core as a shared helper.
.../arm/display/komeda/d71/d71_component.c | 24 +++++++ .../arm/display/komeda/komeda_color_mgmt.c | 66 +++++++++++++++++++ .../arm/display/komeda/komeda_color_mgmt.h | 10 ++- .../gpu/drm/arm/display/komeda/komeda_crtc.c | 2 + .../drm/arm/display/komeda/komeda_pipeline.h | 3 + .../display/komeda/komeda_pipeline_state.c | 6 ++ drivers/gpu/drm/drm_color_mgmt.c | 23 +++++++ include/drm/drm_color_mgmt.h | 2 + 8 files changed, 135 insertions(+), 1 deletion(-)
-- 2.20.1
Add a new helper function drm_color_ctm_s31_32_to_qm_n() for driver to convert S31.32 sign-magnitude to Qm.n 2's complement that supported by hardware.
Signed-off-by: james qian wang (Arm Technology China) james.qian.wang@arm.com --- drivers/gpu/drm/drm_color_mgmt.c | 23 +++++++++++++++++++++++ include/drm/drm_color_mgmt.h | 2 ++ 2 files changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index 4ce5c6d8de99..3d533d0b45af 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -132,6 +132,29 @@ uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision) } EXPORT_SYMBOL(drm_color_lut_extract);
+/** + * drm_color_ctm_s31_32_to_qm_n + * + * @user_input: input value + * @m: number of integer bits + * @n: number of fractinal bits + * + * Convert and clamp S31.32 sign-magnitude to Qm.n 2's complement. + */ +uint64_t drm_color_ctm_s31_32_to_qm_n(uint64_t user_input, + uint32_t m, uint32_t n) +{ + u64 mag = (user_input & ~BIT_ULL(63)) >> (32 - n); + bool negative = !!(user_input & BIT_ULL(63)); + s64 val; + + /* the range of signed 2s complement is [-2^n+m, 2^n+m - 1] */ + val = clamp_val(mag, 0, negative ? BIT(n + m) : BIT(n + m) - 1); + + return negative ? 0ll - val : val; +} +EXPORT_SYMBOL(drm_color_ctm_s31_32_to_qm_n); + /** * drm_crtc_enable_color_mgmt - enable color management properties * @crtc: DRM CRTC diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h index d1c662d92ab7..60fea5501886 100644 --- a/include/drm/drm_color_mgmt.h +++ b/include/drm/drm_color_mgmt.h @@ -30,6 +30,8 @@ struct drm_crtc; struct drm_plane;
uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision); +uint64_t drm_color_ctm_s31_32_to_qm_n(uint64_t user_input, + uint32_t m, uint32_t n);
void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc, uint degamma_lut_size, -- 2.20.1
Hi James,
On Friday, 11 October 2019 06:45:27 BST james qian wang (Arm Technology China) wrote:
Add a new helper function drm_color_ctm_s31_32_to_qm_n() for driver to convert S31.32 sign-magnitude to Qm.n 2's complement that supported by hardware.
Signed-off-by: james qian wang (Arm Technology China) james.qian.wang@arm.com
drivers/gpu/drm/drm_color_mgmt.c | 23 +++++++++++++++++++++++ include/drm/drm_color_mgmt.h | 2 ++ 2 files changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index 4ce5c6d8de99..3d533d0b45af 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -132,6 +132,29 @@ uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision) } EXPORT_SYMBOL(drm_color_lut_extract);
+/**
- drm_color_ctm_s31_32_to_qm_n
- @user_input: input value
- @m: number of integer bits
- @n: number of fractinal bits
- Convert and clamp S31.32 sign-magnitude to Qm.n 2's complement.
- */
+uint64_t drm_color_ctm_s31_32_to_qm_n(uint64_t user_input,
uint32_t m, uint32_t n)+{
- u64 mag = (user_input & ~BIT_ULL(63)) >> (32 - n);
This doesn't account for n > 32, which is perfectly possible (e.g. Q1.63).
- bool negative = !!(user_input & BIT_ULL(63));
- s64 val;
- /* the range of signed 2s complement is [-2^n+m, 2^n+m - 1] */
- val = clamp_val(mag, 0, negative ? BIT(n + m) : BIT(n + m) - 1);
This also doesn't account for n + m == 64.
- return negative ? 0ll - val : val;
+} +EXPORT_SYMBOL(drm_color_ctm_s31_32_to_qm_n);
/**
- drm_crtc_enable_color_mgmt - enable color management properties
- @crtc: DRM CRTC
diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h index d1c662d92ab7..60fea5501886 100644 --- a/include/drm/drm_color_mgmt.h +++ b/include/drm/drm_color_mgmt.h @@ -30,6 +30,8 @@ struct drm_crtc; struct drm_plane;
uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision); +uint64_t drm_color_ctm_s31_32_to_qm_n(uint64_t user_input,
uint32_t m, uint32_t n);void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc, uint degamma_lut_size, -- 2.20.1
On Fri, Oct 11, 2019 at 08:26:53AM +0000, Mihail Atanassov wrote:
Hi James,
On Friday, 11 October 2019 06:45:27 BST james qian wang (Arm Technology China) wrote:
Add a new helper function drm_color_ctm_s31_32_to_qm_n() for driver to convert S31.32 sign-magnitude to Qm.n 2's complement that supported by hardware.
Signed-off-by: james qian wang (Arm Technology China) james.qian.wang@arm.com
drivers/gpu/drm/drm_color_mgmt.c | 23 +++++++++++++++++++++++ include/drm/drm_color_mgmt.h | 2 ++ 2 files changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index 4ce5c6d8de99..3d533d0b45af 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -132,6 +132,29 @@ uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision) } EXPORT_SYMBOL(drm_color_lut_extract);
+/**
- drm_color_ctm_s31_32_to_qm_n
- @user_input: input value
- @m: number of integer bits, the m must <= 31
- @n: number of fractinal bits the n must <= 32
@m: number of integer bits, only support m <= 31 @n: number of fractinal bitsm only support n <= 32
- Convert and clamp S31.32 sign-magnitude to Qm.n 2's complement.
- */
+uint64_t drm_color_ctm_s31_32_to_qm_n(uint64_t user_input,
uint32_t m, uint32_t n)+{
- u64 mag = (user_input & ~BIT_ULL(63)) >> (32 - n);
This doesn't account for n > 32, which is perfectly possible (e.g. Q1.63).
- bool negative = !!(user_input & BIT_ULL(63));
- s64 val;
- /* the range of signed 2s complement is [-2^n+m, 2^n+m - 1] */
- val = clamp_val(mag, 0, negative ? BIT(n + m) : BIT(n + m) - 1);
This also doesn't account for n + m == 64.
Yes the func is only for support m <= 31, n <= 32
But I'm not sure, how to handle the unsupport case ? Maybe just mention it in Doc is enough.
- return negative ? 0ll - val : val;
+} +EXPORT_SYMBOL(drm_color_ctm_s31_32_to_qm_n);
/**
- drm_crtc_enable_color_mgmt - enable color management properties
- @crtc: DRM CRTC
diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h index d1c662d92ab7..60fea5501886 100644 --- a/include/drm/drm_color_mgmt.h +++ b/include/drm/drm_color_mgmt.h @@ -30,6 +30,8 @@ struct drm_crtc; struct drm_plane;
uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision); +uint64_t drm_color_ctm_s31_32_to_qm_n(uint64_t user_input,
uint32_t m, uint32_t n);void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc, uint degamma_lut_size, -- 2.20.1
-- Mihail
On Monday, 14 October 2019 10:43:39 BST james qian wang (Arm Technology China) wrote:
On Fri, Oct 11, 2019 at 08:26:53AM +0000, Mihail Atanassov wrote:
Hi James,
On Friday, 11 October 2019 06:45:27 BST james qian wang (Arm Technology China) wrote:
Add a new helper function drm_color_ctm_s31_32_to_qm_n() for driver to convert S31.32 sign-magnitude to Qm.n 2's complement that supported by hardware.
Signed-off-by: james qian wang (Arm Technology China) james.qian.wang@arm.com
drivers/gpu/drm/drm_color_mgmt.c | 23 +++++++++++++++++++++++ include/drm/drm_color_mgmt.h | 2 ++ 2 files changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index 4ce5c6d8de99..3d533d0b45af 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -132,6 +132,29 @@ uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision) } EXPORT_SYMBOL(drm_color_lut_extract);
+/**
- drm_color_ctm_s31_32_to_qm_n
- @user_input: input value
- @m: number of integer bits, the m must <= 31
- @n: number of fractinal bits the n must <= 32
@m: number of integer bits, only support m <= 31 @n: number of fractinal bitsm only support n <= 32
Hehe, guess what I didn't do? Also, [nit], s/fractinal/fractional/.
- Convert and clamp S31.32 sign-magnitude to Qm.n 2's complement.
- */
+uint64_t drm_color_ctm_s31_32_to_qm_n(uint64_t user_input,
uint32_t m, uint32_t n)+{
- u64 mag = (user_input & ~BIT_ULL(63)) >> (32 - n);
This doesn't account for n > 32, which is perfectly possible (e.g. Q1.63).
- bool negative = !!(user_input & BIT_ULL(63));
- s64 val;
- /* the range of signed 2s complement is [-2^n+m, 2^n+m - 1] */
- val = clamp_val(mag, 0, negative ? BIT(n + m) : BIT(n + m) - 1);
This also doesn't account for n + m == 64.
Yes the func is only for support m <= 31, n <= 32
But I'm not sure, how to handle the unsupport case ? Maybe just mention it in Doc is enough.
I'd personally appreciate a WARN_ON(...)*. My comment was motivated by the unchecked nature of the limitation, which might surprise a dev who didn't read the doc before using the function (like myself :)).
Actually, the limitations are more than specified, BIT(n + m) is only valid for (n + m < 32) on LP32 systems.
At least change those to BIT_ULL(), then:
Reviewed-by: Mihail Atanassov mihail.atanassov@arm.com
* - gcc9.2 doesn't give me any compile-time warnings for using this func incorrectly.
- return negative ? 0ll - val : val;
+} +EXPORT_SYMBOL(drm_color_ctm_s31_32_to_qm_n);
/**
- drm_crtc_enable_color_mgmt - enable color management properties
- @crtc: DRM CRTC
diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h index d1c662d92ab7..60fea5501886 100644 --- a/include/drm/drm_color_mgmt.h +++ b/include/drm/drm_color_mgmt.h @@ -30,6 +30,8 @@ struct drm_crtc; struct drm_plane;
uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision); +uint64_t drm_color_ctm_s31_32_to_qm_n(uint64_t user_input,
uint32_t m, uint32_t n);void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc, uint degamma_lut_size, -- 2.20.1
This function is used to convert drm 3dlut to komeda HW required 1d curve coeffs values.
Signed-off-by: james qian wang (Arm Technology China) james.qian.wang@arm.com --- .../arm/display/komeda/komeda_color_mgmt.c | 52 +++++++++++++++++++ .../arm/display/komeda/komeda_color_mgmt.h | 9 +++- 2 files changed, 60 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.c b/drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.c index 9d14a92dbb17..c180ce70c26c 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.c @@ -65,3 +65,55 @@ const s32 *komeda_select_yuv2rgb_coeffs(u32 color_encoding, u32 color_range)
return coeffs; } + +struct gamma_curve_sector { + u32 boundary_start; + u32 num_of_segments; + u32 segment_width; +}; + +struct gamma_curve_segment { + u32 start; + u32 end; +}; + +static struct gamma_curve_sector sector_tbl[] = { + { 0, 4, 4 }, + { 16, 4, 4 }, + { 32, 4, 8 }, + { 64, 4, 16 }, + { 128, 4, 32 }, + { 256, 4, 64 }, + { 512, 16, 32 }, + { 1024, 24, 128 }, +}; + +static void +drm_lut_to_coeffs(struct drm_property_blob *lut_blob, u32 *coeffs, + struct gamma_curve_sector *sector_tbl, u32 num_sectors) +{ + struct drm_color_lut *lut; + u32 i, j, in, num = 0; + + if (!lut_blob) + return; + + lut = lut_blob->data; + + for (i = 0; i < num_sectors; i++) { + for (j = 0; j < sector_tbl[i].num_of_segments; j++) { + in = sector_tbl[i].boundary_start + + j * sector_tbl[i].segment_width; + + coeffs[num++] = drm_color_lut_extract(lut[in].red, + KOMEDA_COLOR_PRECISION); + } + } + + coeffs[num] = BIT(KOMEDA_COLOR_PRECISION); +} + +void drm_lut_to_fgamma_coeffs(struct drm_property_blob *lut_blob, u32 *coeffs) +{ + drm_lut_to_coeffs(lut_blob, coeffs, sector_tbl, ARRAY_SIZE(sector_tbl)); +} diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.h b/drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.h index a2df218f58e7..08ab69281648 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.h +++ b/drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.h @@ -11,7 +11,14 @@ #include <drm/drm_color_mgmt.h>
#define KOMEDA_N_YUV2RGB_COEFFS 12 +#define KOMEDA_N_RGB2YUV_COEFFS 12 +#define KOMEDA_COLOR_PRECISION 12 +#define KOMEDA_N_GAMMA_COEFFS 65 +#define KOMEDA_COLOR_LUT_SIZE BIT(KOMEDA_COLOR_PRECISION) +#define KOMEDA_N_CTM_COEFFS 9 + +void drm_lut_to_fgamma_coeffs(struct drm_property_blob *lut_blob, u32 *coeffs);
const s32 *komeda_select_yuv2rgb_coeffs(u32 color_encoding, u32 color_range);
-#endif +#endif /*_KOMEDA_COLOR_MGMT_H_*/
On Friday, 11 October 2019 06:45:35 BST james qian wang (Arm Technology China) wrote:
This function is used to convert drm 3dlut to komeda HW required 1d curve coeffs values.
Signed-off-by: james qian wang (Arm Technology China) james.qian.wang@arm.com
.../arm/display/komeda/komeda_color_mgmt.c | 52 +++++++++++++++++++ .../arm/display/komeda/komeda_color_mgmt.h | 9 +++- 2 files changed, 60 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.c b/drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.c index 9d14a92dbb17..c180ce70c26c 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.c @@ -65,3 +65,55 @@ const s32 *komeda_select_yuv2rgb_coeffs(u32 color_encoding, u32 color_range)
return coeffs; }
+struct gamma_curve_sector {
- u32 boundary_start;
- u32 num_of_segments;
- u32 segment_width;
+};
+struct gamma_curve_segment {
- u32 start;
- u32 end;
+};
+static struct gamma_curve_sector sector_tbl[] = {
[bikeshed] I'd name this fgamma_sector_tbl (didn't the previous version of this patch stack have an gamma_curve_sector for igamma?).
- { 0, 4, 4 },
- { 16, 4, 4 },
- { 32, 4, 8 },
- { 64, 4, 16 },
- { 128, 4, 32 },
- { 256, 4, 64 },
- { 512, 16, 32 },
- { 1024, 24, 128 },
+};
+static void +drm_lut_to_coeffs(struct drm_property_blob *lut_blob, u32 *coeffs,
struct gamma_curve_sector *sector_tbl, u32 num_sectors)+{
- struct drm_color_lut *lut;
- u32 i, j, in, num = 0;
- if (!lut_blob)
return;- lut = lut_blob->data;
- for (i = 0; i < num_sectors; i++) {
for (j = 0; j < sector_tbl[i].num_of_segments; j++) {in = sector_tbl[i].boundary_start +j * sector_tbl[i].segment_width;coeffs[num++] = drm_color_lut_extract(lut[in].red,KOMEDA_COLOR_PRECISION);}- }
- coeffs[num] = BIT(KOMEDA_COLOR_PRECISION);
+}
+void drm_lut_to_fgamma_coeffs(struct drm_property_blob *lut_blob, u32 *coeffs) +{
- drm_lut_to_coeffs(lut_blob, coeffs, sector_tbl, ARRAY_SIZE(sector_tbl));
+} diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.h b/drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.h index a2df218f58e7..08ab69281648 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.h +++ b/drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.h @@ -11,7 +11,14 @@ #include <drm/drm_color_mgmt.h>
#define KOMEDA_N_YUV2RGB_COEFFS 12 +#define KOMEDA_N_RGB2YUV_COEFFS 12 +#define KOMEDA_COLOR_PRECISION 12 +#define KOMEDA_N_GAMMA_COEFFS 65 +#define KOMEDA_COLOR_LUT_SIZE BIT(KOMEDA_COLOR_PRECISION) +#define KOMEDA_N_CTM_COEFFS 9
[nit] The alignment with the group above seems a bit off.
+void drm_lut_to_fgamma_coeffs(struct drm_property_blob *lut_blob, u32 *coeffs);
const s32 *komeda_select_yuv2rgb_coeffs(u32 color_encoding, u32 color_range);
-#endif +#endif /*_KOMEDA_COLOR_MGMT_H_*/
Reviewed-by: Mihail Atanassov mihail.atanassov@arm.com
This function is for converting drm_color_ctm matrix to komeda hardware required required Q2.12 2's complement CSC matrix.
v2: Move the fixpoint conversion function s31_32_to_q2_12() to drm core as a shared helper.
Signed-off-by: james qian wang (Arm Technology China) james.qian.wang@arm.com --- .../gpu/drm/arm/display/komeda/komeda_color_mgmt.c | 14 ++++++++++++++ .../gpu/drm/arm/display/komeda/komeda_color_mgmt.h | 1 + 2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.c b/drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.c index c180ce70c26c..ad668accbdf4 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.c @@ -117,3 +117,17 @@ void drm_lut_to_fgamma_coeffs(struct drm_property_blob *lut_blob, u32 *coeffs) { drm_lut_to_coeffs(lut_blob, coeffs, sector_tbl, ARRAY_SIZE(sector_tbl)); } + +void drm_ctm_to_coeffs(struct drm_property_blob *ctm_blob, u32 *coeffs) +{ + struct drm_color_ctm *ctm; + u32 i; + + if (!ctm_blob) + return; + + ctm = ctm_blob->data; + + for (i = 0; i < KOMEDA_N_CTM_COEFFS; i++) + coeffs[i] = drm_color_ctm_s31_32_to_qm_n(ctm->matrix[i], 2, 12); +} diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.h b/drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.h index 08ab69281648..2f4668466112 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.h +++ b/drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.h @@ -18,6 +18,7 @@ #define KOMEDA_N_CTM_COEFFS 9
void drm_lut_to_fgamma_coeffs(struct drm_property_blob *lut_blob, u32 *coeffs); +void drm_ctm_to_coeffs(struct drm_property_blob *ctm_blob, u32 *coeffs);
const s32 *komeda_select_yuv2rgb_coeffs(u32 color_encoding, u32 color_range);
On Friday, 11 October 2019 06:45:42 BST james qian wang (Arm Technology China) wrote:
This function is for converting drm_color_ctm matrix to komeda hardware required required Q2.12 2's complement CSC matrix.
v2: Move the fixpoint conversion function s31_32_to_q2_12() to drm core as a shared helper.
Signed-off-by: james qian wang (Arm Technology China) james.qian.wang@arm.com
.../gpu/drm/arm/display/komeda/komeda_color_mgmt.c | 14 ++++++++++++++ .../gpu/drm/arm/display/komeda/komeda_color_mgmt.h | 1 + 2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.c b/drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.c index c180ce70c26c..ad668accbdf4 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.c @@ -117,3 +117,17 @@ void drm_lut_to_fgamma_coeffs(struct drm_property_blob *lut_blob, u32 *coeffs) { drm_lut_to_coeffs(lut_blob, coeffs, sector_tbl, ARRAY_SIZE(sector_tbl)); }
+void drm_ctm_to_coeffs(struct drm_property_blob *ctm_blob, u32 *coeffs)
[nit] Could do with an extra const or two on the drm_property_blob, otherwise...
+{
- struct drm_color_ctm *ctm;
- u32 i;
- if (!ctm_blob)
return;- ctm = ctm_blob->data;
- for (i = 0; i < KOMEDA_N_CTM_COEFFS; i++)
coeffs[i] = drm_color_ctm_s31_32_to_qm_n(ctm->matrix[i], 2, 12);+} diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.h b/drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.h index 08ab69281648..2f4668466112 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.h +++ b/drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.h @@ -18,6 +18,7 @@ #define KOMEDA_N_CTM_COEFFS 9
void drm_lut_to_fgamma_coeffs(struct drm_property_blob *lut_blob, u32 *coeffs); +void drm_ctm_to_coeffs(struct drm_property_blob *ctm_blob, u32 *coeffs);
const s32 *komeda_select_yuv2rgb_coeffs(u32 color_encoding, u32 color_range);
... Reviewed-by: Mihail Atanassov mihail.atanassov@arm.com
From: "Lowry Li (Arm Technology China)" Lowry.Li@arm.com
Adds gamma and color-transform support for DOU-IPS. Adds two caps members fgamma_coeffs and ctm_coeffs to komeda_improc_state. If color management changed, set gamma and color-transform accordingly.
Signed-off-by: Lowry Li (Arm Technology China) lowry.li@arm.com --- .../arm/display/komeda/d71/d71_component.c | 24 +++++++++++++++++++ .../gpu/drm/arm/display/komeda/komeda_crtc.c | 2 ++ .../drm/arm/display/komeda/komeda_pipeline.h | 3 +++ .../display/komeda/komeda_pipeline_state.c | 6 +++++ 4 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c index c3d29c0b051b..e7e5a8e4430e 100644 --- a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c @@ -942,15 +942,39 @@ static int d71_merger_init(struct d71_dev *d71, static void d71_improc_update(struct komeda_component *c, struct komeda_component_state *state) { + struct drm_crtc_state *crtc_st = state->crtc->state; struct komeda_improc_state *st = to_improc_st(state); + struct d71_pipeline *pipe = to_d71_pipeline(c->pipeline); u32 __iomem *reg = c->reg; u32 index; + u32 mask = 0, ctrl = 0;
for_each_changed_input(state, index) malidp_write32(reg, BLK_INPUT_ID0 + index * 4, to_d71_input_id(state, index));
malidp_write32(reg, BLK_SIZE, HV_SIZE(st->hsize, st->vsize)); + + if (crtc_st->color_mgmt_changed) { + mask |= IPS_CTRL_FT | IPS_CTRL_RGB; + + if (crtc_st->gamma_lut) { + malidp_write_group(pipe->dou_ft_coeff_addr, FT_COEFF0, + KOMEDA_N_GAMMA_COEFFS, + st->fgamma_coeffs); + ctrl |= IPS_CTRL_FT; /* enable gamma */ + } + + if (crtc_st->ctm) { + malidp_write_group(reg, IPS_RGB_RGB_COEFF0, + KOMEDA_N_CTM_COEFFS, + st->ctm_coeffs); + ctrl |= IPS_CTRL_RGB; /* enable gamut */ + } + } + + if (mask) + malidp_write32_mask(reg, BLK_CONTROL, mask, ctrl); }
static void d71_improc_dump(struct komeda_component *c, struct seq_file *sf) diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c index 9beeda04818b..406b9d0ca058 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c @@ -590,6 +590,8 @@ static int komeda_crtc_add(struct komeda_kms_dev *kms,
crtc->port = kcrtc->master->of_output_port;
+ drm_crtc_enable_color_mgmt(crtc, 0, true, KOMEDA_COLOR_LUT_SIZE); + return err; }
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h index b322f52ba8f2..c5ab8096c85d 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h +++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h @@ -11,6 +11,7 @@ #include <drm/drm_atomic.h> #include <drm/drm_atomic_helper.h> #include "malidp_utils.h" +#include "komeda_color_mgmt.h"
#define KOMEDA_MAX_PIPELINES 2 #define KOMEDA_PIPELINE_MAX_LAYERS 4 @@ -324,6 +325,8 @@ struct komeda_improc { struct komeda_improc_state { struct komeda_component_state base; u16 hsize, vsize; + u32 fgamma_coeffs[KOMEDA_N_GAMMA_COEFFS]; + u32 ctm_coeffs[KOMEDA_N_CTM_COEFFS]; };
/* display timing controller */ diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c index 0ba9c6aa3708..4a40b37eb1a6 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c @@ -756,6 +756,12 @@ komeda_improc_validate(struct komeda_improc *improc, st->hsize = dflow->in_w; st->vsize = dflow->in_h;
+ if (kcrtc_st->base.color_mgmt_changed) { + drm_lut_to_fgamma_coeffs(kcrtc_st->base.gamma_lut, + st->fgamma_coeffs); + drm_ctm_to_coeffs(kcrtc_st->base.ctm, st->ctm_coeffs); + } + komeda_component_add_input(&st->base, &dflow->input, 0); komeda_component_set_output(&dflow->input, &improc->base, 0);
Hi James, Lowry,
On Friday, 11 October 2019 06:45:50 BST james qian wang (Arm Technology China) wrote:
From: "Lowry Li (Arm Technology China)" Lowry.Li@arm.com
Adds gamma and color-transform support for DOU-IPS. Adds two caps members fgamma_coeffs and ctm_coeffs to komeda_improc_state. If color management changed, set gamma and color-transform accordingly.
Signed-off-by: Lowry Li (Arm Technology China) lowry.li@arm.com
.../arm/display/komeda/d71/d71_component.c | 24 +++++++++++++++++++ .../gpu/drm/arm/display/komeda/komeda_crtc.c | 2 ++ .../drm/arm/display/komeda/komeda_pipeline.h | 3 +++ .../display/komeda/komeda_pipeline_state.c | 6 +++++ 4 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c index c3d29c0b051b..e7e5a8e4430e 100644 --- a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c @@ -942,15 +942,39 @@ static int d71_merger_init(struct d71_dev *d71, static void d71_improc_update(struct komeda_component *c, struct komeda_component_state *state) {
- struct drm_crtc_state *crtc_st = state->crtc->state;
I'm not sure it's a good idea to introduce a dependency on drm state so far down in the HW funcs, is there a good reason for the direct prod?
struct komeda_improc_state *st = to_improc_st(state);
struct d71_pipeline *pipe = to_d71_pipeline(c->pipeline); u32 __iomem *reg = c->reg; u32 index;
u32 mask = 0, ctrl = 0;
for_each_changed_input(state, index) malidp_write32(reg, BLK_INPUT_ID0 + index * 4, to_d71_input_id(state, index));
malidp_write32(reg, BLK_SIZE, HV_SIZE(st->hsize, st->vsize));
if (crtc_st->color_mgmt_changed) {
mask |= IPS_CTRL_FT | IPS_CTRL_RGB;if (crtc_st->gamma_lut) {malidp_write_group(pipe->dou_ft_coeff_addr, FT_COEFF0,KOMEDA_N_GAMMA_COEFFS,st->fgamma_coeffs);ctrl |= IPS_CTRL_FT; /* enable gamma */}if (crtc_st->ctm) {malidp_write_group(reg, IPS_RGB_RGB_COEFF0,KOMEDA_N_CTM_COEFFS,st->ctm_coeffs);ctrl |= IPS_CTRL_RGB; /* enable gamut */}}
if (mask)
malidp_write32_mask(reg, BLK_CONTROL, mask, ctrl);}
static void d71_improc_dump(struct komeda_component *c, struct seq_file *sf) diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c index 9beeda04818b..406b9d0ca058 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c @@ -590,6 +590,8 @@ static int komeda_crtc_add(struct komeda_kms_dev *kms,
crtc->port = kcrtc->master->of_output_port;
- drm_crtc_enable_color_mgmt(crtc, 0, true, KOMEDA_COLOR_LUT_SIZE);
- return err;
}
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h index b322f52ba8f2..c5ab8096c85d 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h +++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h @@ -11,6 +11,7 @@ #include <drm/drm_atomic.h> #include <drm/drm_atomic_helper.h> #include "malidp_utils.h" +#include "komeda_color_mgmt.h"
#define KOMEDA_MAX_PIPELINES 2 #define KOMEDA_PIPELINE_MAX_LAYERS 4 @@ -324,6 +325,8 @@ struct komeda_improc { struct komeda_improc_state { struct komeda_component_state base; u16 hsize, vsize;
- u32 fgamma_coeffs[KOMEDA_N_GAMMA_COEFFS];
- u32 ctm_coeffs[KOMEDA_N_CTM_COEFFS];
};
/* display timing controller */ diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c index 0ba9c6aa3708..4a40b37eb1a6 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c @@ -756,6 +756,12 @@ komeda_improc_validate(struct komeda_improc *improc, st->hsize = dflow->in_w; st->vsize = dflow->in_h;
- if (kcrtc_st->base.color_mgmt_changed) {
drm_lut_to_fgamma_coeffs(kcrtc_st->base.gamma_lut,st->fgamma_coeffs);drm_ctm_to_coeffs(kcrtc_st->base.ctm, st->ctm_coeffs);- }
- komeda_component_add_input(&st->base, &dflow->input, 0); komeda_component_set_output(&dflow->input, &improc->base, 0);
Hi Mihail, On Fri, Oct 11, 2019 at 08:54:03AM +0000, Mihail Atanassov wrote:
Hi James, Lowry,
On Friday, 11 October 2019 06:45:50 BST james qian wang (Arm Technology China) wrote:
From: "Lowry Li (Arm Technology China)" Lowry.Li@arm.com
Adds gamma and color-transform support for DOU-IPS. Adds two caps members fgamma_coeffs and ctm_coeffs to komeda_improc_state. If color management changed, set gamma and color-transform accordingly.
Signed-off-by: Lowry Li (Arm Technology China) lowry.li@arm.com
.../arm/display/komeda/d71/d71_component.c | 24 +++++++++++++++++++ .../gpu/drm/arm/display/komeda/komeda_crtc.c | 2 ++ .../drm/arm/display/komeda/komeda_pipeline.h | 3 +++ .../display/komeda/komeda_pipeline_state.c | 6 +++++ 4 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c index c3d29c0b051b..e7e5a8e4430e 100644 --- a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c @@ -942,15 +942,39 @@ static int d71_merger_init(struct d71_dev *d71, static void d71_improc_update(struct komeda_component *c, struct komeda_component_state *state) {
- struct drm_crtc_state *crtc_st = state->crtc->state;
I'm not sure it's a good idea to introduce a dependency on drm state so far down in the HW funcs, is there a good reason for the direct prod?
We dicussed about this before. To decide using this way is to avoid of duplicated state between DRM and Komeda.
Regards, Lowry
struct komeda_improc_state *st = to_improc_st(state);
struct d71_pipeline *pipe = to_d71_pipeline(c->pipeline); u32 __iomem *reg = c->reg; u32 index;
u32 mask = 0, ctrl = 0;
for_each_changed_input(state, index) malidp_write32(reg, BLK_INPUT_ID0 + index * 4, to_d71_input_id(state, index));
malidp_write32(reg, BLK_SIZE, HV_SIZE(st->hsize, st->vsize));
if (crtc_st->color_mgmt_changed) {
mask |= IPS_CTRL_FT | IPS_CTRL_RGB;if (crtc_st->gamma_lut) {malidp_write_group(pipe->dou_ft_coeff_addr, FT_COEFF0,KOMEDA_N_GAMMA_COEFFS,st->fgamma_coeffs);ctrl |= IPS_CTRL_FT; /* enable gamma */}if (crtc_st->ctm) {malidp_write_group(reg, IPS_RGB_RGB_COEFF0,KOMEDA_N_CTM_COEFFS,st->ctm_coeffs);ctrl |= IPS_CTRL_RGB; /* enable gamut */}}
if (mask)
malidp_write32_mask(reg, BLK_CONTROL, mask, ctrl);}
static void d71_improc_dump(struct komeda_component *c, struct seq_file *sf) diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c index 9beeda04818b..406b9d0ca058 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c @@ -590,6 +590,8 @@ static int komeda_crtc_add(struct komeda_kms_dev *kms,
crtc->port = kcrtc->master->of_output_port;
- drm_crtc_enable_color_mgmt(crtc, 0, true, KOMEDA_COLOR_LUT_SIZE);
- return err;
}
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h index b322f52ba8f2..c5ab8096c85d 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h +++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h @@ -11,6 +11,7 @@ #include <drm/drm_atomic.h> #include <drm/drm_atomic_helper.h> #include "malidp_utils.h" +#include "komeda_color_mgmt.h"
#define KOMEDA_MAX_PIPELINES 2 #define KOMEDA_PIPELINE_MAX_LAYERS 4 @@ -324,6 +325,8 @@ struct komeda_improc { struct komeda_improc_state { struct komeda_component_state base; u16 hsize, vsize;
- u32 fgamma_coeffs[KOMEDA_N_GAMMA_COEFFS];
- u32 ctm_coeffs[KOMEDA_N_CTM_COEFFS];
};
/* display timing controller */ diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c index 0ba9c6aa3708..4a40b37eb1a6 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c @@ -756,6 +756,12 @@ komeda_improc_validate(struct komeda_improc *improc, st->hsize = dflow->in_w; st->vsize = dflow->in_h;
- if (kcrtc_st->base.color_mgmt_changed) {
drm_lut_to_fgamma_coeffs(kcrtc_st->base.gamma_lut,st->fgamma_coeffs);drm_ctm_to_coeffs(kcrtc_st->base.ctm, st->ctm_coeffs);- }
- komeda_component_add_input(&st->base, &dflow->input, 0); komeda_component_set_output(&dflow->input, &improc->base, 0);
-- Mihail
On Friday, 11 October 2019 11:12:51 BST Lowry Li (Arm Technology China) wrote:
Hi Mihail, On Fri, Oct 11, 2019 at 08:54:03AM +0000, Mihail Atanassov wrote:
Hi James, Lowry,
On Friday, 11 October 2019 06:45:50 BST james qian wang (Arm Technology China) wrote:
From: "Lowry Li (Arm Technology China)" Lowry.Li@arm.com
Adds gamma and color-transform support for DOU-IPS. Adds two caps members fgamma_coeffs and ctm_coeffs to komeda_improc_state. If color management changed, set gamma and color-transform accordingly.
Signed-off-by: Lowry Li (Arm Technology China) lowry.li@arm.com
.../arm/display/komeda/d71/d71_component.c | 24 +++++++++++++++++++ .../gpu/drm/arm/display/komeda/komeda_crtc.c | 2 ++ .../drm/arm/display/komeda/komeda_pipeline.h | 3 +++ .../display/komeda/komeda_pipeline_state.c | 6 +++++ 4 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c index c3d29c0b051b..e7e5a8e4430e 100644 --- a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c @@ -942,15 +942,39 @@ static int d71_merger_init(struct d71_dev *d71, static void d71_improc_update(struct komeda_component *c, struct komeda_component_state *state) {
- struct drm_crtc_state *crtc_st = state->crtc->state;
I'm not sure it's a good idea to introduce a dependency on drm state so far down in the HW funcs, is there a good reason for the direct prod?
We dicussed about this before. To decide using this way is to avoid of duplicated state between DRM and Komeda.
Fair, r-b me.
Regards, Lowry
struct komeda_improc_state *st = to_improc_st(state);
struct d71_pipeline *pipe = to_d71_pipeline(c->pipeline); u32 __iomem *reg = c->reg; u32 index;
u32 mask = 0, ctrl = 0;
for_each_changed_input(state, index) malidp_write32(reg, BLK_INPUT_ID0 + index * 4, to_d71_input_id(state, index));
malidp_write32(reg, BLK_SIZE, HV_SIZE(st->hsize, st->vsize));
if (crtc_st->color_mgmt_changed) {
mask |= IPS_CTRL_FT | IPS_CTRL_RGB;if (crtc_st->gamma_lut) {malidp_write_group(pipe->dou_ft_coeff_addr, FT_COEFF0,KOMEDA_N_GAMMA_COEFFS,st->fgamma_coeffs);ctrl |= IPS_CTRL_FT; /* enable gamma */}if (crtc_st->ctm) {malidp_write_group(reg, IPS_RGB_RGB_COEFF0,KOMEDA_N_CTM_COEFFS,st->ctm_coeffs);ctrl |= IPS_CTRL_RGB; /* enable gamut */}}
if (mask)
malidp_write32_mask(reg, BLK_CONTROL, mask, ctrl);}
static void d71_improc_dump(struct komeda_component *c, struct seq_file *sf) diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c index 9beeda04818b..406b9d0ca058 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c @@ -590,6 +590,8 @@ static int komeda_crtc_add(struct komeda_kms_dev *kms,
crtc->port = kcrtc->master->of_output_port;
- drm_crtc_enable_color_mgmt(crtc, 0, true, KOMEDA_COLOR_LUT_SIZE);
- return err;
}
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h index b322f52ba8f2..c5ab8096c85d 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h +++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h @@ -11,6 +11,7 @@ #include <drm/drm_atomic.h> #include <drm/drm_atomic_helper.h> #include "malidp_utils.h" +#include "komeda_color_mgmt.h"
#define KOMEDA_MAX_PIPELINES 2 #define KOMEDA_PIPELINE_MAX_LAYERS 4 @@ -324,6 +325,8 @@ struct komeda_improc { struct komeda_improc_state { struct komeda_component_state base; u16 hsize, vsize;
- u32 fgamma_coeffs[KOMEDA_N_GAMMA_COEFFS];
- u32 ctm_coeffs[KOMEDA_N_CTM_COEFFS];
};
/* display timing controller */ diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c index 0ba9c6aa3708..4a40b37eb1a6 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c @@ -756,6 +756,12 @@ komeda_improc_validate(struct komeda_improc *improc, st->hsize = dflow->in_w; st->vsize = dflow->in_h;
- if (kcrtc_st->base.color_mgmt_changed) {
drm_lut_to_fgamma_coeffs(kcrtc_st->base.gamma_lut,st->fgamma_coeffs);drm_ctm_to_coeffs(kcrtc_st->base.ctm, st->ctm_coeffs);- }
- komeda_component_add_input(&st->base, &dflow->input, 0); komeda_component_set_output(&dflow->input, &improc->base, 0);
dri-devel@lists.freedesktop.org
-
james qian wang (Arm Technology China) -
Lowry Li (Arm Technology China) -
Mihail Atanassov