On Mon, Sep 23, 2013 at 3:42 AM, Christian König deathsimple@vodafone.de wrote:

From: Christian König christian.koenig@amd.com

Starting with UVD3 message and feedback buffers have their own 256MB segment, so no need to force them into VRAM any more.

Signed-off-by: Christian König christian.koenig@amd.com

Applied. Thanks!

Alex

---

drivers/gpu/drm/radeon/radeon_cs.c | 3 ++- drivers/gpu/drm/radeon/radeon_uvd.c | 3 +-- drivers/gpu/drm/radeon/uvd_v1_0.c | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c index ac6ece6..1806f4d 100644 --- a/drivers/gpu/drm/radeon/radeon_cs.c +++ b/drivers/gpu/drm/radeon/radeon_cs.c @@ -85,8 +85,9 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) VRAM, also but everything into VRAM on AGP cards to avoid image corruptions */ if (p->ring == R600_RING_TYPE_UVD_INDEX &&

•               p->rdev->family < CHIP_PALM &&
                (i == 0 || p->rdev->flags & RADEON_IS_AGP)) {
  

•                   /* TODO: is this still needed for NI+ ? */
  

•                   p->relocs[i].lobj.domain =
                            RADEON_GEM_DOMAIN_VRAM;
  
  

diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c b/drivers/gpu/drm/radeon/radeon_uvd.c index 1a01bbf..a0f1185 100644 --- a/drivers/gpu/drm/radeon/radeon_uvd.c +++ b/drivers/gpu/drm/radeon/radeon_uvd.c @@ -476,8 +476,7 @@ static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p, return -EINVAL; }

•   /* TODO: is this still necessary on NI+ ? */
  

•   if ((cmd == 0 || cmd == 0x3) &&
  

•   if (p->rdev->family < CHIP_PALM && (cmd == 0 || cmd == 0x3) &&
        (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {
            DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
                      start, end);
  

diff --git a/drivers/gpu/drm/radeon/uvd_v1_0.c b/drivers/gpu/drm/radeon/uvd_v1_0.c index 7266805..3100fa9 100644 --- a/drivers/gpu/drm/radeon/uvd_v1_0.c +++ b/drivers/gpu/drm/radeon/uvd_v1_0.c @@ -212,8 +212,8 @@ int uvd_v1_0_start(struct radeon_device *rdev) /* enable VCPU clock */ WREG32(UVD_VCPU_CNTL, 1 << 9);

•   /* enable UMC */
  

•   WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8));
  

•   /* enable UMC and NC0 */
  

•   WREG32_P(UVD_LMI_CTRL2, 1 << 13, ~((1 << 8) | (1 << 13)));
  
    /* boot up the VCPU */
    WREG32(UVD_SOFT_RESET, 0);
  

-- 1.8.1.2