This patch set adds Color Manager implementation in DRM layer. Color Manager is an extension in DRM framework to support color correction/enhancement.
Various Hardware platforms can support several color correction capabilities. Color Manager provides abstraction of these capabilities and allows a user space UI agent to correct/enhance the display using the DRM property interface.
How is this going to work? ========================== 1. This patch series adds a few new properties in DRM framework. These properties are: a. color_capabilities property (type blob) b. Color Transformation Matrix property for corrections like CSC (called CTM, type blob) c. Palette correction properties for corrections like gamma fixup (called palette_correction, type blob) 2. Also, this patch series adds few structures to indicate specifications of a property like size, no_of_samples for correction etc. 3. These properties are present in mode_config. 4. When the platform's display driver loads, it fills up the values of color_capabilities property using the standard structures (added in step 2). For example, Intel's I915 driver adds following color correction capabilities: a. gamma correction capability as palette correction property, with 257 correction coefficients and a max/min value b. csc correction capability as CTM correction property, with 3x3 transformation matrix values and max/min values 5. Now when userspace comes up, it queries the platform's color capabilities by doing a get_property() on color_capabilities DRM property 6. Reading the blob, the userspace understands the color capabilities of the platform. For example, userspace will understand it can support: a. palette_correction with 257 coefficients b. CSC correction with 3x3 = 9 values 7. To set color correction values, userspace: a. creates a blob using the create_blob_ioctl in standard palette_correction structure format, with the correction values b. calls the set_property_ioctl with the blob_id as value for the property 8. Driver refers to the blob, gets the correction values and applies the correction in HW. 9. To get currently applied color correction values, userspace: a. calls a get_property_ioctl on that color property b. gets the blob_id for the currently applied correction from DRM infrastructure c. gets the blob using get_blob_ioctl and hence the currently applied values
That's all! :)
About the patch series: ======================= The patch series first adds the color management support in DRM layer. Then it adds the color management framework in I915 layer. After that, it implements platform specific core color correction functios.
Intel color manager registers color correction with DRM color manager in this way: - CSC transformation is registered as CTM DRM property - Gamma correction is registered as palette_after_ctm DRM property - Degamma correction is registered as palette_before_ctm DRM property
Our thanks to all the reviewers who have given valuable comments in terms of design and implementation to our previous sets of patches. Special mention of thanks should go to Matt Roper for all his inputs/suggestions in implementation of this module, using DRM atomic CRTC commit path.
V2: Worked on review comments from Matt, Jim, Thierry, Rob. V3: Worked on review comments from Matt, Jim, Rob: - Jim, Rob: ======== Re-arranged the whole patch series in the sequence of features, currently: First 5 patches add color management support in DRM layer Next 7 patches add Intel color management framework in I915 driver Next 5 patches add color correction for CHV (gamma, degamma and CSC) Next 2 patches enable color management, by attaching the properties to CRTC(Matt) Next 4 patches add color correction for BDW (gamma, degamma) - Matt: ===== Patch 3: Added refernce/unreference for blob Patch 7: return -EINVAL and added debug message Patch 8: check for valid blob, from create blob moved call to intel_crtc_attach_color_prop in the end of full implementation (CHV) Patch 9: DRM_ERROR->DRM_DEBUG for NULL blob case Patch 13: Added static for internal functions Patch 20-24: renamed gen9_* functions to bdw_* Added new variables in device_info structure num_samples_after_ctm and num_samples_before_ctm Added new function in patch 8 to load capabilities based on device_info across all platforms
V4: Worked on review comments from Daniel, Matt, Rob, Jim - Rob, Jim: ========= Patch 15, 22: Prepare CSC coeff properly(chv, bdw). Patch 13, 20: Gamma max should be (1<<24) -1(chv, bdw). - Daniel, Matt: ============= Patch 2: Create separate properties to query color capabilities, not a single blob. Patch 4, 5, 10: Add set/get property interface in DRM layer, not in I915 layer.
Shashank Sharma (22): drm: Create Color Management DRM properties drm: Create Color Management query properties drm: Add color correction blobs in CRTC state drm: Add set property support for color manager drm: Add get property support for color manager drm: Add drm structures for palette color property drm: Add structure to set/get a CTM color property drm/i915: Add set property interface for CRTC drm/i915: Create color management files drm/i915: Register color correction capabilities drm/i915: CHV: Load gamma color correction values drm/i915: CHV: Load degamma color correction values drm/i915: CHV: Pipe level Gamma correction drm/i915: CHV: Pipe level degamma correction drm/i915: CHV: Pipe level CSC correction drm/i915: Commit color correction to CRTC drm/i915: Attach color properties to CRTC drm/i915: BDW: Load gamma correction values drm/i915: BDW: Pipe level Gamma correction drm/i915: BDW: Load degamma correction values drm/i915: BDW: Pipe level degamma correction drm/i915: BDW: Pipe level CSC correction
drivers/gpu/drm/drm_atomic.c | 61 ++- drivers/gpu/drm/drm_atomic_helper.c | 12 + drivers/gpu/drm/drm_crtc.c | 32 ++ drivers/gpu/drm/i915/Makefile | 3 +- drivers/gpu/drm/i915/i915_drv.c | 17 + drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_reg.h | 58 +- drivers/gpu/drm/i915/intel_color_manager.c | 825 +++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_color_manager.h | 111 ++++ drivers/gpu/drm/i915/intel_display.c | 4 + drivers/gpu/drm/i915/intel_drv.h | 5 + include/drm/drm_crtc.h | 14 + include/uapi/drm/drm.h | 36 ++ 13 files changed, 1175 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_color_manager.c create mode 100644 drivers/gpu/drm/i915/intel_color_manager.h
Color Management is an extension to DRM framework. It allows abstraction of hardware color correction and enhancement capabilities by virtue of DRM properties.
There are two major types of color correction supported by DRM color manager: - CTM: color transformation matrix, properties where a correction matrix is used for color correction. - Palette correction: Where direct LUT values are sent to be applied on a color palette.
This patch initializes color management framework by: 1. Introducing new pointers in DRM mode_config structure to carry CTM and Palette color correction properties. 2. Creating these DRM properties in DRM standard properties creation sequence.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com --- drivers/gpu/drm/drm_crtc.c | 19 +++++++++++++++++++ include/drm/drm_crtc.h | 5 +++++ 2 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index e600a5f..30bd43d 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -1472,6 +1472,25 @@ static int drm_mode_create_standard_properties(struct drm_device *dev) return -ENOMEM; dev->mode_config.prop_mode_id = prop;
+ /* Color Management properties */ + prop = drm_property_create(dev, + DRM_MODE_PROP_BLOB, "PALETTE_AFTER_CTM", 0); + if (!prop) + return -ENOMEM; + dev->mode_config.cm_palette_after_ctm_property = prop; + + prop = drm_property_create(dev, + DRM_MODE_PROP_BLOB, "PALETTE_BEFORE_CTM", 0); + if (!prop) + return -ENOMEM; + dev->mode_config.cm_palette_before_ctm_property = prop; + + prop = drm_property_create(dev, + DRM_MODE_PROP_BLOB, "CTM", 0); + if (!prop) + return -ENOMEM; + dev->mode_config.cm_ctm_property = prop; + return 0; }
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 683f142..debd6c2 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -1146,6 +1146,11 @@ struct drm_mode_config { struct drm_property *suggested_x_property; struct drm_property *suggested_y_property;
+ /* Color Management Properties */ + struct drm_property *cm_palette_before_ctm_property; + struct drm_property *cm_palette_after_ctm_property; + struct drm_property *cm_ctm_property; + /* dumb ioctl parameters */ uint32_t preferred_depth, prefer_shadow;
Hi Shashank,
[auto build test WARNING on next-20151009 -- if it's inappropriate base, please ignore]
reproduce: make htmldocs
All warnings (new ones prefixed by >>):
drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'wedged' drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'fmt' include/drm/drm_crtc.h:310: warning: No description found for parameter 'mode_blob' include/drm/drm_crtc.h:742: warning: No description found for parameter 'tile_blob_ptr' include/drm/drm_crtc.h:781: warning: No description found for parameter 'rotation' include/drm/drm_crtc.h:877: warning: No description found for parameter 'mutex' include/drm/drm_crtc.h:877: warning: No description found for parameter 'helper_private' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'tile_idr' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'delayed_event' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'edid_property' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'dpms_property' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'path_property' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'tile_property' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'plane_type_property' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'rotation_property' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'prop_src_x' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'prop_src_y' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'prop_src_w' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'prop_src_h' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'prop_crtc_x' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'prop_crtc_y' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'prop_crtc_w' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'prop_crtc_h' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'prop_fb_id' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'prop_crtc_id' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'prop_active' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'prop_mode_id' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'dvi_i_subconnector_property' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'dvi_i_select_subconnector_property' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'tv_subconnector_property' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'tv_select_subconnector_property' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'tv_mode_property' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'tv_left_margin_property' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'tv_right_margin_property' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'tv_top_margin_property' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'tv_bottom_margin_property' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'tv_brightness_property' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'tv_contrast_property' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'tv_flicker_reduction_property' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'tv_overscan_property' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'tv_saturation_property' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'tv_hue_property' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'scaling_mode_property' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'aspect_ratio_property' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'dirty_info_property' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'suggested_x_property' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'suggested_y_property'
include/drm/drm_crtc.h:1167: warning: No description found for parameter 'cm_palette_before_ctm_property' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'cm_palette_after_ctm_property' include/drm/drm_crtc.h:1167: warning: No description found for parameter 'cm_ctm_property'
include/drm/drm_crtc.h:1167: warning: No description found for parameter 'allow_fb_modifiers' include/drm/drm_fb_helper.h:148: warning: No description found for parameter 'connector_info' include/drm/drm_dp_helper.h:713: warning: No description found for parameter 'i2c_nack_count' include/drm/drm_dp_helper.h:713: warning: No description found for parameter 'i2c_defer_count' drivers/gpu/drm/drm_dp_mst_topology.c:2226: warning: No description found for parameter 'connector' include/drm/drm_dp_mst_helper.h:97: warning: No description found for parameter 'cached_edid' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'max_dpcd_transaction_bytes' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'sink_count' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'total_slots' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'avail_slots' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'total_pbn' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'qlock' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'tx_msg_downq' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'tx_msg_upq' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'tx_down_in_progress' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'tx_up_in_progress' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'payload_lock' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'proposed_vcpis' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'payloads' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'payload_mask' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'vcpi_mask' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'tx_waitq' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'work' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'tx_work' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'destroy_connector_list' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'destroy_connector_lock' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'destroy_connector_work' drivers/gpu/drm/drm_dp_mst_topology.c:2226: warning: No description found for parameter 'connector' drivers/gpu/drm/drm_irq.c:173: warning: No description found for parameter 'flags' include/drm/drmP.h:164: warning: No description found for parameter 'fmt' include/drm/drmP.h:180: warning: No description found for parameter 'fmt' include/drm/drmP.h:198: warning: No description found for parameter 'fmt' include/drm/drmP.h:238: warning: No description found for parameter 'dev' include/drm/drmP.h:238: warning: No description found for parameter 'data' include/drm/drmP.h:238: warning: No description found for parameter 'file_priv' include/drm/drmP.h:271: warning: No description found for parameter 'ioctl' include/drm/drmP.h:271: warning: No description found for parameter '_func' include/drm/drmP.h:271: warning: No description found for parameter '_flags' include/drm/drmP.h:344: warning: cannot understand function prototype: 'struct drm_lock_data ' include/drm/drmP.h:397: warning: cannot understand function prototype: 'struct drm_driver ' include/drm/drmP.h:647: warning: cannot understand function prototype: 'struct drm_info_list ' include/drm/drmP.h:657: warning: cannot understand function prototype: 'struct drm_info_node ' include/drm/drmP.h:667: warning: cannot understand function prototype: 'struct drm_minor ' include/drm/drmP.h:715: warning: cannot understand function prototype: 'struct drm_device ' drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'wedged' drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'fmt' drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'wedged' drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'fmt' drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'wedged' drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'fmt' drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'wedged' drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'fmt' drivers/gpu/drm/i915/i915_gem.c:421: warning: No description found for parameter 'dev' drivers/gpu/drm/i915/i915_gem.c:421: warning: No description found for parameter 'data' drivers/gpu/drm/i915/i915_gem.c:421: warning: No description found for parameter 'file' drivers/gpu/drm/i915/i915_gem.c:686: warning: No description found for parameter 'dev' drivers/gpu/drm/i915/i915_gem.c:686: warning: No description found for parameter 'data' drivers/gpu/drm/i915/i915_gem.c:686: warning: No description found for parameter 'file' drivers/gpu/drm/i915/i915_gem.c:767: warning: No description found for parameter 'dev' drivers/gpu/drm/i915/i915_gem.c:767: warning: No description found for parameter 'obj' drivers/gpu/drm/i915/i915_gem.c:767: warning: No description found for parameter 'args' drivers/gpu/drm/i915/i915_gem.c:767: warning: No description found for parameter 'file' drivers/gpu/drm/i915/i915_gem.c:1029: warning: No description found for parameter 'dev' drivers/gpu/drm/i915/i915_gem.c:1029: warning: No description found for parameter 'data' drivers/gpu/drm/i915/i915_gem.c:1029: warning: No description found for parameter 'file' drivers/gpu/drm/i915/i915_gem.c:1194: warning: No description found for parameter 'rps' drivers/gpu/drm/i915/i915_gem.c:1400: warning: No description found for parameter 'req' drivers/gpu/drm/i915/i915_gem.c:1435: warning: No description found for parameter 'obj' drivers/gpu/drm/i915/i915_gem.c:1435: warning: No description found for parameter 'readonly' drivers/gpu/drm/i915/i915_gem.c:1558: warning: No description found for parameter 'dev' drivers/gpu/drm/i915/i915_gem.c:1558: warning: No description found for parameter 'data' drivers/gpu/drm/i915/i915_gem.c:1558: warning: No description found for parameter 'file' drivers/gpu/drm/i915/i915_gem.c:1621: warning: No description found for parameter 'dev' drivers/gpu/drm/i915/i915_gem.c:1621: warning: No description found for parameter 'data' drivers/gpu/drm/i915/i915_gem.c:1621: warning: No description found for parameter 'file' drivers/gpu/drm/i915/i915_gem.c:1666: warning: No description found for parameter 'dev' drivers/gpu/drm/i915/i915_gem.c:1666: warning: No description found for parameter 'data' drivers/gpu/drm/i915/i915_gem.c:1666: warning: No description found for parameter 'file' drivers/gpu/drm/i915/i915_gem.c:1954: warning: No description found for parameter 'dev' drivers/gpu/drm/i915/i915_gem.c:1954: warning: No description found for parameter 'size' drivers/gpu/drm/i915/i915_gem.c:1954: warning: No description found for parameter 'tiling_mode' drivers/gpu/drm/i915/i915_gem.c:1954: warning: No description found for parameter 'fenced' drivers/gpu/drm/i915/i915_gem.c:1954: warning: Excess function parameter 'obj' description in 'i915_gem_get_gtt_alignment' drivers/gpu/drm/i915/i915_gem.c:2816: warning: No description found for parameter 'ring' drivers/gpu/drm/i915/i915_gem.c:2945: warning: No description found for parameter 'obj' drivers/gpu/drm/i915/i915_gem.c:2995: warning: No description found for parameter 'dev' drivers/gpu/drm/i915/i915_gem.c:2995: warning: No description found for parameter 'data' drivers/gpu/drm/i915/i915_gem.c:2995: warning: No description found for parameter 'file' drivers/gpu/drm/i915/i915_gem.c:2995: warning: Excess function parameter 'DRM_IOCTL_ARGS' description in 'i915_gem_wait_ioctl' drivers/gpu/drm/i915/i915_gem.c:3364: warning: No description found for parameter 'obj' drivers/gpu/drm/i915/i915_gem.c:3364: warning: No description found for parameter 'vm' drivers/gpu/drm/i915/i915_gem.c:3364: warning: No description found for parameter 'ggtt_view' drivers/gpu/drm/i915/i915_gem.c:3364: warning: No description found for parameter 'alignment' drivers/gpu/drm/i915/i915_gem.c:3364: warning: No description found for parameter 'flags' drivers/gpu/drm/i915/i915_gem.c:3599: warning: No description found for parameter 'obj' drivers/gpu/drm/i915/i915_gem.c:3599: warning: No description found for parameter 'write' drivers/gpu/drm/i915/i915_gem.c:3891: warning: No description found for parameter 'obj' drivers/gpu/drm/i915/i915_gem.c:3891: warning: No description found for parameter 'write' drivers/gpu/drm/i915/intel_lrc.c:871: warning: No description found for parameter 'params' drivers/gpu/drm/i915/intel_lrc.c:871: warning: Excess function parameter 'dev' description in 'intel_execlists_submission'
vim +/cm_palette_before_ctm_property +1167 include/drm/drm_crtc.h
9302c2fa Shashank Sharma 2015-10-10 1151 /* Color Management Properties */ 9302c2fa Shashank Sharma 2015-10-10 1152 struct drm_property *cm_palette_before_ctm_property; 9302c2fa Shashank Sharma 2015-10-10 1153 struct drm_property *cm_palette_after_ctm_property; 9302c2fa Shashank Sharma 2015-10-10 1154 struct drm_property *cm_ctm_property; 9302c2fa Shashank Sharma 2015-10-10 1155 019d96cb Dave Airlie 2011-09-29 1156 /* dumb ioctl parameters */ 019d96cb Dave Airlie 2011-09-29 1157 uint32_t preferred_depth, prefer_shadow; 62f2104f Keith Packard 2013-07-22 1158 62f2104f Keith Packard 2013-07-22 1159 /* whether async page flip is supported or not */ 62f2104f Keith Packard 2013-07-22 1160 bool async_page_flip; 8716ed4e Alex Deucher 2014-02-12 1161 e3eb3250 Rob Clark 2015-02-05 1162 /* whether the driver supports fb modifiers */ e3eb3250 Rob Clark 2015-02-05 1163 bool allow_fb_modifiers; e3eb3250 Rob Clark 2015-02-05 1164 8716ed4e Alex Deucher 2014-02-12 1165 /* cursor size */ 8716ed4e Alex Deucher 2014-02-12 1166 uint32_t cursor_width, cursor_height; f453ba04 Dave Airlie 2008-11-07 @1167 }; f453ba04 Dave Airlie 2008-11-07 1168 dd275956 Rob Clark 2014-11-25 1169 /** dd275956 Rob Clark 2014-11-25 1170 * drm_for_each_plane_mask - iterate over planes specified by bitmask dd275956 Rob Clark 2014-11-25 1171 * @plane: the loop cursor dd275956 Rob Clark 2014-11-25 1172 * @dev: the DRM device dd275956 Rob Clark 2014-11-25 1173 * @plane_mask: bitmask of plane indices dd275956 Rob Clark 2014-11-25 1174 * dd275956 Rob Clark 2014-11-25 1175 * Iterate over all planes specified by bitmask.
:::::: The code at line 1167 was first introduced by commit :::::: f453ba0460742ad027ae0c4c7d61e62817b3e7ef DRM: add mode setting support
:::::: TO: Dave Airlie airlied@redhat.com :::::: CC: Dave Airlie airlied@linux.ie
--- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
DRM color management is written to extract the color correction capabilities of various platforms, and every platform can showcase its capabilities using the query properties.
Different hardwares can have different no of coefficients for palette correction. Also the correction can be applied after/before color transformation (CTM) unit in the display pipeline.
This patch adds two new read-only properties, - cm_coeff_before_ctm_property: A platform driver should use this property to show supported no_of_coefficients for palette correction, which gets applied before ctm correction. - cm_coeff_after_ctm_property: A platform driver should use this property to show supported no_of_coefficients for palette correction, which gets applied after ctm correction.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com --- drivers/gpu/drm/drm_crtc.c | 13 +++++++++++++ include/drm/drm_crtc.h | 4 ++++ 2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index 30bd43d..76abeca 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -1491,6 +1491,19 @@ static int drm_mode_create_standard_properties(struct drm_device *dev) return -ENOMEM; dev->mode_config.cm_ctm_property = prop;
+ /* DRM properties to query color capabilities */ + prop = drm_property_create(dev, DRM_MODE_PROP_IMMUTABLE, + "COEFFICIENTS_BEFORE_CTM", 0); + if (!prop) + return -ENOMEM; + dev->mode_config.cm_coeff_before_ctm_property = prop; + + prop = drm_property_create(dev, DRM_MODE_PROP_IMMUTABLE, + "COEFFICIENTS_AFTER_CTM", 0); + if (!prop) + return -ENOMEM; + dev->mode_config.cm_coeff_after_ctm_property = prop; + return 0; }
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index debd6c2..6e0f177 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -1151,6 +1151,10 @@ struct drm_mode_config { struct drm_property *cm_palette_after_ctm_property; struct drm_property *cm_ctm_property;
+ /* Coor management capabilities query */ + struct drm_property *cm_coeff_before_ctm_property; + struct drm_property *cm_coeff_after_ctm_property; + /* dumb ioctl parameters */ uint32_t preferred_depth, prefer_shadow;
Hi Shashank,
[auto build test WARNING on next-20151009 -- if it's inappropriate base, please ignore]
reproduce: make htmldocs
All warnings (new ones prefixed by >>):
drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'wedged' drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'fmt' include/drm/drm_crtc.h:310: warning: No description found for parameter 'mode_blob' include/drm/drm_crtc.h:742: warning: No description found for parameter 'tile_blob_ptr' include/drm/drm_crtc.h:781: warning: No description found for parameter 'rotation' include/drm/drm_crtc.h:877: warning: No description found for parameter 'mutex' include/drm/drm_crtc.h:877: warning: No description found for parameter 'helper_private' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'tile_idr' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'delayed_event' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'edid_property' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'dpms_property' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'path_property' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'tile_property' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'plane_type_property' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'rotation_property' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'prop_src_x' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'prop_src_y' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'prop_src_w' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'prop_src_h' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'prop_crtc_x' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'prop_crtc_y' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'prop_crtc_w' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'prop_crtc_h' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'prop_fb_id' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'prop_crtc_id' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'prop_active' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'prop_mode_id' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'dvi_i_subconnector_property' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'dvi_i_select_subconnector_property' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'tv_subconnector_property' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'tv_select_subconnector_property' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'tv_mode_property' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'tv_left_margin_property' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'tv_right_margin_property' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'tv_top_margin_property' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'tv_bottom_margin_property' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'tv_brightness_property' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'tv_contrast_property' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'tv_flicker_reduction_property' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'tv_overscan_property' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'tv_saturation_property' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'tv_hue_property' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'scaling_mode_property' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'aspect_ratio_property' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'dirty_info_property' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'suggested_x_property' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'suggested_y_property' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'cm_palette_before_ctm_property' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'cm_palette_after_ctm_property' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'cm_ctm_property'
include/drm/drm_crtc.h:1171: warning: No description found for parameter 'cm_coeff_before_ctm_property' include/drm/drm_crtc.h:1171: warning: No description found for parameter 'cm_coeff_after_ctm_property'
include/drm/drm_crtc.h:1171: warning: No description found for parameter 'allow_fb_modifiers' include/drm/drm_fb_helper.h:148: warning: No description found for parameter 'connector_info' include/drm/drm_dp_helper.h:713: warning: No description found for parameter 'i2c_nack_count' include/drm/drm_dp_helper.h:713: warning: No description found for parameter 'i2c_defer_count' drivers/gpu/drm/drm_dp_mst_topology.c:2226: warning: No description found for parameter 'connector' include/drm/drm_dp_mst_helper.h:97: warning: No description found for parameter 'cached_edid' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'max_dpcd_transaction_bytes' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'sink_count' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'total_slots' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'avail_slots' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'total_pbn' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'qlock' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'tx_msg_downq' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'tx_msg_upq' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'tx_down_in_progress' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'tx_up_in_progress' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'payload_lock' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'proposed_vcpis' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'payloads' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'payload_mask' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'vcpi_mask' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'tx_waitq' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'work' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'tx_work' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'destroy_connector_list' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'destroy_connector_lock' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'destroy_connector_work' drivers/gpu/drm/drm_dp_mst_topology.c:2226: warning: No description found for parameter 'connector' drivers/gpu/drm/drm_irq.c:173: warning: No description found for parameter 'flags' include/drm/drmP.h:164: warning: No description found for parameter 'fmt' include/drm/drmP.h:180: warning: No description found for parameter 'fmt' include/drm/drmP.h:198: warning: No description found for parameter 'fmt' include/drm/drmP.h:238: warning: No description found for parameter 'dev' include/drm/drmP.h:238: warning: No description found for parameter 'data' include/drm/drmP.h:238: warning: No description found for parameter 'file_priv' include/drm/drmP.h:271: warning: No description found for parameter 'ioctl' include/drm/drmP.h:271: warning: No description found for parameter '_func' include/drm/drmP.h:271: warning: No description found for parameter '_flags' include/drm/drmP.h:344: warning: cannot understand function prototype: 'struct drm_lock_data ' include/drm/drmP.h:397: warning: cannot understand function prototype: 'struct drm_driver ' include/drm/drmP.h:647: warning: cannot understand function prototype: 'struct drm_info_list ' include/drm/drmP.h:657: warning: cannot understand function prototype: 'struct drm_info_node ' include/drm/drmP.h:667: warning: cannot understand function prototype: 'struct drm_minor ' include/drm/drmP.h:715: warning: cannot understand function prototype: 'struct drm_device ' drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'wedged' drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'fmt' drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'wedged' drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'fmt' drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'wedged' drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'fmt' drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'wedged' drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'fmt' drivers/gpu/drm/i915/i915_gem.c:421: warning: No description found for parameter 'dev' drivers/gpu/drm/i915/i915_gem.c:421: warning: No description found for parameter 'data' drivers/gpu/drm/i915/i915_gem.c:421: warning: No description found for parameter 'file' drivers/gpu/drm/i915/i915_gem.c:686: warning: No description found for parameter 'dev' drivers/gpu/drm/i915/i915_gem.c:686: warning: No description found for parameter 'data' drivers/gpu/drm/i915/i915_gem.c:686: warning: No description found for parameter 'file' drivers/gpu/drm/i915/i915_gem.c:767: warning: No description found for parameter 'dev' drivers/gpu/drm/i915/i915_gem.c:767: warning: No description found for parameter 'obj' drivers/gpu/drm/i915/i915_gem.c:767: warning: No description found for parameter 'args' drivers/gpu/drm/i915/i915_gem.c:767: warning: No description found for parameter 'file' drivers/gpu/drm/i915/i915_gem.c:1029: warning: No description found for parameter 'dev' drivers/gpu/drm/i915/i915_gem.c:1029: warning: No description found for parameter 'data' drivers/gpu/drm/i915/i915_gem.c:1029: warning: No description found for parameter 'file' drivers/gpu/drm/i915/i915_gem.c:1194: warning: No description found for parameter 'rps' drivers/gpu/drm/i915/i915_gem.c:1400: warning: No description found for parameter 'req' drivers/gpu/drm/i915/i915_gem.c:1435: warning: No description found for parameter 'obj' drivers/gpu/drm/i915/i915_gem.c:1435: warning: No description found for parameter 'readonly' drivers/gpu/drm/i915/i915_gem.c:1558: warning: No description found for parameter 'dev' drivers/gpu/drm/i915/i915_gem.c:1558: warning: No description found for parameter 'data' drivers/gpu/drm/i915/i915_gem.c:1558: warning: No description found for parameter 'file' drivers/gpu/drm/i915/i915_gem.c:1621: warning: No description found for parameter 'dev' drivers/gpu/drm/i915/i915_gem.c:1621: warning: No description found for parameter 'data' drivers/gpu/drm/i915/i915_gem.c:1621: warning: No description found for parameter 'file' drivers/gpu/drm/i915/i915_gem.c:1666: warning: No description found for parameter 'dev' drivers/gpu/drm/i915/i915_gem.c:1666: warning: No description found for parameter 'data' drivers/gpu/drm/i915/i915_gem.c:1666: warning: No description found for parameter 'file' drivers/gpu/drm/i915/i915_gem.c:1954: warning: No description found for parameter 'dev' drivers/gpu/drm/i915/i915_gem.c:1954: warning: No description found for parameter 'size' drivers/gpu/drm/i915/i915_gem.c:1954: warning: No description found for parameter 'tiling_mode' drivers/gpu/drm/i915/i915_gem.c:1954: warning: No description found for parameter 'fenced' drivers/gpu/drm/i915/i915_gem.c:1954: warning: Excess function parameter 'obj' description in 'i915_gem_get_gtt_alignment' drivers/gpu/drm/i915/i915_gem.c:2816: warning: No description found for parameter 'ring' drivers/gpu/drm/i915/i915_gem.c:2945: warning: No description found for parameter 'obj' drivers/gpu/drm/i915/i915_gem.c:2995: warning: No description found for parameter 'dev' drivers/gpu/drm/i915/i915_gem.c:2995: warning: No description found for parameter 'data' drivers/gpu/drm/i915/i915_gem.c:2995: warning: No description found for parameter 'file' drivers/gpu/drm/i915/i915_gem.c:2995: warning: Excess function parameter 'DRM_IOCTL_ARGS' description in 'i915_gem_wait_ioctl' drivers/gpu/drm/i915/i915_gem.c:3364: warning: No description found for parameter 'obj' drivers/gpu/drm/i915/i915_gem.c:3364: warning: No description found for parameter 'vm' drivers/gpu/drm/i915/i915_gem.c:3364: warning: No description found for parameter 'ggtt_view' drivers/gpu/drm/i915/i915_gem.c:3364: warning: No description found for parameter 'alignment' drivers/gpu/drm/i915/i915_gem.c:3364: warning: No description found for parameter 'flags' drivers/gpu/drm/i915/i915_gem.c:3599: warning: No description found for parameter 'obj' drivers/gpu/drm/i915/i915_gem.c:3599: warning: No description found for parameter 'write' drivers/gpu/drm/i915/i915_gem.c:3891: warning: No description found for parameter 'obj' drivers/gpu/drm/i915/i915_gem.c:3891: warning: No description found for parameter 'write' drivers/gpu/drm/i915/intel_lrc.c:871: warning: No description found for parameter 'params' drivers/gpu/drm/i915/intel_lrc.c:871: warning: Excess function parameter 'dev' description in 'intel_execlists_submission'
vim +/cm_coeff_before_ctm_property +1171 include/drm/drm_crtc.h
9302c2fa Shashank Sharma 2015-10-10 1155 e508eb9a Shashank Sharma 2015-10-10 1156 /* Coor management capabilities query */ e508eb9a Shashank Sharma 2015-10-10 1157 struct drm_property *cm_coeff_before_ctm_property; e508eb9a Shashank Sharma 2015-10-10 1158 struct drm_property *cm_coeff_after_ctm_property; e508eb9a Shashank Sharma 2015-10-10 1159 019d96cb Dave Airlie 2011-09-29 1160 /* dumb ioctl parameters */ 019d96cb Dave Airlie 2011-09-29 1161 uint32_t preferred_depth, prefer_shadow; 62f2104f Keith Packard 2013-07-22 1162 62f2104f Keith Packard 2013-07-22 1163 /* whether async page flip is supported or not */ 62f2104f Keith Packard 2013-07-22 1164 bool async_page_flip; 8716ed4e Alex Deucher 2014-02-12 1165 e3eb3250 Rob Clark 2015-02-05 1166 /* whether the driver supports fb modifiers */ e3eb3250 Rob Clark 2015-02-05 1167 bool allow_fb_modifiers; e3eb3250 Rob Clark 2015-02-05 1168 8716ed4e Alex Deucher 2014-02-12 1169 /* cursor size */ 8716ed4e Alex Deucher 2014-02-12 1170 uint32_t cursor_width, cursor_height; f453ba04 Dave Airlie 2008-11-07 @1171 }; f453ba04 Dave Airlie 2008-11-07 1172 dd275956 Rob Clark 2014-11-25 1173 /** dd275956 Rob Clark 2014-11-25 1174 * drm_for_each_plane_mask - iterate over planes specified by bitmask dd275956 Rob Clark 2014-11-25 1175 * @plane: the loop cursor dd275956 Rob Clark 2014-11-25 1176 * @dev: the DRM device dd275956 Rob Clark 2014-11-25 1177 * @plane_mask: bitmask of plane indices dd275956 Rob Clark 2014-11-25 1178 * dd275956 Rob Clark 2014-11-25 1179 * Iterate over all planes specified by bitmask.
:::::: The code at line 1171 was first introduced by commit :::::: f453ba0460742ad027ae0c4c7d61e62817b3e7ef DRM: add mode setting support
:::::: TO: Dave Airlie airlied@redhat.com :::::: CC: Dave Airlie airlied@linux.ie
--- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
This patch adds new variables in CRTC state, to hold respective color correction blobs. These blobs will be required during the atomic commit for writing the color correction values in correction registers.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com --- drivers/gpu/drm/drm_atomic_helper.c | 12 ++++++++++++ include/drm/drm_crtc.h | 7 ++++++- 2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index 87a2a44..d73ca9b9 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -2193,6 +2193,12 @@ void __drm_atomic_helper_crtc_duplicate_state(struct drm_crtc *crtc,
if (state->mode_blob) drm_property_reference_blob(state->mode_blob); + if (state->ctm_blob) + drm_property_reference_blob(state->ctm_blob); + if (state->palette_after_ctm_blob) + drm_property_reference_blob(state->palette_after_ctm_blob); + if (state->palette_before_ctm_blob) + drm_property_reference_blob(state->palette_before_ctm_blob); state->mode_changed = false; state->active_changed = false; state->planes_changed = false; @@ -2238,6 +2244,12 @@ void __drm_atomic_helper_crtc_destroy_state(struct drm_crtc *crtc, { if (state->mode_blob) drm_property_unreference_blob(state->mode_blob); + if (state->ctm_blob) + drm_property_unreference_blob(state->ctm_blob); + if (state->palette_after_ctm_blob) + drm_property_unreference_blob(state->palette_after_ctm_blob); + if (state->palette_before_ctm_blob) + drm_property_unreference_blob(state->palette_before_ctm_blob); } EXPORT_SYMBOL(__drm_atomic_helper_crtc_destroy_state);
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 6e0f177..9cd4123 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -302,6 +302,11 @@ struct drm_crtc_state { /* blob property to expose current mode to atomic userspace */ struct drm_property_blob *mode_blob;
+ /* blob properties to hold the color properties' blobs */ + struct drm_property_blob *palette_before_ctm_blob; + struct drm_property_blob *palette_after_ctm_blob; + struct drm_property_blob *ctm_blob; + struct drm_pending_vblank_event *event;
struct drm_atomic_state *state; @@ -1151,7 +1156,7 @@ struct drm_mode_config { struct drm_property *cm_palette_after_ctm_property; struct drm_property *cm_ctm_property;
- /* Coor management capabilities query */ + /* Color management capabilities query */ struct drm_property *cm_coeff_before_ctm_property; struct drm_property *cm_coeff_after_ctm_property;
Hi Shashank,
[auto build test WARNING on next-20151009 -- if it's inappropriate base, please ignore]
reproduce: make htmldocs
All warnings (new ones prefixed by >>):
drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'wedged' drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'fmt' include/drm/drm_crtc.h:315: warning: No description found for parameter 'mode_blob'
include/drm/drm_crtc.h:315: warning: No description found for parameter 'palette_before_ctm_blob' include/drm/drm_crtc.h:315: warning: No description found for parameter 'palette_after_ctm_blob' include/drm/drm_crtc.h:315: warning: No description found for parameter 'ctm_blob'
include/drm/drm_crtc.h:747: warning: No description found for parameter 'tile_blob_ptr' include/drm/drm_crtc.h:786: warning: No description found for parameter 'rotation' include/drm/drm_crtc.h:882: warning: No description found for parameter 'mutex' include/drm/drm_crtc.h:882: warning: No description found for parameter 'helper_private' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'tile_idr' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'delayed_event' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'edid_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'dpms_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'path_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'tile_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'plane_type_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'rotation_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'prop_src_x' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'prop_src_y' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'prop_src_w' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'prop_src_h' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'prop_crtc_x' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'prop_crtc_y' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'prop_crtc_w' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'prop_crtc_h' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'prop_fb_id' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'prop_crtc_id' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'prop_active' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'prop_mode_id' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'dvi_i_subconnector_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'dvi_i_select_subconnector_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'tv_subconnector_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'tv_select_subconnector_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'tv_mode_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'tv_left_margin_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'tv_right_margin_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'tv_top_margin_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'tv_bottom_margin_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'tv_brightness_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'tv_contrast_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'tv_flicker_reduction_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'tv_overscan_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'tv_saturation_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'tv_hue_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'scaling_mode_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'aspect_ratio_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'dirty_info_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'suggested_x_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'suggested_y_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'cm_palette_before_ctm_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'cm_palette_after_ctm_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'cm_ctm_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'cm_coeff_before_ctm_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'cm_coeff_after_ctm_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'allow_fb_modifiers' include/drm/drm_fb_helper.h:148: warning: No description found for parameter 'connector_info' include/drm/drm_dp_helper.h:713: warning: No description found for parameter 'i2c_nack_count' include/drm/drm_dp_helper.h:713: warning: No description found for parameter 'i2c_defer_count' drivers/gpu/drm/drm_dp_mst_topology.c:2226: warning: No description found for parameter 'connector' include/drm/drm_dp_mst_helper.h:97: warning: No description found for parameter 'cached_edid' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'max_dpcd_transaction_bytes' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'sink_count' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'total_slots' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'avail_slots' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'total_pbn' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'qlock' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'tx_msg_downq' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'tx_msg_upq' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'tx_down_in_progress' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'tx_up_in_progress' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'payload_lock' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'proposed_vcpis' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'payloads' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'payload_mask' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'vcpi_mask' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'tx_waitq' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'work' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'tx_work' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'destroy_connector_list' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'destroy_connector_lock' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'destroy_connector_work' drivers/gpu/drm/drm_dp_mst_topology.c:2226: warning: No description found for parameter 'connector' drivers/gpu/drm/drm_irq.c:173: warning: No description found for parameter 'flags' include/drm/drmP.h:164: warning: No description found for parameter 'fmt' include/drm/drmP.h:180: warning: No description found for parameter 'fmt' include/drm/drmP.h:198: warning: No description found for parameter 'fmt' include/drm/drmP.h:238: warning: No description found for parameter 'dev' include/drm/drmP.h:238: warning: No description found for parameter 'data' include/drm/drmP.h:238: warning: No description found for parameter 'file_priv' include/drm/drmP.h:271: warning: No description found for parameter 'ioctl' include/drm/drmP.h:271: warning: No description found for parameter '_func' include/drm/drmP.h:271: warning: No description found for parameter '_flags' include/drm/drmP.h:344: warning: cannot understand function prototype: 'struct drm_lock_data ' include/drm/drmP.h:397: warning: cannot understand function prototype: 'struct drm_driver ' include/drm/drmP.h:647: warning: cannot understand function prototype: 'struct drm_info_list ' include/drm/drmP.h:657: warning: cannot understand function prototype: 'struct drm_info_node ' include/drm/drmP.h:667: warning: cannot understand function prototype: 'struct drm_minor ' include/drm/drmP.h:715: warning: cannot understand function prototype: 'struct drm_device ' drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'wedged' drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'fmt' drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'wedged' drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'fmt' drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'wedged' drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'fmt' drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'wedged'
vim +/palette_before_ctm_blob +315 include/drm/drm_crtc.h
2f324b42 Daniel Vetter 2014-10-29 299 /* adjusted_mode: for use by helpers and drivers */ 2f324b42 Daniel Vetter 2014-10-29 300 struct drm_display_mode adjusted_mode; 2f324b42 Daniel Vetter 2014-10-29 301 144ecb97 Daniel Vetter 2014-10-27 302 struct drm_display_mode mode; 144ecb97 Daniel Vetter 2014-10-27 303 99cf4a29 Daniel Stone 2015-05-25 304 /* blob property to expose current mode to atomic userspace */ 99cf4a29 Daniel Stone 2015-05-25 305 struct drm_property_blob *mode_blob; 99cf4a29 Daniel Stone 2015-05-25 306 076c6f91 Shashank Sharma 2015-10-10 307 /* blob properties to hold the color properties' blobs */ 076c6f91 Shashank Sharma 2015-10-10 308 struct drm_property_blob *palette_before_ctm_blob; 076c6f91 Shashank Sharma 2015-10-10 309 struct drm_property_blob *palette_after_ctm_blob; 076c6f91 Shashank Sharma 2015-10-10 310 struct drm_property_blob *ctm_blob; 076c6f91 Shashank Sharma 2015-10-10 311 144ecb97 Daniel Vetter 2014-10-27 312 struct drm_pending_vblank_event *event; 144ecb97 Daniel Vetter 2014-10-27 313 144ecb97 Daniel Vetter 2014-10-27 314 struct drm_atomic_state *state; 144ecb97 Daniel Vetter 2014-10-27 @315 }; f453ba04 Dave Airlie 2008-11-07 316 f453ba04 Dave Airlie 2008-11-07 317 /** 3bf0401c Daniel Vetter 2014-10-27 318 * struct drm_crtc_funcs - control CRTCs for a given device f453ba04 Dave Airlie 2008-11-07 319 * @save: save CRTC state 3b02ab88 Laurent Pinchart 2012-05-17 320 * @restore: restore CRTC state 715f59cc Christopher Harvey 2013-04-05 321 * @reset: reset CRTC after state has been invalidated (e.g. resume) 3b02ab88 Laurent Pinchart 2012-05-17 322 * @cursor_set: setup the cursor 2c0c33d4 Daniel Vetter 2014-10-27 323 * @cursor_set2: setup the cursor with hotspot, superseeds @cursor_set if set
:::::: The code at line 315 was first introduced by commit :::::: 144ecb97cd57d2a61cc455730a3337e413499cae drm: Add atomic driver interface definitions for objects
:::::: TO: Daniel Vetter daniel.vetter@ffwll.ch :::::: CC: Daniel Vetter daniel.vetter@ffwll.ch
--- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
Hi Shashank,
On 9 October 2015 at 20:28, Shashank Sharma shashank.sharma@intel.com wrote:
This patch adds new variables in CRTC state, to hold respective color correction blobs. These blobs will be required during the atomic commit for writing the color correction values in correction registers.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com
drivers/gpu/drm/drm_atomic_helper.c | 12 ++++++++++++ include/drm/drm_crtc.h | 7 ++++++- 2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index 87a2a44..d73ca9b9 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -2193,6 +2193,12 @@ void __drm_atomic_helper_crtc_duplicate_state(struct drm_crtc *crtc,
if (state->mode_blob) drm_property_reference_blob(state->mode_blob);
if (state->ctm_blob)drm_property_reference_blob(state->ctm_blob);if (state->palette_after_ctm_blob)drm_property_reference_blob(state->palette_after_ctm_blob);if (state->palette_before_ctm_blob)drm_property_reference_blob(state->palette_before_ctm_blob); state->mode_changed = false; state->active_changed = false; state->planes_changed = false;@@ -2238,6 +2244,12 @@ void __drm_atomic_helper_crtc_destroy_state(struct drm_crtc *crtc, { if (state->mode_blob) drm_property_unreference_blob(state->mode_blob);
if (state->ctm_blob)drm_property_unreference_blob(state->ctm_blob);if (state->palette_after_ctm_blob)drm_property_unreference_blob(state->palette_after_ctm_blob);if (state->palette_before_ctm_blob)drm_property_unreference_blob(state->palette_before_ctm_blob);} EXPORT_SYMBOL(__drm_atomic_helper_crtc_destroy_state);
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 6e0f177..9cd4123 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -302,6 +302,11 @@ struct drm_crtc_state { /* blob property to expose current mode to atomic userspace */ struct drm_property_blob *mode_blob;
/* blob properties to hold the color properties' blobs */struct drm_property_blob *palette_before_ctm_blob;struct drm_property_blob *palette_after_ctm_blob;struct drm_property_blob *ctm_blob;struct drm_pending_vblank_event *event; struct drm_atomic_state *state;@@ -1151,7 +1156,7 @@ struct drm_mode_config { struct drm_property *cm_palette_after_ctm_property; struct drm_property *cm_ctm_property;
/* Coor management capabilities query */
/* Color management capabilities query */
This should be part of the previous patch.
Regards, Emil
Thanks for the review comments, Emil.
Regards Shashank On 10/10/2015 3:53 AM, Emil Velikov wrote:
Hi Shashank,
On 9 October 2015 at 20:28, Shashank Sharma shashank.sharma@intel.com wrote:
This patch adds new variables in CRTC state, to hold respective color correction blobs. These blobs will be required during the atomic commit for writing the color correction values in correction registers.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com
drivers/gpu/drm/drm_atomic_helper.c | 12 ++++++++++++ include/drm/drm_crtc.h | 7 ++++++- 2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index 87a2a44..d73ca9b9 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -2193,6 +2193,12 @@ void __drm_atomic_helper_crtc_duplicate_state(struct drm_crtc *crtc,
if (state->mode_blob) drm_property_reference_blob(state->mode_blob);
if (state->ctm_blob)drm_property_reference_blob(state->ctm_blob);if (state->palette_after_ctm_blob)drm_property_reference_blob(state->palette_after_ctm_blob);if (state->palette_before_ctm_blob)drm_property_reference_blob(state->palette_before_ctm_blob); state->mode_changed = false; state->active_changed = false; state->planes_changed = false;@@ -2238,6 +2244,12 @@ void __drm_atomic_helper_crtc_destroy_state(struct drm_crtc *crtc, { if (state->mode_blob) drm_property_unreference_blob(state->mode_blob);
if (state->ctm_blob)drm_property_unreference_blob(state->ctm_blob);if (state->palette_after_ctm_blob)drm_property_unreference_blob(state->palette_after_ctm_blob);if (state->palette_before_ctm_blob)drm_property_unreference_blob(state->palette_before_ctm_blob);diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 6e0f177..9cd4123 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -302,6 +302,11 @@ struct drm_crtc_state { /* blob property to expose current mode to atomic userspace */ struct drm_property_blob *mode_blob;
/* blob properties to hold the color properties' blobs */struct drm_property_blob *palette_before_ctm_blob;struct drm_property_blob *palette_after_ctm_blob;struct drm_property_blob *ctm_blob;struct drm_pending_vblank_event *event; struct drm_atomic_state *state;@@ -1151,7 +1156,7 @@ struct drm_mode_config { struct drm_property *cm_palette_after_ctm_property; struct drm_property *cm_ctm_property;
/* Coor management capabilities query */
/* Color management capabilities query */This should be part of the previous patch.
Agree, will do it.
Regards, Emil
As per DRM color manager design, if a userspace wants to set a correction blob, it prepares it and sends the blob_id to kernel via set_property call. DRM framework takes this blob_id, gets the blob, and saves it in the CRTC state, so that, during the atomic_commit, the color correction values from the blob can referred and applied on display controller registers.
This patch adds this set_property support for color correction blobs in drm framework.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal malladi kausalmalladi@gmail.com --- drivers/gpu/drm/drm_atomic.c | 53 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 51 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index 7bb3845..0b286d2 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -390,6 +390,38 @@ int drm_atomic_set_mode_prop_for_crtc(struct drm_crtc_state *state, EXPORT_SYMBOL(drm_atomic_set_mode_prop_for_crtc);
/** + * drm_atomic_crtc_set_blob - find and set a blob + * @state_blob: reference pointer to the color blob in the crtc_state + * @blob_id: blob_id coming from set_property() call + * + * Set a color correction blob (originating from a set blob property) on the + * desired CRTC state. This function will take reference of the blob property + * in the CRTC state, finds the blob based on blob_id (which comes from + * set_property call) and set the blob at the proper place. + * + * RETURNS: + * Zero on success, error code on failure. + */ +int drm_atomic_crtc_set_blob(struct drm_device *dev, + struct drm_property_blob **state_blob, uint32_t blob_id) +{ + struct drm_property_blob *blob; + + blob = drm_property_lookup_blob(dev, blob_id); + if (!blob) { + DRM_DEBUG_KMS("Invalid Blob ID\n"); + return -EINVAL; + } + + if (*state_blob) + drm_property_unreference_blob(*state_blob); + + /* Attach the blob to be committed in state */ + *state_blob = blob; + return 0; +} + +/** * drm_atomic_crtc_set_property - set property on CRTC * @crtc: the drm CRTC to set a property on * @state: the state object to update with the new property value @@ -422,8 +454,25 @@ int drm_atomic_crtc_set_property(struct drm_crtc *crtc, if (mode) drm_property_unreference_blob(mode); return ret; - } - else if (crtc->funcs->atomic_set_property) + } else if (property == config->cm_palette_after_ctm_property) { + ret = drm_atomic_crtc_set_blob(dev, + &state->palette_after_ctm_blob, val); + if (ret) + DRM_ERROR("Failed to load blob palette_after_ctm\n"); + return ret; + } else if (property == config->cm_palette_before_ctm_property) { + ret = drm_atomic_crtc_set_blob(dev, + &state->palette_before_ctm_blob, val); + if (ret) + DRM_ERROR("Failed to load blob palette_before_ctm\n"); + return ret; + } else if (property == config->cm_ctm_property) { + ret = drm_atomic_crtc_set_blob(dev, + &state->ctm_blob, val); + if (ret) + DRM_ERROR("Failed to load blob ctm\n"); + return ret; + } else if (crtc->funcs->atomic_set_property) return crtc->funcs->atomic_set_property(crtc, state, property, val); else return -EINVAL;
Hi Shashank,
[auto build test WARNING on next-20151009 -- if it's inappropriate base, please ignore]
reproduce: make htmldocs
All warnings (new ones prefixed by >>):
drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'wedged' drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'fmt'
drivers/gpu/drm/drm_atomic.c:407: warning: No description found for parameter 'dev'
include/drm/drm_crtc.h:315: warning: No description found for parameter 'mode_blob' include/drm/drm_crtc.h:315: warning: No description found for parameter 'palette_before_ctm_blob' include/drm/drm_crtc.h:315: warning: No description found for parameter 'palette_after_ctm_blob' include/drm/drm_crtc.h:315: warning: No description found for parameter 'ctm_blob' include/drm/drm_crtc.h:747: warning: No description found for parameter 'tile_blob_ptr' include/drm/drm_crtc.h:786: warning: No description found for parameter 'rotation' include/drm/drm_crtc.h:882: warning: No description found for parameter 'mutex' include/drm/drm_crtc.h:882: warning: No description found for parameter 'helper_private' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'tile_idr' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'delayed_event' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'edid_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'dpms_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'path_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'tile_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'plane_type_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'rotation_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'prop_src_x' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'prop_src_y' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'prop_src_w' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'prop_src_h' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'prop_crtc_x' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'prop_crtc_y' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'prop_crtc_w' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'prop_crtc_h' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'prop_fb_id' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'prop_crtc_id' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'prop_active' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'prop_mode_id' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'dvi_i_subconnector_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'dvi_i_select_subconnector_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'tv_subconnector_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'tv_select_subconnector_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'tv_mode_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'tv_left_margin_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'tv_right_margin_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'tv_top_margin_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'tv_bottom_margin_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'tv_brightness_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'tv_contrast_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'tv_flicker_reduction_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'tv_overscan_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'tv_saturation_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'tv_hue_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'scaling_mode_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'aspect_ratio_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'dirty_info_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'suggested_x_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'suggested_y_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'cm_palette_before_ctm_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'cm_palette_after_ctm_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'cm_ctm_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'cm_coeff_before_ctm_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'cm_coeff_after_ctm_property' include/drm/drm_crtc.h:1176: warning: No description found for parameter 'allow_fb_modifiers' include/drm/drm_fb_helper.h:148: warning: No description found for parameter 'connector_info' include/drm/drm_dp_helper.h:713: warning: No description found for parameter 'i2c_nack_count' include/drm/drm_dp_helper.h:713: warning: No description found for parameter 'i2c_defer_count' drivers/gpu/drm/drm_dp_mst_topology.c:2226: warning: No description found for parameter 'connector' include/drm/drm_dp_mst_helper.h:97: warning: No description found for parameter 'cached_edid' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'max_dpcd_transaction_bytes' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'sink_count' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'total_slots' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'avail_slots' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'total_pbn' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'qlock' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'tx_msg_downq' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'tx_msg_upq' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'tx_down_in_progress' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'tx_up_in_progress' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'payload_lock' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'proposed_vcpis' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'payloads' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'payload_mask' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'vcpi_mask' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'tx_waitq' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'work' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'tx_work' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'destroy_connector_list' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'destroy_connector_lock' include/drm/drm_dp_mst_helper.h:471: warning: No description found for parameter 'destroy_connector_work' drivers/gpu/drm/drm_dp_mst_topology.c:2226: warning: No description found for parameter 'connector' drivers/gpu/drm/drm_irq.c:173: warning: No description found for parameter 'flags' include/drm/drmP.h:164: warning: No description found for parameter 'fmt' include/drm/drmP.h:180: warning: No description found for parameter 'fmt' include/drm/drmP.h:198: warning: No description found for parameter 'fmt' include/drm/drmP.h:238: warning: No description found for parameter 'dev' include/drm/drmP.h:238: warning: No description found for parameter 'data' include/drm/drmP.h:238: warning: No description found for parameter 'file_priv' include/drm/drmP.h:271: warning: No description found for parameter 'ioctl' include/drm/drmP.h:271: warning: No description found for parameter '_func' include/drm/drmP.h:271: warning: No description found for parameter '_flags' include/drm/drmP.h:344: warning: cannot understand function prototype: 'struct drm_lock_data ' include/drm/drmP.h:397: warning: cannot understand function prototype: 'struct drm_driver ' include/drm/drmP.h:647: warning: cannot understand function prototype: 'struct drm_info_list ' include/drm/drmP.h:657: warning: cannot understand function prototype: 'struct drm_info_node ' include/drm/drmP.h:667: warning: cannot understand function prototype: 'struct drm_minor ' include/drm/drmP.h:715: warning: cannot understand function prototype: 'struct drm_device ' drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'wedged' drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'fmt' drivers/gpu/drm/i915/i915_irq.c:2582: warning: No description found for parameter 'wedged'
vim +/dev +407 drivers/gpu/drm/drm_atomic.c
391 392 /** 393 * drm_atomic_crtc_set_blob - find and set a blob 394 * @state_blob: reference pointer to the color blob in the crtc_state 395 * @blob_id: blob_id coming from set_property() call 396 * 397 * Set a color correction blob (originating from a set blob property) on the 398 * desired CRTC state. This function will take reference of the blob property 399 * in the CRTC state, finds the blob based on blob_id (which comes from 400 * set_property call) and set the blob at the proper place. 401 * 402 * RETURNS: 403 * Zero on success, error code on failure. 404 */ 405 int drm_atomic_crtc_set_blob(struct drm_device *dev, 406 struct drm_property_blob **state_blob, uint32_t blob_id)
407 {
408 struct drm_property_blob *blob; 409 410 blob = drm_property_lookup_blob(dev, blob_id); 411 if (!blob) { 412 DRM_DEBUG_KMS("Invalid Blob ID\n"); 413 return -EINVAL; 414 } 415
--- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
Hi Shashank,
On 9 October 2015 at 20:28, Shashank Sharma shashank.sharma@intel.com wrote:
As per DRM color manager design, if a userspace wants to set a correction blob, it prepares it and sends the blob_id to kernel via set_property call. DRM framework takes this blob_id, gets the blob, and saves it in the CRTC state, so that, during the atomic_commit, the color correction values from the blob can referred and applied on display controller registers.
This patch adds this set_property support for color correction blobs in drm framework.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal malladi kausalmalladi@gmail.com
drivers/gpu/drm/drm_atomic.c | 53 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 51 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index 7bb3845..0b286d2 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -390,6 +390,38 @@ int drm_atomic_set_mode_prop_for_crtc(struct drm_crtc_state *state, EXPORT_SYMBOL(drm_atomic_set_mode_prop_for_crtc);
/**
- drm_atomic_crtc_set_blob - find and set a blob
- @state_blob: reference pointer to the color blob in the crtc_state
- @blob_id: blob_id coming from set_property() call
- Set a color correction blob (originating from a set blob property) on the
- desired CRTC state. This function will take reference of the blob property
- in the CRTC state, finds the blob based on blob_id (which comes from
- set_property call) and set the blob at the proper place.
- RETURNS:
- Zero on success, error code on failure.
- */
+int drm_atomic_crtc_set_blob(struct drm_device *dev,
struct drm_property_blob **state_blob, uint32_t blob_id)
You are missing the function declaration. Set it as static perhaps ?
Regards, Emil
Regards Shashank
On 10/10/2015 3:55 AM, Emil Velikov wrote:
Hi Shashank,
On 9 October 2015 at 20:28, Shashank Sharma shashank.sharma@intel.com wrote:
As per DRM color manager design, if a userspace wants to set a correction blob, it prepares it and sends the blob_id to kernel via set_property call. DRM framework takes this blob_id, gets the blob, and saves it in the CRTC state, so that, during the atomic_commit, the color correction values from the blob can referred and applied on display controller registers.
This patch adds this set_property support for color correction blobs in drm framework.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal malladi kausalmalladi@gmail.com
drivers/gpu/drm/drm_atomic.c | 53 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 51 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index 7bb3845..0b286d2 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -390,6 +390,38 @@ int drm_atomic_set_mode_prop_for_crtc(struct drm_crtc_state *state, EXPORT_SYMBOL(drm_atomic_set_mode_prop_for_crtc);
/**
- drm_atomic_crtc_set_blob - find and set a blob
- @state_blob: reference pointer to the color blob in the crtc_state
- @blob_id: blob_id coming from set_property() call
- Set a color correction blob (originating from a set blob property) on the
- desired CRTC state. This function will take reference of the blob property
- in the CRTC state, finds the blob based on blob_id (which comes from
- set_property call) and set the blob at the proper place.
- RETURNS:
- Zero on success, error code on failure.
- */
+int drm_atomic_crtc_set_blob(struct drm_device *dev,
struct drm_property_blob **state_blob, uint32_t blob_id)You are missing the function declaration. Set it as static perhaps ?
Yes, This was meant to be used internally, I can make it static.
Regards, Emil
As per the DRM get_property implementation for a blob, framework is supposed to return the blob_id to the caller. All the color management blobs are saved in CRTC state during the set call.
This patch adds get_property support for color management properties, by referring to the existing blob for the property and passing its blob_id.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com --- drivers/gpu/drm/drm_atomic.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index 0b286d2..f9ecc49 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -499,6 +499,14 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc, *val = state->active; else if (property == config->prop_mode_id) *val = (state->mode_blob) ? state->mode_blob->base.id : 0; + else if (property == config->cm_palette_after_ctm_property) + *val = (state->palette_after_ctm_blob) ? + state->palette_after_ctm_blob->base.id : 0; + else if (property == config->cm_palette_before_ctm_property) + *val = (state->palette_before_ctm_blob) ? + state->palette_before_ctm_blob->base.id : 0; + else if (property == config->cm_ctm_property) + *val = (state->ctm_blob) ? state->ctm_blob->base.id : 0; else if (crtc->funcs->atomic_get_property) return crtc->funcs->atomic_get_property(crtc, state, property, val); else
This patch adds new structures in DRM layer for Palette color correction.These structures will be used by user space agents to configure appropriate number of samples and Palette LUT for a platform.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com --- include/uapi/drm/drm.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+)
diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h index 3801584..681d5af 100644 --- a/include/uapi/drm/drm.h +++ b/include/uapi/drm/drm.h @@ -829,6 +829,32 @@ struct drm_event_vblank { __u32 reserved; };
+struct drm_r32g32b32 { + /* + * Data is in U8.24 fixed point format. + * All platforms support values within [0, 1.0] range, + * for Red, Green and Blue colors. + */ + __u32 r32; + __u32 g32; + __u32 b32; + __u32 reserved; +}; + +struct drm_palette { + /* + * This has to be a supported value during get call. + * Feature will be disabled if this is 0 while set + */ + __u32 num_samples; + /* + * Starting of palette LUT in R32G32B32 format. + * Each of RGB value is in U8.24 fixed point format. + * Actual number of samples will depend upon num_samples + */ + struct drm_r32g32b32 lut[0]; +}; + /* typedef area */ #ifndef __KERNEL__ typedef struct drm_clip_rect drm_clip_rect_t;
Color Manager framework defines a DRM property for color space transformation and Gamut mapping. This property is called CTM (Color Transformation Matrix).
This patch adds a new structure in DRM layer for CTM. This structure can be used by all user space agents to configure CTM coefficients for color correction.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com --- include/uapi/drm/drm.h | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h index 681d5af..f347c69 100644 --- a/include/uapi/drm/drm.h +++ b/include/uapi/drm/drm.h @@ -855,6 +855,16 @@ struct drm_palette { struct drm_r32g32b32 lut[0]; };
+struct drm_ctm { + /* + * Each value is in S31.32 format. + * This is 3x3 matrix in row major format. + * Integer part will be clipped to nearest + * max/min boundary as supported by the HW platform. + */ + __s64 ctm_coeff[9]; +}; + /* typedef area */ #ifndef __KERNEL__ typedef struct drm_clip_rect drm_clip_rect_t;
This patch adds set property interface for intel CRTC. This interface will be used for set operation on any DRM properties.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com --- drivers/gpu/drm/i915/intel_display.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 7f3c482..98cc97a 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -13237,6 +13237,7 @@ static const struct drm_crtc_funcs intel_crtc_funcs = { .page_flip = intel_crtc_page_flip, .atomic_duplicate_state = intel_crtc_duplicate_state, .atomic_destroy_state = intel_crtc_destroy_state, + .set_property = drm_atomic_helper_crtc_set_property, };
static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
This patch create new files intel_color_manager.c which will contain the core color correction code for I915 driver and its header intel_color_manager.h
The per color property patches coming up in this patch series will fill the appropriate functions in this file.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com --- drivers/gpu/drm/i915/Makefile | 3 +- drivers/gpu/drm/i915/intel_color_manager.c | 33 ++++++++++++++++++++ drivers/gpu/drm/i915/intel_color_manager.h | 50 ++++++++++++++++++++++++++++++ 3 files changed, 85 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/i915/intel_color_manager.c create mode 100644 drivers/gpu/drm/i915/intel_color_manager.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 44d290a..56caf9e 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -64,7 +64,8 @@ i915-y += intel_audio.o \ intel_overlay.o \ intel_psr.o \ intel_sideband.o \ - intel_sprite.o + intel_sprite.o \ + intel_color_manager.o i915-$(CONFIG_ACPI) += intel_acpi.o intel_opregion.o i915-$(CONFIG_DRM_FBDEV_EMULATION) += intel_fbdev.o
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c new file mode 100644 index 0000000..7357d99 --- /dev/null +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -0,0 +1,33 @@ +/* + * Copyright © 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Shashank Sharma shashank.sharma@intel.com + * Kausal Malladi Kausal.Malladi@intel.com + */ + +#include "intel_color_manager.h" + +void intel_attach_color_properties_to_crtc(struct drm_device *dev, + struct drm_mode_object *mode_obj) +{ +} diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h new file mode 100644 index 0000000..eec52a7 --- /dev/null +++ b/drivers/gpu/drm/i915/intel_color_manager.h @@ -0,0 +1,50 @@ +/* + * Copyright © 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Shashank Sharma shashank.sharma@intel.com + * Kausal Malladi Kausal.Malladi@intel.com + */ +#include <drm/drmP.h> +#include <drm/drm_crtc_helper.h> +#include "i915_drv.h" + +/* Color management bit utilities */ +#define GET_BIT_MASK(n) ((1 << n) - 1) + +/* Read bits of a word from bit no. 'start'(lsb) till 'n' bits */ +#define GET_BITS(x, start, nbits) ((x >> start) & GET_BIT_MASK(nbits)) + +/* Round off by adding 1 to the immediate lower bit */ +#define GET_BITS_ROUNDOFF(x, start, nbits) \ + ((GET_BITS(x, start, (nbits + 1)) + 1) >> 1) + +/* Clear bits of a word from bit no. 'start' till nbits */ +#define CLEAR_BITS(x, start, nbits) ( \ + x &= ~((GET_BIT_MASK(nbits) << start))) + +/* Write bit_pattern of no_bits bits in a target word */ +#define SET_BITS(target, bit_pattern, start_bit, no_bits) \ + do { \ + CLEAR_BITS(target, start_bit, no_bits); \ + target |= (bit_pattern << start_bit); \ + } while (0)
Hi Shashank,
On 9 October 2015 at 20:28, Shashank Sharma shashank.sharma@intel.com wrote: [snip]
+/* Color management bit utilities */ +#define GET_BIT_MASK(n) ((1 << n) - 1)
+/* Read bits of a word from bit no. 'start'(lsb) till 'n' bits */ +#define GET_BITS(x, start, nbits) ((x >> start) & GET_BIT_MASK(nbits))
+/* Round off by adding 1 to the immediate lower bit */ +#define GET_BITS_ROUNDOFF(x, start, nbits) \
((GET_BITS(x, start, (nbits + 1)) + 1) >> 1)+/* Clear bits of a word from bit no. 'start' till nbits */ +#define CLEAR_BITS(x, start, nbits) ( \
x &= ~((GET_BIT_MASK(nbits) << start)))+/* Write bit_pattern of no_bits bits in a target word */ +#define SET_BITS(target, bit_pattern, start_bit, no_bits) \
do { \CLEAR_BITS(target, start_bit, no_bits); \target |= (bit_pattern << start_bit); \} while (0)
It feels suspicious that the kernel does not have macros for either one of these.
I would invite you to take a look at include/linux/bitops.h and other kernel headers.
Regards, Emil
Regards Shashank
On 10/10/2015 4:17 AM, Emil Velikov wrote:
Hi Shashank,
On 9 October 2015 at 20:28, Shashank Sharma shashank.sharma@intel.com wrote: [snip]
+/* Color management bit utilities */ +#define GET_BIT_MASK(n) ((1 << n) - 1)
+/* Read bits of a word from bit no. 'start'(lsb) till 'n' bits */ +#define GET_BITS(x, start, nbits) ((x >> start) & GET_BIT_MASK(nbits))
+/* Round off by adding 1 to the immediate lower bit */ +#define GET_BITS_ROUNDOFF(x, start, nbits) \
((GET_BITS(x, start, (nbits + 1)) + 1) >> 1)+/* Clear bits of a word from bit no. 'start' till nbits */ +#define CLEAR_BITS(x, start, nbits) ( \
x &= ~((GET_BIT_MASK(nbits) << start)))+/* Write bit_pattern of no_bits bits in a target word */ +#define SET_BITS(target, bit_pattern, start_bit, no_bits) \
do { \CLEAR_BITS(target, start_bit, no_bits); \target |= (bit_pattern << start_bit); \} while (0)It feels suspicious that the kernel does not have macros for either one of these.
I would invite you to take a look at include/linux/bitops.h and other kernel headers.
Thanks for pointing this out, but if you closely observe, these macros are well tested, and created for color management operations, which have specific requirements, like: - pick 8 bits from 16th bit onwards, make them LSB, and give result: GET_BITS - take these 8 bits and move to bit 17th of the word, clearing the existing ones: SET_BITS For core register programming, this was required, so we created it. I would still have a look at the existing ones which you pointed out to avoid any duplication, if they fall directly in the implementation, else I would like to continue with these.
Regards, Emil
On 10 October 2015 at 05:55, Sharma, Shashank shashank.sharma@intel.com wrote:
On 10/10/2015 4:17 AM, Emil Velikov wrote:
Hi Shashank,
On 9 October 2015 at 20:28, Shashank Sharma shashank.sharma@intel.com wrote: [snip]
+/* Color management bit utilities */ +#define GET_BIT_MASK(n) ((1 << n) - 1)
+/* Read bits of a word from bit no. 'start'(lsb) till 'n' bits */ +#define GET_BITS(x, start, nbits) ((x >> start) & GET_BIT_MASK(nbits))
+/* Round off by adding 1 to the immediate lower bit */ +#define GET_BITS_ROUNDOFF(x, start, nbits) \
((GET_BITS(x, start, (nbits + 1)) + 1) >> 1)+/* Clear bits of a word from bit no. 'start' till nbits */ +#define CLEAR_BITS(x, start, nbits) ( \
x &= ~((GET_BIT_MASK(nbits) << start)))+/* Write bit_pattern of no_bits bits in a target word */ +#define SET_BITS(target, bit_pattern, start_bit, no_bits) \
do { \CLEAR_BITS(target, start_bit, no_bits); \target |= (bit_pattern << start_bit); \} while (0)It feels suspicious that the kernel does not have macros for either one of these.
I would invite you to take a look at include/linux/bitops.h and other kernel headers.
Thanks for pointing this out, but if you closely observe, these macros are well tested, and created for color management operations, which have specific requirements, like:
- pick 8 bits from 16th bit onwards, make them LSB, and give result:
GET_BITS
- take these 8 bits and move to bit 17th of the word, clearing the existing
ones: SET_BITS For core register programming, this was required, so we created it. I would still have a look at the existing ones which you pointed out to avoid any duplication, if they fall directly in the implementation, else I would like to continue with these.
Unless I'm missing something, these are generic bit manipulation macros, are they not ? As such I'd imagine we have some of these already available, but I cannot say which ones off-hand.
Regards, Emil
Thanks for the review Emil. Please find my comments inline
Regards Shashank On 10/13/2015 6:29 PM, Emil Velikov wrote:
On 10 October 2015 at 05:55, Sharma, Shashank shashank.sharma@intel.com wrote:
On 10/10/2015 4:17 AM, Emil Velikov wrote:
Hi Shashank,
On 9 October 2015 at 20:28, Shashank Sharma shashank.sharma@intel.com wrote: [snip]
+/* Color management bit utilities */ +#define GET_BIT_MASK(n) ((1 << n) - 1)
+/* Read bits of a word from bit no. 'start'(lsb) till 'n' bits */ +#define GET_BITS(x, start, nbits) ((x >> start) & GET_BIT_MASK(nbits))
+/* Round off by adding 1 to the immediate lower bit */ +#define GET_BITS_ROUNDOFF(x, start, nbits) \
((GET_BITS(x, start, (nbits + 1)) + 1) >> 1)+/* Clear bits of a word from bit no. 'start' till nbits */ +#define CLEAR_BITS(x, start, nbits) ( \
x &= ~((GET_BIT_MASK(nbits) << start)))+/* Write bit_pattern of no_bits bits in a target word */ +#define SET_BITS(target, bit_pattern, start_bit, no_bits) \
do { \CLEAR_BITS(target, start_bit, no_bits); \target |= (bit_pattern << start_bit); \} while (0)It feels suspicious that the kernel does not have macros for either one of these.
I would invite you to take a look at include/linux/bitops.h and other kernel headers.
Thanks for pointing this out, but if you closely observe, these macros are well tested, and created for color management operations, which have specific requirements, like:
- pick 8 bits from 16th bit onwards, make them LSB, and give result:
GET_BITS
- take these 8 bits and move to bit 17th of the word, clearing the existing
ones: SET_BITS For core register programming, this was required, so we created it. I would still have a look at the existing ones which you pointed out to avoid any duplication, if they fall directly in the implementation, else I would like to continue with these.
Unless I'm missing something, these are generic bit manipulation macros, are they not ? As such I'd imagine we have some of these already available, but I cannot say which ones off-hand.
If you closely observe, what set_bit does is picks up the bit pattern from nth to n+reqd bit, moves it to LSB and returns it. similarly set bits clears the bits, then copy the bit pattern in the respective bits and manipulates the shifts. I could not find any such examples which I can directly use from suggested macros.
Regards, Emil
From DRM color management:
============================ DRM color manager supports these color properties: 1. "ctm": Color transformation matrix property, where a color transformation matrix of 9 correction values gets applied as correction. 2. "palette_before_ctm": for corrections which get applied beore color transformation matrix correction. 3. "palette_after_ctm": for corrections which get applied after color transformation matrix correction.
These color correction capabilities may differ per platform, supporting various different no. of correction coefficients. So DRM color manager support few properties using which a user space can query the platform's capability, and prepare color correction accordingly. These query properties are: 1. cm_coeff_after_ctm_property 2. cm_coeff_before_ctm_property (CTM is fix to 9 coefficients across industry)
Now, Intel color manager registers: ====================================== 1. Gamma correction property as "palette_after_ctm" property 2. Degamma correction capability as "palette_bafore_ctm" property capability as "palette_after_ctm" DRM color property hook. 3. CSC as "ctm" property.
So finally, This patch does the following: 1. Add a function which loads the platform's color correction capabilities in the cm_crtc_palette_capabilities_property structure. 2. Attaches the cm_crtc_palette_capabilities_property to every CRTC getting initiaized. 3. Adds two new parameters "num_samples_after_ctm" and "num_samples_before_ctm" in intel_device_info as gamma and degamma coefficients vary per platform basis.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/intel_color_manager.c | 33 +++++++++++++++++++++++++++++- 2 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index ad37b25..8bf1d6f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -798,6 +798,8 @@ struct intel_device_info { u8 num_sprites[I915_MAX_PIPES]; u8 gen; u8 ring_mask; /* Rings supported by the HW */ + u16 num_samples_after_ctm; + u16 num_samples_before_ctm; DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); /* Register offsets for the various display pipes and transcoders */ int pipe_offsets[I915_MAX_TRANSCODERS]; diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index 7357d99..e466748 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -28,6 +28,37 @@ #include "intel_color_manager.h"
void intel_attach_color_properties_to_crtc(struct drm_device *dev, - struct drm_mode_object *mode_obj) + struct drm_crtc *crtc) { + struct drm_mode_config *config = &dev->mode_config; + struct drm_mode_object *mode_obj = &crtc->base; + + /* + * Register: + * ========= + * Gamma correction as palette_after_ctm property + * Degamma correction as palette_before_ctm property + * + * Load: + * ===== + * no. of coefficients supported on this platform for gamma + * and degamma with the query properties. A user + * space agent should read these query property, and prepare + * the color correction values accordingly. Its expected from the + * driver to load the right number of coefficients during the init + * phase. + */ + if (config->cm_coeff_after_ctm_property) { + drm_object_attach_property(mode_obj, + config->cm_coeff_after_ctm_property, + INTEL_INFO(dev)->num_samples_after_ctm); + DRM_DEBUG_DRIVER("Gamma query property initialized\n"); + } + + if (config->cm_coeff_before_ctm_property) { + drm_object_attach_property(mode_obj, + config->cm_coeff_before_ctm_property, + INTEL_INFO(dev)->num_samples_before_ctm); + DRM_DEBUG_DRIVER("Degamma query property initialized\n"); + } }
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma shashank.sharma@intel.com wrote:
From DRM color management:
DRM color manager supports these color properties:
- "ctm": Color transformation matrix property, where a color transformation matrix of 9 correction values gets applied as correction.
- "palette_before_ctm": for corrections which get applied beore color transformation matrix correction.
- "palette_after_ctm": for corrections which get applied after color transformation matrix correction.
These color correction capabilities may differ per platform, supporting various different no. of correction coefficients. So DRM color manager support few properties using which a user space can query the platform's capability, and prepare color correction accordingly. These query properties are:
- cm_coeff_after_ctm_property
- cm_coeff_before_ctm_property
(CTM is fix to 9 coefficients across industry)
Now, Intel color manager registers:
- Gamma correction property as "palette_after_ctm" property
- Degamma correction capability as "palette_bafore_ctm" property capability as "palette_after_ctm" DRM color property hook.
- CSC as "ctm" property.
So finally, This patch does the following:
- Add a function which loads the platform's color correction capabilities in the cm_crtc_palette_capabilities_property structure.
- Attaches the cm_crtc_palette_capabilities_property to every CRTC getting initiaized.
- Adds two new parameters "num_samples_after_ctm" and "num_samples_before_ctm" in intel_device_info as gamma and degamma coefficients vary per platform basis.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com
drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/intel_color_manager.c | 33 +++++++++++++++++++++++++++++- 2 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index ad37b25..8bf1d6f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -798,6 +798,8 @@ struct intel_device_info { u8 num_sprites[I915_MAX_PIPES]; u8 gen; u8 ring_mask; /* Rings supported by the HW */
u16 num_samples_after_ctm;u16 num_samples_before_ctm; DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); /* Register offsets for the various display pipes and transcoders */ int pipe_offsets[I915_MAX_TRANSCODERS];diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index 7357d99..e466748 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -28,6 +28,37 @@ #include "intel_color_manager.h"
void intel_attach_color_properties_to_crtc(struct drm_device *dev,
struct drm_mode_object *mode_obj)
struct drm_crtc *crtc){
struct drm_mode_config *config = &dev->mode_config;struct drm_mode_object *mode_obj = &crtc->base;/** Register:* =========* Gamma correction as palette_after_ctm property* Degamma correction as palette_before_ctm property** Load:* =====* no. of coefficients supported on this platform for gamma* and degamma with the query properties. A user* space agent should read these query property, and prepare* the color correction values accordingly. Its expected from the* driver to load the right number of coefficients during the init* phase.*/if (config->cm_coeff_after_ctm_property) {drm_object_attach_property(mode_obj,config->cm_coeff_after_ctm_property,INTEL_INFO(dev)->num_samples_after_ctm);DRM_DEBUG_DRIVER("Gamma query property initialized\n");}if (config->cm_coeff_before_ctm_property) {drm_object_attach_property(mode_obj,config->cm_coeff_before_ctm_property,INTEL_INFO(dev)->num_samples_before_ctm);DRM_DEBUG_DRIVER("Degamma query property initialized\n");}
Shouldn't this commit be squashed with the previous ? You're also missing the function declaration.
Regards, Emil
Regards Shashank
On 10/10/2015 3:51 AM, Emil Velikov wrote:
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma shashank.sharma@intel.com wrote:
From DRM color management:
DRM color manager supports these color properties:
- "ctm": Color transformation matrix property, where a color transformation matrix of 9 correction values gets applied as correction.
- "palette_before_ctm": for corrections which get applied beore color transformation matrix correction.
- "palette_after_ctm": for corrections which get applied after color transformation matrix correction.
These color correction capabilities may differ per platform, supporting various different no. of correction coefficients. So DRM color manager support few properties using which a user space can query the platform's capability, and prepare color correction accordingly. These query properties are:
- cm_coeff_after_ctm_property
- cm_coeff_before_ctm_property
(CTM is fix to 9 coefficients across industry)
Now, Intel color manager registers:
- Gamma correction property as "palette_after_ctm" property
- Degamma correction capability as "palette_bafore_ctm" property capability as "palette_after_ctm" DRM color property hook.
- CSC as "ctm" property.
So finally, This patch does the following:
- Add a function which loads the platform's color correction capabilities in the cm_crtc_palette_capabilities_property structure.
- Attaches the cm_crtc_palette_capabilities_property to every CRTC getting initiaized.
- Adds two new parameters "num_samples_after_ctm" and "num_samples_before_ctm" in intel_device_info as gamma and degamma coefficients vary per platform basis.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com
drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/intel_color_manager.c | 33 +++++++++++++++++++++++++++++- 2 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index ad37b25..8bf1d6f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -798,6 +798,8 @@ struct intel_device_info { u8 num_sprites[I915_MAX_PIPES]; u8 gen; u8 ring_mask; /* Rings supported by the HW */
u16 num_samples_after_ctm;u16 num_samples_before_ctm; DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); /* Register offsets for the various display pipes and transcoders */ int pipe_offsets[I915_MAX_TRANSCODERS];diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index 7357d99..e466748 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -28,6 +28,37 @@ #include "intel_color_manager.h"
void intel_attach_color_properties_to_crtc(struct drm_device *dev,
struct drm_mode_object *mode_obj)
struct drm_crtc *crtc)struct drm_mode_config *config = &dev->mode_config;struct drm_mode_object *mode_obj = &crtc->base;/** Register:* =========* Gamma correction as palette_after_ctm property* Degamma correction as palette_before_ctm property** Load:* =====* no. of coefficients supported on this platform for gamma* and degamma with the query properties. A user* space agent should read these query property, and prepare* the color correction values accordingly. Its expected from the* driver to load the right number of coefficients during the init* phase.*/if (config->cm_coeff_after_ctm_property) {drm_object_attach_property(mode_obj,config->cm_coeff_after_ctm_property,INTEL_INFO(dev)->num_samples_after_ctm);DRM_DEBUG_DRIVER("Gamma query property initialized\n");}if (config->cm_coeff_before_ctm_property) {drm_object_attach_property(mode_obj,config->cm_coeff_before_ctm_property,INTEL_INFO(dev)->num_samples_before_ctm);DRM_DEBUG_DRIVER("Degamma query property initialized\n");}Shouldn't this commit be squashed with the previous ? You're also missing the function declaration.
Please see the history of the review comments, initially this patch was like as you suggested. But one of the previous review comments, suggested to split that into two, as it was 'overdoing' stuff. So I had split it into two separate ones, so I think this is ok :)
Also, one of the previous review comments was to call this function only when the whole framework is in place, so that it would look like we are enabling, when we have stuff ready. So this is just the body of the function, and definition is coming up in next patch, where this function is being called from intel_crtc_init (patch 17/22 to be specific).
Regards, Emil
On 10 October 2015 at 06:01, Sharma, Shashank shashank.sharma@intel.com wrote:
On 10/10/2015 3:51 AM, Emil Velikov wrote:
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma shashank.sharma@intel.com wrote:
From DRM color management:
DRM color manager supports these color properties:
- "ctm": Color transformation matrix property, where a color transformation matrix of 9 correction values gets applied as correction.
- "palette_before_ctm": for corrections which get applied beore color transformation matrix correction.
- "palette_after_ctm": for corrections which get applied after color transformation matrix correction.
These color correction capabilities may differ per platform, supporting various different no. of correction coefficients. So DRM color manager support few properties using which a user space can query the platform's capability, and prepare color correction accordingly. These query properties are:
- cm_coeff_after_ctm_property
- cm_coeff_before_ctm_property
(CTM is fix to 9 coefficients across industry)
Now, Intel color manager registers:
- Gamma correction property as "palette_after_ctm" property
- Degamma correction capability as "palette_bafore_ctm" property capability as "palette_after_ctm" DRM color property hook.
- CSC as "ctm" property.
So finally, This patch does the following:
- Add a function which loads the platform's color correction capabilities in the cm_crtc_palette_capabilities_property structure.
- Attaches the cm_crtc_palette_capabilities_property to every CRTC getting initiaized.
- Adds two new parameters "num_samples_after_ctm" and "num_samples_before_ctm" in intel_device_info as gamma and degamma coefficients vary per platform basis.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com
drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/intel_color_manager.c | 33 +++++++++++++++++++++++++++++- 2 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index ad37b25..8bf1d6f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -798,6 +798,8 @@ struct intel_device_info { u8 num_sprites[I915_MAX_PIPES]; u8 gen; u8 ring_mask; /* Rings supported by the HW */
u16 num_samples_after_ctm;u16 num_samples_before_ctm; DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); /* Register offsets for the various display pipes andtranscoders */ int pipe_offsets[I915_MAX_TRANSCODERS]; diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index 7357d99..e466748 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -28,6 +28,37 @@ #include "intel_color_manager.h"
void intel_attach_color_properties_to_crtc(struct drm_device *dev,
struct drm_mode_object *mode_obj)
struct drm_crtc *crtc)struct drm_mode_config *config = &dev->mode_config;struct drm_mode_object *mode_obj = &crtc->base;/** Register:* =========* Gamma correction as palette_after_ctm property* Degamma correction as palette_before_ctm property** Load:* =====* no. of coefficients supported on this platform for gamma* and degamma with the query properties. A user* space agent should read these query property, and prepare* the color correction values accordingly. Its expected from the* driver to load the right number of coefficients during theinit
* phase.*/if (config->cm_coeff_after_ctm_property) {drm_object_attach_property(mode_obj,config->cm_coeff_after_ctm_property,INTEL_INFO(dev)->num_samples_after_ctm);DRM_DEBUG_DRIVER("Gamma query property initialized\n");}if (config->cm_coeff_before_ctm_property) {drm_object_attach_property(mode_obj,config->cm_coeff_before_ctm_property,INTEL_INFO(dev)->num_samples_before_ctm);DRM_DEBUG_DRIVER("Degamma query property initialized\n");}Shouldn't this commit be squashed with the previous ? You're also missing the function declaration.
Please see the history of the review comments, initially this patch was like as you suggested. But one of the previous review comments, suggested to split that into two, as it was 'overdoing' stuff. So I had split it into two separate ones, so I think this is ok :)
Sorry did not see it. The revision history should be within the patch either above or below the --- line.
So this is just the body of the function, and definition is coming up in next patch, where this function is being called from intel_crtc_init (patch 17/22 to be specific).
This is not how things work I'm afraid. The function declaration and definition must _always_ be in the same patch.
Regards, Emil
Regards Shashank
On 10/13/2015 6:33 PM, Emil Velikov wrote:
On 10 October 2015 at 06:01, Sharma, Shashank shashank.sharma@intel.com wrote:
On 10/10/2015 3:51 AM, Emil Velikov wrote:
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma shashank.sharma@intel.com wrote:
From DRM color management:
DRM color manager supports these color properties:
- "ctm": Color transformation matrix property, where a color transformation matrix of 9 correction values gets applied as correction.
- "palette_before_ctm": for corrections which get applied beore color transformation matrix correction.
- "palette_after_ctm": for corrections which get applied after color transformation matrix correction.
These color correction capabilities may differ per platform, supporting various different no. of correction coefficients. So DRM color manager support few properties using which a user space can query the platform's capability, and prepare color correction accordingly. These query properties are:
- cm_coeff_after_ctm_property
- cm_coeff_before_ctm_property
(CTM is fix to 9 coefficients across industry)
Now, Intel color manager registers:
- Gamma correction property as "palette_after_ctm" property
- Degamma correction capability as "palette_bafore_ctm" property capability as "palette_after_ctm" DRM color property hook.
- CSC as "ctm" property.
So finally, This patch does the following:
- Add a function which loads the platform's color correction capabilities in the cm_crtc_palette_capabilities_property structure.
- Attaches the cm_crtc_palette_capabilities_property to every CRTC getting initiaized.
- Adds two new parameters "num_samples_after_ctm" and "num_samples_before_ctm" in intel_device_info as gamma and degamma coefficients vary per platform basis.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com
drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/intel_color_manager.c | 33 +++++++++++++++++++++++++++++- 2 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index ad37b25..8bf1d6f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -798,6 +798,8 @@ struct intel_device_info { u8 num_sprites[I915_MAX_PIPES]; u8 gen; u8 ring_mask; /* Rings supported by the HW */
u16 num_samples_after_ctm;u16 num_samples_before_ctm; DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); /* Register offsets for the various display pipes andtranscoders */ int pipe_offsets[I915_MAX_TRANSCODERS]; diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index 7357d99..e466748 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -28,6 +28,37 @@ #include "intel_color_manager.h"
void intel_attach_color_properties_to_crtc(struct drm_device *dev,
struct drm_mode_object *mode_obj)
struct drm_crtc *crtc)struct drm_mode_config *config = &dev->mode_config;struct drm_mode_object *mode_obj = &crtc->base;/** Register:* =========* Gamma correction as palette_after_ctm property* Degamma correction as palette_before_ctm property** Load:* =====* no. of coefficients supported on this platform for gamma* and degamma with the query properties. A user* space agent should read these query property, and prepare* the color correction values accordingly. Its expected from the* driver to load the right number of coefficients during theinit
* phase.*/if (config->cm_coeff_after_ctm_property) {drm_object_attach_property(mode_obj,config->cm_coeff_after_ctm_property,INTEL_INFO(dev)->num_samples_after_ctm);DRM_DEBUG_DRIVER("Gamma query property initialized\n");}if (config->cm_coeff_before_ctm_property) {drm_object_attach_property(mode_obj,config->cm_coeff_before_ctm_property,INTEL_INFO(dev)->num_samples_before_ctm);DRM_DEBUG_DRIVER("Degamma query property initialized\n");}Shouldn't this commit be squashed with the previous ? You're also missing the function declaration.
Please see the history of the review comments, initially this patch was like as you suggested. But one of the previous review comments, suggested to split that into two, as it was 'overdoing' stuff. So I had split it into two separate ones, so I think this is ok :)
Sorry did not see it. The revision history should be within the patch either above or below the --- line.
So this is just the body of the function, and definition is coming up in next patch, where this function is being called from intel_crtc_init (patch 17/22 to be specific).
This is not how things work I'm afraid. The function declaration and definition must _always_ be in the same patch.
This is confusing, I have received previous comments which say the other way. But anyways, I can add the definition also in this patch, if you like that.
Regards, Emil
On 13 October 2015 at 14:36, Sharma, Shashank shashank.sharma@intel.com wrote:
On 10/13/2015 6:33 PM, Emil Velikov wrote:
On 10 October 2015 at 06:01, Sharma, Shashank shashank.sharma@intel.com wrote:
On 10/10/2015 3:51 AM, Emil Velikov wrote:
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma shashank.sharma@intel.com wrote:
From DRM color management:
DRM color manager supports these color properties:
- "ctm": Color transformation matrix property, where a color transformation matrix of 9 correction values gets applied as correction.
- "palette_before_ctm": for corrections which get applied beore color transformation matrix correction.
- "palette_after_ctm": for corrections which get applied after color transformation matrix correction.
These color correction capabilities may differ per platform, supporting various different no. of correction coefficients. So DRM color manager support few properties using which a user space can query the platform's capability, and prepare color correction accordingly. These query properties are:
- cm_coeff_after_ctm_property
- cm_coeff_before_ctm_property
(CTM is fix to 9 coefficients across industry)
Now, Intel color manager registers:
- Gamma correction property as "palette_after_ctm" property
- Degamma correction capability as "palette_bafore_ctm" property capability as "palette_after_ctm" DRM color property hook.
- CSC as "ctm" property.
So finally, This patch does the following:
- Add a function which loads the platform's color correction capabilities in the cm_crtc_palette_capabilities_property
structure. 2. Attaches the cm_crtc_palette_capabilities_property to every CRTC getting initiaized. 3. Adds two new parameters "num_samples_after_ctm" and "num_samples_before_ctm" in intel_device_info as gamma and degamma coefficients vary per platform basis.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com
drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/intel_color_manager.c | 33 +++++++++++++++++++++++++++++- 2 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index ad37b25..8bf1d6f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -798,6 +798,8 @@ struct intel_device_info { u8 num_sprites[I915_MAX_PIPES]; u8 gen; u8 ring_mask; /* Rings supported by the HW */
u16 num_samples_after_ctm;u16 num_samples_before_ctm; DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); /* Register offsets for the various display pipes andtranscoders */ int pipe_offsets[I915_MAX_TRANSCODERS]; diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index 7357d99..e466748 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -28,6 +28,37 @@ #include "intel_color_manager.h"
void intel_attach_color_properties_to_crtc(struct drm_device *dev,
struct drm_mode_object *mode_obj)
struct drm_crtc *crtc)struct drm_mode_config *config = &dev->mode_config;struct drm_mode_object *mode_obj = &crtc->base;/** Register:* =========* Gamma correction as palette_after_ctm property* Degamma correction as palette_before_ctm property** Load:* =====* no. of coefficients supported on this platform for gamma* and degamma with the query properties. A user* space agent should read these query property, and prepare* the color correction values accordingly. Its expected fromthe
* driver to load the right number of coefficients during theinit
* phase.*/if (config->cm_coeff_after_ctm_property) {drm_object_attach_property(mode_obj,config->cm_coeff_after_ctm_property,INTEL_INFO(dev)->num_samples_after_ctm);
DRM_DEBUG_DRIVER("Gamma query property initialized\n");}if (config->cm_coeff_before_ctm_property) {drm_object_attach_property(mode_obj,config->cm_coeff_before_ctm_property,INTEL_INFO(dev)->num_samples_before_ctm);
DRM_DEBUG_DRIVER("Degamma query propertyinitialized\n");
}Shouldn't this commit be squashed with the previous ? You're also missing the function declaration.
Please see the history of the review comments, initially this patch was like as you suggested. But one of the previous review comments, suggested to split that into two, as it was 'overdoing' stuff. So I had split it into two separate ones, so I think this is ok :)
Sorry did not see it. The revision history should be within the patch either above or below the --- line.
So this is just the body of the function, and definition is coming up in next patch, where this function is being called from intel_crtc_init (patch 17/22 to be specific).
This is not how things work I'm afraid. The function declaration and definition must _always_ be in the same patch.
This is confusing, I have received previous comments which say the other way. But anyways, I can add the definition also in this patch, if you like that.
Do you have a link handy ? I suspect that something else was mentioned in that comment as splitting function declaration and definition is extremely uncommon.
Thanks Emil
Do you have a link handy ? I suspect that something else was mentioned in that comment as splitting function declaration and definition is extremely uncommon
Yep, maybe I misunderstood. I will add the definition here.
Regards Shashank -----Original Message----- From: Emil Velikov [mailto:emil.l.velikov@gmail.com] Sent: Tuesday, October 13, 2015 7:24 PM To: Sharma, Shashank Cc: Matheson, Annie J; Bradford, Robert; Palleti, Avinash Reddy; intel-gfx@lists.freedesktop.org; ML dri-devel; Mukherjee, Indranil; Bish, Jim; Barnes, Jesse; Smith, Gary K; Kausal Malladi; Vetter, Daniel; Kumar, Kiran S Subject: Re: [PATCH 10/22] drm/i915: Register color correction capabilities
On 13 October 2015 at 14:36, Sharma, Shashank shashank.sharma@intel.com wrote:
On 10/13/2015 6:33 PM, Emil Velikov wrote:
On 10 October 2015 at 06:01, Sharma, Shashank shashank.sharma@intel.com wrote:
On 10/10/2015 3:51 AM, Emil Velikov wrote:
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma shashank.sharma@intel.com wrote:
From DRM color management:
DRM color manager supports these color properties:
- "ctm": Color transformation matrix property, where a color transformation matrix of 9 correction values gets applied as correction.
- "palette_before_ctm": for corrections which get applied beore color transformation matrix correction.
- "palette_after_ctm": for corrections which get applied after color transformation matrix correction.
These color correction capabilities may differ per platform, supporting various different no. of correction coefficients. So DRM color manager support few properties using which a user space can query the platform's capability, and prepare color correction accordingly. These query properties are:
- cm_coeff_after_ctm_property
- cm_coeff_before_ctm_property
(CTM is fix to 9 coefficients across industry)
Now, Intel color manager registers:
- Gamma correction property as "palette_after_ctm" property 2.
Degamma correction capability as "palette_bafore_ctm" property capability as "palette_after_ctm" DRM color property hook. 3. CSC as "ctm" property.
So finally, This patch does the following:
- Add a function which loads the platform's color correction capabilities in the cm_crtc_palette_capabilities_property
structure. 2. Attaches the cm_crtc_palette_capabilities_property to every CRTC getting initiaized. 3. Adds two new parameters "num_samples_after_ctm" and "num_samples_before_ctm" in intel_device_info as gamma and degamma coefficients vary per platform basis.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com
drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/intel_color_manager.c | 33 +++++++++++++++++++++++++++++- 2 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index ad37b25..8bf1d6f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -798,6 +798,8 @@ struct intel_device_info { u8 num_sprites[I915_MAX_PIPES]; u8 gen; u8 ring_mask; /* Rings supported by the HW */
u16 num_samples_after_ctm;u16 num_samples_before_ctm; DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); /* Register offsets for the various display pipes andtranscoders */ int pipe_offsets[I915_MAX_TRANSCODERS]; diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index 7357d99..e466748 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -28,6 +28,37 @@ #include "intel_color_manager.h"
void intel_attach_color_properties_to_crtc(struct drm_device *dev,
struct drm_mode_object *mode_obj)
struct drm_crtc *crtc)struct drm_mode_config *config = &dev->mode_config;struct drm_mode_object *mode_obj = &crtc->base;/** Register:* =========* Gamma correction as palette_after_ctm property* Degamma correction as palette_before_ctm property** Load:* =====* no. of coefficients supported on this platform for gamma* and degamma with the query properties. A user* space agent should read these query property, and prepare* the color correction values accordingly. Its expected- from
the
* driver to load the right number of coefficients during- the
init
* phase.*/if (config->cm_coeff_after_ctm_property) {drm_object_attach_property(mode_obj,config->cm_coeff_after_ctm_property,INTEL_INFO(dev)->num_samples_after_ctm);
DRM_DEBUG_DRIVER("Gamma query property initialized\n");}if (config->cm_coeff_before_ctm_property) {drm_object_attach_property(mode_obj,config->cm_coeff_before_ctm_property,INTEL_INFO(dev)->num_samples_before_ctm);
DRM_DEBUG_DRIVER("Degamma query propertyinitialized\n");
}Shouldn't this commit be squashed with the previous ? You're also missing the function declaration.
Please see the history of the review comments, initially this patch was like as you suggested. But one of the previous review comments, suggested to split that into two, as it was 'overdoing' stuff. So I had split it into two separate ones, so I think this is ok :)
Sorry did not see it. The revision history should be within the patch either above or below the --- line.
So this is just the body of the function, and definition is coming up in next patch, where this function is being called from intel_crtc_init (patch 17/22 to be specific).
This is not how things work I'm afraid. The function declaration and definition must _always_ be in the same patch.
This is confusing, I have received previous comments which say the other way. But anyways, I can add the definition also in this patch, if you like that.
Do you have a link handy ? I suspect that something else was mentioned in that comment as splitting function declaration and definition is extremely uncommon.
Thanks Emil
DRM color manager allows the driver to showcase its best color correction capabilities using the specific query property cm_coeff_after_ctm_property. The driver must loads the no. of coefficients for color correction as per the platform capability during the init time.
This patch adds no of coefficitents for best gamma color correction modes possible in CHV, in device info structure, which is: Gamma(10 bit, CGM HW unit): 257 coeff
These values will be loaded in cm_crtc_palette_capabilities_property during the CRTC init section, by color manager's attach function.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com --- drivers/gpu/drm/i915/i915_drv.c | 2 ++ drivers/gpu/drm/i915/intel_color_manager.h | 3 +++ 2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 1cb6b82..7466dba 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -34,6 +34,7 @@ #include "i915_drv.h" #include "i915_trace.h" #include "intel_drv.h" +#include "intel_color_manager.h"
#include <linux/console.h> #include <linux/module.h> @@ -349,6 +350,7 @@ static const struct intel_device_info intel_cherryview_info = { .gen = 8, .num_pipes = 3, .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, + .num_samples_after_ctm = CHV_10BIT_GAMMA_MAX_VALS, .is_valleyview = 1, .display_mmio_offset = VLV_DISPLAY_BASE, GEN_CHV_PIPEOFFSETS, diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h index eec52a7..a378fe1 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.h +++ b/drivers/gpu/drm/i915/intel_color_manager.h @@ -48,3 +48,6 @@ CLEAR_BITS(target, start_bit, no_bits); \ target |= (bit_pattern << start_bit); \ } while (0) + +/* CHV */ +#define CHV_10BIT_GAMMA_MAX_VALS 257
DRM color manager allows the driver to showcase its best color correction capabilities using the specific query property cm_coeff_before_ctm_property. The driver must loads the no. of coefficients for color correction as per the platform capability during the init time.
This patch adds no of coefficitents for degamma color correction modes possible in CHV, in device info structure, which is: CGM Degamma(10 bit, CGM HW unit): 65 coeff
These values will be loaded in cm_crtc_palette_capabilities_property during the CRTC init section, by color manager's attach function.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@l.com --- drivers/gpu/drm/i915/i915_drv.c | 1 + drivers/gpu/drm/i915/intel_color_manager.h | 1 + 2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 7466dba..5a25a35 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -351,6 +351,7 @@ static const struct intel_device_info intel_cherryview_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, .num_samples_after_ctm = CHV_10BIT_GAMMA_MAX_VALS, + .num_samples_before_ctm = CHV_DEGAMMA_MAX_VALS, .is_valleyview = 1, .display_mmio_offset = VLV_DISPLAY_BASE, GEN_CHV_PIPEOFFSETS, diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h index a378fe1..14a1309 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.h +++ b/drivers/gpu/drm/i915/intel_color_manager.h @@ -51,3 +51,4 @@
/* CHV */ #define CHV_10BIT_GAMMA_MAX_VALS 257 +#define CHV_DEGAMMA_MAX_VALS 65
CHV/BSW platform supports two different pipe level gamma correction modes, which are: 1. Legacy 8-bit mode 2. 10-bit CGM (Color Gamut Mapping) mode
This patch does the following: 1. Attaches Gamma property to CRTC 3. Adds the core Gamma correction function for CHV/BSW 4. Adds Gamma correction macros
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com --- drivers/gpu/drm/i915/i915_reg.h | 12 +++ drivers/gpu/drm/i915/intel_color_manager.c | 114 +++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_color_manager.h | 13 ++++ 3 files changed, 139 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 60e6a73..885ac8a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8038,4 +8038,16 @@ enum skl_disp_power_wells { #define GEN9_VEBOX_MOCS_0 0xcb00 /* Video MOCS base register*/ #define GEN9_BLT_MOCS_0 0xcc00 /* Blitter MOCS base register*/
+/* Color Management */ +#define PIPEA_CGM_CONTROL (VLV_DISPLAY_BASE + 0x67A00) +#define PIPEB_CGM_CONTROL (VLV_DISPLAY_BASE + 0x69A00) +#define PIPEC_CGM_CONTROL (VLV_DISPLAY_BASE + 0x6BA00) +#define PIPEA_CGM_GAMMA (VLV_DISPLAY_BASE + 0x67000) +#define PIPEB_CGM_GAMMA (VLV_DISPLAY_BASE + 0x69000) +#define PIPEC_CGM_GAMMA (VLV_DISPLAY_BASE + 0x6B000) +#define _PIPE_CGM_CONTROL(pipe) \ + (_PIPE3(pipe, PIPEA_CGM_CONTROL, PIPEB_CGM_CONTROL, PIPEC_CGM_CONTROL)) +#define _PIPE_GAMMA_BASE(pipe) \ + (_PIPE3(pipe, PIPEA_CGM_GAMMA, PIPEB_CGM_GAMMA, PIPEC_CGM_GAMMA)) + #endif /* _I915_REG_H_ */ diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index e466748..cf381b8 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -27,6 +27,112 @@
#include "intel_color_manager.h"
+static int chv_set_gamma(struct drm_device *dev, struct drm_property_blob *blob, + struct drm_crtc *crtc) +{ + bool flag = false; + enum pipe pipe; + u16 red_fract, green_fract, blue_fract; + u32 red, green, blue, num_samples; + u32 word = 0; + u32 count = 0; + u32 cgm_gamma_reg = 0; + u32 cgm_control_reg = 0; + int ret = 0, length; + struct drm_r32g32b32 *correction_values = NULL; + struct drm_palette *gamma_data; + struct drm_i915_private *dev_priv = dev->dev_private; + + if (WARN_ON(!blob)) + return -EINVAL; + + gamma_data = (struct drm_palette *)blob->data; + pipe = to_intel_crtc(crtc)->pipe; + num_samples = gamma_data->num_samples; + length = num_samples * sizeof(struct drm_r32g32b32); + + switch (num_samples) { + case GAMMA_DISABLE_VALS: + + /* Disable Gamma functionality on Pipe - CGM Block */ + cgm_control_reg = I915_READ(_PIPE_CGM_CONTROL(pipe)); + cgm_control_reg &= ~CGM_GAMMA_EN; + I915_WRITE(_PIPE_CGM_CONTROL(pipe), cgm_control_reg); + + DRM_DEBUG_DRIVER("Gamma disabled on Pipe %c\n", + pipe_name(pipe)); + ret = 0; + break; + + case CHV_8BIT_GAMMA_MAX_VALS: + case CHV_10BIT_GAMMA_MAX_VALS: + + count = 0; + cgm_gamma_reg = _PIPE_GAMMA_BASE(pipe); + correction_values = (struct drm_r32g32b32 *)&gamma_data->lut; + + while (count < num_samples) { + blue = correction_values[count].b32; + green = correction_values[count].g32; + red = correction_values[count].r32; + + if (blue > CHV_MAX_GAMMA) + blue = CHV_MAX_GAMMA; + + if (green > CHV_MAX_GAMMA) + green = CHV_MAX_GAMMA; + + if (red > CHV_MAX_GAMMA) + red = CHV_MAX_GAMMA; + + /* get MSB 10 bits from fraction part (14:23) */ + blue_fract = GET_BITS(blue, 14, 10); + green_fract = GET_BITS(green, 14, 10); + red_fract = GET_BITS(red, 14, 10); + + /* Green (25:16) and Blue (9:0) to be written */ + SET_BITS(word, green_fract, 16, 10); + SET_BITS(word, blue_fract, 0, 10); + I915_WRITE(cgm_gamma_reg, word); + cgm_gamma_reg += 4; + + /* Red (9:0) to be written */ + word = red_fract; + I915_WRITE(cgm_gamma_reg, word); + + cgm_gamma_reg += 4; + count++; + + /* + * On CHV, the best supported Gamma capability is + * CGM block, that takes 257 samples. + * If user gives 256 samples (legacy mode), then + * duplicate the 256th value to 257th. + * "flag" is used to make sure it happens only once + */ + if (num_samples == CHV_8BIT_GAMMA_MAX_VALS && + count == CHV_8BIT_GAMMA_MAX_VALS && !flag) { + count--; + flag = true; + } + } + + /* Enable (CGM) Gamma on Pipe */ + I915_WRITE(_PIPE_CGM_CONTROL(pipe), + I915_READ(_PIPE_CGM_CONTROL(pipe)) | CGM_GAMMA_EN); + DRM_DEBUG_DRIVER("CGM Gamma enabled on Pipe %c\n", + pipe_name(pipe)); + ret = 0; + break; + + default: + DRM_ERROR("Invalid number of samples for Gamma LUT\n"); + ret = -EINVAL; + } + + return ret; +} + void intel_attach_color_properties_to_crtc(struct drm_device *dev, struct drm_crtc *crtc) { @@ -61,4 +167,12 @@ void intel_attach_color_properties_to_crtc(struct drm_device *dev, INTEL_INFO(dev)->num_samples_before_ctm); DRM_DEBUG_DRIVER("Degamma query property initialized\n"); } + + /* Gamma correction */ + if (config->cm_palette_after_ctm_property) { + drm_object_attach_property(mode_obj, + config->cm_palette_after_ctm_property, 0); + DRM_DEBUG_DRIVER("gamma property attached to CRTC\n"); + } + } diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h index 14a1309..de706d9 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.h +++ b/drivers/gpu/drm/i915/intel_color_manager.h @@ -52,3 +52,16 @@ /* CHV */ #define CHV_10BIT_GAMMA_MAX_VALS 257 #define CHV_DEGAMMA_MAX_VALS 65 + +/* No of coeff for disabling gamma is 0 */ +#define GAMMA_DISABLE_VALS 0 + +/* Gamma on CHV */ +#define CHV_10BIT_GAMMA_MAX_VALS 257 +#define CHV_8BIT_GAMMA_MAX_VALS 256 +#define CHV_10BIT_GAMMA_MSB_SHIFT 6 +#define CHV_GAMMA_SHIFT_GREEN 16 +#define CHV_MAX_GAMMA ((1 << 24) - 1) + +/* CHV CGM Block */ +#define CGM_GAMMA_EN (1 << 2)
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma shashank.sharma@intel.com wrote:
CHV/BSW platform supports two different pipe level gamma correction modes, which are:
- Legacy 8-bit mode
- 10-bit CGM (Color Gamut Mapping) mode
This patch does the following:
- Attaches Gamma property to CRTC
- Adds the core Gamma correction function for CHV/BSW
- Adds Gamma correction macros
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com
drivers/gpu/drm/i915/i915_reg.h | 12 +++ drivers/gpu/drm/i915/intel_color_manager.c | 114 +++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_color_manager.h | 13 ++++ 3 files changed, 139 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 60e6a73..885ac8a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8038,4 +8038,16 @@ enum skl_disp_power_wells { #define GEN9_VEBOX_MOCS_0 0xcb00 /* Video MOCS base register*/ #define GEN9_BLT_MOCS_0 0xcc00 /* Blitter MOCS base register*/
+/* Color Management */ +#define PIPEA_CGM_CONTROL (VLV_DISPLAY_BASE + 0x67A00) +#define PIPEB_CGM_CONTROL (VLV_DISPLAY_BASE + 0x69A00) +#define PIPEC_CGM_CONTROL (VLV_DISPLAY_BASE + 0x6BA00) +#define PIPEA_CGM_GAMMA (VLV_DISPLAY_BASE + 0x67000) +#define PIPEB_CGM_GAMMA (VLV_DISPLAY_BASE + 0x69000) +#define PIPEC_CGM_GAMMA (VLV_DISPLAY_BASE + 0x6B000) +#define _PIPE_CGM_CONTROL(pipe) \
(_PIPE3(pipe, PIPEA_CGM_CONTROL, PIPEB_CGM_CONTROL, PIPEC_CGM_CONTROL))+#define _PIPE_GAMMA_BASE(pipe) \
(_PIPE3(pipe, PIPEA_CGM_GAMMA, PIPEB_CGM_GAMMA, PIPEC_CGM_GAMMA))#endif /* _I915_REG_H_ */ diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index e466748..cf381b8 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -27,6 +27,112 @@
#include "intel_color_manager.h"
+static int chv_set_gamma(struct drm_device *dev, struct drm_property_blob *blob,
struct drm_crtc *crtc)+{
bool flag = false;enum pipe pipe;u16 red_fract, green_fract, blue_fract;u32 red, green, blue, num_samples;u32 word = 0;u32 count = 0;u32 cgm_gamma_reg = 0;u32 cgm_control_reg = 0;int ret = 0, length;struct drm_r32g32b32 *correction_values = NULL;
You can drop the useless initialization of correction_values. Same goes for patches 19 and 21.
struct drm_palette *gamma_data;struct drm_i915_private *dev_priv = dev->dev_private;if (WARN_ON(!blob))return -EINVAL;gamma_data = (struct drm_palette *)blob->data;pipe = to_intel_crtc(crtc)->pipe;num_samples = gamma_data->num_samples;length = num_samples * sizeof(struct drm_r32g32b32);
Calculation can overflow.
switch (num_samples) {case GAMMA_DISABLE_VALS:/* Disable Gamma functionality on Pipe - CGM Block */cgm_control_reg = I915_READ(_PIPE_CGM_CONTROL(pipe));cgm_control_reg &= ~CGM_GAMMA_EN;I915_WRITE(_PIPE_CGM_CONTROL(pipe), cgm_control_reg);DRM_DEBUG_DRIVER("Gamma disabled on Pipe %c\n",pipe_name(pipe));
Indentation looks wrong here.
ret = 0;
Drop the variable and return 0, at the bottom of the function ?
break;case CHV_8BIT_GAMMA_MAX_VALS:case CHV_10BIT_GAMMA_MAX_VALS:count = 0;cgm_gamma_reg = _PIPE_GAMMA_BASE(pipe);correction_values = (struct drm_r32g32b32 *)&gamma_data->lut;while (count < num_samples) {
Using for(i = 0;....) loop seems the more common approach ?
[snip]
/** On CHV, the best supported Gamma capability is* CGM block, that takes 257 samples.* If user gives 256 samples (legacy mode), then* duplicate the 256th value to 257th.* "flag" is used to make sure it happens only once*/if (num_samples == CHV_8BIT_GAMMA_MAX_VALS &&count == CHV_8BIT_GAMMA_MAX_VALS && !flag) {count--;flag = true;}
There is little point in going over this if statement 256 odd times. Split it out of the loop ?
}/* Enable (CGM) Gamma on Pipe */I915_WRITE(_PIPE_CGM_CONTROL(pipe),I915_READ(_PIPE_CGM_CONTROL(pipe)) | CGM_GAMMA_EN);DRM_DEBUG_DRIVER("CGM Gamma enabled on Pipe %c\n",pipe_name(pipe));
Indentation.
ret = 0;
Drop the variable ?
break;default:DRM_ERROR("Invalid number of samples for Gamma LUT\n");ret = -EINVAL;
return -EINVAL;
}return ret;
return 0;
Regards, Emil
Regards Shashank
On 10/10/2015 4:37 AM, Emil Velikov wrote:
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma shashank.sharma@intel.com wrote:
CHV/BSW platform supports two different pipe level gamma correction modes, which are:
- Legacy 8-bit mode
- 10-bit CGM (Color Gamut Mapping) mode
This patch does the following:
- Attaches Gamma property to CRTC
- Adds the core Gamma correction function for CHV/BSW
- Adds Gamma correction macros
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com
drivers/gpu/drm/i915/i915_reg.h | 12 +++ drivers/gpu/drm/i915/intel_color_manager.c | 114 +++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_color_manager.h | 13 ++++ 3 files changed, 139 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 60e6a73..885ac8a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8038,4 +8038,16 @@ enum skl_disp_power_wells { #define GEN9_VEBOX_MOCS_0 0xcb00 /* Video MOCS base register*/ #define GEN9_BLT_MOCS_0 0xcc00 /* Blitter MOCS base register*/
+/* Color Management */ +#define PIPEA_CGM_CONTROL (VLV_DISPLAY_BASE + 0x67A00) +#define PIPEB_CGM_CONTROL (VLV_DISPLAY_BASE + 0x69A00) +#define PIPEC_CGM_CONTROL (VLV_DISPLAY_BASE + 0x6BA00) +#define PIPEA_CGM_GAMMA (VLV_DISPLAY_BASE + 0x67000) +#define PIPEB_CGM_GAMMA (VLV_DISPLAY_BASE + 0x69000) +#define PIPEC_CGM_GAMMA (VLV_DISPLAY_BASE + 0x6B000) +#define _PIPE_CGM_CONTROL(pipe) \
(_PIPE3(pipe, PIPEA_CGM_CONTROL, PIPEB_CGM_CONTROL, PIPEC_CGM_CONTROL))+#define _PIPE_GAMMA_BASE(pipe) \
(_PIPE3(pipe, PIPEA_CGM_GAMMA, PIPEB_CGM_GAMMA, PIPEC_CGM_GAMMA))- #endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index e466748..cf381b8 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -27,6 +27,112 @@
#include "intel_color_manager.h"
+static int chv_set_gamma(struct drm_device *dev, struct drm_property_blob *blob,
struct drm_crtc *crtc)+{
bool flag = false;enum pipe pipe;u16 red_fract, green_fract, blue_fract;u32 red, green, blue, num_samples;u32 word = 0;u32 count = 0;u32 cgm_gamma_reg = 0;u32 cgm_control_reg = 0;int ret = 0, length;struct drm_r32g32b32 *correction_values = NULL;You can drop the useless initialization of correction_values. Same goes for patches 19 and 21.
Agree, thanks for pointing it out.
struct drm_palette *gamma_data;struct drm_i915_private *dev_priv = dev->dev_private;if (WARN_ON(!blob))return -EINVAL;gamma_data = (struct drm_palette *)blob->data;pipe = to_intel_crtc(crtc)->pipe;num_samples = gamma_data->num_samples;length = num_samples * sizeof(struct drm_r32g32b32);Calculation can overflow.
good catch, will take care of this.
switch (num_samples) {case GAMMA_DISABLE_VALS:/* Disable Gamma functionality on Pipe - CGM Block */cgm_control_reg = I915_READ(_PIPE_CGM_CONTROL(pipe));cgm_control_reg &= ~CGM_GAMMA_EN;I915_WRITE(_PIPE_CGM_CONTROL(pipe), cgm_control_reg);DRM_DEBUG_DRIVER("Gamma disabled on Pipe %c\n",pipe_name(pipe));Indentation looks wrong here.
Oops, bloody SI :).
ret = 0;Drop the variable and return 0, at the bottom of the function ?
Let me check this out.
break;case CHV_8BIT_GAMMA_MAX_VALS:case CHV_10BIT_GAMMA_MAX_VALS:count = 0;cgm_gamma_reg = _PIPE_GAMMA_BASE(pipe);correction_values = (struct drm_r32g32b32 *)&gamma_data->lut;while (count < num_samples) {Using for(i = 0;....) loop seems the more common approach ?
Nah, we are good with while. The whole color management series prefers while (and me too.... :))
[snip]
/** On CHV, the best supported Gamma capability is* CGM block, that takes 257 samples.* If user gives 256 samples (legacy mode), then* duplicate the 256th value to 257th.* "flag" is used to make sure it happens only once*/if (num_samples == CHV_8BIT_GAMMA_MAX_VALS &&count == CHV_8BIT_GAMMA_MAX_VALS && !flag) {count--;flag = true;}There is little point in going over this if statement 256 odd times. Split it out of the loop ?
Makes sense for sure, let me try this out.
}/* Enable (CGM) Gamma on Pipe */I915_WRITE(_PIPE_CGM_CONTROL(pipe),I915_READ(_PIPE_CGM_CONTROL(pipe)) | CGM_GAMMA_EN);DRM_DEBUG_DRIVER("CGM Gamma enabled on Pipe %c\n",pipe_name(pipe));Indentation.
Guilty.
ret = 0;Drop the variable ?
Agree
break;default:DRM_ERROR("Invalid number of samples for Gamma LUT\n");ret = -EINVAL;return -EINVAL;
Agree
}return ret;return 0;
Agree
Regards, Emil
On 10 October 2015 at 06:09, Sharma, Shashank shashank.sharma@intel.com wrote:
On 10/10/2015 4:37 AM, Emil Velikov wrote:
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma shashank.sharma@intel.com wrote:
CHV/BSW platform supports two different pipe level gamma correction modes, which are:
- Legacy 8-bit mode
- 10-bit CGM (Color Gamut Mapping) mode
This patch does the following:
- Attaches Gamma property to CRTC
- Adds the core Gamma correction function for CHV/BSW
- Adds Gamma correction macros
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com
[snip]
length = num_samples * sizeof(struct drm_r32g32b32);Calculation can overflow.
good catch, will take care of this.
Actually we do not at all here as the variable is unused. Same applies for patch 21/22.
[snip]
while (count < num_samples) {Using for(i = 0;....) loop seems the more common approach ?
Nah, we are good with while. The whole color management series prefers while (and me too.... :))
Hmm... so you'd prefer your approach/coding style over the one already in i915? Feels a bit strange but as long as others are happy fine go with it.
Regards, Emil
Regards Shashank
On 10/13/2015 6:38 PM, Emil Velikov wrote:
On 10 October 2015 at 06:09, Sharma, Shashank shashank.sharma@intel.com wrote:
On 10/10/2015 4:37 AM, Emil Velikov wrote:
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma shashank.sharma@intel.com wrote:
CHV/BSW platform supports two different pipe level gamma correction modes, which are:
- Legacy 8-bit mode
- 10-bit CGM (Color Gamut Mapping) mode
This patch does the following:
- Attaches Gamma property to CRTC
- Adds the core Gamma correction function for CHV/BSW
- Adds Gamma correction macros
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com
[snip]
length = num_samples * sizeof(struct drm_r32g32b32);Calculation can overflow.
good catch, will take care of this.
Actually we do not at all here as the variable is unused. Same applies for patch 21/22.
Yep, Rob mentioned that in his comment, I have removed this in the latest patch set I have sent.
[snip]
while (count < num_samples) {Using for(i = 0;....) loop seems the more common approach ?
Nah, we are good with while. The whole color management series prefers while (and me too.... :))
Hmm... so you'd prefer your approach/coding style over the one already in i915? Feels a bit strange but as long as others are happy fine go with it.
I am not sure if I915 follows a general rule of using for(...) over while(), coz I see many instances of using a while in i915_gem, i915_drv, i915_irq etc, so it should be good. I would see if someone else can suggest another good reason.
Regards, Emil
On 13 October 2015 at 14:40, Sharma, Shashank shashank.sharma@intel.com wrote:
I am not sure if I915 follows a general rule of using for(...) over while(), coz I see many instances of using a while in i915_gem, i915_drv, i915_irq etc, so it should be good. I would see if someone else can suggest another good reason.
I'm not saying "you should never use while loops", but more of "people use for loops when accessing arrays of information". I cannot see any cases of the latter in i915. Perhaps I'm looking at some old code ?
The point I'm trying to make here is that people are unlikely to make comments about such trivial nitpicks (bikeshedding), but new contributions should stick with the existing approach, rather than going for "I like XXX" :)
Take any and all of my with a grain of salt, just in case.
Regards, Emil
Regards Shashank
On 10/13/2015 7:29 PM, Emil Velikov wrote:
On 13 October 2015 at 14:40, Sharma, Shashank shashank.sharma@intel.com wrote:
I am not sure if I915 follows a general rule of using for(...) over while(), coz I see many instances of using a while in i915_gem, i915_drv, i915_irq etc, so it should be good. I would see if someone else can suggest another good reason.
I'm not saying "you should never use while loops", but more of "people use for loops when accessing arrays of information". I cannot see any cases of the latter in i915. Perhaps I'm looking at some old code ?
The point I'm trying to make here is that people are unlikely to make comments about such trivial nitpicks (bikeshedding), but new contributions should stick with the existing approach, rather than going for "I like XXX" :)
Take any and all of my with a grain of salt, just in case.
Its a very well written and logical comment, but I like this last line the most :) :)
Regards, Emil
CHV/BSW supports Degamma color correction, which linearizes all the non-linear color values. This will be applied before Color Transformation.
This patch does the following: 1. Attach deGamma property to CRTC 2. Add the core function to program DeGamma correction values for CHV/BSW platform 2. Add DeGamma correction macros/defines
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com --- drivers/gpu/drm/i915/i915_reg.h | 6 ++ drivers/gpu/drm/i915/intel_color_manager.c | 93 ++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_color_manager.h | 5 ++ 3 files changed, 104 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 885ac8a..c32e35d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8050,4 +8050,10 @@ enum skl_disp_power_wells { #define _PIPE_GAMMA_BASE(pipe) \ (_PIPE3(pipe, PIPEA_CGM_GAMMA, PIPEB_CGM_GAMMA, PIPEC_CGM_GAMMA))
+#define PIPEA_CGM_DEGAMMA (VLV_DISPLAY_BASE + 0x66000) +#define PIPEB_CGM_DEGAMMA (VLV_DISPLAY_BASE + 0x68000) +#define PIPEC_CGM_DEGAMMA (VLV_DISPLAY_BASE + 0x6A000) +#define _PIPE_DEGAMMA_BASE(pipe) \ + (_PIPE3(pipe, PIPEA_CGM_DEGAMMA, PIPEB_CGM_DEGAMMA, PIPEC_CGM_DEGAMMA)) + #endif /* _I915_REG_H_ */ diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index cf381b8..bbfe185 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -27,6 +27,93 @@
#include "intel_color_manager.h"
+static int chv_set_degamma(struct drm_device *dev, + struct drm_property_blob *blob, struct drm_crtc *crtc) +{ + u16 red_fract, green_fract, blue_fract; + u32 red, green, blue; + u32 num_samples; + u32 word = 0; + u32 count = 0; + u32 cgm_control_reg = 0; + u32 cgm_degamma_reg = 0; + int length; + int ret = 0; + enum pipe pipe; + struct drm_palette *degamma_data; + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_r32g32b32 *correction_values = NULL; + + if (WARN_ON(!blob)) + return -EINVAL; + + degamma_data = (struct drm_palette *)blob->data; + pipe = to_intel_crtc(crtc)->pipe; + num_samples = degamma_data->num_samples; + length = num_samples * sizeof(struct drm_r32g32b32); + + if (num_samples == GAMMA_DISABLE_VALS) { + /* Disable DeGamma functionality on Pipe - CGM Block */ + cgm_control_reg = I915_READ(_PIPE_CGM_CONTROL(pipe)); + cgm_control_reg &= ~CGM_DEGAMMA_EN; + I915_WRITE(_PIPE_CGM_CONTROL(pipe), cgm_control_reg); + DRM_DEBUG_DRIVER("DeGamma disabled on Pipe %c\n", + pipe_name(pipe)); + ret = 0; + } else if (num_samples == CHV_DEGAMMA_MAX_VALS) { + cgm_degamma_reg = _PIPE_DEGAMMA_BASE(pipe); + + count = 0; + correction_values = (struct drm_r32g32b32 *)°amma_data->lut; + while (count < CHV_DEGAMMA_MAX_VALS) { + blue = correction_values[count].b32; + green = correction_values[count].g32; + red = correction_values[count].r32; + + if (blue > CHV_MAX_GAMMA) + blue = CHV_MAX_GAMMA; + + if (green > CHV_MAX_GAMMA) + green = CHV_MAX_GAMMA; + + if (red > CHV_MAX_GAMMA) + red = CHV_MAX_GAMMA; + + blue_fract = GET_BITS(blue, 8, 14); + green_fract = GET_BITS(green, 8, 14); + red_fract = GET_BITS(red, 8, 14); + + /* Green (29:16) and Blue (13:0) in DWORD1 */ + SET_BITS(word, green_fract, 16, 14); + SET_BITS(word, green_fract, 0, 14); + I915_WRITE(cgm_degamma_reg, word); + cgm_degamma_reg += 4; + + /* Red (13:0) to be written to DWORD2 */ + word = red_fract; + I915_WRITE(cgm_degamma_reg, word); + cgm_degamma_reg += 4; + count++; + } + + DRM_DEBUG_DRIVER("DeGamma LUT loaded for Pipe %c\n", + pipe_name(pipe)); + + /* Enable DeGamma on Pipe */ + I915_WRITE(_PIPE_CGM_CONTROL(pipe), + I915_READ(_PIPE_CGM_CONTROL(pipe)) | CGM_DEGAMMA_EN); + + DRM_DEBUG_DRIVER("DeGamma correction enabled on Pipe %c\n", + pipe_name(pipe)); + ret = 0; + } else { + DRM_ERROR("Invalid number of samples for DeGamma LUT\n"); + return -EINVAL; + } + + return ret; +} + static int chv_set_gamma(struct drm_device *dev, struct drm_property_blob *blob, struct drm_crtc *crtc) { @@ -175,4 +262,10 @@ void intel_attach_color_properties_to_crtc(struct drm_device *dev, DRM_DEBUG_DRIVER("gamma property attached to CRTC\n"); }
+ /* Degamma correction */ + if (config->cm_palette_before_ctm_property) { + drm_object_attach_property(mode_obj, + config->cm_palette_before_ctm_property, 0); + DRM_DEBUG_DRIVER("degamma property attached to CRTC\n"); + } } diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h index de706d9..77a2119 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.h +++ b/drivers/gpu/drm/i915/intel_color_manager.h @@ -63,5 +63,10 @@ #define CHV_GAMMA_SHIFT_GREEN 16 #define CHV_MAX_GAMMA ((1 << 24) - 1)
+/* Degamma on CHV */ +#define CHV_DEGAMMA_MSB_SHIFT 2 +#define CHV_DEGAMMA_GREEN_SHIFT 16 + /* CHV CGM Block */ #define CGM_GAMMA_EN (1 << 2) +#define CGM_DEGAMMA_EN (1 << 0)
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma shashank.sharma@intel.com wrote:
CHV/BSW supports Degamma color correction, which linearizes all the non-linear color values. This will be applied before Color Transformation.
This patch does the following:
- Attach deGamma property to CRTC
- Add the core function to program DeGamma correction values for CHV/BSW platform
- Add DeGamma correction macros/defines
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com
drivers/gpu/drm/i915/i915_reg.h | 6 ++ drivers/gpu/drm/i915/intel_color_manager.c | 93 ++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_color_manager.h | 5 ++ 3 files changed, 104 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 885ac8a..c32e35d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8050,4 +8050,10 @@ enum skl_disp_power_wells { #define _PIPE_GAMMA_BASE(pipe) \ (_PIPE3(pipe, PIPEA_CGM_GAMMA, PIPEB_CGM_GAMMA, PIPEC_CGM_GAMMA))
+#define PIPEA_CGM_DEGAMMA (VLV_DISPLAY_BASE + 0x66000) +#define PIPEB_CGM_DEGAMMA (VLV_DISPLAY_BASE + 0x68000) +#define PIPEC_CGM_DEGAMMA (VLV_DISPLAY_BASE + 0x6A000) +#define _PIPE_DEGAMMA_BASE(pipe) \
(_PIPE3(pipe, PIPEA_CGM_DEGAMMA, PIPEB_CGM_DEGAMMA, PIPEC_CGM_DEGAMMA))#endif /* _I915_REG_H_ */ diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index cf381b8..bbfe185 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -27,6 +27,93 @@
#include "intel_color_manager.h"
+static int chv_set_degamma(struct drm_device *dev,
struct drm_property_blob *blob, struct drm_crtc *crtc)+{
u16 red_fract, green_fract, blue_fract;u32 red, green, blue;u32 num_samples;u32 word = 0;u32 count = 0;u32 cgm_control_reg = 0;u32 cgm_degamma_reg = 0;int length;int ret = 0;enum pipe pipe;struct drm_palette *degamma_data;struct drm_i915_private *dev_priv = dev->dev_private;struct drm_r32g32b32 *correction_values = NULL;
Most of the above initializations can go.
if (WARN_ON(!blob))return -EINVAL;degamma_data = (struct drm_palette *)blob->data;pipe = to_intel_crtc(crtc)->pipe;num_samples = degamma_data->num_samples;length = num_samples * sizeof(struct drm_r32g32b32);
This can overflow.
if (num_samples == GAMMA_DISABLE_VALS) {
You've opted for switch statements in other patches. Why the if else ladder in here ?
/* Disable DeGamma functionality on Pipe - CGM Block */cgm_control_reg = I915_READ(_PIPE_CGM_CONTROL(pipe));cgm_control_reg &= ~CGM_DEGAMMA_EN;I915_WRITE(_PIPE_CGM_CONTROL(pipe), cgm_control_reg);DRM_DEBUG_DRIVER("DeGamma disabled on Pipe %c\n",pipe_name(pipe));ret = 0;
Drop the ret variable through the function ?
} else if (num_samples == CHV_DEGAMMA_MAX_VALS) {cgm_degamma_reg = _PIPE_DEGAMMA_BASE(pipe);count = 0;correction_values = (struct drm_r32g32b32 *)°amma_data->lut;while (count < CHV_DEGAMMA_MAX_VALS) {
For loop ?
Regards, Emil
Regards Shashank
On 10/10/2015 4:41 AM, Emil Velikov wrote:
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma shashank.sharma@intel.com wrote:
CHV/BSW supports Degamma color correction, which linearizes all the non-linear color values. This will be applied before Color Transformation.
This patch does the following:
- Attach deGamma property to CRTC
- Add the core function to program DeGamma correction values for CHV/BSW platform
- Add DeGamma correction macros/defines
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com
drivers/gpu/drm/i915/i915_reg.h | 6 ++ drivers/gpu/drm/i915/intel_color_manager.c | 93 ++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_color_manager.h | 5 ++ 3 files changed, 104 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 885ac8a..c32e35d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8050,4 +8050,10 @@ enum skl_disp_power_wells { #define _PIPE_GAMMA_BASE(pipe) \ (_PIPE3(pipe, PIPEA_CGM_GAMMA, PIPEB_CGM_GAMMA, PIPEC_CGM_GAMMA))
+#define PIPEA_CGM_DEGAMMA (VLV_DISPLAY_BASE + 0x66000) +#define PIPEB_CGM_DEGAMMA (VLV_DISPLAY_BASE + 0x68000) +#define PIPEC_CGM_DEGAMMA (VLV_DISPLAY_BASE + 0x6A000) +#define _PIPE_DEGAMMA_BASE(pipe) \
(_PIPE3(pipe, PIPEA_CGM_DEGAMMA, PIPEB_CGM_DEGAMMA, PIPEC_CGM_DEGAMMA))- #endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index cf381b8..bbfe185 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -27,6 +27,93 @@
#include "intel_color_manager.h"
+static int chv_set_degamma(struct drm_device *dev,
struct drm_property_blob *blob, struct drm_crtc *crtc)+{
u16 red_fract, green_fract, blue_fract;u32 red, green, blue;u32 num_samples;u32 word = 0;u32 count = 0;u32 cgm_control_reg = 0;u32 cgm_degamma_reg = 0;int length;int ret = 0;enum pipe pipe;struct drm_palette *degamma_data;struct drm_i915_private *dev_priv = dev->dev_private;struct drm_r32g32b32 *correction_values = NULL;Most of the above initializations can go.
Agree.
if (WARN_ON(!blob))return -EINVAL;degamma_data = (struct drm_palette *)blob->data;pipe = to_intel_crtc(crtc)->pipe;num_samples = degamma_data->num_samples;length = num_samples * sizeof(struct drm_r32g32b32);This can overflow.
Agree
if (num_samples == GAMMA_DISABLE_VALS) {You've opted for switch statements in other patches. Why the if else ladder in here ?
As a general programming rule, we tend to switch to switch, when no of if-else conditions is > 3, here its just 3, enable/disable/invalid so kept as if/else condition for simpler code.
/* Disable DeGamma functionality on Pipe - CGM Block */cgm_control_reg = I915_READ(_PIPE_CGM_CONTROL(pipe));cgm_control_reg &= ~CGM_DEGAMMA_EN;I915_WRITE(_PIPE_CGM_CONTROL(pipe), cgm_control_reg);DRM_DEBUG_DRIVER("DeGamma disabled on Pipe %c\n",pipe_name(pipe));ret = 0;Drop the ret variable through the function ?
Agree
} else if (num_samples == CHV_DEGAMMA_MAX_VALS) {cgm_degamma_reg = _PIPE_DEGAMMA_BASE(pipe);count = 0;correction_values = (struct drm_r32g32b32 *)°amma_data->lut;while (count < CHV_DEGAMMA_MAX_VALS) {For loop ?
Will pass, prefer while.
Regards, Emil
CHV/BSW supports Color Space Conversion (CSC) using a 3x3 matrix that needs to be programmed into CGM (Color Gamut Mapping) registers.
This patch does the following: 1. Attaches CSC property to CRTC 2. Adds the core function to program CSC correction values 3. Adds CSC correction macros
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com Signed-off-by: Kumar, Kiran S kiran.s.kumar@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 8 +++ drivers/gpu/drm/i915/intel_color_manager.c | 94 ++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_color_manager.h | 19 ++++++ 3 files changed, 121 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c32e35d..5825ab2 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8056,4 +8056,12 @@ enum skl_disp_power_wells { #define _PIPE_DEGAMMA_BASE(pipe) \ (_PIPE3(pipe, PIPEA_CGM_DEGAMMA, PIPEB_CGM_DEGAMMA, PIPEC_CGM_DEGAMMA))
+#define PIPEA_CGM_CSC (VLV_DISPLAY_BASE + 0x67900) +#define PIPEB_CGM_CSC (VLV_DISPLAY_BASE + 0x69900) +#define PIPEC_CGM_CSC (VLV_DISPLAY_BASE + 0x6B900) +#define _PIPE_CSC_BASE(pipe) \ + (_PIPE3(pipe, PIPEA_CGM_CSC, PIPEB_CGM_CSC, PIPEC_CGM_CSC)) + + + #endif /* _I915_REG_H_ */ diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index bbfe185..433e50a 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -27,6 +27,93 @@
#include "intel_color_manager.h"
+static s16 chv_prepare_csc_coeff(s64 csc_value) +{ + s32 csc_int_value; + u32 csc_fract_value; + s16 csc_s3_12_format; + + if (csc_value >= 0) { + csc_value += CHV_CSC_FRACT_ROUNDOFF; + if (csc_value > CHV_CSC_COEFF_MAX) + csc_value = CHV_CSC_COEFF_MAX; + } else { + csc_value = -csc_value; + csc_value += CHV_CSC_FRACT_ROUNDOFF; + if (csc_value > CHV_CSC_COEFF_MAX + 1) + csc_value = CHV_CSC_COEFF_MAX + 1; + csc_value = -csc_value; + } + + csc_int_value = csc_value >> CHV_CSC_COEFF_SHIFT; + csc_int_value <<= CHV_CSC_COEFF_INT_SHIFT; + if (csc_value < 0) + csc_int_value |= CSC_COEFF_SIGN; + + csc_fract_value = csc_value; + csc_fract_value >>= CHV_CSC_COEFF_FRACT_SHIFT; + csc_s3_12_format = csc_int_value | csc_fract_value; + + return csc_s3_12_format; +} + +static int chv_set_csc(struct drm_device *dev, struct drm_property_blob *blob, + struct drm_crtc *crtc) +{ + struct drm_ctm *csc_data; + struct drm_i915_private *dev_priv = dev->dev_private; + u32 reg; + enum pipe pipe; + s32 word = 0, temp; + int count = 0; + + if (WARN_ON(!blob)) + return -EINVAL; + + if (blob->length != sizeof(struct drm_ctm)) { + DRM_ERROR("Invalid length of data received\n"); + return -EINVAL; + } + + csc_data = (struct drm_ctm *)blob->data; + pipe = to_intel_crtc(crtc)->pipe; + + /* Disable CSC functionality */ + reg = _PIPE_CGM_CONTROL(pipe); + I915_WRITE(reg, I915_READ(reg) & (~CGM_CSC_EN)); + + DRM_DEBUG_DRIVER("Disabled CSC Functionality on Pipe %c\n", + pipe_name(pipe)); + + reg = _PIPE_CSC_BASE(pipe); + while (count < CSC_MAX_VALS) { + temp = chv_prepare_csc_coeff( + csc_data->ctm_coeff[count]); + SET_BITS(word, GET_BITS(temp, 16, 16), 0, 16); + + /* + * Last value to be written in 1 register. + * Otherwise, each pair of CSC values go + * into 1 register + */ + if (count != (CSC_MAX_VALS - 1)) { + count++; + temp = chv_prepare_csc_coeff( + csc_data->ctm_coeff[count]); + SET_BITS(word, GET_BITS(temp, 16, 16), 16, 16); + } + I915_WRITE(reg, word); + reg += 4; + count++; + } + + /* Enable CSC functionality */ + reg = _PIPE_CGM_CONTROL(pipe); + I915_WRITE(reg, I915_READ(reg) | CGM_CSC_EN); + DRM_DEBUG_DRIVER("CSC enabled on Pipe %c\n", pipe_name(pipe)); + return 0; +} + static int chv_set_degamma(struct drm_device *dev, struct drm_property_blob *blob, struct drm_crtc *crtc) { @@ -268,4 +355,11 @@ void intel_attach_color_properties_to_crtc(struct drm_device *dev, config->cm_palette_before_ctm_property, 0); DRM_DEBUG_DRIVER("degamma property attached to CRTC\n"); } + + /* CSC */ + if (config->cm_ctm_property) { + drm_object_attach_property(mode_obj, + config->cm_ctm_property, 0); + DRM_DEBUG_DRIVER("CSC property attached to CRTC\n"); + } } diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h index 77a2119..7b96512 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.h +++ b/drivers/gpu/drm/i915/intel_color_manager.h @@ -63,10 +63,29 @@ #define CHV_GAMMA_SHIFT_GREEN 16 #define CHV_MAX_GAMMA ((1 << 24) - 1)
+/* + * CSC on CHV + * Fractional part is 32 bit, and we need only 12 MSBs for programming + * into registers. ROUNDOFF is required to minimize loss of precision. + */ +#define CHV_CSC_FRACT_ROUNDOFF (1 << 19) +/* + * CSC values are 64-bit values. For CHV, the maximum CSC value that + * user can program is 7.99999..., which can be represented in fixed point + * S31.32 format like this, with all fractional bits as 1 + */ +#define CHV_CSC_COEFF_MAX 0x00000007FFFFFFFF +#define CHV_CSC_COEFF_SHIFT 32 +#define CHV_CSC_COEFF_INT_SHIFT 28 +#define CSC_COEFF_SIGN (1 << 31) +#define CHV_CSC_COEFF_FRACT_SHIFT 4 +#define CSC_MAX_VALS 9 + /* Degamma on CHV */ #define CHV_DEGAMMA_MSB_SHIFT 2 #define CHV_DEGAMMA_GREEN_SHIFT 16
/* CHV CGM Block */ #define CGM_GAMMA_EN (1 << 2) +#define CGM_CSC_EN (1 << 1) #define CGM_DEGAMMA_EN (1 << 0)
On 9 October 2015 at 20:29, Shashank Sharma shashank.sharma@intel.com wrote:
CHV/BSW supports Color Space Conversion (CSC) using a 3x3 matrix that needs to be programmed into CGM (Color Gamut Mapping) registers.
This patch does the following:
- Attaches CSC property to CRTC
- Adds the core function to program CSC correction values
- Adds CSC correction macros
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com Signed-off-by: Kumar, Kiran S kiran.s.kumar@intel.com
drivers/gpu/drm/i915/i915_reg.h | 8 +++ drivers/gpu/drm/i915/intel_color_manager.c | 94 ++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_color_manager.h | 19 ++++++ 3 files changed, 121 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c32e35d..5825ab2 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8056,4 +8056,12 @@ enum skl_disp_power_wells { #define _PIPE_DEGAMMA_BASE(pipe) \ (_PIPE3(pipe, PIPEA_CGM_DEGAMMA, PIPEB_CGM_DEGAMMA, PIPEC_CGM_DEGAMMA))
+#define PIPEA_CGM_CSC (VLV_DISPLAY_BASE + 0x67900) +#define PIPEB_CGM_CSC (VLV_DISPLAY_BASE + 0x69900) +#define PIPEC_CGM_CSC (VLV_DISPLAY_BASE + 0x6B900) +#define _PIPE_CSC_BASE(pipe) \
(_PIPE3(pipe, PIPEA_CGM_CSC, PIPEB_CGM_CSC, PIPEC_CGM_CSC))#endif /* _I915_REG_H_ */ diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index bbfe185..433e50a 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -27,6 +27,93 @@
#include "intel_color_manager.h"
+static s16 chv_prepare_csc_coeff(s64 csc_value) +{
s32 csc_int_value;u32 csc_fract_value;s16 csc_s3_12_format;
The type of csc_s3_12_format and chv_prepare_csc_coeff() does not see correct. Seem like the fix got merged into another patch :\
[snip]
+static int chv_set_csc(struct drm_device *dev, struct drm_property_blob *blob,
struct drm_crtc *crtc)+{
struct drm_ctm *csc_data;struct drm_i915_private *dev_priv = dev->dev_private;u32 reg;enum pipe pipe;s32 word = 0, temp;int count = 0;if (WARN_ON(!blob))return -EINVAL;if (blob->length != sizeof(struct drm_ctm)) {DRM_ERROR("Invalid length of data received\n");return -EINVAL;}csc_data = (struct drm_ctm *)blob->data;pipe = to_intel_crtc(crtc)->pipe;/* Disable CSC functionality */reg = _PIPE_CGM_CONTROL(pipe);I915_WRITE(reg, I915_READ(reg) & (~CGM_CSC_EN));DRM_DEBUG_DRIVER("Disabled CSC Functionality on Pipe %c\n",pipe_name(pipe));reg = _PIPE_CSC_BASE(pipe);while (count < CSC_MAX_VALS) {temp = chv_prepare_csc_coeff(csc_data->ctm_coeff[count]);SET_BITS(word, GET_BITS(temp, 16, 16), 0, 16);/** Last value to be written in 1 register.* Otherwise, each pair of CSC values go* into 1 register*/if (count != (CSC_MAX_VALS - 1)) {count++;temp = chv_prepare_csc_coeff(csc_data->ctm_coeff[count]);SET_BITS(word, GET_BITS(temp, 16, 16), 16, 16);}
This looks a bit odd. Use the same approach as in bdw_write_12bit_gamma_precision() ?
Regards, Emil
Regards Shashank
On 10/10/2015 5:13 AM, Emil Velikov wrote:
On 9 October 2015 at 20:29, Shashank Sharma shashank.sharma@intel.com wrote:
CHV/BSW supports Color Space Conversion (CSC) using a 3x3 matrix that needs to be programmed into CGM (Color Gamut Mapping) registers.
This patch does the following:
- Attaches CSC property to CRTC
- Adds the core function to program CSC correction values
- Adds CSC correction macros
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com Signed-off-by: Kumar, Kiran S kiran.s.kumar@intel.com
drivers/gpu/drm/i915/i915_reg.h | 8 +++ drivers/gpu/drm/i915/intel_color_manager.c | 94 ++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_color_manager.h | 19 ++++++ 3 files changed, 121 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c32e35d..5825ab2 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8056,4 +8056,12 @@ enum skl_disp_power_wells { #define _PIPE_DEGAMMA_BASE(pipe) \ (_PIPE3(pipe, PIPEA_CGM_DEGAMMA, PIPEB_CGM_DEGAMMA, PIPEC_CGM_DEGAMMA))
+#define PIPEA_CGM_CSC (VLV_DISPLAY_BASE + 0x67900) +#define PIPEB_CGM_CSC (VLV_DISPLAY_BASE + 0x69900) +#define PIPEC_CGM_CSC (VLV_DISPLAY_BASE + 0x6B900) +#define _PIPE_CSC_BASE(pipe) \
(_PIPE3(pipe, PIPEA_CGM_CSC, PIPEB_CGM_CSC, PIPEC_CGM_CSC))- #endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index bbfe185..433e50a 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -27,6 +27,93 @@
#include "intel_color_manager.h"
+static s16 chv_prepare_csc_coeff(s64 csc_value) +{
s32 csc_int_value;u32 csc_fract_value;s16 csc_s3_12_format;The type of csc_s3_12_format and chv_prepare_csc_coeff() does not see correct. Seem like the fix got merged into another patch :\
Can you please elaborate this comment, I dont get it.
[snip]
+static int chv_set_csc(struct drm_device *dev, struct drm_property_blob *blob,
struct drm_crtc *crtc)+{
struct drm_ctm *csc_data;struct drm_i915_private *dev_priv = dev->dev_private;u32 reg;enum pipe pipe;s32 word = 0, temp;int count = 0;if (WARN_ON(!blob))return -EINVAL;if (blob->length != sizeof(struct drm_ctm)) {DRM_ERROR("Invalid length of data received\n");return -EINVAL;}csc_data = (struct drm_ctm *)blob->data;pipe = to_intel_crtc(crtc)->pipe;/* Disable CSC functionality */reg = _PIPE_CGM_CONTROL(pipe);I915_WRITE(reg, I915_READ(reg) & (~CGM_CSC_EN));DRM_DEBUG_DRIVER("Disabled CSC Functionality on Pipe %c\n",pipe_name(pipe));reg = _PIPE_CSC_BASE(pipe);while (count < CSC_MAX_VALS) {temp = chv_prepare_csc_coeff(csc_data->ctm_coeff[count]);SET_BITS(word, GET_BITS(temp, 16, 16), 0, 16);/** Last value to be written in 1 register.* Otherwise, each pair of CSC values go* into 1 register*/if (count != (CSC_MAX_VALS - 1)) {count++;temp = chv_prepare_csc_coeff(csc_data->ctm_coeff[count]);SET_BITS(word, GET_BITS(temp, 16, 16), 16, 16);}This looks a bit odd. Use the same approach as in bdw_write_12bit_gamma_precision() ?
Again, can you please give little more details here ?
Regards, Emil
On 10 October 2015 at 06:26, Sharma, Shashank shashank.sharma@intel.com wrote:
On 10/10/2015 5:13 AM, Emil Velikov wrote:
On 9 October 2015 at 20:29, Shashank Sharma shashank.sharma@intel.com wrote:
CHV/BSW supports Color Space Conversion (CSC) using a 3x3 matrix that needs to be programmed into CGM (Color Gamut Mapping) registers.
This patch does the following:
- Attaches CSC property to CRTC
- Adds the core function to program CSC correction values
- Adds CSC correction macros
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com Signed-off-by: Kumar, Kiran S kiran.s.kumar@intel.com
drivers/gpu/drm/i915/i915_reg.h | 8 +++ drivers/gpu/drm/i915/intel_color_manager.c | 94 ++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_color_manager.h | 19 ++++++ 3 files changed, 121 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c32e35d..5825ab2 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8056,4 +8056,12 @@ enum skl_disp_power_wells { #define _PIPE_DEGAMMA_BASE(pipe) \ (_PIPE3(pipe, PIPEA_CGM_DEGAMMA, PIPEB_CGM_DEGAMMA, PIPEC_CGM_DEGAMMA))
+#define PIPEA_CGM_CSC (VLV_DISPLAY_BASE + 0x67900) +#define PIPEB_CGM_CSC (VLV_DISPLAY_BASE + 0x69900) +#define PIPEC_CGM_CSC (VLV_DISPLAY_BASE + 0x6B900) +#define _PIPE_CSC_BASE(pipe) \
(_PIPE3(pipe, PIPEA_CGM_CSC, PIPEB_CGM_CSC, PIPEC_CGM_CSC))- #endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index bbfe185..433e50a 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -27,6 +27,93 @@
#include "intel_color_manager.h"
+static s16 chv_prepare_csc_coeff(s64 csc_value) +{
s32 csc_int_value;u32 csc_fract_value;s16 csc_s3_12_format;The type of csc_s3_12_format and chv_prepare_csc_coeff() does not see correct. Seem like the fix got merged into another patch :\
Can you please elaborate this comment, I dont get it.
You have two typos above s16 > s32 which you've fixed in the next patch. That fix should belong here imho.
[snip]
while (count < CSC_MAX_VALS) {temp = chv_prepare_csc_coeff(csc_data->ctm_coeff[count]);SET_BITS(word, GET_BITS(temp, 16, 16), 0, 16);/** Last value to be written in 1 register.* Otherwise, each pair of CSC values go* into 1 register*/if (count != (CSC_MAX_VALS - 1)) {count++;temp = chv_prepare_csc_coeff(csc_data->ctm_coeff[count]);SET_BITS(word, GET_BITS(temp, 16, 16), 16, 16);}This looks a bit odd. Use the same approach as in bdw_write_12bit_gamma_precision() ?
Again, can you please give little more details here ?
Take a look at the loop construct in bdw_write_12bit_gamma_precision() - both of them are essentially doing the same thing.
Here you have while(i < odd_number) { foo() if (if != odd_number-1) { I++ foo() } }
while in the mentioned function
while (i < odd_number -1) { foo() foo() i++ } foo()
Normally you'd use one or the other. Esp. since this is a single patchset :-) I'm leaning towards the latter as it's more obvious but others may prefer the former approach.
Regards, Emil
Regards Shashank
On 10/13/2015 7:03 PM, Emil Velikov wrote:
On 10 October 2015 at 06:26, Sharma, Shashank shashank.sharma@intel.com wrote:
On 10/10/2015 5:13 AM, Emil Velikov wrote:
On 9 October 2015 at 20:29, Shashank Sharma shashank.sharma@intel.com wrote:
CHV/BSW supports Color Space Conversion (CSC) using a 3x3 matrix that needs to be programmed into CGM (Color Gamut Mapping) registers.
This patch does the following:
- Attaches CSC property to CRTC
- Adds the core function to program CSC correction values
- Adds CSC correction macros
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com Signed-off-by: Kumar, Kiran S kiran.s.kumar@intel.com
drivers/gpu/drm/i915/i915_reg.h | 8 +++ drivers/gpu/drm/i915/intel_color_manager.c | 94 ++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_color_manager.h | 19 ++++++ 3 files changed, 121 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c32e35d..5825ab2 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8056,4 +8056,12 @@ enum skl_disp_power_wells { #define _PIPE_DEGAMMA_BASE(pipe) \ (_PIPE3(pipe, PIPEA_CGM_DEGAMMA, PIPEB_CGM_DEGAMMA, PIPEC_CGM_DEGAMMA))
+#define PIPEA_CGM_CSC (VLV_DISPLAY_BASE + 0x67900) +#define PIPEB_CGM_CSC (VLV_DISPLAY_BASE + 0x69900) +#define PIPEC_CGM_CSC (VLV_DISPLAY_BASE + 0x6B900) +#define _PIPE_CSC_BASE(pipe) \
(_PIPE3(pipe, PIPEA_CGM_CSC, PIPEB_CGM_CSC, PIPEC_CGM_CSC))- #endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index bbfe185..433e50a 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -27,6 +27,93 @@
#include "intel_color_manager.h"
+static s16 chv_prepare_csc_coeff(s64 csc_value) +{
s32 csc_int_value;u32 csc_fract_value;s16 csc_s3_12_format;The type of csc_s3_12_format and chv_prepare_csc_coeff() does not see correct. Seem like the fix got merged into another patch :\
Can you please elaborate this comment, I dont get it.
You have two typos above s16 > s32 which you've fixed in the next patch. That fix should belong here imho.
Yes, I got that later, current patch set contains this fix.
[snip]
while (count < CSC_MAX_VALS) {temp = chv_prepare_csc_coeff(csc_data->ctm_coeff[count]);SET_BITS(word, GET_BITS(temp, 16, 16), 0, 16);/** Last value to be written in 1 register.* Otherwise, each pair of CSC values go* into 1 register*/if (count != (CSC_MAX_VALS - 1)) {count++;temp = chv_prepare_csc_coeff(csc_data->ctm_coeff[count]);SET_BITS(word, GET_BITS(temp, 16, 16), 16, 16);}This looks a bit odd. Use the same approach as in bdw_write_12bit_gamma_precision() ?
Again, can you please give little more details here ?
Take a look at the loop construct in bdw_write_12bit_gamma_precision()
- both of them are essentially doing the same thing.
Here you have while(i < odd_number) { foo() if (if != odd_number-1) { I++ foo() } }
while in the mentioned function
while (i < odd_number -1) { foo() foo() i++ } foo()
Normally you'd use one or the other. Esp. since this is a single patchset :-) I'm leaning towards the latter as it's more obvious but others may prefer the former approach.
Yes, I got this one also, later :). New patch set has an implementation similar to this, please have a look.
Regards, Emil
The color correction blob values are loaded during set_property calls. This patch adds a function to find the blob and apply the correction values to the display registers, during the atomic commit call.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com --- drivers/gpu/drm/i915/intel_color_manager.c | 44 ++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_display.c | 2 ++ drivers/gpu/drm/i915/intel_drv.h | 3 ++ 3 files changed, 49 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index 433e50a..d5315b2 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -307,6 +307,50 @@ static int chv_set_gamma(struct drm_device *dev, struct drm_property_blob *blob, return ret; }
+void intel_color_manager_crtc_commit(struct drm_device *dev, + struct drm_crtc_state *crtc_state) +{ + struct drm_property_blob *blob; + struct drm_crtc *crtc = crtc_state->crtc; + int ret = -EINVAL; + + blob = crtc_state->palette_after_ctm_blob; + if (blob) { + /* Gamma correction is platform specific */ + if (IS_CHERRYVIEW(dev)) + ret = chv_set_gamma(dev, blob, crtc); + + if (ret) + DRM_ERROR("set Gamma correction failed\n"); + else + DRM_DEBUG_DRIVER("Gamma correction success\n"); + } + + blob = crtc_state->palette_before_ctm_blob; + if (blob) { + /* Degamma correction */ + if (IS_CHERRYVIEW(dev)) + ret = chv_set_degamma(dev, blob, crtc); + + if (ret) + DRM_ERROR("set degamma correction failed\n"); + else + DRM_DEBUG_DRIVER("degamma correction success\n"); + } + + blob = crtc_state->ctm_blob; + if (blob) { + /* CSC correction */ + if (IS_CHERRYVIEW(dev)) + ret = chv_set_csc(dev, blob, crtc); + + if (ret) + DRM_ERROR("set CSC correction failed\n"); + else + DRM_DEBUG_DRIVER("CSC correction success\n"); + } +} + void intel_attach_color_properties_to_crtc(struct drm_device *dev, struct drm_crtc *crtc) { diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 98cc97a..8235341 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -13528,6 +13528,8 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc, intel_update_pipe_config(intel_crtc, old_intel_state); else if (INTEL_INFO(dev)->gen >= 9) skl_detach_scalers(intel_crtc); + + intel_color_manager_crtc_commit(dev, crtc->state); }
static void intel_finish_crtc_commit(struct drm_crtc *crtc, diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index ed66a4f..d100e81 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1469,4 +1469,7 @@ void intel_plane_destroy_state(struct drm_plane *plane, struct drm_plane_state *state); extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
+/* intel_color_mnager.c */ +void intel_color_manager_crtc_commit(struct drm_device *dev, + struct drm_crtc_state *crtc_state); #endif /* __INTEL_DRV_H__ */
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma shashank.sharma@intel.com wrote:
The color correction blob values are loaded during set_property calls. This patch adds a function to find the blob and apply the correction values to the display registers, during the atomic commit call.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com
drivers/gpu/drm/i915/intel_color_manager.c | 44 ++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_display.c | 2 ++ drivers/gpu/drm/i915/intel_drv.h | 3 ++ 3 files changed, 49 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index 433e50a..d5315b2 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -307,6 +307,50 @@ static int chv_set_gamma(struct drm_device *dev, struct drm_property_blob *blob, return ret; }
+void intel_color_manager_crtc_commit(struct drm_device *dev,
struct drm_crtc_state *crtc_state)+{
struct drm_property_blob *blob;struct drm_crtc *crtc = crtc_state->crtc;int ret = -EINVAL;
Most places/people advise against pre-emptively initializing ret.
blob = crtc_state->palette_after_ctm_blob;if (blob) {/* Gamma correction is platform specific */if (IS_CHERRYVIEW(dev))ret = chv_set_gamma(dev, blob, crtc);if (ret)DRM_ERROR("set Gamma correction failed\n");
Do we really want to spam dmesg on for each non Cherryview device ?
elseDRM_DEBUG_DRIVER("Gamma correction success\n");}blob = crtc_state->palette_before_ctm_blob;if (blob) {/* Degamma correction */if (IS_CHERRYVIEW(dev))ret = chv_set_degamma(dev, blob, crtc);if (ret)DRM_ERROR("set degamma correction failed\n");elseDRM_DEBUG_DRIVER("degamma correction success\n");}blob = crtc_state->ctm_blob;if (blob) {/* CSC correction */if (IS_CHERRYVIEW(dev))ret = chv_set_csc(dev, blob, crtc);if (ret)DRM_ERROR("set CSC correction failed\n");elseDRM_DEBUG_DRIVER("CSC correction success\n");}+}
void intel_attach_color_properties_to_crtc(struct drm_device *dev, struct drm_crtc *crtc) { diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 98cc97a..8235341 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -13528,6 +13528,8 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc, intel_update_pipe_config(intel_crtc, old_intel_state); else if (INTEL_INFO(dev)->gen >= 9) skl_detach_scalers(intel_crtc);
intel_color_manager_crtc_commit(dev, crtc->state);}
static void intel_finish_crtc_commit(struct drm_crtc *crtc, diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index ed66a4f..d100e81 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1469,4 +1469,7 @@ void intel_plane_destroy_state(struct drm_plane *plane, struct drm_plane_state *state); extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
+/* intel_color_mnager.c */
Typo -> manager.
Regards, Emil
Regards Shashank
On 10/10/2015 4:54 AM, Emil Velikov wrote:
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma shashank.sharma@intel.com wrote:
The color correction blob values are loaded during set_property calls. This patch adds a function to find the blob and apply the correction values to the display registers, during the atomic commit call.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com
drivers/gpu/drm/i915/intel_color_manager.c | 44 ++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_display.c | 2 ++ drivers/gpu/drm/i915/intel_drv.h | 3 ++ 3 files changed, 49 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index 433e50a..d5315b2 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -307,6 +307,50 @@ static int chv_set_gamma(struct drm_device *dev, struct drm_property_blob *blob, return ret; }
+void intel_color_manager_crtc_commit(struct drm_device *dev,
struct drm_crtc_state *crtc_state)+{
struct drm_property_blob *blob;struct drm_crtc *crtc = crtc_state->crtc;int ret = -EINVAL;Most places/people advise against pre-emptively initializing ret.
Just in this case, if makes sense to keep one, coz there might be multiple blobs which we are applying in the commit action, and every blob can return error, from the core function. Assume that there is a situation where both palette_after_ctm(gamma) and CTM is in place, then we will be going through multiple if() cases and have to check the return values.
blob = crtc_state->palette_after_ctm_blob;if (blob) {/* Gamma correction is platform specific */if (IS_CHERRYVIEW(dev))ret = chv_set_gamma(dev, blob, crtc);if (ret)DRM_ERROR("set Gamma correction failed\n");Do we really want to spam dmesg on for each non Cherryview device ?
If you see the complete implementation, as IS_GEN8()/IS_SKL is coming up here after IS_CHV(patch 19,20,21) which will cover BDW/SKL/BXT. Anything else which comes here, deserves a DRM_ERROR() as this platform will not be supported.
elseDRM_DEBUG_DRIVER("Gamma correction success\n");}blob = crtc_state->palette_before_ctm_blob;if (blob) {/* Degamma correction */if (IS_CHERRYVIEW(dev))ret = chv_set_degamma(dev, blob, crtc);if (ret)DRM_ERROR("set degamma correction failed\n");elseDRM_DEBUG_DRIVER("degamma correction success\n");}blob = crtc_state->ctm_blob;if (blob) {/* CSC correction */if (IS_CHERRYVIEW(dev))ret = chv_set_csc(dev, blob, crtc);if (ret)DRM_ERROR("set CSC correction failed\n");elseDRM_DEBUG_DRIVER("CSC correction success\n");}+}
- void intel_attach_color_properties_to_crtc(struct drm_device *dev, struct drm_crtc *crtc) {
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 98cc97a..8235341 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -13528,6 +13528,8 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc, intel_update_pipe_config(intel_crtc, old_intel_state); else if (INTEL_INFO(dev)->gen >= 9) skl_detach_scalers(intel_crtc);
intel_color_manager_crtc_commit(dev, crtc->state);}
static void intel_finish_crtc_commit(struct drm_crtc *crtc,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index ed66a4f..d100e81 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1469,4 +1469,7 @@ void intel_plane_destroy_state(struct drm_plane *plane, struct drm_plane_state *state); extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
+/* intel_color_mnager.c */
Typo -> manager.
Oops, thanks.
Regards, Emil
On 10 October 2015 at 06:20, Sharma, Shashank shashank.sharma@intel.com wrote:
On 10/10/2015 4:54 AM, Emil Velikov wrote:
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma shashank.sharma@intel.com wrote:
The color correction blob values are loaded during set_property calls. This patch adds a function to find the blob and apply the correction values to the display registers, during the atomic commit call.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com
drivers/gpu/drm/i915/intel_color_manager.c | 44 ++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_display.c | 2 ++ drivers/gpu/drm/i915/intel_drv.h | 3 ++ 3 files changed, 49 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index 433e50a..d5315b2 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -307,6 +307,50 @@ static int chv_set_gamma(struct drm_device *dev, struct drm_property_blob *blob, return ret; }
+void intel_color_manager_crtc_commit(struct drm_device *dev,
struct drm_crtc_state *crtc_state)+{
struct drm_property_blob *blob;struct drm_crtc *crtc = crtc_state->crtc;int ret = -EINVAL;Most places/people advise against pre-emptively initializing ret.
Just in this case, if makes sense to keep one, coz there might be multiple blobs which we are applying in the commit action, and every blob can return error, from the core function. Assume that there is a situation where both palette_after_ctm(gamma) and CTM is in place, then we will be going through multiple if() cases and have to check the return values.
When you have an exception of any rule, this implies that you are using a suboptimal way of doing things.
blob = crtc_state->palette_after_ctm_blob;if (blob) {/* Gamma correction is platform specific */if (IS_CHERRYVIEW(dev))ret = chv_set_gamma(dev, blob, crtc);if (ret)DRM_ERROR("set Gamma correction failed\n");Do we really want to spam dmesg on for each non Cherryview device ?
If you see the complete implementation, as IS_GEN8()/IS_SKL is coming up here after IS_CHV(patch 19,20,21) which will cover BDW/SKL/BXT. Anything else which comes here, deserves a DRM_ERROR() as this platform will not be supported.
Your patches should be independent changes. You cannot say "I'm adding something iffy here, but it will be fixed with another patch". Otherwise you'll get developer/user X bisecting the kernel, which will end up with broken system (flooded dmesg in this case) half way through the bisect.
Regards, Emil
Regards Shashank
On 10/13/2015 6:47 PM, Emil Velikov wrote:
On 10 October 2015 at 06:20, Sharma, Shashank shashank.sharma@intel.com wrote:
On 10/10/2015 4:54 AM, Emil Velikov wrote:
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma shashank.sharma@intel.com wrote:
The color correction blob values are loaded during set_property calls. This patch adds a function to find the blob and apply the correction values to the display registers, during the atomic commit call.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com
drivers/gpu/drm/i915/intel_color_manager.c | 44 ++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_display.c | 2 ++ drivers/gpu/drm/i915/intel_drv.h | 3 ++ 3 files changed, 49 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index 433e50a..d5315b2 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -307,6 +307,50 @@ static int chv_set_gamma(struct drm_device *dev, struct drm_property_blob *blob, return ret; }
+void intel_color_manager_crtc_commit(struct drm_device *dev,
struct drm_crtc_state *crtc_state)+{
struct drm_property_blob *blob;struct drm_crtc *crtc = crtc_state->crtc;int ret = -EINVAL;Most places/people advise against pre-emptively initializing ret.
Just in this case, if makes sense to keep one, coz there might be multiple blobs which we are applying in the commit action, and every blob can return error, from the core function. Assume that there is a situation where both palette_after_ctm(gamma) and CTM is in place, then we will be going through multiple if() cases and have to check the return values.
When you have an exception of any rule, this implies that you are using a suboptimal way of doing things.
Not sure, but if you think its that serious, I will gladly change it to as you suggested :)
blob = crtc_state->palette_after_ctm_blob;if (blob) {/* Gamma correction is platform specific */if (IS_CHERRYVIEW(dev))ret = chv_set_gamma(dev, blob, crtc);if (ret)DRM_ERROR("set Gamma correction failed\n");Do we really want to spam dmesg on for each non Cherryview device ?
If you see the complete implementation, as IS_GEN8()/IS_SKL is coming up here after IS_CHV(patch 19,20,21) which will cover BDW/SKL/BXT. Anything else which comes here, deserves a DRM_ERROR() as this platform will not be supported.
Your patches should be independent changes. You cannot say "I'm adding something iffy here, but it will be fixed with another patch". Otherwise you'll get developer/user X bisecting the kernel, which will end up with broken system (flooded dmesg in this case) half way through the bisect.
There is no confusion here, and its an independent change. Till this patch, we have color management implemented for CHV only and any other platforms, should not even register this property, so naturally it must not hit this part of code. If its hitting, yes I would like to show this DRM_ERROR. So there is nothing wrong even if we bisect.
Regards, Emil
Function intel_attach_color_properties_to_crtc attaches a color property to its CRTC object. This patch calls this function from crtc initialization sequence.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com --- drivers/gpu/drm/i915/intel_display.c | 1 + drivers/gpu/drm/i915/intel_drv.h | 2 ++ 2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 8235341..514cd44 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -13859,6 +13859,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe) intel_crtc->cursor_size = ~0;
intel_crtc->wm.cxsr_allowed = true; + intel_attach_color_properties_to_crtc(dev, &intel_crtc->base);
BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index d100e81..1ce4f2b 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1472,4 +1472,6 @@ extern const struct drm_plane_helper_funcs intel_plane_helper_funcs; /* intel_color_mnager.c */ void intel_color_manager_crtc_commit(struct drm_device *dev, struct drm_crtc_state *crtc_state); +void intel_attach_color_properties_to_crtc(struct drm_device *dev, + struct drm_crtc *crtc); #endif /* __INTEL_DRV_H__ */
On 9 October 2015 at 20:29, Shashank Sharma shashank.sharma@intel.com wrote:
Function intel_attach_color_properties_to_crtc attaches a color property to its CRTC object. This patch calls this function from crtc initialization sequence.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com
Maybe squash this with patch 10, following the pattern set by other patches ?
Regards, Emil
Regards Shashank
On 10/10/2015 5:15 AM, Emil Velikov wrote:
On 9 October 2015 at 20:29, Shashank Sharma shashank.sharma@intel.com wrote:
Function intel_attach_color_properties_to_crtc attaches a color property to its CRTC object. This patch calls this function from crtc initialization sequence.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com
Maybe squash this with patch 10, following the pattern set by other patches ?
As explained in the previous patch, attaching the property is like enabling the framework. It was Matt's comment to do it, only when atleast one platform is ready. That's why we added this patch after CHV implementation is completed.
Regards, Emil
I915 color manager registers pipe gamma correction as palette correction after CTM property.
For BDW and higher platforms, split gamma correction is the best gamma correction. This patch adds the no of coefficients(512) for split gamma correction as "num_samples_after_ctm" parameter in device info structures, for all of those.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com --- drivers/gpu/drm/i915/i915_drv.c | 7 +++++++ drivers/gpu/drm/i915/intel_color_manager.h | 3 +++ 2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 5a25a35..4fa046f 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -302,6 +302,7 @@ static const struct intel_device_info intel_broadwell_d_info = { .gen = 8, .num_pipes = 3, .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, + .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1, @@ -314,6 +315,7 @@ static const struct intel_device_info intel_broadwell_m_info = { .gen = 8, .is_mobile = 1, .num_pipes = 3, .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, + .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1, @@ -326,6 +328,7 @@ static const struct intel_device_info intel_broadwell_gt3d_info = { .gen = 8, .num_pipes = 3, .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, + .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1, @@ -338,6 +341,7 @@ static const struct intel_device_info intel_broadwell_gt3m_info = { .gen = 8, .is_mobile = 1, .num_pipes = 3, .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, + .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1, @@ -363,6 +367,7 @@ static const struct intel_device_info intel_skylake_info = { .gen = 9, .num_pipes = 3, .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, + .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1, @@ -376,6 +381,7 @@ static const struct intel_device_info intel_skylake_gt3_info = { .gen = 9, .num_pipes = 3, .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, + .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1, @@ -389,6 +395,7 @@ static const struct intel_device_info intel_broxton_info = { .gen = 9, .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, + .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, .num_pipes = 3, .has_ddi = 1, .has_fpga_dbg = 1, diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h index 7b96512..271246a 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.h +++ b/drivers/gpu/drm/i915/intel_color_manager.h @@ -89,3 +89,6 @@ #define CGM_GAMMA_EN (1 << 2) #define CGM_CSC_EN (1 << 1) #define CGM_DEGAMMA_EN (1 << 0) + +/* Gamma on BDW */ +#define BDW_SPLITGAMMA_MAX_VALS 512
BDW/SKL/BXT platforms support various Gamma correction modes which are: 1. Legacy 8-bit mode 2. 10-bit Split Gamma mode 3. 12-bit mode
This patch does the following: 1. Adds the core function to program Gamma correction values for BDW/SKL/BXT platforms 2. Adds Gamma correction macros/defines
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com --- drivers/gpu/drm/i915/i915_reg.h | 25 ++- drivers/gpu/drm/i915/intel_color_manager.c | 248 +++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_color_manager.h | 6 + 3 files changed, 277 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5825ab2..ed50f75 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5647,11 +5647,15 @@ enum skl_disp_power_wells { /* legacy palette */ #define _LGC_PALETTE_A 0x4a000 #define _LGC_PALETTE_B 0x4a800 -#define LGC_PALETTE(pipe, i) (_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4) +#define _LGC_PALETTE_C 0x4b000 +#define LGC_PALETTE(pipe, i) (_PIPE3(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B, \ + _LGC_PALETTE_C) + (i) * 4)
#define _GAMMA_MODE_A 0x4a480 #define _GAMMA_MODE_B 0x4ac80 -#define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) +#define _GAMMA_MODE_C 0x4b480 +#define GAMMA_MODE(pipe) \ + _PIPE3(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B, _GAMMA_MODE_C) #define GAMMA_MODE_MODE_MASK (3 << 0) #define GAMMA_MODE_MODE_8BIT (0 << 0) #define GAMMA_MODE_MODE_10BIT (1 << 0) @@ -8062,6 +8066,23 @@ enum skl_disp_power_wells { #define _PIPE_CSC_BASE(pipe) \ (_PIPE3(pipe, PIPEA_CGM_CSC, PIPEB_CGM_CSC, PIPEC_CGM_CSC))
+/* BDW gamma correction */ +#define PAL_PREC_INDEX_A 0x4A400 +#define PAL_PREC_INDEX_B 0x4AC00 +#define PAL_PREC_INDEX_C 0x4B400 +#define PAL_PREC_DATA_A 0x4A404 +#define PAL_PREC_DATA_B 0x4AC04 +#define PAL_PREC_DATA_C 0x4B404 +#define PAL_PREC_GCMAX_A 0x4A410 +#define PAL_PREC_GCMAX_B 0x4AC10 +#define PAL_PREC_GCMAX_C 0x4B410 + +#define _PREC_PAL_INDEX(pipe) \ + (_PIPE3(pipe, PAL_PREC_INDEX_A, PAL_PREC_INDEX_B, PAL_PREC_INDEX_C)) +#define _PREC_PAL_DATA(pipe) \ + (_PIPE3(pipe, PAL_PREC_DATA_A, PAL_PREC_DATA_B, PAL_PREC_DATA_C)) +#define _PREC_PAL_GCMAX(pipe) \ + (_PIPE3(pipe, PAL_PREC_GCMAX_A, PAL_PREC_GCMAX_B, PAL_PREC_GCMAX_C))
#endif /* _I915_REG_H_ */ diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index d5315b2..74f8fc3 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -26,6 +26,252 @@ */
#include "intel_color_manager.h" +static void bdw_write_10bit_gamma_precision(struct drm_device *dev, + struct drm_r32g32b32 *correction_values, u32 pal_prec_data, + u32 no_of_coeff) +{ + u16 blue_fract, green_fract, red_fract; + u32 word = 0; + u32 count = 0; + u32 blue, green, red; + struct drm_i915_private *dev_priv = dev->dev_private; + + while (count < no_of_coeff) { + + blue = correction_values[count].b32; + green = correction_values[count].g32; + red = correction_values[count].r32; + + /* + * Maximum possible gamma correction value supported + * for BDW is 0xFFFFFFFF, so clip the values accordingly + */ + if (blue >= BDW_MAX_GAMMA) + blue = BDW_MAX_GAMMA; + if (green >= BDW_MAX_GAMMA) + green = BDW_MAX_GAMMA; + if (red >= BDW_MAX_GAMMA) + red = BDW_MAX_GAMMA; + + /* + * Gamma correction values are sent in 8.24 format + * with 8 int and 24 fraction bits. BDW 10 bit gamma + * unit expects correction registers to be programmed in + * 0.10 format, with 0 int and 16 fraction bits. So take + * MSB 10 bit values(bits 23-14) from the fraction part and + * prepare the correction registers. + */ + blue_fract = GET_BITS(blue, 14, 10); + green_fract = GET_BITS(green, 14, 10); + red_fract = GET_BITS(red, 14, 10); + + /* Arrange: Red (29:20) Green (19:10) and Blue (9:0) */ + SET_BITS(word, red_fract, 20, 10); + SET_BITS(word, red_fract, 10, 10); + SET_BITS(word, red_fract, 0, 10); + I915_WRITE(pal_prec_data, word); + count++; + } + DRM_DEBUG_DRIVER("Gamma correction programmed\n"); +} + +void bdw_write_12bit_gamma_precision(struct drm_device *dev, + struct drm_r32g32b32 *correction_values, u32 pal_prec_data, + enum pipe pipe) +{ + uint16_t blue_fract, green_fract, red_fract; + uint32_t gcmax; + uint32_t word = 0; + uint32_t count = 0; + uint32_t gcmax_reg; + struct drm_i915_private *dev_priv = dev->dev_private; + + /* Program first 512 values in precision palette */ + while (count < BDW_12BIT_GAMMA_MAX_VALS - 1) { + /* + * Framework's general gamma format is 8.24 (8 int 16 fraction) + * BDW Platform's supported gamma format is 16 bit correction + * values in 0.16 format. So extract higher 16 fraction bits + * from 8.24 gamma correction values. + */ + red_fract = GET_BITS(correction_values[count].r32, 8, 16); + green_fract = GET_BITS(correction_values[count].g32, 8, 16); + blue_fract = GET_BITS(correction_values[count].b32, 8, 16); + + /* + * From the bspec: + * For 12 bit gamma correction, program precision palette + * with 16 bits per color in a 0.16 format with 0 integer and + * 16 fractional bits (upper 10 bits in odd indexes, lower 6 + * bits in even indexes) + */ + + /* Even index: Lower 6 bits from correction should go as MSB */ + SET_BITS(word, GET_BITS(red_fract, 0, 6), 24, 6); + SET_BITS(word, GET_BITS(green_fract, 0, 6), 14, 6); + SET_BITS(word, GET_BITS(blue_fract, 0, 6), 4, 6); + I915_WRITE(pal_prec_data, word); + + word = 0x0; + /* Odd index: Upper 10 bits of correction should go as MSB */ + SET_BITS(word, GET_BITS(red_fract, 6, 10), 20, 10); + SET_BITS(word, GET_BITS(green_fract, 6, 10), 10, 10); + SET_BITS(word, GET_BITS(blue_fract, 6, 10), 0, 10); + + I915_WRITE(pal_prec_data, word); + count++; + } + + /* Now program the 513th value in GCMAX regs */ + word = 0; + gcmax_reg = _PREC_PAL_GCMAX(pipe); + gcmax = min_t(u32, GET_BITS(correction_values[count].r32, 8, 17), + BDW_MAX_GAMMA); + SET_BITS(word, gcmax, 0, 17); + I915_WRITE(gcmax_reg, word); + gcmax_reg += 4; + + word = 0; + gcmax = min_t(u32, GET_BITS(correction_values[count].g32, 8, 17), + BDW_MAX_GAMMA); + SET_BITS(word, gcmax, 0, 17); + I915_WRITE(gcmax_reg, word); + gcmax_reg += 4; + + word = 0; + gcmax = min_t(u32, GET_BITS(correction_values[count].b32, 8, 17), + BDW_MAX_GAMMA); + SET_BITS(word, gcmax, 0, 17); + I915_WRITE(gcmax_reg, word); +} + +/* Apply unity gamma for gamma reset */ +static void bdw_reset_gamma(struct drm_i915_private *dev_priv, + enum pipe pipe) +{ + u16 count = 0; + u32 val; + u32 pal_prec_data = LGC_PALETTE(pipe, 0); + + DRM_DEBUG_DRIVER("\n"); + + /* Reset the palette for unit gamma */ + while (count < BDW_8BIT_GAMMA_MAX_VALS) { + /* Red (23:16) Green (15:8) and Blue (7:0) */ + val = (count << 16) | (count << 8) | count; + I915_WRITE(pal_prec_data, val); + pal_prec_data += 4; + count++; + } +} + +static int bdw_set_gamma(struct drm_device *dev, struct drm_property_blob *blob, + struct drm_crtc *crtc) +{ + u16 blue_fract, green_fract, red_fract; + enum pipe pipe; + int count, num_samples; + u32 blue, green, red; + u32 mode, pal_prec_index, pal_prec_data; + u32 index; + u32 word = 0; + struct drm_palette *gamma_data; + struct drm_crtc_state *state = crtc->state; + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_r32g32b32 *correction_values = NULL; + + if (WARN_ON(!blob)) + return -EINVAL; + + gamma_data = (struct drm_palette *)blob->data; + pipe = to_intel_crtc(crtc)->pipe; + num_samples = gamma_data->num_samples; + + pal_prec_index = _PREC_PAL_INDEX(pipe); + pal_prec_data = _PREC_PAL_DATA(pipe); + + correction_values = (struct drm_r32g32b32 *)&gamma_data->lut; + index = I915_READ(pal_prec_index); + + switch (num_samples) { + case GAMMA_DISABLE_VALS: + + /* Disable Gamma functionality on Pipe */ + DRM_DEBUG_DRIVER("Disabling gamma on Pipe %c\n", + pipe_name(pipe)); + mode = I915_READ(GAMMA_MODE(pipe)); + if ((mode & GAMMA_MODE_MODE_MASK) == GAMMA_MODE_MODE_12BIT) + bdw_reset_gamma(dev_priv, pipe); + state->palette_after_ctm_blob = NULL; + word = GAMMA_MODE_MODE_8BIT; + break; + + case BDW_8BIT_GAMMA_MAX_VALS: + + /* Legacy palette */ + pal_prec_data = LGC_PALETTE(pipe, 0); + count = 0; + while (count < BDW_8BIT_GAMMA_MAX_VALS) { + blue = correction_values[count].b32; + green = correction_values[count].g32; + red = correction_values[count].r32; + + blue_fract = GET_BITS(blue, 16, 8); + green_fract = GET_BITS(green, 16, 8); + red_fract = GET_BITS(red, 16, 8); + + /* Blue (7:0) Green (15:8) and Red (23:16) */ + SET_BITS(word, blue_fract, 0, 8); + SET_BITS(word, green_fract, 8, 8); + SET_BITS(word, blue_fract, 16, 8); + I915_WRITE(pal_prec_data, word); + pal_prec_data += 4; + count++; + } + word = GAMMA_MODE_MODE_8BIT; + break; + + case BDW_SPLITGAMMA_MAX_VALS: + + index |= BDW_INDEX_AUTO_INCREMENT | BDW_INDEX_SPLIT_MODE; + I915_WRITE(pal_prec_index, index); + bdw_write_10bit_gamma_precision(dev, correction_values, + pal_prec_data, BDW_SPLITGAMMA_MAX_VALS); + word = GAMMA_MODE_MODE_SPLIT; + break; + + case BDW_12BIT_GAMMA_MAX_VALS: + + index |= BDW_INDEX_AUTO_INCREMENT; + index &= ~BDW_INDEX_SPLIT_MODE; + I915_WRITE(pal_prec_index, index); + bdw_write_12bit_gamma_precision(dev, correction_values, + pal_prec_data, pipe); + word = GAMMA_MODE_MODE_12BIT; + break; + + case BDW_10BIT_GAMMA_MAX_VALS: + index |= BDW_INDEX_AUTO_INCREMENT; + index &= ~BDW_INDEX_SPLIT_MODE; + I915_WRITE(pal_prec_index, index); + bdw_write_10bit_gamma_precision(dev, correction_values, + pal_prec_data, BDW_10BIT_GAMMA_MAX_VALS); + word = GAMMA_MODE_MODE_10BIT; + break; + + default: + DRM_ERROR("Invalid number of samples\n"); + return -EINVAL; + } + + /* Set gamma mode on pipe control reg */ + mode = I915_READ(GAMMA_MODE(pipe)); + mode &= ~GAMMA_MODE_MODE_MASK; + I915_WRITE(GAMMA_MODE(pipe), mode | word); + DRM_DEBUG_DRIVER("Gamma applied on pipe %c\n", + pipe_name(pipe)); + return 0; +}
static s16 chv_prepare_csc_coeff(s64 csc_value) { @@ -319,6 +565,8 @@ void intel_color_manager_crtc_commit(struct drm_device *dev, /* Gamma correction is platform specific */ if (IS_CHERRYVIEW(dev)) ret = chv_set_gamma(dev, blob, crtc); + else if (IS_BROADWELL(dev) || IS_GEN9(dev)) + ret = bdw_set_gamma(dev, blob, crtc);
if (ret) DRM_ERROR("set Gamma correction failed\n"); diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h index 271246a..6c7cb08 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.h +++ b/drivers/gpu/drm/i915/intel_color_manager.h @@ -92,3 +92,9 @@
/* Gamma on BDW */ #define BDW_SPLITGAMMA_MAX_VALS 512 +#define BDW_8BIT_GAMMA_MAX_VALS 256 +#define BDW_10BIT_GAMMA_MAX_VALS 1024 +#define BDW_12BIT_GAMMA_MAX_VALS 513 +#define BDW_MAX_GAMMA ((1 << 24) - 1) +#define BDW_INDEX_AUTO_INCREMENT (1 << 15) +#define BDW_INDEX_SPLIT_MODE (1 << 31)
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma shashank.sharma@intel.com wrote: [snip]
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index d5315b2..74f8fc3 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -26,6 +26,252 @@ */
#include "intel_color_manager.h" +static void bdw_write_10bit_gamma_precision(struct drm_device *dev,
struct drm_r32g32b32 *correction_values, u32 pal_prec_data,u32 no_of_coeff)+{
u16 blue_fract, green_fract, red_fract;u32 word = 0;u32 count = 0;u32 blue, green, red;struct drm_i915_private *dev_priv = dev->dev_private;while (count < no_of_coeff) {
Use for loop ? Here and through the rest of the patch.
[snip]
+void bdw_write_12bit_gamma_precision(struct drm_device *dev,
struct drm_r32g32b32 *correction_values, u32 pal_prec_data,enum pipe pipe)+{
Make the function static ?
[snip]
+static int bdw_set_gamma(struct drm_device *dev, struct drm_property_blob *blob,
struct drm_crtc *crtc)+{
u16 blue_fract, green_fract, red_fract;enum pipe pipe;int count, num_samples;u32 blue, green, red;u32 mode, pal_prec_index, pal_prec_data;u32 index;u32 word = 0;struct drm_palette *gamma_data;struct drm_crtc_state *state = crtc->state;struct drm_i915_private *dev_priv = dev->dev_private;struct drm_r32g32b32 *correction_values = NULL;if (WARN_ON(!blob))return -EINVAL;gamma_data = (struct drm_palette *)blob->data;pipe = to_intel_crtc(crtc)->pipe;num_samples = gamma_data->num_samples;pal_prec_index = _PREC_PAL_INDEX(pipe);pal_prec_data = _PREC_PAL_DATA(pipe);correction_values = (struct drm_r32g32b32 *)&gamma_data->lut;index = I915_READ(pal_prec_index);switch (num_samples) {case GAMMA_DISABLE_VALS:/* Disable Gamma functionality on Pipe */
Drop the extra newline between the case and the comment ? Here and below.
[snip]
mode = I915_READ(GAMMA_MODE(pipe));mode &= ~GAMMA_MODE_MODE_MASK;I915_WRITE(GAMMA_MODE(pipe), mode | word);DRM_DEBUG_DRIVER("Gamma applied on pipe %c\n",pipe_name(pipe));
Indentation seems off here.
Regards, Emil
Regards Shashank
On 10/10/2015 5:09 AM, Emil Velikov wrote:
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma shashank.sharma@intel.com wrote: [snip]
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index d5315b2..74f8fc3 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -26,6 +26,252 @@ */
#include "intel_color_manager.h" +static void bdw_write_10bit_gamma_precision(struct drm_device *dev,
struct drm_r32g32b32 *correction_values, u32 pal_prec_data,u32 no_of_coeff)+{
u16 blue_fract, green_fract, red_fract;u32 word = 0;u32 count = 0;u32 blue, green, red;struct drm_i915_private *dev_priv = dev->dev_private;while (count < no_of_coeff) {Use for loop ? Here and through the rest of the patch.
Nah, I will prefer while().
[snip]
+void bdw_write_12bit_gamma_precision(struct drm_device *dev,
struct drm_r32g32b32 *correction_values, u32 pal_prec_data,enum pipe pipe)+{
Make the function static ?
Agree.
[snip]
+static int bdw_set_gamma(struct drm_device *dev, struct drm_property_blob *blob,
struct drm_crtc *crtc)+{
u16 blue_fract, green_fract, red_fract;enum pipe pipe;int count, num_samples;u32 blue, green, red;u32 mode, pal_prec_index, pal_prec_data;u32 index;u32 word = 0;struct drm_palette *gamma_data;struct drm_crtc_state *state = crtc->state;struct drm_i915_private *dev_priv = dev->dev_private;struct drm_r32g32b32 *correction_values = NULL;if (WARN_ON(!blob))return -EINVAL;gamma_data = (struct drm_palette *)blob->data;pipe = to_intel_crtc(crtc)->pipe;num_samples = gamma_data->num_samples;pal_prec_index = _PREC_PAL_INDEX(pipe);pal_prec_data = _PREC_PAL_DATA(pipe);correction_values = (struct drm_r32g32b32 *)&gamma_data->lut;index = I915_READ(pal_prec_index);switch (num_samples) {case GAMMA_DISABLE_VALS:/* Disable Gamma functionality on Pipe */Drop the extra newline between the case and the comment ? Here and below.
I was trying to make it look good :(
[snip]
mode = I915_READ(GAMMA_MODE(pipe));mode &= ~GAMMA_MODE_MODE_MASK;I915_WRITE(GAMMA_MODE(pipe), mode | word);DRM_DEBUG_DRIVER("Gamma applied on pipe %c\n",pipe_name(pipe));Indentation seems off here.
Agree.
Regards, Emil
On 10 October 2015 at 06:21, Sharma, Shashank shashank.sharma@intel.com wrote:
On 10/10/2015 5:09 AM, Emil Velikov wrote:
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma shashank.sharma@intel.com
[snip]
switch (num_samples) {case GAMMA_DISABLE_VALS:/* Disable Gamma functionality on Pipe */Drop the extra newline between the case and the comment ? Here and below.
I was trying to make it look good :(
Beauty is in the eye of the beholder. The most important part here is consistency. Afaict there isn't (m)any i915 code the uses this approach, is there ? Some of your other patches use this approach while others don't.
Regards, Emil
Regards Shashank
On 10/13/2015 6:53 PM, Emil Velikov wrote:
On 10 October 2015 at 06:21, Sharma, Shashank shashank.sharma@intel.com wrote:
On 10/10/2015 5:09 AM, Emil Velikov wrote:
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma shashank.sharma@intel.com
[snip]
switch (num_samples) {case GAMMA_DISABLE_VALS:/* Disable Gamma functionality on Pipe */Drop the extra newline between the case and the comment ? Here and below.
I was trying to make it look good :(
Beauty is in the eye of the beholder. The most important part here is consistency. Afaict there isn't (m)any i915 code the uses this approach, is there ? Some of your other patches use this approach while others don't.
I prefer to leave one extra line when I have a comment, so that comment is more visible, instead of being sandwiched between lines of C code. May be I missed some places, so I can make it consistent.
Regards, Emil
On Sat, 2015-10-10 at 00:59 +0530, Shashank Sharma wrote:
BDW/SKL/BXT platforms support various Gamma correction modes which are:
- Legacy 8-bit mode
- 10-bit Split Gamma mode
- 12-bit mode
This patch does the following:
- Adds the core function to program Gamma correction values for BDW/SKL/BXT platforms
- Adds Gamma correction macros/defines
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com
drivers/gpu/drm/i915/i915_reg.h | 25 ++- drivers/gpu/drm/i915/intel_color_manager.c | 248 +++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_color_manager.h | 6 + 3 files changed, 277 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5825ab2..ed50f75 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5647,11 +5647,15 @@ enum skl_disp_power_wells { /* legacy palette */ #define _LGC_PALETTE_A 0x4a000 #define _LGC_PALETTE_B 0x4a800 -#define LGC_PALETTE(pipe, i) (_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4) +#define _LGC_PALETTE_C 0x4b000 +#define LGC_PALETTE(pipe, i) (_PIPE3(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B, \
_LGC_PALETTE_C) + (i) * 4)#define _GAMMA_MODE_A 0x4a480 #define _GAMMA_MODE_B 0x4ac80 -#define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) +#define _GAMMA_MODE_C 0x4b480 +#define GAMMA_MODE(pipe) \
- _PIPE3(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B, _GAMMA_MODE_C)
#define GAMMA_MODE_MODE_MASK (3 << 0) #define GAMMA_MODE_MODE_8BIT (0 << 0) #define GAMMA_MODE_MODE_10BIT (1 << 0) @@ -8062,6 +8066,23 @@ enum skl_disp_power_wells { #define _PIPE_CSC_BASE(pipe) \ (_PIPE3(pipe, PIPEA_CGM_CSC, PIPEB_CGM_CSC, PIPEC_CGM_CSC))
+/* BDW gamma correction */ +#define PAL_PREC_INDEX_A 0x4A400 +#define PAL_PREC_INDEX_B 0x4AC00 +#define PAL_PREC_INDEX_C 0x4B400 +#define PAL_PREC_DATA_A 0x4A404 +#define PAL_PREC_DATA_B 0x4AC04 +#define PAL_PREC_DATA_C 0x4B404 +#define PAL_PREC_GCMAX_A 0x4A410 +#define PAL_PREC_GCMAX_B 0x4AC10 +#define PAL_PREC_GCMAX_C 0x4B410
+#define _PREC_PAL_INDEX(pipe) \
- (_PIPE3(pipe, PAL_PREC_INDEX_A, PAL_PREC_INDEX_B,
PAL_PREC_INDEX_C)) +#define _PREC_PAL_DATA(pipe) \
- (_PIPE3(pipe, PAL_PREC_DATA_A, PAL_PREC_DATA_B,
PAL_PREC_DATA_C)) +#define _PREC_PAL_GCMAX(pipe) \
- (_PIPE3(pipe, PAL_PREC_GCMAX_A, PAL_PREC_GCMAX_B,
PAL_PREC_GCMAX_C))
#endif /* _I915_REG_H_ */ diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index d5315b2..74f8fc3 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -26,6 +26,252 @@ */
#include "intel_color_manager.h" +static void bdw_write_10bit_gamma_precision(struct drm_device *dev,
- struct drm_r32g32b32 *correction_values, u32 pal_prec_data,
u32 no_of_coeff)+{
- u16 blue_fract, green_fract, red_fract;
- u32 word = 0;
- u32 count = 0;
- u32 blue, green, red;
- struct drm_i915_private *dev_priv = dev->dev_private;
- while (count < no_of_coeff) {
blue = correction_values[count].b32;green = correction_values[count].g32;red = correction_values[count].r32;/** Maximum possible gamma correction value supported* for BDW is 0xFFFFFFFF, so clip the valuesaccordingly
*/
I think you mean clamp not clip.
if (blue >= BDW_MAX_GAMMA)blue = BDW_MAX_GAMMA;if (green >= BDW_MAX_GAMMA)green = BDW_MAX_GAMMA;if (red >= BDW_MAX_GAMMA)red = BDW_MAX_GAMMA;
So this handles the issue that was raised before that 1.0 in 8.24 should map to 1023.
/** Gamma correction values are sent in 8.24 format* with 8 int and 24 fraction bits. BDW 10 bit gamma* unit expects correction registers to be programmedin
* 0.10 format, with 0 int and 16 fraction bits. Sotake
* MSB 10 bit values(bits 23-14) from the fractionpart and
* prepare the correction registers.*/blue_fract = GET_BITS(blue, 14, 10);green_fract = GET_BITS(green, 14, 10);red_fract = GET_BITS(red, 14, 10);
I think this should round to the nearest rather than floor.
/* Arrange: Red (29:20) Green (19:10) and Blue (9:0)*/
SET_BITS(word, red_fract, 20, 10);SET_BITS(word, red_fract, 10, 10);SET_BITS(word, red_fract, 0, 10);
Red is my favourite colour too, is that why you programmed all the channels to the red bits? :-)
I915_WRITE(pal_prec_data, word);count++;- }
- DRM_DEBUG_DRIVER("Gamma correction programmed\n");
+}
+void bdw_write_12bit_gamma_precision(struct drm_device *dev,
- struct drm_r32g32b32 *correction_values, u32 pal_prec_data,
enum pipe pipe)+{
- uint16_t blue_fract, green_fract, red_fract;
- uint32_t gcmax;
- uint32_t word = 0;
- uint32_t count = 0;
- uint32_t gcmax_reg;
- struct drm_i915_private *dev_priv = dev->dev_private;
- /* Program first 512 values in precision palette */
- while (count < BDW_12BIT_GAMMA_MAX_VALS - 1) {
/** Framework's general gamma format is 8.24 (8 int 16fraction)
* BDW Platform's supported gamma format is 16 bitcorrection
* values in 0.16 format. So extract higher 16fraction bits
* from 8.24 gamma correction values.*/red_fract = GET_BITS(correction_values[count].r32,8, 16);
green_fract = GET_BITS(correction_values[count].g32,8, 16);
blue_fract = GET_BITS(correction_values[count].b32,8, 16);
Again, 1.0 in 8.24 will result in you programming zeros rather than max.
/** From the bspec:* For 12 bit gamma correction, program precisionpalette
* with 16 bits per color in a 0.16 format with 0integer and
* 16 fractional bits (upper 10 bits in odd indexes,lower 6
* bits in even indexes)*//* Even index: Lower 6 bits from correction shouldgo as MSB */
SET_BITS(word, GET_BITS(red_fract, 0, 6), 24, 6);SET_BITS(word, GET_BITS(green_fract, 0, 6), 14, 6);SET_BITS(word, GET_BITS(blue_fract, 0, 6), 4, 6);I915_WRITE(pal_prec_data, word);word = 0x0;/* Odd index: Upper 10 bits of correction should goas MSB */
SET_BITS(word, GET_BITS(red_fract, 6, 10), 20, 10);SET_BITS(word, GET_BITS(green_fract, 6, 10), 10,10);
SET_BITS(word, GET_BITS(blue_fract, 6, 10), 0, 10);I915_WRITE(pal_prec_data, word);count++;- }
- /* Now program the 513th value in GCMAX regs */
- word = 0;
- gcmax_reg = _PREC_PAL_GCMAX(pipe);
- gcmax = min_t(u32, GET_BITS(correction_values[count].r32, 8,
17),
BDW_MAX_GAMMA);- SET_BITS(word, gcmax, 0, 17);
- I915_WRITE(gcmax_reg, word);
- gcmax_reg += 4;
- word = 0;
- gcmax = min_t(u32, GET_BITS(correction_values[count].g32, 8,
17),
BDW_MAX_GAMMA);- SET_BITS(word, gcmax, 0, 17);
- I915_WRITE(gcmax_reg, word);
- gcmax_reg += 4;
- word = 0;
- gcmax = min_t(u32, GET_BITS(correction_values[count].b32, 8,
17),
BDW_MAX_GAMMA);- SET_BITS(word, gcmax, 0, 17);
- I915_WRITE(gcmax_reg, word);
+}
+/* Apply unity gamma for gamma reset */ +static void bdw_reset_gamma(struct drm_i915_private *dev_priv,
enum pipe pipe)+{
- u16 count = 0;
- u32 val;
- u32 pal_prec_data = LGC_PALETTE(pipe, 0);
- DRM_DEBUG_DRIVER("\n");
- /* Reset the palette for unit gamma */
- while (count < BDW_8BIT_GAMMA_MAX_VALS) {
/* Red (23:16) Green (15:8) and Blue (7:0) */val = (count << 16) | (count << 8) | count;I915_WRITE(pal_prec_data, val);pal_prec_data += 4;count++;- }
+}
+static int bdw_set_gamma(struct drm_device *dev, struct drm_property_blob *blob,
struct drm_crtc *crtc)+{
- u16 blue_fract, green_fract, red_fract;
- enum pipe pipe;
- int count, num_samples;
- u32 blue, green, red;
- u32 mode, pal_prec_index, pal_prec_data;
- u32 index;
- u32 word = 0;
- struct drm_palette *gamma_data;
- struct drm_crtc_state *state = crtc->state;
- struct drm_i915_private *dev_priv = dev->dev_private;
- struct drm_r32g32b32 *correction_values = NULL;
- if (WARN_ON(!blob))
return -EINVAL;- gamma_data = (struct drm_palette *)blob->data;
- pipe = to_intel_crtc(crtc)->pipe;
- num_samples = gamma_data->num_samples;
- pal_prec_index = _PREC_PAL_INDEX(pipe);
- pal_prec_data = _PREC_PAL_DATA(pipe);
- correction_values = (struct drm_r32g32b32 *)&gamma_data
->lut;
- index = I915_READ(pal_prec_index);
- switch (num_samples) {
- case GAMMA_DISABLE_VALS:
/* Disable Gamma functionality on Pipe */DRM_DEBUG_DRIVER("Disabling gamma on Pipe %c\n",pipe_name(pipe));mode = I915_READ(GAMMA_MODE(pipe));if ((mode & GAMMA_MODE_MODE_MASK) ==GAMMA_MODE_MODE_12BIT)
bdw_reset_gamma(dev_priv, pipe);
Why only call bdw_reset_gamma() if we were in 12-bit mode? What about the other modes? What about if somebody has programmed the value through the legacy ioctl?
state->palette_after_ctm_blob = NULL;word = GAMMA_MODE_MODE_8BIT;break;- case BDW_8BIT_GAMMA_MAX_VALS:
/* Legacy palette */pal_prec_data = LGC_PALETTE(pipe, 0);count = 0;while (count < BDW_8BIT_GAMMA_MAX_VALS) {blue = correction_values[count].b32;green = correction_values[count].g32;red = correction_values[count].r32;blue_fract = GET_BITS(blue, 16, 8);green_fract = GET_BITS(green, 16, 8);red_fract = GET_BITS(red, 16, 8);
Shouldn't these round? Rather than always floor. Also 1.0 in 8.24 format will result in you programming zero into the palette. You need to do the max clamping again.
/* Blue (7:0) Green (15:8) and Red (23:16)*/
SET_BITS(word, blue_fract, 0, 8);SET_BITS(word, green_fract, 8, 8);SET_BITS(word, blue_fract, 16, 8);I915_WRITE(pal_prec_data, word);pal_prec_data += 4;count++;
This code also needs to be made to work nicely with other users of LGC_PALETTE.
}word = GAMMA_MODE_MODE_8BIT;break;- case BDW_SPLITGAMMA_MAX_VALS:
index |= BDW_INDEX_AUTO_INCREMENT |BDW_INDEX_SPLIT_MODE;
I915_WRITE(pal_prec_index, index);bdw_write_10bit_gamma_precision(dev,correction_values,
pal_prec_data, BDW_SPLITGAMMA_MAX_VALS);word = GAMMA_MODE_MODE_SPLIT;break;- case BDW_12BIT_GAMMA_MAX_VALS:
index |= BDW_INDEX_AUTO_INCREMENT;index &= ~BDW_INDEX_SPLIT_MODE;I915_WRITE(pal_prec_index, index);bdw_write_12bit_gamma_precision(dev,correction_values,
pal_prec_data, pipe);word = GAMMA_MODE_MODE_12BIT;break;- case BDW_10BIT_GAMMA_MAX_VALS:
index |= BDW_INDEX_AUTO_INCREMENT;index &= ~BDW_INDEX_SPLIT_MODE;I915_WRITE(pal_prec_index, index);bdw_write_10bit_gamma_precision(dev,correction_values,
pal_prec_data, BDW_10BIT_GAMMA_MAX_VALS);word = GAMMA_MODE_MODE_10BIT;break;- default:
DRM_ERROR("Invalid number of samples\n");return -EINVAL;- }
- /* Set gamma mode on pipe control reg */
- mode = I915_READ(GAMMA_MODE(pipe));
- mode &= ~GAMMA_MODE_MODE_MASK;
- I915_WRITE(GAMMA_MODE(pipe), mode | word);
- DRM_DEBUG_DRIVER("Gamma applied on pipe %c\n",
- pipe_name(pipe));
- return 0;
+}
static s16 chv_prepare_csc_coeff(s64 csc_value) { @@ -319,6 +565,8 @@ void intel_color_manager_crtc_commit(struct drm_device *dev, /* Gamma correction is platform specific */ if (IS_CHERRYVIEW(dev)) ret = chv_set_gamma(dev, blob, crtc);
else if (IS_BROADWELL(dev) || IS_GEN9(dev))ret = bdw_set_gamma(dev, blob, crtc);if (ret) DRM_ERROR("set Gamma correction failed\n");
diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h index 271246a..6c7cb08 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.h +++ b/drivers/gpu/drm/i915/intel_color_manager.h @@ -92,3 +92,9 @@
/* Gamma on BDW */ #define BDW_SPLITGAMMA_MAX_VALS 512 +#define BDW_8BIT_GAMMA_MAX_VALS 256 +#define BDW_10BIT_GAMMA_MAX_VALS 1024 +#define BDW_12BIT_GAMMA_MAX_VALS 513 +#define BDW_MAX_GAMMA ((1 << 24) - 1) +#define BDW_INDEX_AUTO_INCREMENT (1 << 15) +#define BDW_INDEX_SPLIT_MODE (1 << 31)
Rob
Regards Shashank
On 10/12/2015 11:39 PM, Rob Bradford wrote:
On Sat, 2015-10-10 at 00:59 +0530, Shashank Sharma wrote:
BDW/SKL/BXT platforms support various Gamma correction modes which are:
- Legacy 8-bit mode
- 10-bit Split Gamma mode
- 12-bit mode
This patch does the following:
- Adds the core function to program Gamma correction values for BDW/SKL/BXT platforms
- Adds Gamma correction macros/defines
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com
drivers/gpu/drm/i915/i915_reg.h | 25 ++- drivers/gpu/drm/i915/intel_color_manager.c | 248 +++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_color_manager.h | 6 + 3 files changed, 277 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5825ab2..ed50f75 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5647,11 +5647,15 @@ enum skl_disp_power_wells { /* legacy palette */ #define _LGC_PALETTE_A 0x4a000 #define _LGC_PALETTE_B 0x4a800 -#define LGC_PALETTE(pipe, i) (_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4) +#define _LGC_PALETTE_C 0x4b000 +#define LGC_PALETTE(pipe, i) (_PIPE3(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B, \
_LGC_PALETTE_C) + (i) * 4)#define _GAMMA_MODE_A 0x4a480 #define _GAMMA_MODE_B 0x4ac80
-#define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) +#define _GAMMA_MODE_C 0x4b480 +#define GAMMA_MODE(pipe) \
- _PIPE3(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B, _GAMMA_MODE_C) #define GAMMA_MODE_MODE_MASK (3 << 0) #define GAMMA_MODE_MODE_8BIT (0 << 0) #define GAMMA_MODE_MODE_10BIT (1 << 0)
@@ -8062,6 +8066,23 @@ enum skl_disp_power_wells { #define _PIPE_CSC_BASE(pipe) \ (_PIPE3(pipe, PIPEA_CGM_CSC, PIPEB_CGM_CSC, PIPEC_CGM_CSC))
+/* BDW gamma correction */ +#define PAL_PREC_INDEX_A 0x4A400 +#define PAL_PREC_INDEX_B 0x4AC00 +#define PAL_PREC_INDEX_C 0x4B400 +#define PAL_PREC_DATA_A 0x4A404 +#define PAL_PREC_DATA_B 0x4AC04 +#define PAL_PREC_DATA_C 0x4B404 +#define PAL_PREC_GCMAX_A 0x4A410 +#define PAL_PREC_GCMAX_B 0x4AC10 +#define PAL_PREC_GCMAX_C 0x4B410
+#define _PREC_PAL_INDEX(pipe) \
- (_PIPE3(pipe, PAL_PREC_INDEX_A, PAL_PREC_INDEX_B,
PAL_PREC_INDEX_C)) +#define _PREC_PAL_DATA(pipe) \
- (_PIPE3(pipe, PAL_PREC_DATA_A, PAL_PREC_DATA_B,
PAL_PREC_DATA_C)) +#define _PREC_PAL_GCMAX(pipe) \
- (_PIPE3(pipe, PAL_PREC_GCMAX_A, PAL_PREC_GCMAX_B,
PAL_PREC_GCMAX_C))
#endif /* _I915_REG_H_ */ diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index d5315b2..74f8fc3 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -26,6 +26,252 @@ */
#include "intel_color_manager.h" +static void bdw_write_10bit_gamma_precision(struct drm_device *dev,
- struct drm_r32g32b32 *correction_values, u32 pal_prec_data,
u32 no_of_coeff)+{
- u16 blue_fract, green_fract, red_fract;
- u32 word = 0;
- u32 count = 0;
- u32 blue, green, red;
- struct drm_i915_private *dev_priv = dev->dev_private;
- while (count < no_of_coeff) {
blue = correction_values[count].b32;green = correction_values[count].g32;red = correction_values[count].r32;/** Maximum possible gamma correction value supported* for BDW is 0xFFFFFFFF, so clip the valuesaccordingly
*/I think you mean clamp not clip.
Yes, will fix this.
if (blue >= BDW_MAX_GAMMA)blue = BDW_MAX_GAMMA;if (green >= BDW_MAX_GAMMA)green = BDW_MAX_GAMMA;if (red >= BDW_MAX_GAMMA)red = BDW_MAX_GAMMA;So this handles the issue that was raised before that 1.0 in 8.24 should map to 1023.
Yes.
/** Gamma correction values are sent in 8.24 format* with 8 int and 24 fraction bits. BDW 10 bit gamma* unit expects correction registers to be programmedin
* 0.10 format, with 0 int and 16 fraction bits. Sotake
* MSB 10 bit values(bits 23-14) from the fractionpart and
* prepare the correction registers.*/blue_fract = GET_BITS(blue, 14, 10);green_fract = GET_BITS(green, 14, 10);red_fract = GET_BITS(red, 14, 10);I think this should round to the nearest rather than floor.
Why ? we are getting the exact values already.
/* Arrange: Red (29:20) Green (19:10) and Blue (9:0)*/
SET_BITS(word, red_fract, 20, 10);SET_BITS(word, red_fract, 10, 10);SET_BITS(word, red_fract, 0, 10);Red is my favourite colour too, is that why you programmed all the channels to the red bits? :-)
Guilty :). While testing, all the channels have the same values, so it dint matter. I will fix this.
I915_WRITE(pal_prec_data, word);count++;- }
- DRM_DEBUG_DRIVER("Gamma correction programmed\n");
+}
+void bdw_write_12bit_gamma_precision(struct drm_device *dev,
- struct drm_r32g32b32 *correction_values, u32 pal_prec_data,
enum pipe pipe)+{
- uint16_t blue_fract, green_fract, red_fract;
- uint32_t gcmax;
- uint32_t word = 0;
- uint32_t count = 0;
- uint32_t gcmax_reg;
- struct drm_i915_private *dev_priv = dev->dev_private;
- /* Program first 512 values in precision palette */
- while (count < BDW_12BIT_GAMMA_MAX_VALS - 1) {
/** Framework's general gamma format is 8.24 (8 int 16fraction)
* BDW Platform's supported gamma format is 16 bitcorrection
* values in 0.16 format. So extract higher 16fraction bits
* from 8.24 gamma correction values.*/red_fract = GET_BITS(correction_values[count].r32,8, 16);
green_fract = GET_BITS(correction_values[count].g32,8, 16);
blue_fract = GET_BITS(correction_values[count].b32,8, 16);
Again, 1.0 in 8.24 will result in you programming zeros rather than max.
Will add the max check and conversion here also.
/** From the bspec:* For 12 bit gamma correction, program precisionpalette
* with 16 bits per color in a 0.16 format with 0integer and
* 16 fractional bits (upper 10 bits in odd indexes,lower 6
* bits in even indexes)*//* Even index: Lower 6 bits from correction shouldgo as MSB */
SET_BITS(word, GET_BITS(red_fract, 0, 6), 24, 6);SET_BITS(word, GET_BITS(green_fract, 0, 6), 14, 6);SET_BITS(word, GET_BITS(blue_fract, 0, 6), 4, 6);I915_WRITE(pal_prec_data, word);word = 0x0;/* Odd index: Upper 10 bits of correction should goas MSB */
SET_BITS(word, GET_BITS(red_fract, 6, 10), 20, 10);SET_BITS(word, GET_BITS(green_fract, 6, 10), 10,10);
SET_BITS(word, GET_BITS(blue_fract, 6, 10), 0, 10);I915_WRITE(pal_prec_data, word);count++;- }
- /* Now program the 513th value in GCMAX regs */
- word = 0;
- gcmax_reg = _PREC_PAL_GCMAX(pipe);
- gcmax = min_t(u32, GET_BITS(correction_values[count].r32, 8,
17),
BDW_MAX_GAMMA);- SET_BITS(word, gcmax, 0, 17);
- I915_WRITE(gcmax_reg, word);
- gcmax_reg += 4;
- word = 0;
- gcmax = min_t(u32, GET_BITS(correction_values[count].g32, 8,
17),
BDW_MAX_GAMMA);- SET_BITS(word, gcmax, 0, 17);
- I915_WRITE(gcmax_reg, word);
- gcmax_reg += 4;
- word = 0;
- gcmax = min_t(u32, GET_BITS(correction_values[count].b32, 8,
17),
BDW_MAX_GAMMA);- SET_BITS(word, gcmax, 0, 17);
- I915_WRITE(gcmax_reg, word);
+}
+/* Apply unity gamma for gamma reset */ +static void bdw_reset_gamma(struct drm_i915_private *dev_priv,
enum pipe pipe)+{
- u16 count = 0;
- u32 val;
- u32 pal_prec_data = LGC_PALETTE(pipe, 0);
- DRM_DEBUG_DRIVER("\n");
- /* Reset the palette for unit gamma */
- while (count < BDW_8BIT_GAMMA_MAX_VALS) {
/* Red (23:16) Green (15:8) and Blue (7:0) */val = (count << 16) | (count << 8) | count;I915_WRITE(pal_prec_data, val);pal_prec_data += 4;count++;- }
+}
+static int bdw_set_gamma(struct drm_device *dev, struct drm_property_blob *blob,
struct drm_crtc *crtc)+{
- u16 blue_fract, green_fract, red_fract;
- enum pipe pipe;
- int count, num_samples;
- u32 blue, green, red;
- u32 mode, pal_prec_index, pal_prec_data;
- u32 index;
- u32 word = 0;
- struct drm_palette *gamma_data;
- struct drm_crtc_state *state = crtc->state;
- struct drm_i915_private *dev_priv = dev->dev_private;
- struct drm_r32g32b32 *correction_values = NULL;
- if (WARN_ON(!blob))
return -EINVAL;- gamma_data = (struct drm_palette *)blob->data;
- pipe = to_intel_crtc(crtc)->pipe;
- num_samples = gamma_data->num_samples;
- pal_prec_index = _PREC_PAL_INDEX(pipe);
- pal_prec_data = _PREC_PAL_DATA(pipe);
- correction_values = (struct drm_r32g32b32 *)&gamma_data
->lut;
- index = I915_READ(pal_prec_index);
- switch (num_samples) {
- case GAMMA_DISABLE_VALS:
/* Disable Gamma functionality on Pipe */DRM_DEBUG_DRIVER("Disabling gamma on Pipe %c\n",pipe_name(pipe));mode = I915_READ(GAMMA_MODE(pipe));if ((mode & GAMMA_MODE_MODE_MASK) ==GAMMA_MODE_MODE_12BIT)
bdw_reset_gamma(dev_priv, pipe);Why only call bdw_reset_gamma() if we were in 12-bit mode? What about the other modes? What about if somebody has programmed the value through the legacy ioctl?
We tested this part, its only required for 12 bit gamma. The legacy IOCTL only programs 8bit gamma, which doesnt need this anyways, coz we are overwriting legacy palette to gamma = 1, while disabling gamma. If we dont do this for 12 bit gamma, screen goes all black.
state->palette_after_ctm_blob = NULL;word = GAMMA_MODE_MODE_8BIT;break;- case BDW_8BIT_GAMMA_MAX_VALS:
/* Legacy palette */pal_prec_data = LGC_PALETTE(pipe, 0);count = 0;while (count < BDW_8BIT_GAMMA_MAX_VALS) {blue = correction_values[count].b32;green = correction_values[count].g32;red = correction_values[count].r32;blue_fract = GET_BITS(blue, 16, 8);green_fract = GET_BITS(green, 16, 8);red_fract = GET_BITS(red, 16, 8);Shouldn't these round? Rather than always floor.
Why ? This is exact value.
Also 1.0 in 8.24 format will result in you programming zero into the palette. You need to do the max clamping again.
Will fix this part.
/* Blue (7:0) Green (15:8) and Red (23:16)*/
SET_BITS(word, blue_fract, 0, 8);SET_BITS(word, green_fract, 8, 8);SET_BITS(word, blue_fract, 16, 8);I915_WRITE(pal_prec_data, word);pal_prec_data += 4;count++;This code also needs to be made to work nicely with other users of LGC_PALETTE.
This is anyways working with LGC IOCTL, but will clean it up further.
}word = GAMMA_MODE_MODE_8BIT;break;- case BDW_SPLITGAMMA_MAX_VALS:
index |= BDW_INDEX_AUTO_INCREMENT |BDW_INDEX_SPLIT_MODE;
I915_WRITE(pal_prec_index, index);bdw_write_10bit_gamma_precision(dev,correction_values,
pal_prec_data, BDW_SPLITGAMMA_MAX_VALS);word = GAMMA_MODE_MODE_SPLIT;break;- case BDW_12BIT_GAMMA_MAX_VALS:
index |= BDW_INDEX_AUTO_INCREMENT;index &= ~BDW_INDEX_SPLIT_MODE;I915_WRITE(pal_prec_index, index);bdw_write_12bit_gamma_precision(dev,correction_values,
pal_prec_data, pipe);word = GAMMA_MODE_MODE_12BIT;break;- case BDW_10BIT_GAMMA_MAX_VALS:
index |= BDW_INDEX_AUTO_INCREMENT;index &= ~BDW_INDEX_SPLIT_MODE;I915_WRITE(pal_prec_index, index);bdw_write_10bit_gamma_precision(dev,correction_values,
pal_prec_data, BDW_10BIT_GAMMA_MAX_VALS);word = GAMMA_MODE_MODE_10BIT;break;- default:
DRM_ERROR("Invalid number of samples\n");return -EINVAL;- }
- /* Set gamma mode on pipe control reg */
- mode = I915_READ(GAMMA_MODE(pipe));
- mode &= ~GAMMA_MODE_MODE_MASK;
- I915_WRITE(GAMMA_MODE(pipe), mode | word);
- DRM_DEBUG_DRIVER("Gamma applied on pipe %c\n",
- pipe_name(pipe));
- return 0;
+}
static s16 chv_prepare_csc_coeff(s64 csc_value) { @@ -319,6 +565,8 @@ void intel_color_manager_crtc_commit(struct drm_device *dev, /* Gamma correction is platform specific */ if (IS_CHERRYVIEW(dev)) ret = chv_set_gamma(dev, blob, crtc);
else if (IS_BROADWELL(dev) || IS_GEN9(dev))ret = bdw_set_gamma(dev, blob, crtc);if (ret) DRM_ERROR("set Gamma correction failed\n");
diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h index 271246a..6c7cb08 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.h +++ b/drivers/gpu/drm/i915/intel_color_manager.h @@ -92,3 +92,9 @@
/* Gamma on BDW */ #define BDW_SPLITGAMMA_MAX_VALS 512 +#define BDW_8BIT_GAMMA_MAX_VALS 256 +#define BDW_10BIT_GAMMA_MAX_VALS 1024 +#define BDW_12BIT_GAMMA_MAX_VALS 513 +#define BDW_MAX_GAMMA ((1 << 24) - 1) +#define BDW_INDEX_AUTO_INCREMENT (1 << 15) +#define BDW_INDEX_SPLIT_MODE (1 << 31)
Rob
I915 color manager registers pipe degamma correction as palette correction before CTM, DRM property.
This patch adds the no of coefficients(65) for degamma correction as "num_samples_before_ctm" parameter in device info structures, for BDW and higher platforms.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com --- drivers/gpu/drm/i915/i915_drv.c | 7 +++++++ drivers/gpu/drm/i915/intel_color_manager.h | 3 +++ 2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 4fa046f..ebf4910 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -303,6 +303,7 @@ static const struct intel_device_info intel_broadwell_d_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1, @@ -316,6 +317,7 @@ static const struct intel_device_info intel_broadwell_m_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1, @@ -329,6 +331,7 @@ static const struct intel_device_info intel_broadwell_gt3d_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1, @@ -342,6 +345,7 @@ static const struct intel_device_info intel_broadwell_gt3m_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1, @@ -368,6 +372,7 @@ static const struct intel_device_info intel_skylake_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1, @@ -382,6 +387,7 @@ static const struct intel_device_info intel_skylake_gt3_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1, @@ -396,6 +402,7 @@ static const struct intel_device_info intel_broxton_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .num_pipes = 3, .has_ddi = 1, .has_fpga_dbg = 1, diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h index 6c7cb08..e0c486e 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.h +++ b/drivers/gpu/drm/i915/intel_color_manager.h @@ -98,3 +98,6 @@ #define BDW_MAX_GAMMA ((1 << 24) - 1) #define BDW_INDEX_AUTO_INCREMENT (1 << 15) #define BDW_INDEX_SPLIT_MODE (1 << 31) + +/* Degamma on BDW */ +#define BDW_DEGAMMA_MAX_VALS 512
On Sat, 2015-10-10 at 00:59 +0530, Shashank Sharma wrote:
I915 color manager registers pipe degamma correction as palette correction before CTM, DRM property.
This patch adds the no of coefficients(65) for degamma correction as "num_samples_before_ctm" parameter in device info structures, for BDW and higher platforms.
Did you copy and paste this from the CHV version? The only constant you add for degamma here is 512?
Rob
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com
drivers/gpu/drm/i915/i915_drv.c | 7 +++++++ drivers/gpu/drm/i915/intel_color_manager.h | 3 +++ 2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 4fa046f..ebf4910 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -303,6 +303,7 @@ static const struct intel_device_info intel_broadwell_d_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
- .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1,
@@ -316,6 +317,7 @@ static const struct intel_device_info intel_broadwell_m_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
- .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1,
@@ -329,6 +331,7 @@ static const struct intel_device_info intel_broadwell_gt3d_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
- .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1,
@@ -342,6 +345,7 @@ static const struct intel_device_info intel_broadwell_gt3m_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
- .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1,
@@ -368,6 +372,7 @@ static const struct intel_device_info intel_skylake_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
- .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1,
@@ -382,6 +387,7 @@ static const struct intel_device_info intel_skylake_gt3_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
- .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1,
@@ -396,6 +402,7 @@ static const struct intel_device_info intel_broxton_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
- .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .num_pipes = 3, .has_ddi = 1, .has_fpga_dbg = 1,
diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h index 6c7cb08..e0c486e 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.h +++ b/drivers/gpu/drm/i915/intel_color_manager.h @@ -98,3 +98,6 @@ #define BDW_MAX_GAMMA ((1 << 24) - 1) #define BDW_INDEX_AUTO_INCREMENT (1 << 15) #define BDW_INDEX_SPLIT_MODE (1 << 31)
+/* Degamma on BDW */ +#define BDW_DEGAMMA_MAX_VALS 512
Regards Shashank
On 10/12/2015 11:43 PM, Rob Bradford wrote:
On Sat, 2015-10-10 at 00:59 +0530, Shashank Sharma wrote:
I915 color manager registers pipe degamma correction as palette correction before CTM, DRM property.
This patch adds the no of coefficients(65) for degamma correction as "num_samples_before_ctm" parameter in device info structures, for BDW and higher platforms.
Did you copy and paste this from the CHV version? The only constant you add for degamma here is 512?
Oops, side effects of too many code-refactoring without proper sleep :) will fix this.
Rob
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com
drivers/gpu/drm/i915/i915_drv.c | 7 +++++++ drivers/gpu/drm/i915/intel_color_manager.h | 3 +++ 2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 4fa046f..ebf4910 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -303,6 +303,7 @@ static const struct intel_device_info intel_broadwell_d_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
- .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1,
@@ -316,6 +317,7 @@ static const struct intel_device_info intel_broadwell_m_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
- .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1,
@@ -329,6 +331,7 @@ static const struct intel_device_info intel_broadwell_gt3d_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
- .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1,
@@ -342,6 +345,7 @@ static const struct intel_device_info intel_broadwell_gt3m_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
- .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1,
@@ -368,6 +372,7 @@ static const struct intel_device_info intel_skylake_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
- .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1,
@@ -382,6 +387,7 @@ static const struct intel_device_info intel_skylake_gt3_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
- .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1,
@@ -396,6 +402,7 @@ static const struct intel_device_info intel_broxton_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
- .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .num_pipes = 3, .has_ddi = 1, .has_fpga_dbg = 1,
diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h index 6c7cb08..e0c486e 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.h +++ b/drivers/gpu/drm/i915/intel_color_manager.h @@ -98,3 +98,6 @@ #define BDW_MAX_GAMMA ((1 << 24) - 1) #define BDW_INDEX_AUTO_INCREMENT (1 << 15) #define BDW_INDEX_SPLIT_MODE (1 << 31)
+/* Degamma on BDW */ +#define BDW_DEGAMMA_MAX_VALS 512
BDW/SKL/BXT supports Degamma color correction feature, which linearizes the non-linearity due to gamma encoded color values. This will be applied before Color Transformation.
This patch does the following: 1. Adds the core function to program DeGamma correction values for BDW/SKL/BXT platform 2. Adds DeGamma correction macros/defines
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com --- drivers/gpu/drm/i915/intel_color_manager.c | 59 ++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index 74f8fc3..e659382 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -273,6 +273,63 @@ static int bdw_set_gamma(struct drm_device *dev, struct drm_property_blob *blob, return 0; }
+static int bdw_set_degamma(struct drm_device *dev, + struct drm_property_blob *blob, struct drm_crtc *crtc) +{ + enum pipe pipe; + int num_samples, length; + u32 index, mode; + u32 pal_prec_index, pal_prec_data; + struct drm_palette *degamma_data; + struct drm_crtc_state *state = crtc->state; + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_r32g32b32 *correction_values = NULL; + + if (WARN_ON(!blob)) + return -EINVAL; + + degamma_data = (struct drm_palette *)blob->data; + pipe = to_intel_crtc(crtc)->pipe; + num_samples = degamma_data->num_samples; + + if (num_samples == GAMMA_DISABLE_VALS) { + /* Disable degamma on Pipe */ + mode = I915_READ(GAMMA_MODE(pipe)) & ~GAMMA_MODE_MODE_MASK; + I915_WRITE(GAMMA_MODE(pipe), mode | GAMMA_MODE_MODE_8BIT); + + state->palette_before_ctm_blob = NULL; + DRM_DEBUG_DRIVER("Disabling degamma on Pipe %c\n", + pipe_name(pipe)); + return 0; + } + + if (num_samples != BDW_SPLITGAMMA_MAX_VALS) { + DRM_ERROR("Invalid number of samples\n"); + return -EINVAL; + } + + length = num_samples * sizeof(struct drm_r32g32b32); + mode = I915_READ(GAMMA_MODE(pipe)); + pal_prec_index = _PREC_PAL_INDEX(pipe); + pal_prec_data = _PREC_PAL_DATA(pipe); + + correction_values = (struct drm_r32g32b32 *)°amma_data->lut; + index = I915_READ(pal_prec_index); + index |= BDW_INDEX_AUTO_INCREMENT | BDW_INDEX_SPLIT_MODE; + I915_WRITE(pal_prec_index, index); + + bdw_write_10bit_gamma_precision(dev, correction_values, + pal_prec_data, BDW_SPLITGAMMA_MAX_VALS); + + /* Enable DeGamma on Pipe */ + mode &= ~GAMMA_MODE_MODE_MASK; + I915_WRITE(GAMMA_MODE(pipe), mode | GAMMA_MODE_MODE_SPLIT); + DRM_DEBUG_DRIVER("DeGamma correction enabled on Pipe %c\n", + pipe_name(pipe)); + + return 0; +} + static s16 chv_prepare_csc_coeff(s64 csc_value) { s32 csc_int_value; @@ -579,6 +636,8 @@ void intel_color_manager_crtc_commit(struct drm_device *dev, /* Degamma correction */ if (IS_CHERRYVIEW(dev)) ret = chv_set_degamma(dev, blob, crtc); + else if (IS_BROADWELL(dev) || IS_GEN9(dev)) + ret = bdw_set_degamma(dev, blob, crtc);
if (ret) DRM_ERROR("set degamma correction failed\n");
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma shashank.sharma@intel.com wrote:
BDW/SKL/BXT supports Degamma color correction feature, which linearizes the non-linearity due to gamma encoded color values. This will be applied before Color Transformation.
This patch does the following:
- Adds the core function to program DeGamma correction values for BDW/SKL/BXT platform
- Adds DeGamma correction macros/defines
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com
drivers/gpu/drm/i915/intel_color_manager.c | 59 ++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index 74f8fc3..e659382 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -273,6 +273,63 @@ static int bdw_set_gamma(struct drm_device *dev, struct drm_property_blob *blob, return 0; }
+static int bdw_set_degamma(struct drm_device *dev,
struct drm_property_blob *blob, struct drm_crtc *crtc)+{
enum pipe pipe;int num_samples, length;u32 index, mode;u32 pal_prec_index, pal_prec_data;struct drm_palette *degamma_data;struct drm_crtc_state *state = crtc->state;struct drm_i915_private *dev_priv = dev->dev_private;struct drm_r32g32b32 *correction_values = NULL;if (WARN_ON(!blob))return -EINVAL;degamma_data = (struct drm_palette *)blob->data;pipe = to_intel_crtc(crtc)->pipe;num_samples = degamma_data->num_samples;if (num_samples == GAMMA_DISABLE_VALS) {/* Disable degamma on Pipe */mode = I915_READ(GAMMA_MODE(pipe)) & ~GAMMA_MODE_MODE_MASK;I915_WRITE(GAMMA_MODE(pipe), mode | GAMMA_MODE_MODE_8BIT);state->palette_before_ctm_blob = NULL;DRM_DEBUG_DRIVER("Disabling degamma on Pipe %c\n",pipe_name(pipe));return 0;}if (num_samples != BDW_SPLITGAMMA_MAX_VALS) {DRM_ERROR("Invalid number of samples\n");return -EINVAL;}
Why don't you use switch statement here ?
length = num_samples * sizeof(struct drm_r32g32b32);mode = I915_READ(GAMMA_MODE(pipe));pal_prec_index = _PREC_PAL_INDEX(pipe);pal_prec_data = _PREC_PAL_DATA(pipe);correction_values = (struct drm_r32g32b32 *)°amma_data->lut;index = I915_READ(pal_prec_index);index |= BDW_INDEX_AUTO_INCREMENT | BDW_INDEX_SPLIT_MODE;I915_WRITE(pal_prec_index, index);bdw_write_10bit_gamma_precision(dev, correction_values,pal_prec_data, BDW_SPLITGAMMA_MAX_VALS);/* Enable DeGamma on Pipe */mode &= ~GAMMA_MODE_MODE_MASK;I915_WRITE(GAMMA_MODE(pipe), mode | GAMMA_MODE_MODE_SPLIT);DRM_DEBUG_DRIVER("DeGamma correction enabled on Pipe %c\n",pipe_name(pipe));
Indentation seems funny here.
Regards, Emil
Regards Shashank
On 10/10/2015 5:19 AM, Emil Velikov wrote:
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma shashank.sharma@intel.com wrote:
BDW/SKL/BXT supports Degamma color correction feature, which linearizes the non-linearity due to gamma encoded color values. This will be applied before Color Transformation.
This patch does the following:
- Adds the core function to program DeGamma correction values for BDW/SKL/BXT platform
- Adds DeGamma correction macros/defines
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com
drivers/gpu/drm/i915/intel_color_manager.c | 59 ++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index 74f8fc3..e659382 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -273,6 +273,63 @@ static int bdw_set_gamma(struct drm_device *dev, struct drm_property_blob *blob, return 0; }
+static int bdw_set_degamma(struct drm_device *dev,
struct drm_property_blob *blob, struct drm_crtc *crtc)+{
enum pipe pipe;int num_samples, length;u32 index, mode;u32 pal_prec_index, pal_prec_data;struct drm_palette *degamma_data;struct drm_crtc_state *state = crtc->state;struct drm_i915_private *dev_priv = dev->dev_private;struct drm_r32g32b32 *correction_values = NULL;if (WARN_ON(!blob))return -EINVAL;degamma_data = (struct drm_palette *)blob->data;pipe = to_intel_crtc(crtc)->pipe;num_samples = degamma_data->num_samples;if (num_samples == GAMMA_DISABLE_VALS) {/* Disable degamma on Pipe */mode = I915_READ(GAMMA_MODE(pipe)) & ~GAMMA_MODE_MODE_MASK;I915_WRITE(GAMMA_MODE(pipe), mode | GAMMA_MODE_MODE_8BIT);state->palette_before_ctm_blob = NULL;DRM_DEBUG_DRIVER("Disabling degamma on Pipe %c\n",pipe_name(pipe));return 0;}if (num_samples != BDW_SPLITGAMMA_MAX_VALS) {DRM_ERROR("Invalid number of samples\n");return -EINVAL;}Why don't you use switch statement here ?
Same as CHV degamma. Degamma has only 3 conditions (enable/disable and invalid), and we generally try to accommodate upto 3 condition within if ... else.
length = num_samples * sizeof(struct drm_r32g32b32);mode = I915_READ(GAMMA_MODE(pipe));pal_prec_index = _PREC_PAL_INDEX(pipe);pal_prec_data = _PREC_PAL_DATA(pipe);correction_values = (struct drm_r32g32b32 *)°amma_data->lut;index = I915_READ(pal_prec_index);index |= BDW_INDEX_AUTO_INCREMENT | BDW_INDEX_SPLIT_MODE;I915_WRITE(pal_prec_index, index);bdw_write_10bit_gamma_precision(dev, correction_values,pal_prec_data, BDW_SPLITGAMMA_MAX_VALS);/* Enable DeGamma on Pipe */mode &= ~GAMMA_MODE_MODE_MASK;I915_WRITE(GAMMA_MODE(pipe), mode | GAMMA_MODE_MODE_SPLIT);DRM_DEBUG_DRIVER("DeGamma correction enabled on Pipe %c\n",pipe_name(pipe));Indentation seems funny here.
Yeah, every time time we try to publish a success story, pipe_name() ruins it :). Will fix it.
Regards, Emil
On 10 October 2015 at 06:31, Sharma, Shashank shashank.sharma@intel.com wrote:
On 10/10/2015 5:19 AM, Emil Velikov wrote:
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma shashank.sharma@intel.com wrote:
BDW/SKL/BXT supports Degamma color correction feature, which linearizes the non-linearity due to gamma encoded color values. This will be applied before Color Transformation.
This patch does the following:
- Adds the core function to program DeGamma correction values for BDW/SKL/BXT platform
- Adds DeGamma correction macros/defines
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com
[snip]
Why don't you use switch statement here ?
Same as CHV degamma. Degamma has only 3 conditions (enable/disable and invalid), and we generally try to accommodate upto 3 condition within if ... else.
That rule sounds a bit funny bth. I'm not sure where it comes from, but as is the codeflow isn't that obvious and the patches look inconsistent with one another.
Regards, Emil
On Sat, 2015-10-10 at 00:59 +0530, Shashank Sharma wrote:
BDW/SKL/BXT supports Degamma color correction feature, which linearizes the non-linearity due to gamma encoded color values. This will be applied before Color Transformation.
This patch does the following:
- Adds the core function to program DeGamma correction values for BDW/SKL/BXT platform
- Adds DeGamma correction macros/defines
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com
drivers/gpu/drm/i915/intel_color_manager.c | 59 ++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index 74f8fc3..e659382 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -273,6 +273,63 @@ static int bdw_set_gamma(struct drm_device *dev, struct drm_property_blob *blob, return 0; }
+static int bdw_set_degamma(struct drm_device *dev,
- struct drm_property_blob *blob, struct drm_crtc *crtc)
+{
- enum pipe pipe;
- int num_samples, length;
- u32 index, mode;
- u32 pal_prec_index, pal_prec_data;
- struct drm_palette *degamma_data;
- struct drm_crtc_state *state = crtc->state;
- struct drm_i915_private *dev_priv = dev->dev_private;
- struct drm_r32g32b32 *correction_values = NULL;
- if (WARN_ON(!blob))
return -EINVAL;- degamma_data = (struct drm_palette *)blob->data;
- pipe = to_intel_crtc(crtc)->pipe;
- num_samples = degamma_data->num_samples;
- if (num_samples == GAMMA_DISABLE_VALS) {
/* Disable degamma on Pipe */mode = I915_READ(GAMMA_MODE(pipe)) &~GAMMA_MODE_MODE_MASK;
I915_WRITE(GAMMA_MODE(pipe), mode |GAMMA_MODE_MODE_8BIT);
When you turn off gamma you call bdw_reset_gamma() should you do the same for degamma?
state->palette_before_ctm_blob = NULL;DRM_DEBUG_DRIVER("Disabling degamma on Pipe %c\n",pipe_name(pipe));return 0;- }
- if (num_samples != BDW_SPLITGAMMA_MAX_VALS) {
DRM_ERROR("Invalid number of samples\n");return -EINVAL;- }
- length = num_samples * sizeof(struct drm_r32g32b32);
Uh, you calculate this length and don't use it anywhere? Was your intention to check the blob length? And the length check should be in the generic DRM code anyway...
I think it was suggested in the past that the number of samples could be derived from the length of the data allowing the removal of the struct member.
- mode = I915_READ(GAMMA_MODE(pipe));
Move this closer to where you use it?
- pal_prec_index = _PREC_PAL_INDEX(pipe);
- pal_prec_data = _PREC_PAL_DATA(pipe);
- correction_values = (struct drm_r32g32b32 *)°amma_data
->lut;
Why do you need this cast?
- index = I915_READ(pal_prec_index);
- index |= BDW_INDEX_AUTO_INCREMENT | BDW_INDEX_SPLIT_MODE;
- I915_WRITE(pal_prec_index, index);
- bdw_write_10bit_gamma_precision(dev, correction_values,
pal_prec_data, BDW_SPLITGAMMA_MAX_VALS);- /* Enable DeGamma on Pipe */
- mode &= ~GAMMA_MODE_MODE_MASK;
- I915_WRITE(GAMMA_MODE(pipe), mode | GAMMA_MODE_MODE_SPLIT);
- DRM_DEBUG_DRIVER("DeGamma correction enabled on Pipe %c\n",
Choose your capitalisation DeGamma or degamma. Pick one and use it consistently to make it easier to grep through the code.
It also looks like you should check if the gamma mode is not something other than split / off. Otherwise strange things could happen. Similarly in the gamma code you shouldn't be able to program something other than split if you have a degamma mode set.
- pipe_name(pipe));
- return 0;
+}
static s16 chv_prepare_csc_coeff(s64 csc_value) { s32 csc_int_value; @@ -579,6 +636,8 @@ void intel_color_manager_crtc_commit(struct drm_device *dev, /* Degamma correction */ if (IS_CHERRYVIEW(dev)) ret = chv_set_degamma(dev, blob, crtc);
else if (IS_BROADWELL(dev) || IS_GEN9(dev))ret = bdw_set_degamma(dev, blob, crtc);if (ret) DRM_ERROR("set degamma correction
failed\n");
Rob
Thanks for the review Rob.
Regards Shashank On 10/12/2015 11:38 PM, Rob Bradford wrote:
On Sat, 2015-10-10 at 00:59 +0530, Shashank Sharma wrote:
BDW/SKL/BXT supports Degamma color correction feature, which linearizes the non-linearity due to gamma encoded color values. This will be applied before Color Transformation.
This patch does the following:
- Adds the core function to program DeGamma correction values for BDW/SKL/BXT platform
- Adds DeGamma correction macros/defines
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com
drivers/gpu/drm/i915/intel_color_manager.c | 59 ++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index 74f8fc3..e659382 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -273,6 +273,63 @@ static int bdw_set_gamma(struct drm_device *dev, struct drm_property_blob *blob, return 0; }
+static int bdw_set_degamma(struct drm_device *dev,
- struct drm_property_blob *blob, struct drm_crtc *crtc)
+{
- enum pipe pipe;
- int num_samples, length;
- u32 index, mode;
- u32 pal_prec_index, pal_prec_data;
- struct drm_palette *degamma_data;
- struct drm_crtc_state *state = crtc->state;
- struct drm_i915_private *dev_priv = dev->dev_private;
- struct drm_r32g32b32 *correction_values = NULL;
- if (WARN_ON(!blob))
return -EINVAL;- degamma_data = (struct drm_palette *)blob->data;
- pipe = to_intel_crtc(crtc)->pipe;
- num_samples = degamma_data->num_samples;
- if (num_samples == GAMMA_DISABLE_VALS) {
/* Disable degamma on Pipe */mode = I915_READ(GAMMA_MODE(pipe)) &~GAMMA_MODE_MODE_MASK;
I915_WRITE(GAMMA_MODE(pipe), mode |GAMMA_MODE_MODE_8BIT);
When you turn off gamma you call bdw_reset_gamma() should you do the same for degamma?
No, we tested this part, its not required, its only required for 12 bit gamma.
state->palette_before_ctm_blob = NULL;DRM_DEBUG_DRIVER("Disabling degamma on Pipe %c\n",pipe_name(pipe));return 0;- }
- if (num_samples != BDW_SPLITGAMMA_MAX_VALS) {
DRM_ERROR("Invalid number of samples\n");return -EINVAL;- }
- length = num_samples * sizeof(struct drm_r32g32b32);
Uh, you calculate this length and don't use it anywhere? Was your intention to check the blob length? And the length check should be in the generic DRM code anyway...
Yes, this was left over from the previous patch set, will remove this.
I think it was suggested in the past that the number of samples could be derived from the length of the data allowing the removal of the struct member.
Right now, its better to have the no of samples coming from userspace. As the platform is under development, its good to have this control available so that userspace will be clear on what it wants to do, I have added this in my to do list, when we are sure that we dont need it, we will remove and optimize it.
- mode = I915_READ(GAMMA_MODE(pipe));
Move this closer to where you use it?
Agree.
- pal_prec_index = _PREC_PAL_INDEX(pipe);
- pal_prec_data = _PREC_PAL_DATA(pipe);
- correction_values = (struct drm_r32g32b32 *)°amma_data
->lut;
Why do you need this cast?
Not required, agree, will remove.
- index = I915_READ(pal_prec_index);
- index |= BDW_INDEX_AUTO_INCREMENT | BDW_INDEX_SPLIT_MODE;
- I915_WRITE(pal_prec_index, index);
- bdw_write_10bit_gamma_precision(dev, correction_values,
pal_prec_data, BDW_SPLITGAMMA_MAX_VALS);- /* Enable DeGamma on Pipe */
- mode &= ~GAMMA_MODE_MODE_MASK;
- I915_WRITE(GAMMA_MODE(pipe), mode | GAMMA_MODE_MODE_SPLIT);
- DRM_DEBUG_DRIVER("DeGamma correction enabled on Pipe %c\n",
Choose your capitalisation DeGamma or degamma. Pick one and use it consistently to make it easier to grep through the code.
Will stick with degamma now.
It also looks like you should check if the gamma mode is not something other than split / off. Otherwise strange things could happen. Similarly in the gamma code you shouldn't be able to program something other than split if you have a degamma mode set.
We discussed this in the design phase itself. This decision has to go to userspcae only, whom should know, what its doing. There are various permutation and combinations possbile which make kernel code unnecessary complex. Kernel will just follow what is being requested from usp.
- pipe_name(pipe));
- return 0;
+}
- static s16 chv_prepare_csc_coeff(s64 csc_value) { s32 csc_int_value;
@@ -579,6 +636,8 @@ void intel_color_manager_crtc_commit(struct drm_device *dev, /* Degamma correction */ if (IS_CHERRYVIEW(dev)) ret = chv_set_degamma(dev, blob, crtc);
else if (IS_BROADWELL(dev) || IS_GEN9(dev))ret = bdw_set_degamma(dev, blob, crtc);if (ret) DRM_ERROR("set degamma correction
failed\n");
Rob
BDW/SKL/BXT support Color Space Conversion (CSC) using a 3x3 matrix that needs to be programmed into respective CSC registers.
This patch does the following: 1. Adds the core function to program CSC correction values for BDW/SKL/BXT platform 2. Adds CSC correction macros/defines
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com Signed-off-by: Kumar, Kiran S kiran.s.kumar@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 7 ++ drivers/gpu/drm/i915/intel_color_manager.c | 114 ++++++++++++++++++++++++++++- drivers/gpu/drm/i915/intel_color_manager.h | 12 ++- 3 files changed, 129 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ed50f75..0e9d252 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8085,4 +8085,11 @@ enum skl_disp_power_wells { (_PIPE3(pipe, PAL_PREC_GCMAX_A, PAL_PREC_GCMAX_B, PAL_PREC_GCMAX_C))
+/* BDW CSC correction */ +#define CSC_COEFF_A 0x49010 +#define CSC_COEFF_B 0x49110 +#define CSC_COEFF_C 0x49210 +#define _PIPE_CSC_COEFF(pipe) \ + (_PIPE3(pipe, CSC_COEFF_A, CSC_COEFF_B, CSC_COEFF_C)) + #endif /* _I915_REG_H_ */ diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index e659382..0a6c00c 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -330,11 +330,119 @@ static int bdw_set_degamma(struct drm_device *dev, return 0; }
-static s16 chv_prepare_csc_coeff(s64 csc_value) +static uint32_t bdw_prepare_csc_coeff(int64_t coeff) +{ + uint32_t reg_val, ls_bit_pos, exponent_bits, sign_bit = 0; + int32_t mantissa; + uint64_t abs_coeff; + + coeff = min_t(int64_t, coeff, BDW_CSC_COEFF_MAX_VAL); + coeff = max_t(int64_t, coeff, BDW_CSC_COEFF_MIN_VAL); + + abs_coeff = abs(coeff); + if (abs_coeff < (BDW_CSC_COEFF_UNITY_VAL >> 3)) { + /* abs_coeff < 0.125 */ + exponent_bits = 3; + ls_bit_pos = 19; + } else if (abs_coeff >= (BDW_CSC_COEFF_UNITY_VAL >> 3) && + abs_coeff < (BDW_CSC_COEFF_UNITY_VAL >> 2)) { + /* abs_coeff >= 0.125 && val < 0.25 */ + exponent_bits = 2; + ls_bit_pos = 20; + } else if (abs_coeff >= (BDW_CSC_COEFF_UNITY_VAL >> 2) + && abs_coeff < (BDW_CSC_COEFF_UNITY_VAL >> 1)) { + /* abs_coeff >= 0.25 && val < 0.5 */ + exponent_bits = 1; + ls_bit_pos = 21; + } else if (abs_coeff >= (BDW_CSC_COEFF_UNITY_VAL >> 1) + && abs_coeff < BDW_CSC_COEFF_UNITY_VAL) { + /* abs_coeff >= 0.5 && val < 1.0 */ + exponent_bits = 0; + ls_bit_pos = 22; + } else if (abs_coeff >= BDW_CSC_COEFF_UNITY_VAL && + abs_coeff < (BDW_CSC_COEFF_UNITY_VAL << 1)) { + /* abs_coeff >= 1.0 && val < 2.0 */ + exponent_bits = 7; + ls_bit_pos = 23; + } else { + /* abs_coeff >= 2.0 && val < 4.0 */ + exponent_bits = 6; + ls_bit_pos = 24; + } + + mantissa = GET_BITS_ROUNDOFF(abs_coeff, ls_bit_pos, CSC_MAX_VALS); + if (coeff < 0) { + sign_bit = 1; + mantissa = -mantissa; + mantissa &= ((1 << CSC_MAX_VALS) - 1); + } + + reg_val = 0; + SET_BITS(reg_val, exponent_bits, 12, 3); + SET_BITS(reg_val, mantissa, 3, 9); + SET_BITS(reg_val, sign_bit, 15, 1); + DRM_DEBUG_DRIVER("CSC: reg_val=0x%x\n", reg_val); + return reg_val; +} + +int bdw_set_csc(struct drm_device *dev, struct drm_property_blob *blob, + struct drm_crtc *crtc) +{ + enum pipe pipe; + enum plane plane; + int i, j, temp; + int word = 0; + u32 reg, plane_ctl, mode; + struct drm_ctm *csc_data; + struct drm_i915_private *dev_priv = dev->dev_private; + + if (WARN_ON(!blob)) + return -EINVAL; + + if (blob->length != sizeof(struct drm_ctm)) { + DRM_ERROR("Invalid length of data received\n"); + return -EINVAL; + } + + csc_data = (struct drm_ctm *)blob->data; + pipe = to_intel_crtc(crtc)->pipe; + plane = to_intel_crtc(crtc)->plane; + + plane_ctl = I915_READ(PLANE_CTL(pipe, plane)); + plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE; + I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl); + reg = _PIPE_CSC_COEFF(pipe); + + /* Write csc coeff to csc regs */ + for (i = 0, j = 0; i < CSC_MAX_VALS; i++) { + if ((i % 3) == 0) { + temp = bdw_prepare_csc_coeff(csc_data->ctm_coeff[i]); + SET_BITS(word, temp, 16, 16); + i++; + temp = bdw_prepare_csc_coeff(csc_data->ctm_coeff[i]); + SET_BITS(word, temp, 0, 16); + } else { + temp = bdw_prepare_csc_coeff(csc_data->ctm_coeff[i]); + SET_BITS(word, temp, 16, 16); + } + + I915_WRITE(reg + j, word); + j = j + 4; + } + + /* Enable CSC functionality */ + mode = I915_READ(PIPE_CSC_MODE(pipe)); + mode |= CSC_POSITION_BEFORE_GAMMA; + I915_WRITE(PIPE_CSC_MODE(pipe), mode); + DRM_DEBUG_DRIVER("CSC enabled on Pipe %c\n", pipe_name(pipe)); + return 0; +} + +static s32 chv_prepare_csc_coeff(s64 csc_value) { s32 csc_int_value; u32 csc_fract_value; - s16 csc_s3_12_format; + s32 csc_s3_12_format;
if (csc_value >= 0) { csc_value += CHV_CSC_FRACT_ROUNDOFF; @@ -650,6 +758,8 @@ void intel_color_manager_crtc_commit(struct drm_device *dev, /* CSC correction */ if (IS_CHERRYVIEW(dev)) ret = chv_set_csc(dev, blob, crtc); + else if (IS_BROADWELL(dev) || IS_GEN9(dev)) + ret = bdw_set_csc(dev, blob, crtc);
if (ret) DRM_ERROR("set CSC correction failed\n"); diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h index e0c486e..853c73c 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.h +++ b/drivers/gpu/drm/i915/intel_color_manager.h @@ -90,7 +90,15 @@ #define CGM_CSC_EN (1 << 1) #define CGM_DEGAMMA_EN (1 << 0)
-/* Gamma on BDW */ +/* BDW CSC */ +/* 1.0000000 in S31.32 format */ +#define BDW_CSC_COEFF_UNITY_VAL 0x100000000 +/* 3.9921875 in S31.32 format */ +#define BDW_CSC_COEFF_MAX_VAL 0x3FE000000 +/*-4.000000 in S31.32 format */ +#define BDW_CSC_COEFF_MIN_VAL 0xFFFFFFFC00000000 + +/* BDW Gamma */ #define BDW_SPLITGAMMA_MAX_VALS 512 #define BDW_8BIT_GAMMA_MAX_VALS 256 #define BDW_10BIT_GAMMA_MAX_VALS 1024 @@ -99,5 +107,5 @@ #define BDW_INDEX_AUTO_INCREMENT (1 << 15) #define BDW_INDEX_SPLIT_MODE (1 << 31)
-/* Degamma on BDW */ +/* BDW Degamma*/ #define BDW_DEGAMMA_MAX_VALS 512
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma shashank.sharma@intel.com wrote:
BDW/SKL/BXT support Color Space Conversion (CSC) using a 3x3 matrix that needs to be programmed into respective CSC registers.
This patch does the following:
- Adds the core function to program CSC correction values for BDW/SKL/BXT platform
- Adds CSC correction macros/defines
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com Signed-off-by: Kumar, Kiran S kiran.s.kumar@intel.com
drivers/gpu/drm/i915/i915_reg.h | 7 ++ drivers/gpu/drm/i915/intel_color_manager.c | 114 ++++++++++++++++++++++++++++- drivers/gpu/drm/i915/intel_color_manager.h | 12 ++- 3 files changed, 129 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ed50f75..0e9d252 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8085,4 +8085,11 @@ enum skl_disp_power_wells { (_PIPE3(pipe, PAL_PREC_GCMAX_A, PAL_PREC_GCMAX_B, PAL_PREC_GCMAX_C))
+/* BDW CSC correction */ +#define CSC_COEFF_A 0x49010 +#define CSC_COEFF_B 0x49110 +#define CSC_COEFF_C 0x49210 +#define _PIPE_CSC_COEFF(pipe) \
(_PIPE3(pipe, CSC_COEFF_A, CSC_COEFF_B, CSC_COEFF_C))#endif /* _I915_REG_H_ */ diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index e659382..0a6c00c 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -330,11 +330,119 @@ static int bdw_set_degamma(struct drm_device *dev, return 0; }
-static s16 chv_prepare_csc_coeff(s64 csc_value)
As mentioned previously, this should be part of the respective patch.
+static uint32_t bdw_prepare_csc_coeff(int64_t coeff) +{
uint32_t reg_val, ls_bit_pos, exponent_bits, sign_bit = 0;int32_t mantissa;uint64_t abs_coeff;coeff = min_t(int64_t, coeff, BDW_CSC_COEFF_MAX_VAL);coeff = max_t(int64_t, coeff, BDW_CSC_COEFF_MIN_VAL);abs_coeff = abs(coeff);if (abs_coeff < (BDW_CSC_COEFF_UNITY_VAL >> 3)) {/* abs_coeff < 0.125 */exponent_bits = 3;ls_bit_pos = 19;} else if (abs_coeff >= (BDW_CSC_COEFF_UNITY_VAL >> 3) &&abs_coeff < (BDW_CSC_COEFF_UNITY_VAL >> 2)) {/* abs_coeff >= 0.125 && val < 0.25 */exponent_bits = 2;ls_bit_pos = 20;} else if (abs_coeff >= (BDW_CSC_COEFF_UNITY_VAL >> 2)&& abs_coeff < (BDW_CSC_COEFF_UNITY_VAL >> 1)) {/* abs_coeff >= 0.25 && val < 0.5 */exponent_bits = 1;ls_bit_pos = 21;} else if (abs_coeff >= (BDW_CSC_COEFF_UNITY_VAL >> 1)&& abs_coeff < BDW_CSC_COEFF_UNITY_VAL) {/* abs_coeff >= 0.5 && val < 1.0 */exponent_bits = 0;ls_bit_pos = 22;} else if (abs_coeff >= BDW_CSC_COEFF_UNITY_VAL &&abs_coeff < (BDW_CSC_COEFF_UNITY_VAL << 1)) {/* abs_coeff >= 1.0 && val < 2.0 */exponent_bits = 7;ls_bit_pos = 23;} else {/* abs_coeff >= 2.0 && val < 4.0 */exponent_bits = 6;ls_bit_pos = 24;}mantissa = GET_BITS_ROUNDOFF(abs_coeff, ls_bit_pos, CSC_MAX_VALS);if (coeff < 0) {sign_bit = 1;mantissa = -mantissa;mantissa &= ((1 << CSC_MAX_VALS) - 1);
I think there is a macro for this already ?
}reg_val = 0;SET_BITS(reg_val, exponent_bits, 12, 3);SET_BITS(reg_val, mantissa, 3, 9);SET_BITS(reg_val, sign_bit, 15, 1);DRM_DEBUG_DRIVER("CSC: reg_val=0x%x\n", reg_val);return reg_val;+}
+int bdw_set_csc(struct drm_device *dev, struct drm_property_blob *blob,
struct drm_crtc *crtc)+{
The function should be static ?
Regards, Emil
Regards Shashank
On 10/10/2015 5:24 AM, Emil Velikov wrote:
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma shashank.sharma@intel.com wrote:
BDW/SKL/BXT support Color Space Conversion (CSC) using a 3x3 matrix that needs to be programmed into respective CSC registers.
This patch does the following:
- Adds the core function to program CSC correction values for BDW/SKL/BXT platform
- Adds CSC correction macros/defines
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com Signed-off-by: Kumar, Kiran S kiran.s.kumar@intel.com
drivers/gpu/drm/i915/i915_reg.h | 7 ++ drivers/gpu/drm/i915/intel_color_manager.c | 114 ++++++++++++++++++++++++++++- drivers/gpu/drm/i915/intel_color_manager.h | 12 ++- 3 files changed, 129 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ed50f75..0e9d252 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8085,4 +8085,11 @@ enum skl_disp_power_wells { (_PIPE3(pipe, PAL_PREC_GCMAX_A, PAL_PREC_GCMAX_B, PAL_PREC_GCMAX_C))
+/* BDW CSC correction */ +#define CSC_COEFF_A 0x49010 +#define CSC_COEFF_B 0x49110 +#define CSC_COEFF_C 0x49210 +#define _PIPE_CSC_COEFF(pipe) \
(_PIPE3(pipe, CSC_COEFF_A, CSC_COEFF_B, CSC_COEFF_C))- #endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index e659382..0a6c00c 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -330,11 +330,119 @@ static int bdw_set_degamma(struct drm_device *dev, return 0; }
-static s16 chv_prepare_csc_coeff(s64 csc_value)
As mentioned previously, this should be part of the respective patch.
Agree. Looks like diff is messing up a bit. Will take care of this.
+static uint32_t bdw_prepare_csc_coeff(int64_t coeff) +{
uint32_t reg_val, ls_bit_pos, exponent_bits, sign_bit = 0;int32_t mantissa;uint64_t abs_coeff;coeff = min_t(int64_t, coeff, BDW_CSC_COEFF_MAX_VAL);coeff = max_t(int64_t, coeff, BDW_CSC_COEFF_MIN_VAL);abs_coeff = abs(coeff);if (abs_coeff < (BDW_CSC_COEFF_UNITY_VAL >> 3)) {/* abs_coeff < 0.125 */exponent_bits = 3;ls_bit_pos = 19;} else if (abs_coeff >= (BDW_CSC_COEFF_UNITY_VAL >> 3) &&abs_coeff < (BDW_CSC_COEFF_UNITY_VAL >> 2)) {/* abs_coeff >= 0.125 && val < 0.25 */exponent_bits = 2;ls_bit_pos = 20;} else if (abs_coeff >= (BDW_CSC_COEFF_UNITY_VAL >> 2)&& abs_coeff < (BDW_CSC_COEFF_UNITY_VAL >> 1)) {/* abs_coeff >= 0.25 && val < 0.5 */exponent_bits = 1;ls_bit_pos = 21;} else if (abs_coeff >= (BDW_CSC_COEFF_UNITY_VAL >> 1)&& abs_coeff < BDW_CSC_COEFF_UNITY_VAL) {/* abs_coeff >= 0.5 && val < 1.0 */exponent_bits = 0;ls_bit_pos = 22;} else if (abs_coeff >= BDW_CSC_COEFF_UNITY_VAL &&abs_coeff < (BDW_CSC_COEFF_UNITY_VAL << 1)) {/* abs_coeff >= 1.0 && val < 2.0 */exponent_bits = 7;ls_bit_pos = 23;} else {/* abs_coeff >= 2.0 && val < 4.0 */exponent_bits = 6;ls_bit_pos = 24;}mantissa = GET_BITS_ROUNDOFF(abs_coeff, ls_bit_pos, CSC_MAX_VALS);if (coeff < 0) {sign_bit = 1;mantissa = -mantissa;mantissa &= ((1 << CSC_MAX_VALS) - 1);I think there is a macro for this already ?
Thats for GAMMA_MAX, not for CSC_MAX. Or you mean the whole (1 << CSC_MAX_VALS -1) to be replaced with GET/SET bits ?
}reg_val = 0;SET_BITS(reg_val, exponent_bits, 12, 3);SET_BITS(reg_val, mantissa, 3, 9);SET_BITS(reg_val, sign_bit, 15, 1);DRM_DEBUG_DRIVER("CSC: reg_val=0x%x\n", reg_val);return reg_val;+}
+int bdw_set_csc(struct drm_device *dev, struct drm_property_blob *blob,
struct drm_crtc *crtc)+{
The function should be static ?
Agree.
Regards, Emil
On 10 October 2015 at 06:34, Sharma, Shashank shashank.sharma@intel.com wrote:
On 10/10/2015 5:24 AM, Emil Velikov wrote:
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma shashank.sharma@intel.com wrote:
BDW/SKL/BXT support Color Space Conversion (CSC) using a 3x3 matrix that needs to be programmed into respective CSC registers.
This patch does the following:
- Adds the core function to program CSC correction values for BDW/SKL/BXT platform
- Adds CSC correction macros/defines
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com Signed-off-by: Kumar, Kiran S kiran.s.kumar@intel.com
drivers/gpu/drm/i915/i915_reg.h | 7 ++ drivers/gpu/drm/i915/intel_color_manager.c | 114 ++++++++++++++++++++++++++++- drivers/gpu/drm/i915/intel_color_manager.h | 12 ++- 3 files changed, 129 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ed50f75..0e9d252 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8085,4 +8085,11 @@ enum skl_disp_power_wells { (_PIPE3(pipe, PAL_PREC_GCMAX_A, PAL_PREC_GCMAX_B, PAL_PREC_GCMAX_C))
+/* BDW CSC correction */ +#define CSC_COEFF_A 0x49010 +#define CSC_COEFF_B 0x49110 +#define CSC_COEFF_C 0x49210 +#define _PIPE_CSC_COEFF(pipe) \
(_PIPE3(pipe, CSC_COEFF_A, CSC_COEFF_B, CSC_COEFF_C))- #endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index e659382..0a6c00c 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -330,11 +330,119 @@ static int bdw_set_degamma(struct drm_device *dev, return 0; }
-static s16 chv_prepare_csc_coeff(s64 csc_value)
As mentioned previously, this should be part of the respective patch.
Agree. Looks like diff is messing up a bit. Will take care of this.
+static uint32_t bdw_prepare_csc_coeff(int64_t coeff) +{
uint32_t reg_val, ls_bit_pos, exponent_bits, sign_bit = 0;int32_t mantissa;uint64_t abs_coeff;coeff = min_t(int64_t, coeff, BDW_CSC_COEFF_MAX_VAL);coeff = max_t(int64_t, coeff, BDW_CSC_COEFF_MIN_VAL);abs_coeff = abs(coeff);if (abs_coeff < (BDW_CSC_COEFF_UNITY_VAL >> 3)) {/* abs_coeff < 0.125 */exponent_bits = 3;ls_bit_pos = 19;} else if (abs_coeff >= (BDW_CSC_COEFF_UNITY_VAL >> 3) &&abs_coeff < (BDW_CSC_COEFF_UNITY_VAL >> 2)) {/* abs_coeff >= 0.125 && val < 0.25 */exponent_bits = 2;ls_bit_pos = 20;} else if (abs_coeff >= (BDW_CSC_COEFF_UNITY_VAL >> 2)&& abs_coeff < (BDW_CSC_COEFF_UNITY_VAL >> 1)) {/* abs_coeff >= 0.25 && val < 0.5 */exponent_bits = 1;ls_bit_pos = 21;} else if (abs_coeff >= (BDW_CSC_COEFF_UNITY_VAL >> 1)&& abs_coeff < BDW_CSC_COEFF_UNITY_VAL) {/* abs_coeff >= 0.5 && val < 1.0 */exponent_bits = 0;ls_bit_pos = 22;} else if (abs_coeff >= BDW_CSC_COEFF_UNITY_VAL &&abs_coeff < (BDW_CSC_COEFF_UNITY_VAL << 1)) {/* abs_coeff >= 1.0 && val < 2.0 */exponent_bits = 7;ls_bit_pos = 23;} else {/* abs_coeff >= 2.0 && val < 4.0 */exponent_bits = 6;ls_bit_pos = 24;}mantissa = GET_BITS_ROUNDOFF(abs_coeff, ls_bit_pos,CSC_MAX_VALS);
if (coeff < 0) {sign_bit = 1;mantissa = -mantissa;mantissa &= ((1 << CSC_MAX_VALS) - 1);I think there is a macro for this already ?
Thats for GAMMA_MAX, not for CSC_MAX. Or you mean the whole (1 << CSC_MAX_VALS -1) to be replaced with GET/SET bits ?
What I mean is - the above looks exactly like the GET_BIT_MASK (which you introduced). Perhaps you can use it ?
Regards, Emil
Regards Shashank
On 10/13/2015 7:15 PM, Emil Velikov wrote:
On 10 October 2015 at 06:34, Sharma, Shashank shashank.sharma@intel.com wrote:
On 10/10/2015 5:24 AM, Emil Velikov wrote:
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma shashank.sharma@intel.com wrote:
BDW/SKL/BXT support Color Space Conversion (CSC) using a 3x3 matrix that needs to be programmed into respective CSC registers.
This patch does the following:
- Adds the core function to program CSC correction values for BDW/SKL/BXT platform
- Adds CSC correction macros/defines
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com Signed-off-by: Kumar, Kiran S kiran.s.kumar@intel.com
drivers/gpu/drm/i915/i915_reg.h | 7 ++ drivers/gpu/drm/i915/intel_color_manager.c | 114 ++++++++++++++++++++++++++++- drivers/gpu/drm/i915/intel_color_manager.h | 12 ++- 3 files changed, 129 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ed50f75..0e9d252 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8085,4 +8085,11 @@ enum skl_disp_power_wells { (_PIPE3(pipe, PAL_PREC_GCMAX_A, PAL_PREC_GCMAX_B, PAL_PREC_GCMAX_C))
+/* BDW CSC correction */ +#define CSC_COEFF_A 0x49010 +#define CSC_COEFF_B 0x49110 +#define CSC_COEFF_C 0x49210 +#define _PIPE_CSC_COEFF(pipe) \
(_PIPE3(pipe, CSC_COEFF_A, CSC_COEFF_B, CSC_COEFF_C))- #endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index e659382..0a6c00c 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -330,11 +330,119 @@ static int bdw_set_degamma(struct drm_device *dev, return 0; }
-static s16 chv_prepare_csc_coeff(s64 csc_value)
As mentioned previously, this should be part of the respective patch.
Agree. Looks like diff is messing up a bit. Will take care of this.
+static uint32_t bdw_prepare_csc_coeff(int64_t coeff) +{
uint32_t reg_val, ls_bit_pos, exponent_bits, sign_bit = 0;int32_t mantissa;uint64_t abs_coeff;coeff = min_t(int64_t, coeff, BDW_CSC_COEFF_MAX_VAL);coeff = max_t(int64_t, coeff, BDW_CSC_COEFF_MIN_VAL);abs_coeff = abs(coeff);if (abs_coeff < (BDW_CSC_COEFF_UNITY_VAL >> 3)) {/* abs_coeff < 0.125 */exponent_bits = 3;ls_bit_pos = 19;} else if (abs_coeff >= (BDW_CSC_COEFF_UNITY_VAL >> 3) &&abs_coeff < (BDW_CSC_COEFF_UNITY_VAL >> 2)) {/* abs_coeff >= 0.125 && val < 0.25 */exponent_bits = 2;ls_bit_pos = 20;} else if (abs_coeff >= (BDW_CSC_COEFF_UNITY_VAL >> 2)&& abs_coeff < (BDW_CSC_COEFF_UNITY_VAL >> 1)) {/* abs_coeff >= 0.25 && val < 0.5 */exponent_bits = 1;ls_bit_pos = 21;} else if (abs_coeff >= (BDW_CSC_COEFF_UNITY_VAL >> 1)&& abs_coeff < BDW_CSC_COEFF_UNITY_VAL) {/* abs_coeff >= 0.5 && val < 1.0 */exponent_bits = 0;ls_bit_pos = 22;} else if (abs_coeff >= BDW_CSC_COEFF_UNITY_VAL &&abs_coeff < (BDW_CSC_COEFF_UNITY_VAL << 1)) {/* abs_coeff >= 1.0 && val < 2.0 */exponent_bits = 7;ls_bit_pos = 23;} else {/* abs_coeff >= 2.0 && val < 4.0 */exponent_bits = 6;ls_bit_pos = 24;}mantissa = GET_BITS_ROUNDOFF(abs_coeff, ls_bit_pos,CSC_MAX_VALS);
if (coeff < 0) {sign_bit = 1;mantissa = -mantissa;mantissa &= ((1 << CSC_MAX_VALS) - 1);I think there is a macro for this already ?
Thats for GAMMA_MAX, not for CSC_MAX. Or you mean the whole (1 << CSC_MAX_VALS -1) to be replaced with GET/SET bits ?
What I mean is - the above looks exactly like the GET_BIT_MASK (which you introduced). Perhaps you can use it ?
Yes, Agree. but in later code review phase we realized that we dont even need this masking for mantissa. New patch set doesnt have this &ing, so we dont need this.
Regards, Emil
On Sat, 2015-10-10 at 00:59 +0530, Shashank Sharma wrote:
BDW/SKL/BXT support Color Space Conversion (CSC) using a 3x3 matrix that needs to be programmed into respective CSC registers.
This patch does the following:
- Adds the core function to program CSC correction values for BDW/SKL/BXT platform
- Adds CSC correction macros/defines
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com Signed-off-by: Kumar, Kiran S kiran.s.kumar@intel.com
drivers/gpu/drm/i915/i915_reg.h | 7 ++ drivers/gpu/drm/i915/intel_color_manager.c | 114 ++++++++++++++++++++++++++++- drivers/gpu/drm/i915/intel_color_manager.h | 12 ++- 3 files changed, 129 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ed50f75..0e9d252 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8085,4 +8085,11 @@ enum skl_disp_power_wells { (_PIPE3(pipe, PAL_PREC_GCMAX_A, PAL_PREC_GCMAX_B, PAL_PREC_GCMAX_C))
+/* BDW CSC correction */ +#define CSC_COEFF_A 0x49010 +#define CSC_COEFF_B 0x49110 +#define CSC_COEFF_C 0x49210 +#define _PIPE_CSC_COEFF(pipe) \
- (_PIPE3(pipe, CSC_COEFF_A, CSC_COEFF_B, CSC_COEFF_C))
#endif /* _I915_REG_H_ */ diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index e659382..0a6c00c 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -330,11 +330,119 @@ static int bdw_set_degamma(struct drm_device *dev, return 0; }
-static s16 chv_prepare_csc_coeff(s64 csc_value) +static uint32_t bdw_prepare_csc_coeff(int64_t coeff) +{
- uint32_t reg_val, ls_bit_pos, exponent_bits, sign_bit = 0;
- int32_t mantissa;
- uint64_t abs_coeff;
- coeff = min_t(int64_t, coeff, BDW_CSC_COEFF_MAX_VAL);
- coeff = max_t(int64_t, coeff, BDW_CSC_COEFF_MIN_VAL);
- abs_coeff = abs(coeff);
- if (abs_coeff < (BDW_CSC_COEFF_UNITY_VAL >> 3)) {
/* abs_coeff < 0.125 */exponent_bits = 3;ls_bit_pos = 19;- } else if (abs_coeff >= (BDW_CSC_COEFF_UNITY_VAL >> 3) &&
abs_coeff < (BDW_CSC_COEFF_UNITY_VAL >> 2)) {/* abs_coeff >= 0.125 && val < 0.25 */exponent_bits = 2;ls_bit_pos = 20;- } else if (abs_coeff >= (BDW_CSC_COEFF_UNITY_VAL >> 2)
&& abs_coeff < (BDW_CSC_COEFF_UNITY_VAL >> 1)) {/* abs_coeff >= 0.25 && val < 0.5 */exponent_bits = 1;ls_bit_pos = 21;- } else if (abs_coeff >= (BDW_CSC_COEFF_UNITY_VAL >> 1)
&& abs_coeff < BDW_CSC_COEFF_UNITY_VAL) {/* abs_coeff >= 0.5 && val < 1.0 */exponent_bits = 0;ls_bit_pos = 22;- } else if (abs_coeff >= BDW_CSC_COEFF_UNITY_VAL &&
abs_coeff < (BDW_CSC_COEFF_UNITY_VAL << 1)) {/* abs_coeff >= 1.0 && val < 2.0 */exponent_bits = 7;ls_bit_pos = 23;- } else {
/* abs_coeff >= 2.0 && val < 4.0 */exponent_bits = 6;ls_bit_pos = 24;- }
- mantissa = GET_BITS_ROUNDOFF(abs_coeff, ls_bit_pos,
CSC_MAX_VALS);
Is GET_BITS_ROUNDOFF safe for negative values?
- if (coeff < 0) {
sign_bit = 1;mantissa = -mantissa;mantissa &= ((1 << CSC_MAX_VALS) - 1);
Oops. It looks like you are reusing the macro/define for the number of coefficients for the size of the mantissa. Also you defined a macro for this very purpose in your other patch.
- }
- reg_val = 0;
- SET_BITS(reg_val, exponent_bits, 12, 3);
- SET_BITS(reg_val, mantissa, 3, 9);
- SET_BITS(reg_val, sign_bit, 15, 1);
- DRM_DEBUG_DRIVER("CSC: reg_val=0x%x\n", reg_val);
This debug message is superfluous as you can easily read register values out with i-g-t.
- return reg_val;
+}
+int bdw_set_csc(struct drm_device *dev, struct drm_property_blob *blob,
struct drm_crtc *crtc)+{
- enum pipe pipe;
- enum plane plane;
- int i, j, temp;
- int word = 0;
- u32 reg, plane_ctl, mode;
- struct drm_ctm *csc_data;
- struct drm_i915_private *dev_priv = dev->dev_private;
- if (WARN_ON(!blob))
return -EINVAL;- if (blob->length != sizeof(struct drm_ctm)) {
DRM_ERROR("Invalid length of data received\n");return -EINVAL;- }
- csc_data = (struct drm_ctm *)blob->data;
- pipe = to_intel_crtc(crtc)->pipe;
- plane = to_intel_crtc(crtc)->plane;
- plane_ctl = I915_READ(PLANE_CTL(pipe, plane));
- plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
- I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
- reg = _PIPE_CSC_COEFF(pipe);
- /* Write csc coeff to csc regs */
- for (i = 0, j = 0; i < CSC_MAX_VALS; i++) {
if ((i % 3) == 0) {temp = bdw_prepare_csc_coeff(csc_data->ctm_coeff[i]);
SET_BITS(word, temp, 16, 16);i++;temp = bdw_prepare_csc_coeff(csc_data->ctm_coeff[i]);
SET_BITS(word, temp, 0, 16);} else {temp = bdw_prepare_csc_coeff(csc_data->ctm_coeff[i]);
SET_BITS(word, temp, 16, 16);}I915_WRITE(reg + j, word);j = j + 4;}
Although this loops looks like it should work, i'm not convinced of it's merits over programming the 5 registers directly. That's a style question for the more experienced kernel folk.
- /* Enable CSC functionality */
- mode = I915_READ(PIPE_CSC_MODE(pipe));
- mode |= CSC_POSITION_BEFORE_GAMMA;
- I915_WRITE(PIPE_CSC_MODE(pipe), mode);
The specs indicate that this value is ignored in split gamma mode, but at the same time say that this register arms the CSC registers above. A comment to that affect might would be helpful.
- DRM_DEBUG_DRIVER("CSC enabled on Pipe %c\n",
pipe_name(pipe));
- return 0;
+}
+static s32 chv_prepare_csc_coeff(s64 csc_value) { s32 csc_int_value; u32 csc_fract_value;
- s16 csc_s3_12_format;
- s32 csc_s3_12_format;
Why is this change in this patch?
if (csc_value >= 0) { csc_value += CHV_CSC_FRACT_ROUNDOFF; @@ -650,6 +758,8 @@ void intel_color_manager_crtc_commit(struct drm_device *dev, /* CSC correction */ if (IS_CHERRYVIEW(dev)) ret = chv_set_csc(dev, blob, crtc);
else if (IS_BROADWELL(dev) || IS_GEN9(dev))ret = bdw_set_csc(dev, blob, crtc);if (ret) DRM_ERROR("set CSC correction failed\n");
diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h index e0c486e..853c73c 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.h +++ b/drivers/gpu/drm/i915/intel_color_manager.h @@ -90,7 +90,15 @@ #define CGM_CSC_EN (1 << 1) #define CGM_DEGAMMA_EN (1 << 0)
-/* Gamma on BDW */ +/* BDW CSC */ +/* 1.0000000 in S31.32 format */ +#define BDW_CSC_COEFF_UNITY_VAL 0x100000000 +/* 3.9921875 in S31.32 format */ +#define BDW_CSC_COEFF_MAX_VAL 0x3FE000000 +/*-4.000000 in S31.32 format */ +#define BDW_CSC_COEFF_MIN_VAL 0xFFFFFFFC00000000
+/* BDW Gamma */
Another change that has nothing to do with CSC.
#define BDW_SPLITGAMMA_MAX_VALS 512 #define BDW_8BIT_GAMMA_MAX_VALS 256 #define BDW_10BIT_GAMMA_MAX_VALS 1024 @@ -99,5 +107,5 @@ #define BDW_INDEX_AUTO_INCREMENT (1 << 15) #define BDW_INDEX_SPLIT_MODE (1 << 31)
-/* Degamma on BDW */ +/* BDW Degamma*/
Ditto.
#define BDW_DEGAMMA_MAX_VALS 512
Rob
dri-devel@lists.freedesktop.org
-
Emil Velikov -
kbuild test robot -
Rob Bradford -
Sharma, Shashank -
Shashank Sharma