Radeon power management restricts the maximum engine clock to the initial default clock. However, on APUs the default clock usually is not the fastest allowed by their defined power states. Change restriction to the fastest engine clock found in power states.

Signed-off-by: Alan Swanson swanson@ukfsn.org --- drivers/gpu/drm/radeon/radeon.h | 1 + drivers/gpu/drm/radeon/radeon_pm.c | 25 ++++++++++++++++++++++--- 2 files changed, 23 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 1442ce7..83d1e76 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -1111,6 +1111,7 @@ struct radeon_pm { u32 default_mclk; u16 default_vddc; u16 default_vddci; + u32 max_sclk; struct radeon_i2c_chan *i2c_bus; /* selected pm method */ enum radeon_pm_method pm_method; diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c index 788c64c..3512af9 100644 --- a/drivers/gpu/drm/radeon/radeon_pm.c +++ b/drivers/gpu/drm/radeon/radeon_pm.c @@ -164,8 +164,8 @@ static void radeon_set_power_state(struct radeon_device *rdev) if (radeon_gui_idle(rdev)) { sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. clock_info[rdev->pm.requested_clock_mode_index].sclk; - if (sclk > rdev->pm.default_sclk) - sclk = rdev->pm.default_sclk; + if (sclk > rdev->pm.max_sclk) + sclk = rdev->pm.max_sclk;

/* starting with BTC, there is one state that is used for both * MH and SH. Difference is that we always use the high clock index for @@ -307,7 +307,7 @@ static void radeon_pm_print_states(struct radeon_device *rdev) DRM_DEBUG_DRIVER("State %d: %s\n", i, radeon_pm_state_type_name[power_state->type]); if (i == rdev->pm.default_power_state_index) - DRM_DEBUG_DRIVER("\tDefault"); + DRM_DEBUG_DRIVER("\tDEFAULT\n"); if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP)) DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes); if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) @@ -329,6 +329,22 @@ static void radeon_pm_print_states(struct radeon_device *rdev) } }

+static void radeon_pm_get_max_clocks(struct radeon_device *rdev) +{ + int i, j; + struct radeon_power_state *power_state; + struct radeon_pm_clock_info *clock_info; + + for (i = 0; i < rdev->pm.num_power_states; i++) { + power_state = &rdev->pm.power_state[i]; + for (j = 0; j < power_state->num_clock_modes; j++) { + clock_info = &(power_state->clock_info[j]); + if (clock_info->sclk > rdev->pm.max_sclk) + rdev->pm.max_sclk = clock_info->sclk; + } + } +} + static ssize_t radeon_get_pm_profile(struct device *dev, struct device_attribute *attr, char *buf) @@ -588,6 +604,7 @@ int radeon_pm_init(struct radeon_device *rdev) rdev->pm.default_mclk = rdev->clock.default_mclk; rdev->pm.current_sclk = rdev->clock.default_sclk; rdev->pm.current_mclk = rdev->clock.default_mclk; + rdev->pm.max_sclk = rdev->clock.default_sclk; rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;

if (rdev->bios) { @@ -597,6 +614,7 @@ int radeon_pm_init(struct radeon_device *rdev) radeon_combios_get_power_modes(rdev); radeon_pm_print_states(rdev); radeon_pm_init_profile(rdev); + radeon_pm_get_max_clocks(rdev); /* set up the default clocks if the MC ucode is loaded */ if ((rdev->family >= CHIP_BARTS) && (rdev->family <= CHIP_CAYMAN) && @@ -848,6 +866,7 @@ static int radeon_debugfs_pm_info(struct seq_file *m, void *data) seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk); else seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev)); + seq_printf(m, "maximum engine clock: %u0 kHz\n", rdev->pm.max_sclk); seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk); if (rdev->asic->pm.get_memory_clock) seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));