The sequence for Source DP PHY CTS automation[1]: 1- Emulate successful Link Training 2- Short HPD and Change link rates and number of lanes 3- Short HPD and Change PHY test pattern and swing/pre-emp levels

With DP PHY CTS setup as follow:

[DPTX + on board LTTPR]------Main Link--->[Scope] ^ | | | | | ----------Aux Ch------>[Aux Emulator]

Writing to LINK_BW_SET on a port that has LTTPR is an indication of the LT start for LTTPR [Check DP 2.0 E11 - Sec 3.6.8.2 & 3.6.8.6.3]. As LTTPR snoops LINK_BW_SET/LANE_COUNT_SET, it will stop sending DP signals to DP Scope causing the measurements to fail.

This can be tested with a monitor connected to LTTPR port by writing to LINK_BW_SET as follow:

igt/tools/dpcd_reg write --offset=0x100 --value 0x14 --device=2

OR

printf '\x14' | sudo dd of=/dev/drm_dp_aux2 bs=1 count=1 conv=notrunc seek=$((0x100))

This single aux write causes the screen to blank, sending short HPD to DPTX, setting LINK_STATUS_UPDATE = 1 in DPCD 0x204, and triggering LT.

However, sending the same aux write on a port without LTTPR (direct port to the monitor) has no effect.

In the case of DP PHY CTS setup described above, the AUX emulator executes a script file of aux transactoins it sends to DPTX. For setting PHY pattern the relevant segment of the script looks like the following: # Set TEST_REQUEST (0x0218): PHY_TEST_PATTERN (0x0218.3) to 1 SetByte 0x218 0 SetBit 0x201 1 SetBit 0x218 3

# Set Test Pattern SetPattern

# Trigger 1ms HPD Pulse HPDPulse 0x06

# Wait For 2 seconds Wait 2000000

MODULEEND

After the aux emulator finish executing the above segment, the scope waits for the required pattern from DPTX to verify it is the right one and perform the measurements. No more aux transactions the AUX emulator will send. So, when DPTX update LINK_BW_SET/LANE_COUNT_SET, the LTTPR will stop the signals on the main link to DPRX/Scope in order to adjust rate and lane count it snooped and will wait for link training to start which will never happen given the script file for aux transactions already finished.

The fix for this issue, is to not rewrite link config that is already done in step 2 by modeset, and just change PHY test patterns and swing/pre-emph levels.

[1]: LTTPR Re-timer PHY test procedure proposal https://groups.vesa.org/wg/Link/document/16521

Cc: Imre Deak imre.deak@intel.com Cc: Jani Nikula jani.nikula@intel.com Signed-off-by: Khaled Almahallawy khaled.almahallawy@intel.com --- drivers/gpu/drm/dp/drm_dp.c | 9 --------- 1 file changed, 9 deletions(-)

diff --git a/drivers/gpu/drm/dp/drm_dp.c b/drivers/gpu/drm/dp/drm_dp.c index 580016a1b9eb..f72d48e59b89 100644 --- a/drivers/gpu/drm/dp/drm_dp.c +++ b/drivers/gpu/drm/dp/drm_dp.c @@ -2613,17 +2613,8 @@ int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux, struct drm_dp_phy_test_params *data, u8 dp_rev) { int err, i; - u8 link_config[2]; u8 test_pattern;

- link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate); - link_config[1] = data->num_lanes; - if (data->enhanced_frame_cap) - link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; - err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2); - if (err < 0) - return err; - test_pattern = data->phy_pattern; if (dp_rev < 0x12) { test_pattern = (test_pattern << 2) &