Enabling pcie gen2 speed was skipped for Northern Islands AISCs, although it looks like it works just fine with the same initialization sequence used for evergreen.
According to Alex D. gen2 init was skipped to prevent a crash that has been caused by some other bug that has been fixed in the meantime; so now it should be safe to enable it.
Signed-off-by: Ilija Hadzic ihadzic@research.bell-labs.com --- drivers/gpu/drm/radeon/evergreen.c | 3 +-- 1 files changed, 1 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index f09bace..208b59c 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -2987,8 +2987,7 @@ static int evergreen_startup(struct radeon_device *rdev) int r;
/* enable pcie gen2 link */ - if (!ASIC_IS_DCE5(rdev)) - evergreen_pcie_gen2_enable(rdev); + evergreen_pcie_gen2_enable(rdev);
if (ASIC_IS_DCE5(rdev)) { if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
Looks like the same pcie gen2 speed initialization for Evergreen also works on Cayman and seems to come up fine, so enable it if the module parameter says so
Signed-off-by: Ilija Hadzic ihadzic@research.bell-labs.com --- drivers/gpu/drm/radeon/evergreen.c | 4 ++-- drivers/gpu/drm/radeon/ni.c | 4 ++++ 2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 208b59c..d843a57 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -39,7 +39,7 @@
static void evergreen_gpu_init(struct radeon_device *rdev); void evergreen_fini(struct radeon_device *rdev); -static void evergreen_pcie_gen2_enable(struct radeon_device *rdev); +void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc) { @@ -3233,7 +3233,7 @@ void evergreen_fini(struct radeon_device *rdev) rdev->bios = NULL; }
-static void evergreen_pcie_gen2_enable(struct radeon_device *rdev) +void evergreen_pcie_gen2_enable(struct radeon_device *rdev) { u32 link_width_cntl, speed_cntl;
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c index 2a7bdf1..38205ef 100644 --- a/drivers/gpu/drm/radeon/ni.c +++ b/drivers/gpu/drm/radeon/ni.c @@ -39,6 +39,7 @@ extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev); extern void evergreen_mc_program(struct radeon_device *rdev); extern void evergreen_irq_suspend(struct radeon_device *rdev); extern int evergreen_mc_init(struct radeon_device *rdev); +extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
#define EVERGREEN_PFP_UCODE_SIZE 1120 #define EVERGREEN_PM4_UCODE_SIZE 1376 @@ -1378,6 +1379,9 @@ static int cayman_startup(struct radeon_device *rdev) { int r;
+ /* enable pcie gen2 link */ + evergreen_pcie_gen2_enable(rdev); + if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { r = ni_init_microcode(rdev); if (r) {
On Tue, Sep 20, 2011 at 10:22 AM, Ilija Hadzic ihadzic@research.bell-labs.com wrote:
Enabling pcie gen2 speed was skipped for Northern Islands AISCs, although it looks like it works just fine with the same initialization sequence used for evergreen.
According to Alex D. gen2 init was skipped to prevent a crash that has been caused by some other bug that has been fixed in the meantime; so now it should be safe to enable it.
Signed-off-by: Ilija Hadzic ihadzic@research.bell-labs.com
I just double checked and BTC and cayman use the same programming method. Both patches:
Reviewed-by: Alex Deucher alexander.deucher@amd.com
Thanks!
Alex
drivers/gpu/drm/radeon/evergreen.c | 3 +-- 1 files changed, 1 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index f09bace..208b59c 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -2987,8 +2987,7 @@ static int evergreen_startup(struct radeon_device *rdev) int r;
/* enable pcie gen2 link */
- if (!ASIC_IS_DCE5(rdev))
- evergreen_pcie_gen2_enable(rdev);
- evergreen_pcie_gen2_enable(rdev);
if (ASIC_IS_DCE5(rdev)) { if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { -- 1.7.6
dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
Hi Dave,
A few weeks ago I sent the two patches that allow PCI Express interface to run at Gen 2 speed on NI parts. Links to the patches in the mailing list archive + review from Alex quoted below:
http://lists.freedesktop.org/archives/dri-devel/2011-September/014474.html http://lists.freedesktop.org/archives/dri-devel/2011-September/014475.html
I saw some activity on drm-next and drm-core-next branches, but I have not seen these two patches merge yet. Just wondering if they are in the queue for merging or if they may have fell through the cracks?
thanks,
Ilija
On Tue, 20 Sep 2011, Alex Deucher wrote:
On Tue, Sep 20, 2011 at 10:22 AM, Ilija Hadzic ihadzic@research.bell-labs.com wrote:
Enabling pcie gen2 speed was skipped for Northern Islands AISCs, although it looks like it works just fine with the same initialization sequence used for evergreen.
According to Alex D. gen2 init was skipped to prevent a crash that has been caused by some other bug that has been fixed in the meantime; so now it should be safe to enable it.
Signed-off-by: Ilija Hadzic ihadzic@research.bell-labs.com
I just double checked and BTC and cayman use the same programming method. Both patches:
Reviewed-by: Alex Deucher alexander.deucher@amd.com
Thanks!
Alex
drivers/gpu/drm/radeon/evergreen.c | 3 +-- 1 files changed, 1 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index f09bace..208b59c 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -2987,8 +2987,7 @@ static int evergreen_startup(struct radeon_device *rdev) int r;
/* enable pcie gen2 link */
- if (!ASIC_IS_DCE5(rdev))
- evergreen_pcie_gen2_enable(rdev);
- evergreen_pcie_gen2_enable(rdev);
if (ASIC_IS_DCE5(rdev)) { if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { -- 1.7.6
dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
On Wed, Oct 12, 2011 at 2:25 PM, Ilija Hadzic ihadzic@research.bell-labs.com wrote:
Hi Dave,
A few weeks ago I sent the two patches that allow PCI Express interface to run at Gen 2 speed on NI parts. Links to the patches in the mailing list archive + review from Alex quoted below:
http://lists.freedesktop.org/archives/dri-devel/2011-September/014474.html http://lists.freedesktop.org/archives/dri-devel/2011-September/014475.html
I saw some activity on drm-next and drm-core-next branches, but I have not seen these two patches merge yet. Just wondering if they are in the queue for merging or if they may have fell through the cracks?
/me misses patchwork a lot.
I've picked them up now.
Thanks, Dave.
dri-devel@lists.freedesktop.org
-
Alex Deucher -
Dave Airlie -
Ilija Hadzic