Hi,

I had some minor comments. Sorry about sharing this late. Otherwise, the looks good to me.

On 02/26/2016 02:10 PM, Xinliang Liu wrote:

Add kirin DRM master driver for hi6220 SoC which used in HiKey board. Add dumb buffer feature. Add prime dmabuf feature.

v6: None. v5: None. v4: None. v3:

• Move and rename all the files to kirin sub-directory. So that we could separate different seires SoCs' driver.
• Replace drm_platform_init, load, unload implementation.

v2:

• Remove abtraction layer.

Signed-off-by: Xinliang Liu xinliang.liu@linaro.org

drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/hisilicon/Kconfig | 5 + drivers/gpu/drm/hisilicon/Makefile | 5 + drivers/gpu/drm/hisilicon/kirin/Kconfig | 9 + drivers/gpu/drm/hisilicon/kirin/Makefile | 3 + drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c | 321 ++++++++++++++++++++++++ drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h | 20 ++ 8 files changed, 366 insertions(+) create mode 100644 drivers/gpu/drm/hisilicon/Kconfig create mode 100644 drivers/gpu/drm/hisilicon/Makefile create mode 100644 drivers/gpu/drm/hisilicon/kirin/Kconfig create mode 100644 drivers/gpu/drm/hisilicon/kirin/Makefile create mode 100644 drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c create mode 100644 drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index b50ae60f5f50..f5c5656e2547 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -277,3 +277,5 @@ source "drivers/gpu/drm/imx/Kconfig" source "drivers/gpu/drm/vc4/Kconfig"

source "drivers/gpu/drm/etnaviv/Kconfig"

+source "drivers/gpu/drm/hisilicon/Kconfig" diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 61766dec6a8d..60554832079c 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -74,3 +74,4 @@ obj-y += panel/ obj-y += bridge/ obj-$(CONFIG_DRM_FSL_DCU) += fsl-dcu/ obj-$(CONFIG_DRM_ETNAVIV) += etnaviv/ +obj-y += hisilicon/ diff --git a/drivers/gpu/drm/hisilicon/Kconfig b/drivers/gpu/drm/hisilicon/Kconfig new file mode 100644 index 000000000000..558c61b1b8e8 --- /dev/null +++ b/drivers/gpu/drm/hisilicon/Kconfig @@ -0,0 +1,5 @@ +# +# hisilicon drm device configuration. +# Please keep this list sorted alphabetically

+source "drivers/gpu/drm/hisilicon/kirin/Kconfig" diff --git a/drivers/gpu/drm/hisilicon/Makefile b/drivers/gpu/drm/hisilicon/Makefile new file mode 100644 index 000000000000..e3f6d493c996 --- /dev/null +++ b/drivers/gpu/drm/hisilicon/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for hisilicon drm drivers. +# Please keep this list sorted alphabetically

+obj-$(CONFIG_DRM_HISI_KIRIN) += kirin/ diff --git a/drivers/gpu/drm/hisilicon/kirin/Kconfig b/drivers/gpu/drm/hisilicon/kirin/Kconfig new file mode 100644 index 000000000000..3ac4b8edeac1 --- /dev/null +++ b/drivers/gpu/drm/hisilicon/kirin/Kconfig @@ -0,0 +1,9 @@ +config DRM_HISI_KIRIN

• tristate "DRM Support for Hisilicon Kirin series SoCs Platform"
• depends on DRM
• select DRM_KMS_HELPER
• select DRM_GEM_CMA_HELPER
• select DRM_KMS_CMA_HELPER
• help

•  Choose this option if you have a hisilicon Kirin chipsets(hi6220).
  

•  If M is selected the module will be called kirin-drm.
  

diff --git a/drivers/gpu/drm/hisilicon/kirin/Makefile b/drivers/gpu/drm/hisilicon/kirin/Makefile new file mode 100644 index 000000000000..cb346de47d48 --- /dev/null +++ b/drivers/gpu/drm/hisilicon/kirin/Makefile @@ -0,0 +1,3 @@ +kirin-drm-y := kirin_drm_drv.o

+obj-$(CONFIG_DRM_HISI_KIRIN) += kirin-drm.o diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c new file mode 100644 index 000000000000..789ebd1f5922 --- /dev/null +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c @@ -0,0 +1,321 @@ +/*

• • Hisilicon Kirin SoCs drm master driver
• • Copyright (c) 2016 Linaro Limited.
• • Copyright (c) 2014-2016 Hisilicon Limited.
• • Author:
• • Xinliang Liu z.liuxinliang@hisilicon.com
• • Xinliang Liu xinliang.liu@linaro.org
• • Xinwei Kong kong.kongxinwei@hisilicon.com
• • This program is free software; you can redistribute it and/or modify
• • it under the terms of the GNU General Public License version 2 as
• • published by the Free Software Foundation.
• */

+#include <linux/of_platform.h> +#include <linux/component.h> +#include <linux/of_graph.h>

+#include <drm/drmP.h> +#include <drm/drm_gem_cma_helper.h> +#include <drm/drm_fb_cma_helper.h> +#include <drm/drm_atomic_helper.h>

+#include "kirin_drm_drv.h"

+static struct kirin_dc_ops *dc_ops;

+static int kirin_drm_kms_cleanup(struct drm_device *dev) +{

• dc_ops->cleanup(dev);
• drm_mode_config_cleanup(dev);
• return 0;

+}

+static const struct drm_mode_config_funcs kirin_drm_mode_config_funcs = {

• .fb_create = drm_fb_cma_create,
• .atomic_check = drm_atomic_helper_check,
• .atomic_commit = drm_atomic_helper_commit,

+};

+static void kirin_drm_mode_config_init(struct drm_device *dev) +{

• dev->mode_config.min_width = 0;
• dev->mode_config.min_height = 0;
• dev->mode_config.max_width = 2048;
• dev->mode_config.max_height = 2048;
• dev->mode_config.funcs = &kirin_drm_mode_config_funcs;

+}

+static int kirin_drm_kms_init(struct drm_device *dev) +{

• int ret;
• dev_set_drvdata(dev->dev, dev);
• /* dev->mode_config initialization */
• drm_mode_config_init(dev);
• kirin_drm_mode_config_init(dev);
• /* display controller init */
• ret = dc_ops->init(dev);
• if (ret)

• goto err_mode_config_cleanup;
  

• /* bind and init sub drivers */
• ret = component_bind_all(dev->dev, dev);
• if (ret) {

• DRM_ERROR("failed to bind all component.\n");
  

• goto err_dc_cleanup;
  

• }
• /* reset all the states of crtc/plane/encoder/connector */
• drm_mode_config_reset(dev);
• return 0;

+err_dc_cleanup:

• dc_ops->cleanup(dev);

+err_mode_config_cleanup:

• drm_mode_config_cleanup(dev);
• return ret;

+}

+static const struct file_operations kirin_drm_fops = {

• .owner = THIS_MODULE,
• .open = drm_open,
• .release = drm_release,
• .unlocked_ioctl = drm_ioctl,

+#ifdef CONFIG_COMPAT

• .compat_ioctl = drm_compat_ioctl,

+#endif

• .poll = drm_poll,
• .read = drm_read,
• .llseek = no_llseek,
• .mmap = drm_gem_cma_mmap,

+};

+static int kirin_gem_cma_dumb_create(struct drm_file *file,

• 		     struct drm_device *dev,
  

• 		     struct drm_mode_create_dumb *args)
  

+{

• return drm_gem_cma_dumb_create_internal(file, dev, args);

+}

+static struct drm_driver kirin_drm_driver = {

• .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME |

• 		  DRIVER_ATOMIC,
  

• .fops = &kirin_drm_fops,
• .set_busid = drm_platform_set_busid,
• .gem_free_object = drm_gem_cma_free_object,
• .gem_vm_ops = &drm_gem_cma_vm_ops,
• .dumb_create = kirin_gem_cma_dumb_create,
• .dumb_map_offset = drm_gem_cma_dumb_map_offset,
• .dumb_destroy = drm_gem_dumb_destroy,
• .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
• .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
• .gem_prime_export = drm_gem_prime_export,
• .gem_prime_import = drm_gem_prime_import,
• .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
• .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
• .gem_prime_vmap = drm_gem_cma_prime_vmap,
• .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
• .gem_prime_mmap = drm_gem_cma_prime_mmap,
• .name = "kirin",
• .desc = "Hisilicon Kirin SoCs' DRM Driver",
• .date = "20150718",
• .major = 1,
• .minor = 0,

+};

+static int compare_of(struct device *dev, void *data) +{

• return dev->of_node == data;

+}

+static int kirin_drm_connectors_register(struct drm_device *dev) +{

• struct drm_connector *connector;
• struct drm_connector *failed_connector;
• int ret;

This access needs to be protected by the dev->mode_config.mutex

• list_for_each_entry(connector, &dev->mode_config.connector_list, head) {

The above can be replaced with:

drm_for_each_connector(connector, dev) {

• ret = drm_connector_register(connector);
  

• if (ret) {
  

• 	failed_connector = connector;
  

• 	goto err;
  

• }
  

• }
• return 0;

+err:

• list_for_each_entry(connector, &dev->mode_config.connector_list, head) {

• if (failed_connector == connector)
  

• 	break;
  

• drm_connector_unregister(connector);
  

• }

Same points as above.

• return ret;

+}

+static int kirin_drm_bind(struct device *dev) +{

• struct drm_driver *driver = &kirin_drm_driver;
• struct drm_device *drm_dev;
• int ret;
• drm_dev = drm_dev_alloc(driver, dev);
• if (!drm_dev)

• return -ENOMEM;
  

• drm_dev->platformdev = to_platform_device(dev);
• ret = kirin_drm_kms_init(drm_dev);
• if (ret)

• goto err_drm_dev_unref;
  

• ret = drm_dev_register(drm_dev, 0);
• if (ret)

• goto err_kms_cleanup;
  

• /* connectors should be registered after drm device register */
• ret = kirin_drm_connectors_register(drm_dev);
• if (ret)

• goto err_drm_dev_unregister;
  

• DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n",

•  driver->name, driver->major, driver->minor, driver->patchlevel,
  

•  driver->date, drm_dev->primary->index);
  

• return 0;

+err_drm_dev_unregister:

• drm_dev_unregister(drm_dev);

+err_kms_cleanup:

• kirin_drm_kms_cleanup(drm_dev);

+err_drm_dev_unref:

• drm_dev_unref(drm_dev);
• return ret;

+}

+static void kirin_drm_unbind(struct device *dev) +{

• drm_put_dev(dev_get_drvdata(dev));

+}

+static const struct component_master_ops kirin_drm_ops = {

• .bind = kirin_drm_bind,
• .unbind = kirin_drm_unbind,

+};

+static const struct of_device_id kirin_drm_dt_ids[] = {

• { /* end node */ },

+}; +MODULE_DEVICE_TABLE(of, kirin_drm_dt_ids);

+static int kirin_get_dc_ops(struct device_node *np) +{

• const struct of_device_id *match_id;
• match_id = of_match_node(kirin_drm_dt_ids, np);
• if (!match_id) {

• DRM_ERROR("failed to match dt id\n");
  

• return -EINVAL;
  

• }
• dc_ops = (struct kirin_dc_ops *)match_id->data;
• if (!dc_ops) {

• DRM_ERROR("dt id data is null\n");
  

• return -EINVAL;
  

• }

We can use of_device_get_match_data to get the match data, and move the kirin_drm_dt_ids table down where the driver is defined.

<snip>

Thanks, Archit

Hi,

On 1 March 2016 at 02:48, Archit Taneja architt@codeaurora.org wrote:

On 2/26/2016 2:10 PM, Xinliang Liu wrote:

...

Add crtc funcs and helper funcs for ADE.

v6:

• Cleanup reg-names dt parsing.

v5:

• Use syscon to access ADE media NOC QoS registers instread of directly writing registers.
• Use reset controller to reset ADE instead of directly writing registers.

v4: None. v3:

• Make ade as the master driver.
• Use port to connect with encoder.
• A few cleanup.

v2:

• Remove abtraction layer.

Signed-off-by: Xinliang Liu xinliang.liu@linaro.org

drivers/gpu/drm/hisilicon/kirin/Makefile | 3 +- drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h | 290 +++++++++++++++ drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 452 ++++++++++++++++++++++++ drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c | 15 + drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h | 8 + 5 files changed, 767 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h create mode 100644 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c

diff --git a/drivers/gpu/drm/hisilicon/kirin/Makefile b/drivers/gpu/drm/hisilicon/kirin/Makefile index cb346de47d48..2a61ab006ddb 100644 --- a/drivers/gpu/drm/hisilicon/kirin/Makefile +++ b/drivers/gpu/drm/hisilicon/kirin/Makefile @@ -1,3 +1,4 @@ -kirin-drm-y := kirin_drm_drv.o +kirin-drm-y := kirin_drm_drv.o \

•          kirin_drm_ade.o
  
  

  obj-$(CONFIG_DRM_HISI_KIRIN) += kirin-drm.o

diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h b/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h new file mode 100644 index 000000000000..eb444b899c7b --- /dev/null +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h @@ -0,0 +1,290 @@ +/*

• • Copyright (c) 2016 Linaro Limited.
• • Copyright (c) 2014-2016 Hisilicon Limited.
• • This program is free software; you can redistribute it and/or modify
• • it under the terms of the GNU General Public License version 2 as
• • published by the Free Software Foundation.
• */

+#ifndef __KIRIN_ADE_REG_H__ +#define __KIRIN_ADE_REG_H__

+/*

• • ADE Registers
• */

+#define MASK(x) (BIT(x) - 1)

+#define ADE_CTRL 0x0004 +#define FRM_END_START_OFST 0 +#define FRM_END_START_MASK MASK(2) +#define ADE_CTRL1 0x008C +#define AUTO_CLK_GATE_EN_OFST 0 +#define AUTO_CLK_GATE_EN BIT(0) +#define ADE_ROT_SRC_CFG 0x0010 +#define ADE_DISP_SRC_CFG 0x0018 +#define ADE_WDMA2_SRC_CFG 0x001C +#define ADE_SEC_OVLY_SRC_CFG 0x0020 +#define ADE_WDMA3_SRC_CFG 0x0024 +#define ADE_OVLY1_TRANS_CFG 0x002C +#define ADE_EN 0x0100 +#define ADE_DISABLE 0 +#define ADE_ENABLE 1 +#define INTR_MASK_CPU(x) (0x0C10 + (x) * 0x4) +#define ADE_FRM_DISGARD_CTRL 0x00A4 +/* reset and reload regs */ +#define ADE_SOFT_RST_SEL(x) (0x0078 + (x) * 0x4) +#define ADE_RELOAD_DIS(x) (0x00AC + (x) * 0x4) +#define RDMA_OFST 0 +#define CLIP_OFST 15 +#define SCL_OFST 21 +#define CTRAN_OFST 24 +#define OVLY_OFST 37 /* 32+5 */ +/* channel regs */ +#define RD_CH_PE(x) (0x1000 + (x) * 0x80) +#define RD_CH_CTRL(x) (0x1004 + (x) * 0x80) +#define RD_CH_ADDR(x) (0x1008 + (x) * 0x80) +#define RD_CH_SIZE(x) (0x100C + (x) * 0x80) +#define RD_CH_STRIDE(x) (0x1010 + (x) * 0x80) +#define RD_CH_SPACE(x) (0x1014 + (x) * 0x80) +#define RD_CH_PARTIAL_SIZE(x) (0x1018 + (x) * 0x80) +#define RD_CH_PARTIAL_SPACE(x) (0x101C + (x) * 0x80) +#define RD_CH_EN(x) (0x1020 + (x) * 0x80) +#define RD_CH_STATUS(x) (0x1024 + (x) * 0x80) +#define RD_CH_DISP_CTRL 0x1404 +#define RD_CH_DISP_ADDR 0x1408 +#define RD_CH_DISP_SIZE 0x140C +#define RD_CH_DISP_STRIDE 0x1410 +#define RD_CH_DISP_SPACE 0x1414 +#define RD_CH_DISP_EN 0x142C +/* clip regs */ +#define ADE_CLIP_DISABLE(x) (0x6800 + (x) * 0x100) +#define ADE_CLIP_SIZE0(x) (0x6804 + (x) * 0x100) +#define ADE_CLIP_SIZE1(x) (0x6808 + (x) * 0x100) +#define ADE_CLIP_SIZE2(x) (0x680C + (x) * 0x100) +#define ADE_CLIP_CFG_OK(x) (0x6810 + (x) * 0x100) +/* scale regs */ +#define ADE_SCL1_MUX_CFG 0x000C +#define ADE_SCL2_SRC_CFG 0x0014 +#define ADE_SCL3_MUX_CFG 0x0008 +#define ADE_SCL_CTRL(x) (0x3000 + (x) * 0x800) +#define ADE_SCL_HSP(x) (0x3004 + (x) * 0x800) +#define ADE_SCL_UV_HSP(x) (0x3008 + (x) * 0x800) +#define ADE_SCL_VSP(x) (0x300C + (x) * 0x800) +#define ADE_SCL_UV_VSP(x) (0x3010 + (x) * 0x800) +#define ADE_SCL_ORES(x) (0x3014 + (x) * 0x800) +#define ADE_SCL_IRES(x) (0x3018 + (x) * 0x800) +#define ADE_SCL_START(x) (0x301C + (x) * 0x800) +#define ADE_SCL_ERR(x) (0x3020 + (x) * 0x800) +#define ADE_SCL_PIX_OFST(x) (0x3024 + (x) * 0x800) +#define ADE_SCL_UV_PIX_OFST(x) (0x3028 + (x) * 0x800) +#define ADE_SCL_COEF_CLR(x) (0x3030 + (x) * 0x800) +#define ADE_SCL_HCOEF(x, m, n) (0x3100 + (x) * 0x800 + \

•                                   12 * (m) + 4 * (n))
  

+#define ADE_SCL_VCOEF(x, i, j) (0x340C + (x) * 0x800 + \

•                                   12 * (i) + 4 * (j))
  

+/* ctran regs */ +#define ADE_CTRAN5_TRANS_CFG 0x0040 +#define ADE_CTRAN_DIS(x) (0x5004 + (x) * 0x100) +#define CTRAN_BYPASS_ON 1 +#define CTRAN_BYPASS_OFF 0 +#define ADE_CTRAN_MODE_CHOOSE(x) (0x5008 + (x) * 0x100) +#define ADE_CTRAN_STAT(x) (0x500C + (x) * 0x100) +#define ADE_CTRAN_CHDC0(x) (0x5010 + (x) * 0x100) +#define ADE_CTRAN_CHDC1(x) (0x5014 + (x) * 0x100) +#define ADE_CTRAN_CHDC2(x) (0x5018 + (x) * 0x100) +#define ADE_CTRAN_CHDC3(x) (0x501C + (x) * 0x100) +#define ADE_CTRAN_CHDC4(x) (0x5020 + (x) * 0x100) +#define ADE_CTRAN_CHDC5(x) (0x5024 + (x) * 0x100) +#define ADE_CTRAN_CSC0(x) (0x5028 + (x) * 0x100) +#define ADE_CTRAN_CSC1(x) (0x502C + (x) * 0x100) +#define ADE_CTRAN_CSC2(x) (0x5030 + (x) * 0x100) +#define ADE_CTRAN_CSC3(x) (0x5034 + (x) * 0x100) +#define ADE_CTRAN_CSC4(x) (0x5038 + (x) * 0x100) +#define ADE_CTRAN_IMAGE_SIZE(x) (0x503C + (x) * 0x100) +#define ADE_CTRAN_CFG_OK(x) (0x5040 + (x) * 0x100) +/* overlay regs */ +#define ADE_OVLY_ALPHA_ST 0x2000 +#define ADE_OVLY_CH_XY0(x) (0x2004 + (x) * 4) +#define ADE_OVLY_CH_XY1(x) (0x2024 + (x) * 4) +#define ADE_OVLY_CH_CTL(x) (0x204C + (x) * 4) +#define ADE_OVLY_OUTPUT_SIZE(x) (0x2070 + (x) * 8) +#define OUTPUT_XSIZE_OFST 16 +#define ADE_OVLY_BASE_COLOR(x) (0x2074 + (x) * 8) +#define ADE_OVLYX_CTL(x) (0x209C + (x) * 4) +#define ADE_OVLY_CTL 0x0098 +#define CH_OVLY_SEL_OFST(x) ((x) * 4) +#define CH_OVLY_SEL_MASK MASK(2) +#define CH_OVLY_SEL_VAL(x) ((x) + 1) +#define CH_ALP_MODE_OFST 0 +#define CH_ALP_SEL_OFST 2 +#define CH_UNDER_ALP_SEL_OFST 4 +#define CH_EN_OFST 6 +#define CH_ALP_GBL_OFST 15 +#define CH_SEL_OFST 28

+/*

• • LDI Registers
• */

+#define LDI_HRZ_CTRL0 0x7400 +#define HBP_OFST 20 +#define LDI_HRZ_CTRL1 0x7404 +#define LDI_VRT_CTRL0 0x7408 +#define VBP_OFST 20 +#define LDI_VRT_CTRL1 0x740C +#define LDI_PLR_CTRL 0x7410 +#define FLAG_NVSYNC BIT(0) +#define FLAG_NHSYNC BIT(1) +#define FLAG_NPIXCLK BIT(2) +#define FLAG_NDE BIT(3) +#define LDI_DSP_SIZE 0x7414 +#define VSIZE_OFST 20 +#define LDI_INT_EN 0x741C +#define FRAME_END_INT_EN_OFST 1 +#define LDI_CTRL 0x7420 +#define BPP_OFST 3 +#define DATA_GATE_EN BIT(2) +#define LDI_EN BIT(0) +#define LDI_ORG_INT 0x7424 +#define LDI_MSK_INT 0x7428 +#define LDI_INT_CLR 0x742C +#define LDI_WORK_MODE 0x7430 +#define LDI_DE_SPACE_LOW 0x7438 +#define LDI_MCU_INTS 0x7450 +#define LDI_MCU_INTE 0x7454 +#define LDI_MCU_INTC 0x7458 +#define LDI_HDMI_DSI_GT 0x7434

Maybe place this one after LDI_WORK_MODE to maintain the increasing order?

Agree, will fix in next version.

...

+/*

• • ADE media bus service regs
• */

+#define ADE0_QOSGENERATOR_MODE 0x010C +#define QOSGENERATOR_MODE_MASK MASK(2) +#define ADE0_QOSGENERATOR_EXTCONTROL 0x0118 +#define SOCKET_QOS_EN BIT(0) +#define ADE1_QOSGENERATOR_MODE 0x020C +#define ADE1_QOSGENERATOR_EXTCONTROL 0x0218

+/*

• • ADE regs relevant enums
• */

+enum frame_end_start {

•   /* regs take effective in every vsync */
  

s/effective/effect

will fix in next version.

...

•   REG_EFFECTIVE_IN_VSYNC = 0,
  

•   /* regs take effective in fist ade en and every frame end */
  

•   REG_EFFECTIVE_IN_ADEEN_FRMEND,
  

•   /* regs take effective in ade en immediately */
  

•   REG_EFFECTIVE_IN_ADEEN,
  

•   /* regs take effective in first vsync and every frame end */
  

•   REG_EFFECTIVE_IN_VSYNC_FRMEND
  

+};

+enum ade_fb_format {

•   ADE_RGB_565 = 0,
  

•   ADE_BGR_565,
  

•   ADE_XRGB_8888,
  

•   ADE_XBGR_8888,
  

•   ADE_ARGB_8888,
  

•   ADE_ABGR_8888,
  

•   ADE_RGBA_8888,
  

•   ADE_BGRA_8888,
  

•   ADE_RGB_888,
  

•   ADE_BGR_888 = 9,
  

•   ADE_FORMAT_NOT_SUPPORT = 800
  

ADE_FORMAT_UNSUPPORTED would be better here.

Agree, will fix in next version.

...

+};

+enum ade_channel {

•   ADE_CH1 = 0,    /* channel 1 for primary plane */
  

•   ADE_CH_NUM
  

+};

+enum ade_scale {

•   ADE_SCL1 = 0,
  

•   ADE_SCL2,
  

•   ADE_SCL3,
  

•   ADE_SCL_NUM
  

+};

+enum ade_ctran {

•   ADE_CTRAN1 = 0,
  

•   ADE_CTRAN2,
  

•   ADE_CTRAN3,
  

•   ADE_CTRAN4,
  

•   ADE_CTRAN5,
  

•   ADE_CTRAN6,
  

•   ADE_CTRAN_NUM
  

+};

+enum ade_overlay {

•   ADE_OVLY1 = 0,
  

•   ADE_OVLY2,
  

•   ADE_OVLY3,
  

•   ADE_OVLY_NUM
  

+};

+enum ade_alpha_mode {

•   ADE_ALP_GLOBAL = 0,
  

•   ADE_ALP_PIXEL,
  

•   ADE_ALP_PIXEL_AND_GLB
  

+};

+enum ade_alpha_blending_mode {

•   ADE_ALP_MUL_COEFF_0 = 0,        /* alpha */
  

•   ADE_ALP_MUL_COEFF_1,            /* 1-alpha */
  

•   ADE_ALP_MUL_COEFF_2,            /* 0 */
  

•   ADE_ALP_MUL_COEFF_3             /* 1 */
  

+};

+/*

• • LDI regs relevant enums
• */

+enum dsi_pclk_en {

•   DSI_PCLK_ON = 0,
  

•   DSI_PCLK_OFF
  

+};

+enum ldi_output_format {

•   LDI_OUT_RGB_565 = 0,
  

•   LDI_OUT_RGB_666,
  

•   LDI_OUT_RGB_888
  

+};

+enum ldi_work_mode {

•   TEST_MODE = 0,
  

•   NORMAL_MODE
  

+};

+enum ldi_input_source {

•   DISP_SRC_NONE = 0,
  

•   DISP_SRC_OVLY2,
  

•   DISP_SRC_DISP,
  

•   DISP_SRC_ROT,
  

•   DISP_SRC_SCL2
  

+};

+/*

• • ADE media bus service relevant enums
• */

+enum qos_generator_mode {

•   FIXED_MODE = 0,
  

•   LIMITER_MODE,
  

•   BYPASS_MODE,
  

•   REGULATOR_MODE
  

+};

+/*

• • Register Write/Read Helper functions
• */

+static inline void ade_update_bits(void __iomem *addr, u32 bit_start,

•                              u32 mask, u32 val)
  

+{

•   u32 tmp, orig;
  

•   orig = readl(addr);
  

•   tmp = orig & ~(mask << bit_start);
  

•   tmp |= (val & mask) << bit_start;
  

•   writel(tmp, addr);
  

+}

+#endif diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c new file mode 100644 index 000000000000..bb93616dcf3d --- /dev/null +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c @@ -0,0 +1,452 @@ +/*

• • Hisilicon Hi6220 SoC ADE(Advanced Display Engine)'s crtc&plane driver
• • Copyright (c) 2016 Linaro Limited.
• • Copyright (c) 2014-2016 Hisilicon Limited.
• • Author:

• • Xinliang Liu <z.liuxinliang@hisilicon.com>
    

• • Xinliang Liu <xinliang.liu@linaro.org>
    

• • Xinwei Kong <kong.kongxinwei@hisilicon.com>
    

• • This program is free software; you can redistribute it and/or modify
• • it under the terms of the GNU General Public License version 2 as
• • published by the Free Software Foundation.
• */

+#include <linux/bitops.h> +#include <linux/clk.h> +#include <video/display_timing.h> +#include <linux/mfd/syscon.h> +#include <linux/regmap.h> +#include <linux/reset.h>

+#include <drm/drmP.h> +#include <drm/drm_crtc.h> +#include <drm/drm_crtc_helper.h> +#include <drm/drm_atomic.h> +#include <drm/drm_atomic_helper.h>

+#include "kirin_drm_drv.h" +#include "kirin_ade_reg.h"

+#define to_ade_crtc(crtc) \

•   container_of(crtc, struct ade_crtc, base)
  

+struct ade_hw_ctx {

•   void __iomem  *base;
  

•   struct regmap *noc_regmap;
  

•   struct clk *ade_core_clk;
  

•   struct clk *media_noc_clk;
  

•   struct clk *ade_pix_clk;
  

•   struct reset_control *reset;
  

•   bool power_on;
  

•   int irq;
  

+};

+struct ade_crtc {

•   struct drm_crtc base;
  

•   struct ade_hw_ctx *ctx;
  

•   bool enable;
  

•   u32 out_format;
  

+};

+struct ade_data {

•   struct ade_crtc acrtc;
  

•   struct ade_hw_ctx ctx;
  

+};

+static void ade_update_reload_bit(void __iomem *base, u32 bit_num, u32 val) +{

•   u32 bit_ofst, reg_num;
  

•   bit_ofst = bit_num % 32;
  

•   reg_num = bit_num / 32;
  

•   ade_update_bits(base + ADE_RELOAD_DIS(reg_num), bit_ofst,
  

•                   MASK(1), !!val);
  

+}

+static u32 ade_read_reload_bit(void __iomem *base, u32 bit_num) +{

•   u32 tmp, bit_ofst, reg_num;
  

•   bit_ofst = bit_num % 32;
  

•   reg_num = bit_num / 32;
  

•   tmp = readl(base + ADE_RELOAD_DIS(reg_num));
  

•   return !!(BIT(bit_ofst) & tmp);
  

+}

+static void ade_init(struct ade_hw_ctx *ctx) +{

•   void __iomem *base = ctx->base;
  

•   /* enable clk gate */
  

•   ade_update_bits(base + ADE_CTRL1, AUTO_CLK_GATE_EN_OFST,
  

•                   AUTO_CLK_GATE_EN, ADE_ENABLE);
  

•   /* clear overlay */
  

•   writel(0, base + ADE_OVLY1_TRANS_CFG);
  

•   writel(0, base + ADE_OVLY_CTL);
  

•   writel(0, base + ADE_OVLYX_CTL(ADE_OVLY2));
  

•   /* clear reset and reload regs */
  

•   writel(MASK(32), base + ADE_SOFT_RST_SEL(0));
  

•   writel(MASK(32), base + ADE_SOFT_RST_SEL(1));
  

•   writel(MASK(32), base + ADE_RELOAD_DIS(0));
  

•   writel(MASK(32), base + ADE_RELOAD_DIS(1));
  

•   /* for video mode, that ade registers
  

•    * became effective at frame end
  

s/became/become

Consider re-writing this comment

Agree, will fix in next version.

...

•    */
  

•   ade_update_bits(base + ADE_CTRL, FRM_END_START_OFST,
  

•                   FRM_END_START_MASK,
  

REG_EFFECTIVE_IN_ADEEN_FRMEND); +}

+static void ade_ldi_set_mode(struct ade_crtc *acrtc,

•                        struct drm_display_mode *mode,
  

•                        struct drm_display_mode *adj_mode)
  

+{

•   struct ade_hw_ctx *ctx = acrtc->ctx;
  

•   void __iomem *base = ctx->base;
  

•   u32 width = mode->hdisplay;
  

•   u32 height = mode->vdisplay;
  

•   u32 hfp, hbp, hsw, vfp, vbp, vsw;
  

•   u32 plr_flags;
  

•   int ret;
  

•   plr_flags = (mode->flags & DRM_MODE_FLAG_NVSYNC) ? FLAG_NVSYNC :
  

0;

•   plr_flags |= (mode->flags & DRM_MODE_FLAG_NHSYNC) ? FLAG_NHSYNC :
  

0;

•   hfp = mode->hsync_start - mode->hdisplay;
  

•   hbp = mode->htotal - mode->hsync_end;
  

•   hsw = mode->hsync_end - mode->hsync_start;
  

•   vfp = mode->vsync_start - mode->vdisplay;
  

•   vbp = mode->vtotal - mode->vsync_end;
  

•   vsw = mode->vsync_end - mode->vsync_start;
  

•   if (vsw > 15) {
  

•           DRM_DEBUG_DRIVER("vsw exceeded 15\n");
  

•           vsw = 15;
  

•   }
  

•   writel((hbp << HBP_OFST) | hfp, base + LDI_HRZ_CTRL0);
  

•    /* the configured value is actual value - 1 */
  

•   writel(hsw - 1, base + LDI_HRZ_CTRL1);
  

•   writel((vbp << VBP_OFST) | vfp, base + LDI_VRT_CTRL0);
  

•    /* the configured value is actual value - 1 */
  

•   writel(vsw - 1, base + LDI_VRT_CTRL1);
  

•    /* the configured value is actual value - 1 */
  

•   writel(((height - 1) << VSIZE_OFST) | (width - 1),
  

•          base + LDI_DSP_SIZE);
  

•   writel(plr_flags, base + LDI_PLR_CTRL);
  

•   /* Success should be guaranteed in mode_valid call back,
  

•    * so failer shouldn't happen here
  

s/failer/failure

Also, please use the standard way of writing multiple lines of comments here and elsewhere in the driver.

The standard way should be:

/* * Some comments. */

right?

...

•    */
  

•   ret = clk_set_rate(ctx->ade_pix_clk, mode->clock * 1000);
  

•   if (ret)
  

•           DRM_ERROR("failed to set pixel clk %dHz (%d)\n",
  

•                     mode->clock * 1000, ret);
  

•   adj_mode->clock = clk_get_rate(ctx->ade_pix_clk) / 1000;
  

•   /* ctran6 setting */
  

•   writel(CTRAN_BYPASS_ON, base + ADE_CTRAN_DIS(ADE_CTRAN6));
  

•    /* the configured value is actual value - 1 */
  

•   writel(width * height - 1, base +
  

ADE_CTRAN_IMAGE_SIZE(ADE_CTRAN6));

•   ade_update_reload_bit(base, CTRAN_OFST + ADE_CTRAN6, 0);
  

•   DRM_DEBUG_DRIVER("set mode: %dx%d\n", width, height);
  

+}

+static int ade_power_up(struct ade_hw_ctx *ctx) +{

•   int ret;
  

•   ret = clk_prepare_enable(ctx->media_noc_clk);
  

•   if (ret) {
  

•           DRM_ERROR("failed to enable media_noc_clk (%d)\n", ret);
  

•           return ret;
  

•   }
  

•   ret = reset_control_deassert(ctx->reset);
  

•   if (ret) {
  

•           DRM_ERROR("failed to deassert reset\n");
  

•           return ret;
  

•   }
  

•   ret = clk_prepare_enable(ctx->ade_core_clk);
  

•   if (ret) {
  

•           DRM_ERROR("failed to enable ade_core_clk (%d)\n", ret);
  

•           return ret;
  

•   }
  

•   ade_init(ctx);
  

•   ctx->power_on = true;
  

•   return 0;
  

+}

+static void ade_power_down(struct ade_hw_ctx *ctx) +{

•   void __iomem *base = ctx->base;
  

•   writel(ADE_DISABLE, base + LDI_CTRL);
  

•   /* dsi pixel off */
  

•   writel(DSI_PCLK_OFF, base + LDI_HDMI_DSI_GT);
  

•   clk_disable_unprepare(ctx->ade_core_clk);
  

•   reset_control_assert(ctx->reset);
  

•   clk_disable_unprepare(ctx->media_noc_clk);
  

•   ctx->power_on = false;
  

+}

+static void ade_set_medianoc_qos(struct ade_crtc *acrtc) +{

•   struct ade_hw_ctx *ctx = acrtc->ctx;
  

•   struct regmap *map = ctx->noc_regmap;
  

•   regmap_update_bits(map, ADE0_QOSGENERATOR_MODE,
  

•                      QOSGENERATOR_MODE_MASK, BYPASS_MODE);
  

•   regmap_update_bits(map, ADE0_QOSGENERATOR_EXTCONTROL,
  

•                      SOCKET_QOS_EN, SOCKET_QOS_EN);
  

•   regmap_update_bits(map, ADE1_QOSGENERATOR_MODE,
  

•                      QOSGENERATOR_MODE_MASK, BYPASS_MODE);
  

•   regmap_update_bits(map, ADE1_QOSGENERATOR_EXTCONTROL,
  

•                      SOCKET_QOS_EN, SOCKET_QOS_EN);
  

+}

+static void ade_display_enable(struct ade_crtc *acrtc) +{

•   struct ade_hw_ctx *ctx = acrtc->ctx;
  

•   void __iomem *base = ctx->base;
  

•   u32 out_fmt = acrtc->out_format;
  

•   /* display source setting */
  

•   writel(DISP_SRC_OVLY2, base + ADE_DISP_SRC_CFG);
  

•   /* enable ade */
  

•   writel(ADE_ENABLE, base + ADE_EN);
  

•   /* enable ldi */
  

•   writel(NORMAL_MODE, base + LDI_WORK_MODE);
  

•   writel((out_fmt << BPP_OFST) | DATA_GATE_EN | LDI_EN,
  

•          base + LDI_CTRL);
  

•   /* dsi pixel on */
  

•   writel(DSI_PCLK_ON, base + LDI_HDMI_DSI_GT);
  

+}

+static void ade_crtc_enable(struct drm_crtc *crtc) +{

•   struct ade_crtc *acrtc = to_ade_crtc(crtc);
  

•   struct ade_hw_ctx *ctx = acrtc->ctx;
  

•   int ret;
  

•   if (acrtc->enable)
  

•           return;
  

•   if (!ctx->power_on) {
  

•           ret = ade_power_up(ctx);
  

•           if (ret)
  

•                   return;
  

•   }
  

•   ade_set_medianoc_qos(acrtc);
  

•   ade_display_enable(acrtc);
  

•   acrtc->enable = true;
  

+}

+static void ade_crtc_disable(struct drm_crtc *crtc) +{

•   struct ade_crtc *acrtc = to_ade_crtc(crtc);
  

•   struct ade_hw_ctx *ctx = acrtc->ctx;
  

•   if (!acrtc->enable)
  

•           return;
  

•   ade_power_down(ctx);
  

•   acrtc->enable = false;
  

+}

+static int ade_crtc_atomic_check(struct drm_crtc *crtc,

•                            struct drm_crtc_state *state)
  

+{

•   /* do nothing */
  

•   return 0;
  

+}

+static void ade_crtc_mode_set_nofb(struct drm_crtc *crtc) +{

•   struct ade_crtc *acrtc = to_ade_crtc(crtc);
  

•   struct ade_hw_ctx *ctx = acrtc->ctx;
  

•   struct drm_display_mode *mode = &crtc->state->mode;
  

•   struct drm_display_mode *adj_mode = &crtc->state->adjusted_mode;
  

•   if (!ctx->power_on)
  

•           (void)ade_power_up(ctx);
  

•   ade_ldi_set_mode(acrtc, mode, adj_mode);
  

+}

+static void ade_crtc_atomic_begin(struct drm_crtc *crtc,

•                             struct drm_crtc_state *old_state)
  

+{

•   struct ade_crtc *acrtc = to_ade_crtc(crtc);
  

•   struct ade_hw_ctx *ctx = acrtc->ctx;
  

•   if (!ctx->power_on)
  

•           (void)ade_power_up(ctx);
  

+}

+static void ade_crtc_atomic_flush(struct drm_crtc *crtc,

•                             struct drm_crtc_state *old_state)
  

+{

•   struct ade_crtc *acrtc = to_ade_crtc(crtc);
  

•   struct ade_hw_ctx *ctx = acrtc->ctx;
  

•   void __iomem *base = ctx->base;
  

•   /* only crtc is eanbled regs take effect */
  

s/eanbled/enabled

will fix in next version.

...

•   if (acrtc->enable) {
  

•           /* flush ade regitsters */
  

s/regitsters/registers

Other than the minor comments:

Reviewed-by: Archit Taneja architt@codeaurora.org

Thanks -:)

...

•           writel(ADE_ENABLE, base + ADE_EN);
  

•   }
  

+}

+static const struct drm_crtc_helper_funcs ade_crtc_helper_funcs = {

•   .enable         = ade_crtc_enable,
  

•   .disable        = ade_crtc_disable,
  

•   .atomic_check   = ade_crtc_atomic_check,
  

•   .mode_set_nofb  = ade_crtc_mode_set_nofb,
  

•   .atomic_begin   = ade_crtc_atomic_begin,
  

•   .atomic_flush   = ade_crtc_atomic_flush,
  

+};

+static const struct drm_crtc_funcs ade_crtc_funcs = {

•   .destroy        = drm_crtc_cleanup,
  

•   .set_config     = drm_atomic_helper_set_config,
  

•   .page_flip      = drm_atomic_helper_page_flip,
  

•   .reset          = drm_atomic_helper_crtc_reset,
  

•   .set_property = drm_atomic_helper_crtc_set_property,
  

•   .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
  

•   .atomic_destroy_state   = drm_atomic_helper_crtc_destroy_state,
  

+};

+static int ade_crtc_init(struct drm_device *dev, struct drm_crtc *crtc,

•                    struct drm_plane *plane)
  

+{

•   struct kirin_drm_private *priv = dev->dev_private;
  

•   struct device_node *port;
  

•   int ret;
  

•   /* set crtc port so that
  

•    * drm_of_find_possible_crtcs call works
  

•    */
  

•   port = of_get_child_by_name(dev->dev->of_node, "port");
  

•   if (!port) {
  

•           DRM_ERROR("no port node found in %s\n",
  

•                     dev->dev->of_node->full_name);
  

•           return -EINVAL;
  

•   }
  

•   of_node_put(port);
  

•   crtc->port = port;
  

•   ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL,
  

•                                   &ade_crtc_funcs, NULL);
  

•   if (ret) {
  

•           DRM_ERROR("failed to init crtc.\n");
  

•           return ret;
  

•   }
  

•   drm_crtc_helper_add(crtc, &ade_crtc_helper_funcs);
  

•   priv->crtc[drm_crtc_index(crtc)] = crtc;
  

•   return 0;
  

+}

+static int ade_dts_parse(struct platform_device *pdev, struct ade_hw_ctx *ctx) +{

•   struct resource *res;
  

•   struct device *dev = &pdev->dev;
  

•   struct device_node *np = pdev->dev.of_node;
  

•   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  

•   ctx->base = devm_ioremap_resource(dev, res);
  

•   if (IS_ERR(ctx->base)) {
  

•           DRM_ERROR("failed to remap ade io base\n");
  

•           return  PTR_ERR(ctx->base);
  

•   }
  

•   ctx->reset = devm_reset_control_get(dev, NULL);
  

•   if (IS_ERR(ctx->reset))
  

•           return PTR_ERR(ctx->reset);
  

•   ctx->noc_regmap =
  

•           syscon_regmap_lookup_by_phandle(np,
  

"hisilicon,noc-syscon");

•   if (IS_ERR(ctx->noc_regmap)) {
  

•           DRM_ERROR("failed to get noc regmap\n");
  

•           return PTR_ERR(ctx->noc_regmap);
  

•   }
  

•   ctx->irq = platform_get_irq(pdev, 0);
  

•   if (ctx->irq < 0) {
  

•           DRM_ERROR("failed to get irq\n");
  

•           return -ENODEV;
  

•   }
  

•   ctx->ade_core_clk = devm_clk_get(dev, "clk_ade_core");
  

•   if (!ctx->ade_core_clk) {
  

•           DRM_ERROR("failed to parse clk ADE_CORE\n");
  

•           return -ENODEV;
  

•   }
  

•   ctx->media_noc_clk = devm_clk_get(dev, "clk_codec_jpeg");
  

•   if (!ctx->media_noc_clk) {
  

•           DRM_ERROR("failed to parse clk CODEC_JPEG\n");
  

•       return -ENODEV;
  

•   }
  

•   ctx->ade_pix_clk = devm_clk_get(dev, "clk_ade_pix");
  

•   if (!ctx->ade_pix_clk) {
  

•           DRM_ERROR("failed to parse clk ADE_PIX\n");
  

•       return -ENODEV;
  

•   }
  

•   return 0;
  

+}

+int ade_drm_init(struct drm_device *dev) +{

•   struct platform_device *pdev = dev->platformdev;
  

•   struct ade_data *ade;
  

•   struct ade_hw_ctx *ctx;
  

•   struct ade_crtc *acrtc;
  

•   int ret;
  

•   ade = devm_kzalloc(dev->dev, sizeof(*ade), GFP_KERNEL);
  

•   if (!ade) {
  

•           DRM_ERROR("failed to alloc ade_data\n");
  

•           return -ENOMEM;
  

•   }
  

•   platform_set_drvdata(pdev, ade);
  

•   ctx = &ade->ctx;
  

•   acrtc = &ade->acrtc;
  

•   acrtc->ctx = ctx;
  

•   acrtc->out_format = LDI_OUT_RGB_888;
  

•   ret = ade_dts_parse(pdev, ctx);
  

•   if (ret)
  

•           return ret;
  

•   return 0;
  

+}

+void ade_drm_cleanup(struct drm_device *dev) +{

•   struct platform_device *pdev = dev->platformdev;
  

•   struct ade_data *ade = platform_get_drvdata(pdev);
  

•   struct drm_crtc *crtc = &ade->acrtc.base;
  

•   drm_crtc_cleanup(crtc);
  

+}

+const struct kirin_dc_ops ade_dc_ops = {

•   .init = ade_drm_init,
  

•   .cleanup = ade_drm_cleanup
  

+}; diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c index 789ebd1f5922..055729c1889c 100644 --- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c @@ -30,8 +30,12 @@ static struct kirin_dc_ops *dc_ops;

static int kirin_drm_kms_cleanup(struct drm_device *dev) {

•   struct kirin_drm_private *priv = dev->dev_private;
  

•   dc_ops->cleanup(dev);
    drm_mode_config_cleanup(dev);
  

•   devm_kfree(dev->dev, priv);
  

•   dev->dev_private = NULL;
  
    return 0;
  

  }

@@ -55,8 +59,14 @@ static void kirin_drm_mode_config_init(struct drm_device *dev)

static int kirin_drm_kms_init(struct drm_device *dev) {

•   struct kirin_drm_private *priv;
    int ret;
  
  

•   priv = devm_kzalloc(dev->dev, sizeof(*priv), GFP_KERNEL);
  

•   if (!priv)
  

•           return -ENOMEM;
  

•   dev->dev_private = priv;
    dev_set_drvdata(dev->dev, dev);
  
    /* dev->mode_config initialization */
  

@@ -84,6 +94,8 @@ err_dc_cleanup: dc_ops->cleanup(dev); err_mode_config_cleanup: drm_mode_config_cleanup(dev);

•   devm_kfree(dev->dev, priv);
  

•   dev->dev_private = NULL;
  
    return ret;
  

  }

@@ -221,6 +233,9 @@ static const struct component_master_ops kirin_drm_ops = { };

static const struct of_device_id kirin_drm_dt_ids[] = {

•   { .compatible = "hisilicon,hi6220-ade",
  

•     .data = &ade_dc_ops,
  

•   },
    { /* end node */ },
  

  }; MODULE_DEVICE_TABLE(of, kirin_drm_dt_ids);

diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h index 75e9d82356d4..5a05ad6a81db 100644 --- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h @@ -11,10 +11,18 @@ #ifndef __KIRIN_DRM_DRV_H__ #define __KIRIN_DRM_DRV_H__

+#define MAX_CRTC 2

• /* display controller init/cleanup ops */ struct kirin_dc_ops { int (*init)(struct drm_device *dev); void (*cleanup)(struct drm_device *dev); };

+struct kirin_drm_private {

•   struct drm_crtc *crtc[MAX_CRTC];
  

+};

+extern const struct kirin_dc_ops ade_dc_ops;

• #endif /* __KIRIN_DRM_DRV_H__ */

-- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project

On 2/26/2016 2:10 PM, Xinliang Liu wrote:

Add plane funcs and helper funcs for ADE.

v6: None. v5: None. v4: None. v3:

• A few cleanup.

v2:

• Remove abtraction layer.

Signed-off-by: Xinliang Liu xinliang.liu@linaro.org

drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 535 +++++++++++++++++++++++- 1 file changed, 534 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c index bb93616dcf3d..aa2cf75cab39 100644 --- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c @@ -27,13 +27,23 @@ #include <drm/drm_crtc_helper.h> #include <drm/drm_atomic.h> #include <drm/drm_atomic_helper.h> +#include <drm/drm_plane_helper.h> +#include <drm/drm_gem_cma_helper.h> +#include <drm/drm_fb_cma_helper.h>

#include "kirin_drm_drv.h" #include "kirin_ade_reg.h"

+#define PRIMARY_CH ADE_CH1 /* primary plane */ +#define OUT_OVLY ADE_OVLY2 /* output overlay compositor */

Could you briefly explain this overlay/channel mapping? It looks like it's something that is hard coded at the moment.

Do channels map to planes, and OVLs map to crtcs?

+#define ADE_DEBUG 1

• #define to_ade_crtc(crtc) \ container_of(crtc, struct ade_crtc, base)

+#define to_ade_plane(plane) \

• container_of(plane, struct ade_plane, base)
• struct ade_hw_ctx { void __iomem *base; struct regmap *noc_regmap;

@@ -52,11 +62,76 @@ struct ade_crtc { u32 out_format; };

+struct ade_plane {

• struct drm_plane base;
• void *ctx;
• u8 ch; /* channel */

+};

• struct ade_data { struct ade_crtc acrtc;
• struct ade_plane aplane[ADE_CH_NUM]; struct ade_hw_ctx ctx; };

+/* ade-format info: */ +struct ade_format {

• u32 pixel_format;
• enum ade_fb_format ade_format;

+};

+static const struct ade_format ade_formats[] = {

• /* 16bpp RGB: */
• { DRM_FORMAT_RGB565, ADE_RGB_565 },
• { DRM_FORMAT_BGR565, ADE_BGR_565 },
• /* 24bpp RGB: */
• { DRM_FORMAT_RGB888, ADE_RGB_888 },
• { DRM_FORMAT_BGR888, ADE_BGR_888 },
• /* 32bpp [A]RGB: */
• { DRM_FORMAT_XRGB8888, ADE_XRGB_8888 },
• { DRM_FORMAT_XBGR8888, ADE_XBGR_8888 },
• { DRM_FORMAT_RGBA8888, ADE_RGBA_8888 },
• { DRM_FORMAT_BGRA8888, ADE_BGRA_8888 },
• { DRM_FORMAT_ARGB8888, ADE_ARGB_8888 },
• { DRM_FORMAT_ABGR8888, ADE_ABGR_8888 },

+};

+static const u32 channel_formats1[] = {

• /* channel 1,2,3,4 */
• DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, DRM_FORMAT_RGB888,
• DRM_FORMAT_BGR888, DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888,
• DRM_FORMAT_RGBA8888, DRM_FORMAT_BGRA8888, DRM_FORMAT_ARGB8888,
• DRM_FORMAT_ABGR8888

+};

+u32 ade_get_channel_formats(u8 ch, const u32 **formats) +{

• switch (ch) {
• case ADE_CH1:

• *formats = channel_formats1;
  

• return ARRAY_SIZE(channel_formats1);
  

• default:

• DRM_ERROR("no this channel %d\n", ch);
  

• *formats = NULL;
  

• return 0;
  

• }

+}

+/* convert from fourcc format to ade format */ +static u32 ade_get_format(u32 pixel_format) +{

• int i;
• for (i = 0; i < ARRAY_SIZE(ade_formats); i++)

• if (ade_formats[i].pixel_format == pixel_format)
  

• 	return ade_formats[i].ade_format;
  

• /* not found */
• DRM_ERROR("Not found pixel format!!fourcc_format= %d\n",

•   pixel_format);
  

• return ADE_FORMAT_NOT_SUPPORT;

+}

• static void ade_update_reload_bit(void __iomem *base, u32 bit_num, u32 val) { u32 bit_ofst, reg_num;

@@ -89,7 +164,7 @@ static void ade_init(struct ade_hw_ctx *ctx) /* clear overlay */ writel(0, base + ADE_OVLY1_TRANS_CFG); writel(0, base + ADE_OVLY_CTL);

• writel(0, base + ADE_OVLYX_CTL(ADE_OVLY2));

• writel(0, base + ADE_OVLYX_CTL(OUT_OVLY)); /* clear reset and reload regs */ writel(MASK(32), base + ADE_SOFT_RST_SEL(0)); writel(MASK(32), base + ADE_SOFT_RST_SEL(1));

@@ -147,6 +222,10 @@ static void ade_ldi_set_mode(struct ade_crtc *acrtc, mode->clock * 1000, ret); adj_mode->clock = clk_get_rate(ctx->ade_pix_clk) / 1000;

• /* set overlay compositor output size */
• writel(((width - 1) << OUTPUT_XSIZE_OFST) | (height - 1),

•       base + ADE_OVLY_OUTPUT_SIZE(OUT_OVLY));
  

• /* ctran6 setting */ writel(CTRAN_BYPASS_ON, base + ADE_CTRAN_DIS(ADE_CTRAN6)); /* the configured value is actual value - 1 */

@@ -219,6 +298,10 @@ static void ade_display_enable(struct ade_crtc *acrtc) void __iomem *base = ctx->base; u32 out_fmt = acrtc->out_format;

• /* enable output overlay compositor */
• writel(ADE_ENABLE, base + ADE_OVLYX_CTL(OUT_OVLY));
• ade_update_reload_bit(base, OVLY_OFST + OUT_OVLY, 0);
• /* display source setting */ writel(DISP_SRC_OVLY2, base + ADE_DISP_SRC_CFG);

@@ -232,6 +315,97 @@ static void ade_display_enable(struct ade_crtc *acrtc) writel(DSI_PCLK_ON, base + LDI_HDMI_DSI_GT); }

+#if ADE_DEBUG +static void ade_rdma_dump_regs(void __iomem *base, u32 ch) +{

• u32 reg_ctrl, reg_addr, reg_size, reg_stride, reg_space, reg_en;
• u32 val;
• reg_ctrl = RD_CH_CTRL(ch);
• reg_addr = RD_CH_ADDR(ch);
• reg_size = RD_CH_SIZE(ch);
• reg_stride = RD_CH_STRIDE(ch);
• reg_space = RD_CH_SPACE(ch);
• reg_en = RD_CH_EN(ch);
• val = ade_read_reload_bit(base, RDMA_OFST + ch);
• DRM_DEBUG_DRIVER("[rdma%d]: reload(%d)\n", ch + 1, val);
• val = readl(base + reg_ctrl);
• DRM_DEBUG_DRIVER("[rdma%d]: reg_ctrl(0x%08x)\n", ch + 1, val);
• val = readl(base + reg_addr);
• DRM_DEBUG_DRIVER("[rdma%d]: reg_addr(0x%08x)\n", ch + 1, val);
• val = readl(base + reg_size);
• DRM_DEBUG_DRIVER("[rdma%d]: reg_size(0x%08x)\n", ch + 1, val);
• val = readl(base + reg_stride);
• DRM_DEBUG_DRIVER("[rdma%d]: reg_stride(0x%08x)\n", ch + 1, val);
• val = readl(base + reg_space);
• DRM_DEBUG_DRIVER("[rdma%d]: reg_space(0x%08x)\n", ch + 1, val);
• val = readl(base + reg_en);
• DRM_DEBUG_DRIVER("[rdma%d]: reg_en(0x%08x)\n", ch + 1, val);

+}

+static void ade_clip_dump_regs(void __iomem *base, u32 ch) +{

• u32 val;
• val = ade_read_reload_bit(base, CLIP_OFST + ch);
• DRM_DEBUG_DRIVER("[clip%d]: reload(%d)\n", ch + 1, val);
• val = readl(base + ADE_CLIP_DISABLE(ch));
• DRM_DEBUG_DRIVER("[clip%d]: reg_clip_disable(0x%08x)\n", ch + 1, val);
• val = readl(base + ADE_CLIP_SIZE0(ch));
• DRM_DEBUG_DRIVER("[clip%d]: reg_clip_size0(0x%08x)\n", ch + 1, val);
• val = readl(base + ADE_CLIP_SIZE1(ch));
• DRM_DEBUG_DRIVER("[clip%d]: reg_clip_size1(0x%08x)\n", ch + 1, val);

+}

+static void ade_compositor_routing_dump_regs(void __iomem *base, u32 ch) +{

• u8 ovly_ch = 0; /* TODO: Only primary plane now */
• u32 val;
• val = readl(base + ADE_OVLY_CH_XY0(ovly_ch));
• DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_xy0(0x%08x)\n", ovly_ch, val);
• val = readl(base + ADE_OVLY_CH_XY1(ovly_ch));
• DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_xy1(0x%08x)\n", ovly_ch, val);
• val = readl(base + ADE_OVLY_CH_CTL(ovly_ch));
• DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_ctl(0x%08x)\n", ovly_ch, val);

+}

+static void ade_dump_overlay_compositor_regs(void __iomem *base, u32 comp) +{

• u32 val;
• val = ade_read_reload_bit(base, OVLY_OFST + comp);
• DRM_DEBUG_DRIVER("[overlay%d]: reload(%d)\n", comp + 1, val);
• writel(ADE_ENABLE, base + ADE_OVLYX_CTL(comp));
• DRM_DEBUG_DRIVER("[overlay%d]: reg_ctl(0x%08x)\n", comp + 1, val);
• val = readl(base + ADE_OVLY_CTL);
• DRM_DEBUG_DRIVER("ovly_ctl(0x%08x)\n", val);

+}

+static void ade_dump_regs(void __iomem *base) +{

• u32 i;
• /* dump channel regs */
• for (i = 0; i < ADE_CH_NUM; i++) {

• /* dump rdma regs */
  

• ade_rdma_dump_regs(base, i);
  

• /* dump clip regs */
  

• ade_clip_dump_regs(base, i);
  

• /* dump compositor routing regs */
  

• ade_compositor_routing_dump_regs(base, i);
  

• }
• /* dump overlay compositor regs */
• ade_dump_overlay_compositor_regs(base, OUT_OVLY);

+} +#else +static void ade_dump_regs(void __iomem *base) { } +#endif

• static void ade_crtc_enable(struct drm_crtc *crtc) { struct ade_crtc *acrtc = to_ade_crtc(crtc);

@@ -249,6 +423,7 @@ static void ade_crtc_enable(struct drm_crtc *crtc)

ade_set_medianoc_qos(acrtc); ade_display_enable(acrtc);

• ade_dump_regs(ctx->base); acrtc->enable = true; }

@@ -303,6 +478,7 @@ static void ade_crtc_atomic_flush(struct drm_crtc *crtc,

/* only crtc is eanbled regs take effect */ if (acrtc->enable) {

• ade_dump_regs(base);
  

  /* flush ade regitsters */ writel(ADE_ENABLE, base + ADE_EN); }

@@ -359,6 +535,338 @@ static int ade_crtc_init(struct drm_device *dev, struct drm_crtc *crtc, return 0; }

+static void ade_rdma_set(void __iomem *base, struct drm_framebuffer *fb,

• 	 u32 ch, u32 y, u32 in_h, u32 fmt)
  

+{

• struct drm_gem_cma_object *obj = drm_fb_cma_get_gem_obj(fb, 0);
• u32 reg_ctrl, reg_addr, reg_size, reg_stride, reg_space, reg_en;
• u32 stride = fb->pitches[0];
• u32 addr = (u32)obj->paddr + y * stride;
• DRM_DEBUG_DRIVER("rdma%d: (y=%d, height=%d), stride=%d, paddr=0x%x\n",

• 	 ch + 1, y, in_h, stride, (u32)obj->paddr);
  

• DRM_DEBUG_DRIVER("addr=0x%x, fb:%dx%d, pixel_format=%d(%s)\n",

• 	 addr, fb->width, fb->height, fmt,
  

• 	 drm_get_format_name(fb->pixel_format));
  

• /* get reg offset */
• reg_ctrl = RD_CH_CTRL(ch);
• reg_addr = RD_CH_ADDR(ch);
• reg_size = RD_CH_SIZE(ch);
• reg_stride = RD_CH_STRIDE(ch);
• reg_space = RD_CH_SPACE(ch);
• reg_en = RD_CH_EN(ch);
• /*

• * TODO: set rotation
  

• */
  

• writel((fmt << 16) & 0x1f0000, base + reg_ctrl);
• writel(addr, base + reg_addr);
• writel((in_h << 16) | stride, base + reg_size);
• writel(stride, base + reg_stride);
• writel(in_h * stride, base + reg_space);
• writel(ADE_ENABLE, base + reg_en);
• ade_update_reload_bit(base, RDMA_OFST + ch, 0);

+}

+static void ade_rdma_disable(void __iomem *base, u32 ch) +{

• u32 reg_en;
• /* get reg offset */
• reg_en = RD_CH_EN(ch);
• writel(0, base + reg_en);
• ade_update_reload_bit(base, RDMA_OFST + ch, 1);

+}

+static void ade_clip_set(void __iomem *base, u32 ch, u32 fb_w, u32 x,

• 	 u32 in_w, u32 in_h)
  

+{

• u32 disable_val;
• u32 clip_left;
• u32 clip_right;
• /*

• * clip width, no need to clip height
  

• */
  

• if (fb_w == in_w) { /* bypass */

• disable_val = 1;
  

• clip_left = 0;
  

• clip_right = 0;
  

• } else {

• disable_val = 0;
  

• clip_left = x;
  

• clip_right = fb_w - (x + in_w) - 1;
  

• }
• DRM_DEBUG_DRIVER("clip%d: clip_left=%d, clip_right=%d\n",

• 	 ch + 1, clip_left, clip_right);
  

• writel(disable_val, base + ADE_CLIP_DISABLE(ch));
• writel((fb_w - 1) << 16 | (in_h - 1), base + ADE_CLIP_SIZE0(ch));
• writel(clip_left << 16 | clip_right, base + ADE_CLIP_SIZE1(ch));
• ade_update_reload_bit(base, CLIP_OFST + ch, 0);

+}

+static void ade_clip_disable(void __iomem *base, u32 ch) +{

• writel(1, base + ADE_CLIP_DISABLE(ch));
• ade_update_reload_bit(base, CLIP_OFST + ch, 1);

+}

+static bool has_Alpha_channel(int format) +{

• switch (format) {
• case ADE_ARGB_8888:
• case ADE_ABGR_8888:
• case ADE_RGBA_8888:
• case ADE_BGRA_8888:

• return true;
  

• default:

• return false;
  

• }

+}

+static void ade_get_blending_params(u32 fmt, u8 glb_alpha, u8 *alp_mode,

• 		    u8 *alp_sel, u8 *under_alp_sel)
  

+{

• bool has_alpha = has_Alpha_channel(fmt);
• /*

• * get alp_mode
  

• */
  

• if (has_alpha && glb_alpha < 255)

• *alp_mode = ADE_ALP_PIXEL_AND_GLB;
  

• else if (has_alpha)

• *alp_mode = ADE_ALP_PIXEL;
  

• else

• *alp_mode = ADE_ALP_GLOBAL;
  

• /*

• * get alp sel
  

• */
  

• *alp_sel = ADE_ALP_MUL_COEFF_3; /* 1 */
• *under_alp_sel = ADE_ALP_MUL_COEFF_2; /* 0 */

+}

+static void ade_compositor_routing_set(void __iomem *base, u8 ch,

• 		       u32 x0, u32 y0,
  

• 		       u32 in_w, u32 in_h, u32 fmt)
  

+{

• u8 ovly_ch = 0; /* TODO: This is the zpos, only one plane now */

Does the ovly_ch map to the crtc here? If so, maybe instead of hard coding it here, you could extract the channel number via plane->crtc?

Other than the hard coding, it looks fine to me.

Thanks, Archit

Hi,

On 1 March 2016 at 02:48, Archit Taneja architt@codeaurora.org wrote:

On 2/26/2016 2:10 PM, Xinliang Liu wrote:

...

Add vblank irq handle.

v6: None. v5: None. v4: None. v3:

• Remove hisi_get_crtc_from_index func.
• A few cleanup.

v2:

• Remove abtraction layer.

Signed-off-by: Xinliang Liu xinliang.liu@linaro.org

drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 62 +++++++++++++++++++++++++ drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c | 14 +++++- 2 files changed, 75 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c index aa2cf75cab39..749382952ab7 100644 --- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c @@ -292,6 +292,59 @@ static void ade_set_medianoc_qos(struct ade_crtc *acrtc) SOCKET_QOS_EN, SOCKET_QOS_EN); }

+static int ade_enable_vblank(struct drm_device *dev, unsigned int pipe) +{

•   struct kirin_drm_private *priv = dev->dev_private;
  

•   struct ade_crtc *acrtc = to_ade_crtc(priv->crtc[pipe]);
  

•   struct ade_hw_ctx *ctx = acrtc->ctx;
  

•   void __iomem *base = ctx->base;
  

•   if (!ctx->power_on)
  

•           (void)ade_power_up(ctx);
  

•   ade_update_bits(base + LDI_INT_EN, FRAME_END_INT_EN_OFST,
  

•                   MASK(1), 1);
  

•   return 0;
  

+}

+static void ade_disable_vblank(struct drm_device *dev, unsigned int pipe) +{

•   struct kirin_drm_private *priv = dev->dev_private;
  

•   struct ade_crtc *acrtc = to_ade_crtc(priv->crtc[pipe]);
  

•   struct ade_hw_ctx *ctx = acrtc->ctx;
  

•   void __iomem *base = ctx->base;
  

•   if (!ctx->power_on) {
  

•           DRM_ERROR("power is down! vblank disable fail\n");
  

•           return;
  

•   }
  

•   ade_update_bits(base + LDI_INT_EN, FRAME_END_INT_EN_OFST,
  

•                   MASK(1), 0);
  

+}

+static irqreturn_t ade_irq_handler(int irq, void *data) +{

•   struct ade_crtc *acrtc = data;
  

•   struct ade_hw_ctx *ctx = acrtc->ctx;
  

•   struct drm_crtc *crtc = &acrtc->base;
  

•   void __iomem *base = ctx->base;
  

•   u32 status;
  

•   status = readl(base + LDI_MSK_INT);
  

•   DRM_DEBUG_VBL("LDI IRQ: status=0x%X\n", status);
  

•   /* vblank irq */
  

•   if (status & BIT(FRAME_END_INT_EN_OFST)) {
  

•           ade_update_bits(base + LDI_INT_CLR, FRAME_END_INT_EN_OFST,
  

•                           MASK(1), 1);
  

•           drm_crtc_handle_vblank(crtc);
  

•   }
  

•   return IRQ_HANDLED;
  

+}

• static void ade_display_enable(struct ade_crtc *acrtc) { struct ade_hw_ctx *ctx = acrtc->ctx;

@@ -967,6 +1020,15 @@ int ade_drm_init(struct drm_device *dev) if (ret) return ret;

•   /* vblank irq init */
  

•   ret = devm_request_irq(dev->dev, ctx->irq, ade_irq_handler,
  

•                          DRIVER_IRQ_SHARED, dev->driver->name,
  

acrtc);

This isn't the way we set up interrupts for kms drivers. We need to provide the handler in drm_driver and call drm_irq_install.

I prefer to set up interrupts here for two reasons. One is that it is easy to pass any interrupt private "void * data" to the interrupt handler here. As I discussed with Daniel Vetter before: https://lkml.org/lkml/2015/9/10/204.

Second is setting up interrupt here in the specific SoC display controller driver, make other SoC reuse the kirin_drm_drv.c code easily. Different Hisilicon SoC may has different display controller interrupts.

...

•   if (ret)
  

•           return ret;
  

•   dev->driver->get_vblank_counter = drm_vblank_no_hw_counter;
  

•   dev->driver->enable_vblank = ade_enable_vblank;
  

•   dev->driver->disable_vblank = ade_disable_vblank;
  

•   return 0;
  

  }

diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c index 055729c1889c..723888feb760 100644 --- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c @@ -32,6 +32,7 @@ static int kirin_drm_kms_cleanup(struct drm_device *dev) { struct kirin_drm_private *priv = dev->dev_private;

•   drm_vblank_cleanup(dev);
    dc_ops->cleanup(dev);
    drm_mode_config_cleanup(dev);
    devm_kfree(dev->dev, priv);
  

@@ -85,11 +86,22 @@ static int kirin_drm_kms_init(struct drm_device *dev) goto err_dc_cleanup; }

•   /* vblank init */
  

•   ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
  

•   if (ret) {
  

•           DRM_ERROR("failed to initialize vblank.\n");
  

•           goto err_unbind_all;
  

•   }
  

•   /* with irq_enabled = true, we can use the vblank feature. */
  

•   dev->irq_enabled = true;
  

•   /* reset all the states of crtc/plane/encoder/connector */
    drm_mode_config_reset(dev);
  
    return 0;
  
  

+err_unbind_all:

•   component_unbind_all(dev->dev, dev);
  

  err_dc_cleanup: dc_ops->cleanup(dev); err_mode_config_cleanup:

@@ -123,7 +135,7 @@ static int kirin_gem_cma_dumb_create(struct drm_file *file,

static struct drm_driver kirin_drm_driver = { .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME |

•                             DRIVER_ATOMIC,
  

•                             DRIVER_ATOMIC | DRIVER_HAVE_IRQ,
  

DRIVER_IRQ_SHARED should be added here if you want IRQF_SHARED flag set when requesting the handler.

If not using the drm_irq_install to set up interrupts, DRIVER_IRQ_SHARED may not be required to set.

Thanks, -xinliang

Archit

...

    .fops                   = &kirin_drm_fops,
    .set_busid              = drm_platform_set_busid,

-- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project

On 1 March 2016 at 20:40, Archit Taneja architt@codeaurora.org wrote:

On 3/1/2016 3:44 PM, Xinliang Liu wrote:

...

Hi,

On 1 March 2016 at 02:48, Archit Taneja architt@codeaurora.org wrote:

...

On 2/26/2016 2:10 PM, Xinliang Liu wrote:

...

Add vblank irq handle.

v6: None. v5: None. v4: None. v3:

• Remove hisi_get_crtc_from_index func.
• A few cleanup.

v2:

• Remove abtraction layer.

Signed-off-by: Xinliang Liu xinliang.liu@linaro.org

drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 62 +++++++++++++++++++++++++ drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c | 14 +++++- 2 files changed, 75 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c index aa2cf75cab39..749382952ab7 100644 --- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c @@ -292,6 +292,59 @@ static void ade_set_medianoc_qos(struct ade_crtc *acrtc) SOCKET_QOS_EN, SOCKET_QOS_EN); }

+static int ade_enable_vblank(struct drm_device *dev, unsigned int pipe) +{

•   struct kirin_drm_private *priv = dev->dev_private;
  

•   struct ade_crtc *acrtc = to_ade_crtc(priv->crtc[pipe]);
  

•   struct ade_hw_ctx *ctx = acrtc->ctx;
  

•   void __iomem *base = ctx->base;
  

•   if (!ctx->power_on)
  

•           (void)ade_power_up(ctx);
  

•   ade_update_bits(base + LDI_INT_EN, FRAME_END_INT_EN_OFST,
  

•                   MASK(1), 1);
  

•   return 0;
  

+}

+static void ade_disable_vblank(struct drm_device *dev, unsigned int pipe) +{

•   struct kirin_drm_private *priv = dev->dev_private;
  

•   struct ade_crtc *acrtc = to_ade_crtc(priv->crtc[pipe]);
  

•   struct ade_hw_ctx *ctx = acrtc->ctx;
  

•   void __iomem *base = ctx->base;
  

•   if (!ctx->power_on) {
  

•           DRM_ERROR("power is down! vblank disable fail\n");
  

•           return;
  

•   }
  

•   ade_update_bits(base + LDI_INT_EN, FRAME_END_INT_EN_OFST,
  

•                   MASK(1), 0);
  

+}

+static irqreturn_t ade_irq_handler(int irq, void *data) +{

•   struct ade_crtc *acrtc = data;
  

•   struct ade_hw_ctx *ctx = acrtc->ctx;
  

•   struct drm_crtc *crtc = &acrtc->base;
  

•   void __iomem *base = ctx->base;
  

•   u32 status;
  

•   status = readl(base + LDI_MSK_INT);
  

•   DRM_DEBUG_VBL("LDI IRQ: status=0x%X\n", status);
  

•   /* vblank irq */
  

•   if (status & BIT(FRAME_END_INT_EN_OFST)) {
  

•           ade_update_bits(base + LDI_INT_CLR,
  

FRAME_END_INT_EN_OFST,

•                           MASK(1), 1);
  

•           drm_crtc_handle_vblank(crtc);
  

•   }
  

•   return IRQ_HANDLED;
  

+}

• static void ade_display_enable(struct ade_crtc *acrtc) { struct ade_hw_ctx *ctx = acrtc->ctx;

@@ -967,6 +1020,15 @@ int ade_drm_init(struct drm_device *dev) if (ret) return ret;

•   /* vblank irq init */
  

•   ret = devm_request_irq(dev->dev, ctx->irq, ade_irq_handler,
  

•                          DRIVER_IRQ_SHARED, dev->driver->name,
  

acrtc);

This isn't the way we set up interrupts for kms drivers. We need to provide the handler in drm_driver and call drm_irq_install.

I prefer to set up interrupts here for two reasons. One is that it is easy to pass any interrupt private "void * data" to the interrupt handler here. As I discussed with Daniel Vetter before: https://lkml.org/lkml/2015/9/10/204.

Second is setting up interrupt here in the specific SoC display controller driver, make other SoC reuse the kirin_drm_drv.c code easily. Different Hisilicon SoC may has different display controller interrupts.

Sure, as long as this has been discussed before.

...

...

...

•   if (ret)
  

•           return ret;
  

•   dev->driver->get_vblank_counter = drm_vblank_no_hw_counter;
  

•   dev->driver->enable_vblank = ade_enable_vblank;
  

•   dev->driver->disable_vblank = ade_disable_vblank;
  

•    return 0;
  

  }

diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c index 055729c1889c..723888feb760 100644 --- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c @@ -32,6 +32,7 @@ static int kirin_drm_kms_cleanup(struct drm_device *dev) { struct kirin_drm_private *priv = dev->dev_private;

•   drm_vblank_cleanup(dev);
     dc_ops->cleanup(dev);
     drm_mode_config_cleanup(dev);
     devm_kfree(dev->dev, priv);
  

@@ -85,11 +86,22 @@ static int kirin_drm_kms_init(struct drm_device *dev) goto err_dc_cleanup; }

•   /* vblank init */
  

•   ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
  

•   if (ret) {
  

•           DRM_ERROR("failed to initialize vblank.\n");
  

•           goto err_unbind_all;
  

•   }
  

•   /* with irq_enabled = true, we can use the vblank feature. */
  

•   dev->irq_enabled = true;
  

•    /* reset all the states of crtc/plane/encoder/connector */
     drm_mode_config_reset(dev);
  
     return 0;
  
  

+err_unbind_all:

•   component_unbind_all(dev->dev, dev);
  

  err_dc_cleanup: dc_ops->cleanup(dev); err_mode_config_cleanup:

@@ -123,7 +135,7 @@ static int kirin_gem_cma_dumb_create(struct drm_file *file,

static struct drm_driver kirin_drm_driver = { .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME |

•                             DRIVER_ATOMIC,
  

•                             DRIVER_ATOMIC | DRIVER_HAVE_IRQ,
  

DRIVER_IRQ_SHARED should be added here if you want IRQF_SHARED flag set when requesting the handler.

If not using the drm_irq_install to set up interrupts, DRIVER_IRQ_SHARED may not be required to set.

Yes. In any case, you should use IRQF_SHARED and not DRIVER_IRQ_SHARED in the call to devm_request_irq(). The latter is a drm flag meant to be used only for driver_features.

agree, will fix in next version.

Thanks, Archit

-- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project

Hi,

On 1 March 2016 at 02:49, Archit Taneja architt@codeaurora.org wrote:

On 2/26/2016 2:10 PM, Xinliang Liu wrote:

...

Add DesignWare MIPI DSI Host Controller v1.02 encoder driver for hi6220 SoC.

v6:

• Change "pclk_dsi" to "pclk".

v5: None. v4: None. v3:

• Rename file name to dw_drm_dsi.c
• Make encoder type as DRM_MODE_ENCODER_DSI.
• A few cleanup.

v2:

• Remove abtraction layer.

Signed-off-by: Xinliang Liu xinliang.liu@linaro.org Signed-off-by: Xinwei Kong kong.kongxinwei@hisilicon.com Signed-off-by: Andy Green andy.green@linaro.org

---

drivers/gpu/drm/hisilicon/kirin/Kconfig | 1 + drivers/gpu/drm/hisilicon/kirin/Makefile | 3 +- drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c | 743 +++++++++++++++++++++++++++ drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h | 83 +++ 4 files changed, 829 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c create mode 100644 drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h

diff --git a/drivers/gpu/drm/hisilicon/kirin/Kconfig b/drivers/gpu/drm/hisilicon/kirin/Kconfig index 3ac4b8edeac1..de0d454c5c13 100644 --- a/drivers/gpu/drm/hisilicon/kirin/Kconfig +++ b/drivers/gpu/drm/hisilicon/kirin/Kconfig @@ -4,6 +4,7 @@ config DRM_HISI_KIRIN select DRM_KMS_HELPER select DRM_GEM_CMA_HELPER select DRM_KMS_CMA_HELPER

•   select DRM_MIPI_DSI
    help
      Choose this option if you have a hisilicon Kirin
  

chipsets(hi6220). If M is selected the module will be called kirin-drm. diff --git a/drivers/gpu/drm/hisilicon/kirin/Makefile b/drivers/gpu/drm/hisilicon/kirin/Makefile index 2a61ab006ddb..5dcd0d4328b6 100644 --- a/drivers/gpu/drm/hisilicon/kirin/Makefile +++ b/drivers/gpu/drm/hisilicon/kirin/Makefile @@ -1,4 +1,5 @@ kirin-drm-y := kirin_drm_drv.o \

•          kirin_drm_ade.o
  

•          kirin_drm_ade.o \
  

•          dw_drm_dsi.o
  
  

  obj-$(CONFIG_DRM_HISI_KIRIN) += kirin-drm.o

diff --git a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c new file mode 100644 index 000000000000..8329148cc89d --- /dev/null +++ b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c @@ -0,0 +1,743 @@ +/*

• • DesignWare MIPI DSI Host Controller v1.02 driver
• • Copyright (c) 2016 Linaro Limited.
• • Copyright (c) 2014-2016 Hisilicon Limited.
• • Author:

• • Xinliang Liu <z.liuxinliang@hisilicon.com>
    

• • Xinliang Liu <xinliang.liu@linaro.org>
    

• • Xinwei Kong <kong.kongxinwei@hisilicon.com>
    

• • This program is free software; you can redistribute it and/or modify
• • it under the terms of the GNU General Public License version 2 as
• • published by the Free Software Foundation.
• */

+#include <linux/clk.h> +#include <linux/component.h> +#include <linux/of_graph.h>

+#include <drm/drm_of.h> +#include <drm/drm_crtc_helper.h> +#include <drm/drm_mipi_dsi.h> +#include <drm/drm_encoder_slave.h> +#include <drm/drm_atomic_helper.h>

+#include "dw_dsi_reg.h"

+#define MAX_TX_ESC_CLK (10) +#define ROUND(x, y) ((x) / (y) + ((x) % (y) * 10 / (y) >= 5 ? 1 : 0)) +#define PHY_REF_CLK_RATE 19200000 +#define PHY_REF_CLK_PERIOD_PS (1000000000 / (PHY_REF_CLK_RATE / 1000))

+#define encoder_to_dsi(encoder) \

•   container_of(encoder, struct dw_dsi, encoder)
  

+#define host_to_dsi(host) \

•   container_of(host, struct dw_dsi, host)
  

+struct mipi_phy_params {

•   u32 clk_t_lpx;
  

•   u32 clk_t_hs_prepare;
  

•   u32 clk_t_hs_zero;
  

•   u32 clk_t_hs_trial;
  

•   u32 clk_t_wakeup;
  

•   u32 data_t_lpx;
  

•   u32 data_t_hs_prepare;
  

•   u32 data_t_hs_zero;
  

•   u32 data_t_hs_trial;
  

•   u32 data_t_ta_go;
  

•   u32 data_t_ta_get;
  

•   u32 data_t_wakeup;
  

•   u32 hstx_ckg_sel;
  

•   u32 pll_fbd_div5f;
  

•   u32 pll_fbd_div1f;
  

•   u32 pll_fbd_2p;
  

•   u32 pll_enbwt;
  

•   u32 pll_fbd_p;
  

•   u32 pll_fbd_s;
  

•   u32 pll_pre_div1p;
  

•   u32 pll_pre_p;
  

•   u32 pll_vco_750M;
  

•   u32 pll_lpf_rs;
  

•   u32 pll_lpf_cs;
  

•   u32 clklp2hs_time;
  

•   u32 clkhs2lp_time;
  

•   u32 lp2hs_time;
  

•   u32 hs2lp_time;
  

•   u32 clk_to_data_delay;
  

•   u32 data_to_clk_delay;
  

•   u32 lane_byte_clk_kHz;
  

•   u32 clk_division;
  

+};

+struct dsi_hw_ctx {

•   void __iomem *base;
  

•   struct clk *pclk;
  

+};

+struct dw_dsi {

•   struct drm_encoder encoder;
  

•   struct drm_display_mode cur_mode;
  

•   struct dsi_hw_ctx *ctx;
  

•   struct mipi_phy_params phy;
  

•   u32 lanes;
  

•   enum mipi_dsi_pixel_format format;
  

•   unsigned long mode_flags;
  

•   bool enable;
  

+};

+struct dsi_data {

•   struct dw_dsi dsi;
  

•   struct dsi_hw_ctx ctx;
  

+};

+struct dsi_phy_range {

•   u32 min_range_kHz;
  

•   u32 max_range_kHz;
  

•   u32 pll_vco_750M;
  

•   u32 hstx_ckg_sel;
  

+};

+static const struct dsi_phy_range dphy_range_info[] = {

•   {   46875,    62500,   1,    7 },
  

•   {   62500,    93750,   0,    7 },
  

•   {   93750,   125000,   1,    6 },
  

•   {  125000,   187500,   0,    6 },
  

•   {  187500,   250000,   1,    5 },
  

•   {  250000,   375000,   0,    5 },
  

•   {  375000,   500000,   1,    4 },
  

•   {  500000,   750000,   0,    4 },
  

•   {  750000,  1000000,   1,    0 },
  

•   { 1000000,  1500000,   0,    0 }
  

+};

+static void dsi_get_phy_params(u32 phy_freq_kHz,

•                          struct mipi_phy_params *phy)
  

+{

•   u32 ui = 0;
  

•   u32 cfg_clk_ps = PHY_REF_CLK_PERIOD_PS;
  

•   u32 i = 0;
  

•   u32 q_pll = 1;
  

•   u32 m_pll = 0;
  

•   u32 n_pll = 0;
  

•   u32 r_pll = 1;
  

•   u32 m_n = 0;
  

•   u32 m_n_int = 0;
  

•   u64 f_kHz;
  

•   u64 temp;
  

•   u64 tmp_kHz = phy_freq_kHz;
  

•   do {
  

•           f_kHz = tmp_kHz;
  

•           /* Find the PLL clock range from the table */
  

•           for (i = 0; i < ARRAY_SIZE(dphy_range_info); i++)
  

•                   if (f_kHz >= dphy_range_info[i].min_range_kHz &&
  

•                       f_kHz <= dphy_range_info[i].max_range_kHz)
  

•                           break;
  

•           if (i == ARRAY_SIZE(dphy_range_info)) {
  

•                   DRM_ERROR("%lldkHz out of range\n", f_kHz);
  

•                   return;
  

•           }
  

•           phy->pll_vco_750M = dphy_range_info[i].pll_vco_750M;
  

•           phy->hstx_ckg_sel = dphy_range_info[i].hstx_ckg_sel;
  

•           if (phy->hstx_ckg_sel <= 7 &&
  

•               phy->hstx_ckg_sel >= 4)
  

•                   q_pll = 0x10 >> (7 - phy->hstx_ckg_sel);
  

•           temp = f_kHz * (u64)q_pll * (u64)cfg_clk_ps;
  

•           m_n_int = temp / (u64)1000000000;
  

•           m_n = (temp % (u64)1000000000) / (u64)100000000;
  

•           if (m_n_int % 2 == 0) {
  

•                   if (m_n * 6 >= 50) {
  

•                           n_pll = 2;
  

•                           m_pll = (m_n_int + 1) * n_pll;
  

•                   } else if (m_n * 6 >= 30) {
  

•                           n_pll = 3;
  

•                           m_pll = m_n_int * n_pll + 2;
  

•                   } else {
  

•                           n_pll = 1;
  

•                           m_pll = m_n_int * n_pll;
  

•                   }
  

•           } else {
  

•                   if (m_n * 6 >= 50) {
  

•                           n_pll = 1;
  

•                           m_pll = (m_n_int + 1) * n_pll;
  

•                   } else if (m_n * 6 >= 30) {
  

•                           n_pll = 1;
  

•                           m_pll = (m_n_int + 1) * n_pll;
  

•                   } else if (m_n * 6 >= 10) {
  

•                           n_pll = 3;
  

•                           m_pll = m_n_int * n_pll + 1;
  

•                   } else {
  

•                           n_pll = 2;
  

•                           m_pll = m_n_int * n_pll;
  

•                   }
  

•           }
  

•           if (n_pll == 1) {
  

•                   phy->pll_fbd_p = 0;
  

•                   phy->pll_pre_div1p = 1;
  

•           } else {
  

•                   phy->pll_fbd_p = n_pll;
  

•                   phy->pll_pre_div1p = 0;
  

•           }
  

•           if (phy->pll_fbd_2p <= 7 && phy->pll_fbd_2p >= 4)
  

•                   r_pll = 0x10 >> (7 - phy->pll_fbd_2p);
  

•           if (m_pll == 2) {
  

•                   phy->pll_pre_p = 0;
  

•                   phy->pll_fbd_s = 0;
  

•                   phy->pll_fbd_div1f = 0;
  

•                   phy->pll_fbd_div5f = 1;
  

•           } else if (m_pll >= 2 * 2 * r_pll && m_pll <= 2 * 4 *
  

r_pll) {

•                   phy->pll_pre_p = m_pll / (2 * r_pll);
  

•                   phy->pll_fbd_s = 0;
  

•                   phy->pll_fbd_div1f = 1;
  

•                   phy->pll_fbd_div5f = 0;
  

•           } else if (m_pll >= 2 * 5 * r_pll && m_pll <= 2 * 150 *
  

r_pll) {

•                   if (((m_pll / (2 * r_pll)) % 2) == 0) {
  

•                           phy->pll_pre_p =
  

•                                   (m_pll / (2 * r_pll)) / 2 - 1;
  

•                           phy->pll_fbd_s =
  

•                                   (m_pll / (2 * r_pll)) % 2 + 2;
  

•                   } else {
  

•                           phy->pll_pre_p =
  

•                                   (m_pll / (2 * r_pll)) / 2;
  

•                           phy->pll_fbd_s =
  

•                                   (m_pll / (2 * r_pll)) % 2;
  

•                   }
  

•                   phy->pll_fbd_div1f = 0;
  

•                   phy->pll_fbd_div5f = 0;
  

•           } else {
  

•                   phy->pll_pre_p = 0;
  

•                   phy->pll_fbd_s = 0;
  

•                   phy->pll_fbd_div1f = 0;
  

•                   phy->pll_fbd_div5f = 1;
  

•           }
  

•           f_kHz = (u64)1000000000 * (u64)m_pll /
  

•                   ((u64)cfg_clk_ps * (u64)n_pll * (u64)q_pll);
  

•           if (f_kHz >= phy_freq_kHz)
  

•                   break;
  

•           tmp_kHz += 10;
  

•   } while (1);
  

•   ui = 1000000 / f_kHz;
  

•   phy->clk_t_lpx = ROUND(50, 8 * ui);
  

•   phy->clk_t_hs_prepare = ROUND(133, 16 * ui) - 1;
  

•   phy->clk_t_hs_zero = ROUND(262, 8 * ui);
  

•   phy->clk_t_hs_trial = 2 * (ROUND(60, 8 * ui) - 1);
  

•   phy->clk_t_wakeup = ROUND(1000000, (cfg_clk_ps / 1000) - 1);
  

•   if (phy->clk_t_wakeup > 0xff)
  

•           phy->clk_t_wakeup = 0xff;
  

•   phy->data_t_wakeup = phy->clk_t_wakeup;
  

•   phy->data_t_lpx = phy->clk_t_lpx;
  

•   phy->data_t_hs_prepare = ROUND(125 + 10 * ui, 16 * ui) - 1;
  

•   phy->data_t_hs_zero = ROUND(105 + 6 * ui, 8 * ui);
  

•   phy->data_t_hs_trial = 2 * (ROUND(60 + 4 * ui, 8 * ui) - 1);
  

•   phy->data_t_ta_go = 3;
  

•   phy->data_t_ta_get = 4;
  

•   phy->pll_enbwt = 1;
  

•   phy->clklp2hs_time = ROUND(407, 8 * ui) + 12;
  

•   phy->clkhs2lp_time = ROUND(105 + 12 * ui, 8 * ui);
  

•   phy->lp2hs_time = ROUND(240 + 12 * ui, 8 * ui) + 1;
  

•   phy->hs2lp_time = phy->clkhs2lp_time;
  

•   phy->clk_to_data_delay = 1 + phy->clklp2hs_time;
  

•   phy->data_to_clk_delay = ROUND(60 + 52 * ui, 8 * ui) +
  

•                           phy->clkhs2lp_time;
  

•   phy->lane_byte_clk_kHz = f_kHz / 8;
  

•   phy->clk_division = phy->lane_byte_clk_kHz / MAX_TX_ESC_CLK;
  

•   if (phy->lane_byte_clk_kHz % MAX_TX_ESC_CLK)
  

•           phy->clk_division++;
  

+}

+static u32 dsi_get_dpi_color_coding(enum mipi_dsi_pixel_format format) +{

•   u32 val;
  

•   /* TODO: only support RGB888 now, to support more */
  

•   switch (format) {
  

•   case MIPI_DSI_FMT_RGB888:
  

•           val = DSI_24BITS_1;
  

•           break;
  

•   default:
  

•           val = DSI_24BITS_1;
  

•           break;
  

•   }
  

•   return val;
  

+}

+/*

• • dsi phy reg write function
• */

+static void dsi_phy_tst_set(void __iomem *base, u32 reg, u32 val) +{

•   writel(reg, base + PHY_TST_CTRL1);
  

•   /* reg addr written at first */
  

•   wmb();
  

•   writel(0x02, base + PHY_TST_CTRL0);
  

•   /* cmd1 sent for write */
  

•   wmb();
  

•   writel(0x00, base + PHY_TST_CTRL0);
  

•   /* cmd2 sent for write */
  

•   wmb();
  

•   writel(val, base + PHY_TST_CTRL1);
  

•   /* Then write data */
  

•   wmb();
  

•   writel(0x02, base + PHY_TST_CTRL0);
  

•   /* cmd2 sent for write */
  

•   wmb();
  

•   writel(0x00, base + PHY_TST_CTRL0);
  

You can use iowrite32 here to prevent calling wmb before each write.