Now that the necessary GuC-based hardware workarounds have landed, we're finally ready to actually enable compute engines for use by userspace. All of the "under-the-hood" heavy lifting already landed a while back in other series so all that remains now is to add I915_ENGINE_CLASS_COMPUTE to the uapi enum and add the CCS engines to the engine lists for the Xe_HP SDV and DG2.
Userspace (both Mesa and compute drivers) are linked in the ABI patch. Existing IGT tests (e.g., i915_hangman) provide test coverage for general engine behavior since compute engines should follow the same general rules as other engines. We've also recently added some additional subtests like igt@gem_reset_stats@shared-reset-domain to cover the user-visible impacts of the compute engines sharing the same hardware reset domain as the render engine.
Cc: Lucas De Marchi lucas.demarchi@intel.com
Daniele Ceraolo Spurio (1): drm/i915: Xe_HP SDV and DG2 have up to 4 CCS engines
Matt Roper (1): drm/i915/xehp: Add compute engine ABI
drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt.c | 1 + drivers/gpu/drm/i915/i915_drm_client.c | 1 + drivers/gpu/drm/i915/i915_drm_client.h | 2 +- drivers/gpu/drm/i915/i915_pci.c | 6 +- include/uapi/drm/i915_drm.h | 62 +++++++++++++++++++-- 6 files changed, 64 insertions(+), 10 deletions(-)
We're now ready to start exposing compute engines to userspace.
While we're at it, let's extend the kerneldoc description for the other engine types as well.
Cc: Daniele Ceraolo Spurio daniele.ceraolospurio@intel.com Cc: Tvrtko Ursulin tvrtko.ursulin@linux.intel.com Cc: Vinay Belgaumkar vinay.belgaumkar@intel.com Cc: Jordan Justen jordan.l.justen@intel.com Cc: Szymon Morek szymon.morek@intel.com UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14395 UMD (compute): https://github.com/intel/compute-runtime/pull/451 Signed-off-by: Matt Roper matthew.d.roper@intel.com --- drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt.c | 1 + drivers/gpu/drm/i915/i915_drm_client.c | 1 + drivers/gpu/drm/i915/i915_drm_client.h | 2 +- include/uapi/drm/i915_drm.h | 62 +++++++++++++++++++-- 5 files changed, 60 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c index 0f6cd96b459f..46a174f8aa00 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c @@ -47,7 +47,7 @@ static const u8 uabi_classes[] = { [COPY_ENGINE_CLASS] = I915_ENGINE_CLASS_COPY, [VIDEO_DECODE_CLASS] = I915_ENGINE_CLASS_VIDEO, [VIDEO_ENHANCEMENT_CLASS] = I915_ENGINE_CLASS_VIDEO_ENHANCE, - /* TODO: Add COMPUTE_CLASS mapping once ABI is available */ + [COMPUTE_CLASS] = I915_ENGINE_CLASS_COMPUTE, };
static int engine_cmp(void *priv, const struct list_head *A, diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 92394f13b42f..c96e123496a5 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -1175,6 +1175,7 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR, [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR, [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR, + [COMPUTE_CLASS] = GEN12_GFX_TLB_INV_CR, }; struct drm_i915_private *i915 = gt->i915; struct intel_uncore *uncore = gt->uncore; diff --git a/drivers/gpu/drm/i915/i915_drm_client.c b/drivers/gpu/drm/i915/i915_drm_client.c index 475a6f824cad..18d38cb59923 100644 --- a/drivers/gpu/drm/i915/i915_drm_client.c +++ b/drivers/gpu/drm/i915/i915_drm_client.c @@ -81,6 +81,7 @@ static const char * const uabi_class_names[] = { [I915_ENGINE_CLASS_COPY] = "copy", [I915_ENGINE_CLASS_VIDEO] = "video", [I915_ENGINE_CLASS_VIDEO_ENHANCE] = "video-enhance", + [I915_ENGINE_CLASS_COMPUTE] = "compute", };
static u64 busy_add(struct i915_gem_context *ctx, unsigned int class) diff --git a/drivers/gpu/drm/i915/i915_drm_client.h b/drivers/gpu/drm/i915/i915_drm_client.h index 5f5b02b01ba0..f796c5e8e060 100644 --- a/drivers/gpu/drm/i915/i915_drm_client.h +++ b/drivers/gpu/drm/i915/i915_drm_client.h @@ -13,7 +13,7 @@
#include "gt/intel_engine_types.h"
-#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_VIDEO_ENHANCE +#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_COMPUTE
struct drm_i915_private;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 35ca528803fd..a2def7b27009 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -154,21 +154,71 @@ enum i915_mocs_table_index { I915_MOCS_CACHED, };
-/* +/** + * enum drm_i915_gem_engine_class - uapi engine type enumeration + * * Different engines serve different roles, and there may be more than one - * engine serving each role. enum drm_i915_gem_engine_class provides a - * classification of the role of the engine, which may be used when requesting - * operations to be performed on a certain subset of engines, or for providing - * information about that group. + * engine serving each role. This enum provides a classification of the role + * of the engine, which may be used when requesting operations to be performed + * on a certain subset of engines, or for providing information about that + * group. */ enum drm_i915_gem_engine_class { + /** + * @I915_ENGINE_CLASS_RENDER: + * + * Render engines support instructions used for 3D, Compute (GPGPU), + * and programmable media workloads. These instructions fetch data and + * dispatch individual work items to threads that operate in parallel. + * The threads run small programs (called "kernels" or "shaders") on + * the GPU's execution units (EUs). + */ I915_ENGINE_CLASS_RENDER = 0, + + /** + * @I915_ENGINE_CLASS_COPY: + * + * Copy engines (also referred to as "blitters") support instructions + * that move blocks of data from one location in memory to another, + * or that fill a specified location of memory with fixed data. + * Copy engines can perform pre-defined logical or bitwise operations + * on the source, destination, or pattern data. + */ I915_ENGINE_CLASS_COPY = 1, + + /** + * @I915_ENGINE_CLASS_VIDEO: + * + * Video engines (also referred to as "bit stream decode" (BSD) or + * "vdbox") support instructions that perform fixed-function media + * decode and encode. + */ I915_ENGINE_CLASS_VIDEO = 2, + + /** + * @I915_ENGINE_CLASS_VIDEO_ENHANCE: + * + * Video enhancement engines (also referred to as "vebox") support + * instructions related to image enhancement. + */ I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
- /* should be kept compact */ + /** + * @I915_ENGINE_CLASS_COMPUTE: + * + * Compute engines support a subset of the instructions available + * on render engines: compute engines support Compute (GPGPU) and + * programmable media workloads, but do not support the 3D pipeline. + */ + I915_ENGINE_CLASS_COMPUTE = 4, + + /* Values in this enum should be kept compact. */
+ /** + * @I915_ENGINE_CLASS_INVALID: + * + * Placeholder value to represent an invalid engine class assignment. + */ I915_ENGINE_CLASS_INVALID = -1 };
On 22/04/2022 20:50, Matt Roper wrote:
We're now ready to start exposing compute engines to userspace.
While we're at it, let's extend the kerneldoc description for the other engine types as well.
Cc: Daniele Ceraolo Spurio daniele.ceraolospurio@intel.com Cc: Tvrtko Ursulin tvrtko.ursulin@linux.intel.com Cc: Vinay Belgaumkar vinay.belgaumkar@intel.com Cc: Jordan Justen jordan.l.justen@intel.com Cc: Szymon Morek szymon.morek@intel.com UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14395 UMD (compute): https://github.com/intel/compute-runtime/pull/451
The compute one points to a commit named "Add compute engine class for xehp" but content of which seems more about engine query, including the yet non-existent distance query (and more)?! I certainly does not appear to be adding a definition of I915_ENGINE_CLASS_COMPUTE. This needs clarifying.
Signed-off-by: Matt Roper matthew.d.roper@intel.com
drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt.c | 1 + drivers/gpu/drm/i915/i915_drm_client.c | 1 + drivers/gpu/drm/i915/i915_drm_client.h | 2 +- include/uapi/drm/i915_drm.h | 62 +++++++++++++++++++-- 5 files changed, 60 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c index 0f6cd96b459f..46a174f8aa00 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c @@ -47,7 +47,7 @@ static const u8 uabi_classes[] = { [COPY_ENGINE_CLASS] = I915_ENGINE_CLASS_COPY, [VIDEO_DECODE_CLASS] = I915_ENGINE_CLASS_VIDEO, [VIDEO_ENHANCEMENT_CLASS] = I915_ENGINE_CLASS_VIDEO_ENHANCE,
- /* TODO: Add COMPUTE_CLASS mapping once ABI is available */
[COMPUTE_CLASS] = I915_ENGINE_CLASS_COMPUTE, };
static int engine_cmp(void *priv, const struct list_head *A,
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 92394f13b42f..c96e123496a5 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -1175,6 +1175,7 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR, [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR, [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR,
[COMPUTE_CLASS] = GEN12_GFX_TLB_INV_CR,
Do you know what 0xcf04 is?
Or if GEN12_GFX_TLB_INV_CR is correct then I think get_reg_and_bit() might need adjusting to always select bit 0 for any compute engine instance. Not sure how hardware would behave if value other than '1' would be written into 0xced8.
Regards,
Tvrtko
}; struct drm_i915_private *i915 = gt->i915; struct intel_uncore *uncore = gt->uncore; diff --git a/drivers/gpu/drm/i915/i915_drm_client.c b/drivers/gpu/drm/i915/i915_drm_client.c index 475a6f824cad..18d38cb59923 100644 --- a/drivers/gpu/drm/i915/i915_drm_client.c +++ b/drivers/gpu/drm/i915/i915_drm_client.c @@ -81,6 +81,7 @@ static const char * const uabi_class_names[] = { [I915_ENGINE_CLASS_COPY] = "copy", [I915_ENGINE_CLASS_VIDEO] = "video", [I915_ENGINE_CLASS_VIDEO_ENHANCE] = "video-enhance",
[I915_ENGINE_CLASS_COMPUTE] = "compute", };
static u64 busy_add(struct i915_gem_context *ctx, unsigned int class)
diff --git a/drivers/gpu/drm/i915/i915_drm_client.h b/drivers/gpu/drm/i915/i915_drm_client.h index 5f5b02b01ba0..f796c5e8e060 100644 --- a/drivers/gpu/drm/i915/i915_drm_client.h +++ b/drivers/gpu/drm/i915/i915_drm_client.h @@ -13,7 +13,7 @@
#include "gt/intel_engine_types.h"
-#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_VIDEO_ENHANCE +#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_COMPUTE
struct drm_i915_private;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 35ca528803fd..a2def7b27009 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -154,21 +154,71 @@ enum i915_mocs_table_index { I915_MOCS_CACHED, };
-/* +/**
- enum drm_i915_gem_engine_class - uapi engine type enumeration
- Different engines serve different roles, and there may be more than one
- engine serving each role. enum drm_i915_gem_engine_class provides a
- classification of the role of the engine, which may be used when requesting
- operations to be performed on a certain subset of engines, or for providing
- information about that group.
- engine serving each role. This enum provides a classification of the role
- of the engine, which may be used when requesting operations to be performed
- on a certain subset of engines, or for providing information about that
*/ enum drm_i915_gem_engine_class {
- group.
- /**
* @I915_ENGINE_CLASS_RENDER:** Render engines support instructions used for 3D, Compute (GPGPU),* and programmable media workloads. These instructions fetch data and* dispatch individual work items to threads that operate in parallel.* The threads run small programs (called "kernels" or "shaders") on* the GPU's execution units (EUs).*/- /**
* @I915_ENGINE_CLASS_COPY:** Copy engines (also referred to as "blitters") support instructions* that move blocks of data from one location in memory to another,* or that fill a specified location of memory with fixed data.* Copy engines can perform pre-defined logical or bitwise operations* on the source, destination, or pattern data.*/- /**
* @I915_ENGINE_CLASS_VIDEO:** Video engines (also referred to as "bit stream decode" (BSD) or* "vdbox") support instructions that perform fixed-function media* decode and encode.*/- /**
* @I915_ENGINE_CLASS_VIDEO_ENHANCE:** Video enhancement engines (also referred to as "vebox") support* instructions related to image enhancement.*/
- /* should be kept compact */
/**
* @I915_ENGINE_CLASS_COMPUTE:** Compute engines support a subset of the instructions available* on render engines: compute engines support Compute (GPGPU) and* programmable media workloads, but do not support the 3D pipeline.*/I915_ENGINE_CLASS_COMPUTE = 4,
/* Values in this enum should be kept compact. */
/**
* @I915_ENGINE_CLASS_INVALID:** Placeholder value to represent an invalid engine class assignment.*/I915_ENGINE_CLASS_INVALID = -1 };
On Mon, Apr 25, 2022 at 11:41:36AM +0100, Tvrtko Ursulin wrote:
On 22/04/2022 20:50, Matt Roper wrote:
We're now ready to start exposing compute engines to userspace.
While we're at it, let's extend the kerneldoc description for the other engine types as well.
Cc: Daniele Ceraolo Spurio daniele.ceraolospurio@intel.com Cc: Tvrtko Ursulin tvrtko.ursulin@linux.intel.com Cc: Vinay Belgaumkar vinay.belgaumkar@intel.com Cc: Jordan Justen jordan.l.justen@intel.com Cc: Szymon Morek szymon.morek@intel.com UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14395 UMD (compute): https://github.com/intel/compute-runtime/pull/451
The compute one points to a commit named "Add compute engine class for xehp" but content of which seems more about engine query, including the yet non-existent distance query (and more)?! I certainly does not appear to be adding a definition of I915_ENGINE_CLASS_COMPUTE. This needs clarifying.
Signed-off-by: Matt Roper matthew.d.roper@intel.com
drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt.c | 1 + drivers/gpu/drm/i915/i915_drm_client.c | 1 + drivers/gpu/drm/i915/i915_drm_client.h | 2 +- include/uapi/drm/i915_drm.h | 62 +++++++++++++++++++-- 5 files changed, 60 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c index 0f6cd96b459f..46a174f8aa00 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c @@ -47,7 +47,7 @@ static const u8 uabi_classes[] = { [COPY_ENGINE_CLASS] = I915_ENGINE_CLASS_COPY, [VIDEO_DECODE_CLASS] = I915_ENGINE_CLASS_VIDEO, [VIDEO_ENHANCEMENT_CLASS] = I915_ENGINE_CLASS_VIDEO_ENHANCE,
- /* TODO: Add COMPUTE_CLASS mapping once ABI is available */
- [COMPUTE_CLASS] = I915_ENGINE_CLASS_COMPUTE, }; static int engine_cmp(void *priv, const struct list_head *A,
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 92394f13b42f..c96e123496a5 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -1175,6 +1175,7 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR, [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR, [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR,
[COMPUTE_CLASS] = GEN12_GFX_TLB_INV_CR,Do you know what 0xcf04 is?
Or if GEN12_GFX_TLB_INV_CR is correct then I think get_reg_and_bit() might need adjusting to always select bit 0 for any compute engine instance. Not sure how hardware would behave if value other than '1' would be written into 0xced8.
I think Prathap and Fei have more familiarity with the MMIO TLB invalidation; adding them for their thoughts.
Matt
Regards,
Tvrtko
}; struct drm_i915_private *i915 = gt->i915; struct intel_uncore *uncore = gt->uncore; diff --git a/drivers/gpu/drm/i915/i915_drm_client.c b/drivers/gpu/drm/i915/i915_drm_client.c index 475a6f824cad..18d38cb59923 100644 --- a/drivers/gpu/drm/i915/i915_drm_client.c +++ b/drivers/gpu/drm/i915/i915_drm_client.c @@ -81,6 +81,7 @@ static const char * const uabi_class_names[] = { [I915_ENGINE_CLASS_COPY] = "copy", [I915_ENGINE_CLASS_VIDEO] = "video", [I915_ENGINE_CLASS_VIDEO_ENHANCE] = "video-enhance",
- [I915_ENGINE_CLASS_COMPUTE] = "compute", }; static u64 busy_add(struct i915_gem_context *ctx, unsigned int class)
diff --git a/drivers/gpu/drm/i915/i915_drm_client.h b/drivers/gpu/drm/i915/i915_drm_client.h index 5f5b02b01ba0..f796c5e8e060 100644 --- a/drivers/gpu/drm/i915/i915_drm_client.h +++ b/drivers/gpu/drm/i915/i915_drm_client.h @@ -13,7 +13,7 @@ #include "gt/intel_engine_types.h" -#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_VIDEO_ENHANCE +#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_COMPUTE struct drm_i915_private; diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 35ca528803fd..a2def7b27009 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -154,21 +154,71 @@ enum i915_mocs_table_index { I915_MOCS_CACHED, }; -/* +/**
- enum drm_i915_gem_engine_class - uapi engine type enumeration
- Different engines serve different roles, and there may be more than one
- engine serving each role. enum drm_i915_gem_engine_class provides a
- classification of the role of the engine, which may be used when requesting
- operations to be performed on a certain subset of engines, or for providing
- information about that group.
- engine serving each role. This enum provides a classification of the role
- of the engine, which may be used when requesting operations to be performed
- on a certain subset of engines, or for providing information about that
*/ enum drm_i915_gem_engine_class {
- group.
- /**
* @I915_ENGINE_CLASS_RENDER:** Render engines support instructions used for 3D, Compute (GPGPU),* and programmable media workloads. These instructions fetch data and* dispatch individual work items to threads that operate in parallel.* The threads run small programs (called "kernels" or "shaders") on* the GPU's execution units (EUs).*/- /**
* @I915_ENGINE_CLASS_COPY:** Copy engines (also referred to as "blitters") support instructions* that move blocks of data from one location in memory to another,* or that fill a specified location of memory with fixed data.* Copy engines can perform pre-defined logical or bitwise operations* on the source, destination, or pattern data.*/- /**
* @I915_ENGINE_CLASS_VIDEO:** Video engines (also referred to as "bit stream decode" (BSD) or* "vdbox") support instructions that perform fixed-function media* decode and encode.*/- /**
* @I915_ENGINE_CLASS_VIDEO_ENHANCE:** Video enhancement engines (also referred to as "vebox") support* instructions related to image enhancement.*/
- /* should be kept compact */
- /**
* @I915_ENGINE_CLASS_COMPUTE:** Compute engines support a subset of the instructions available* on render engines: compute engines support Compute (GPGPU) and* programmable media workloads, but do not support the 3D pipeline.*/- I915_ENGINE_CLASS_COMPUTE = 4,
- /* Values in this enum should be kept compact. */
- /**
* @I915_ENGINE_CLASS_INVALID:** Placeholder value to represent an invalid engine class assignment.*/
--- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -1175,6 +1175,7 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR, [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR, [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR,
[COMPUTE_CLASS] = GEN12_GFX_TLB_INV_CR,Do you know what 0xcf04 is?
Looks like that is the TLB invalidation register for each compute context.
Or if GEN12_GFX_TLB_INV_CR is correct then I think get_reg_and_bit() might need adjusting to always select bit 0 for any compute engine instance. Not sure how hardware would behave if value other than '1' would be written into 0xced8.
I think Prathap and Fei have more familiarity with the MMIO TLB invalidation; adding them for their thoughts.
I believe GEN12_GFX_TLB_INV_CR is the right one to use because we are invalidating the TLB for each engine. I'm not sure if we could narrow down to exact which compute context the TLB needs to be invalidated though. If that's possible it might be a bit more efficient.
Matt
Regards,
Tvrtko
On 25/04/2022 19:40, Yang, Fei wrote:
--- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -1175,6 +1175,7 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR, [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR, [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR,
[COMPUTE_CLASS] = GEN12_GFX_TLB_INV_CR,Do you know what 0xcf04 is?
Looks like that is the TLB invalidation register for each compute context.
What does compute "context" stand for in this context, as used in bspec? Not compute command streamer? Suspiciously individual bits (eight of them) are reserved per context, just like for example in GEN12_VD_TLB_INV_CR.
Or if GEN12_GFX_TLB_INV_CR is correct then I think get_reg_and_bit() might need adjusting to always select bit 0 for any compute engine instance. Not sure how hardware would behave if value other than '1' would be written into 0xced8.
I think Prathap and Fei have more familiarity with the MMIO TLB invalidation; adding them for their thoughts.
I believe GEN12_GFX_TLB_INV_CR is the right one to use because we are invalidating the TLB for each engine.
I don't understand this argument, I guess because I don't understand 0xcf04 still.
I'm not sure if we could narrow down to exact which compute context the TLB needs to be invalidated though. If that's possible it might be a bit more efficient.
Or even correct if 0xcf04 is for compute command streamers? That's my concern.
Regards,
Tvrtko
On Mon, Apr 25, 2022 at 11:41:36AM +0100, Tvrtko Ursulin wrote:
On 22/04/2022 20:50, Matt Roper wrote:
We're now ready to start exposing compute engines to userspace.
While we're at it, let's extend the kerneldoc description for the other engine types as well.
Cc: Daniele Ceraolo Spurio daniele.ceraolospurio@intel.com Cc: Tvrtko Ursulin tvrtko.ursulin@linux.intel.com Cc: Vinay Belgaumkar vinay.belgaumkar@intel.com Cc: Jordan Justen jordan.l.justen@intel.com Cc: Szymon Morek szymon.morek@intel.com UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14395 UMD (compute): https://github.com/intel/compute-runtime/pull/451
The compute one points to a commit named "Add compute engine class for xehp" but content of which seems more about engine query, including the yet non-existent distance query (and more)?! I certainly does not appear to be adding a definition of I915_ENGINE_CLASS_COMPUTE. This needs clarifying.
Signed-off-by: Matt Roper matthew.d.roper@intel.com
drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt.c | 1 + drivers/gpu/drm/i915/i915_drm_client.c | 1 + drivers/gpu/drm/i915/i915_drm_client.h | 2 +- include/uapi/drm/i915_drm.h | 62 +++++++++++++++++++-- 5 files changed, 60 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c index 0f6cd96b459f..46a174f8aa00 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c @@ -47,7 +47,7 @@ static const u8 uabi_classes[] = { [COPY_ENGINE_CLASS] = I915_ENGINE_CLASS_COPY, [VIDEO_DECODE_CLASS] = I915_ENGINE_CLASS_VIDEO, [VIDEO_ENHANCEMENT_CLASS] = I915_ENGINE_CLASS_VIDEO_ENHANCE,
- /* TODO: Add COMPUTE_CLASS mapping once ABI is available */
- [COMPUTE_CLASS] = I915_ENGINE_CLASS_COMPUTE, }; static int engine_cmp(void *priv, const struct list_head *A,
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 92394f13b42f..c96e123496a5 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -1175,6 +1175,7 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR, [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR, [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR,
[COMPUTE_CLASS] = GEN12_GFX_TLB_INV_CR,Do you know what 0xcf04 is?
The mmio 0xcf04 is the one we should use for compute class. And the context bit in 0xcf04 represents engine instance.
GEN12_GFX_TLB_INV_CR is for render class.
Thanks, Prathap
Or if GEN12_GFX_TLB_INV_CR is correct then I think get_reg_and_bit() might need adjusting to always select bit 0 for any compute engine instance. Not sure how hardware would behave if value other than '1' would be written into 0xced8.
Regards,
Tvrtko
}; struct drm_i915_private *i915 = gt->i915; struct intel_uncore *uncore = gt->uncore; diff --git a/drivers/gpu/drm/i915/i915_drm_client.c b/drivers/gpu/drm/i915/i915_drm_client.c index 475a6f824cad..18d38cb59923 100644 --- a/drivers/gpu/drm/i915/i915_drm_client.c +++ b/drivers/gpu/drm/i915/i915_drm_client.c @@ -81,6 +81,7 @@ static const char * const uabi_class_names[] = { [I915_ENGINE_CLASS_COPY] = "copy", [I915_ENGINE_CLASS_VIDEO] = "video", [I915_ENGINE_CLASS_VIDEO_ENHANCE] = "video-enhance",
- [I915_ENGINE_CLASS_COMPUTE] = "compute", }; static u64 busy_add(struct i915_gem_context *ctx, unsigned int class)
diff --git a/drivers/gpu/drm/i915/i915_drm_client.h b/drivers/gpu/drm/i915/i915_drm_client.h index 5f5b02b01ba0..f796c5e8e060 100644 --- a/drivers/gpu/drm/i915/i915_drm_client.h +++ b/drivers/gpu/drm/i915/i915_drm_client.h @@ -13,7 +13,7 @@ #include "gt/intel_engine_types.h" -#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_VIDEO_ENHANCE +#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_COMPUTE struct drm_i915_private; diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 35ca528803fd..a2def7b27009 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -154,21 +154,71 @@ enum i915_mocs_table_index { I915_MOCS_CACHED, }; -/* +/**
- enum drm_i915_gem_engine_class - uapi engine type enumeration
- Different engines serve different roles, and there may be more than one
- engine serving each role. enum drm_i915_gem_engine_class provides a
- classification of the role of the engine, which may be used when requesting
- operations to be performed on a certain subset of engines, or for providing
- information about that group.
- engine serving each role. This enum provides a classification of the role
- of the engine, which may be used when requesting operations to be performed
- on a certain subset of engines, or for providing information about that
*/ enum drm_i915_gem_engine_class {
- group.
- /**
* @I915_ENGINE_CLASS_RENDER:** Render engines support instructions used for 3D, Compute (GPGPU),* and programmable media workloads. These instructions fetch data and* dispatch individual work items to threads that operate in parallel.* The threads run small programs (called "kernels" or "shaders") on* the GPU's execution units (EUs).*/- /**
* @I915_ENGINE_CLASS_COPY:** Copy engines (also referred to as "blitters") support instructions* that move blocks of data from one location in memory to another,* or that fill a specified location of memory with fixed data.* Copy engines can perform pre-defined logical or bitwise operations* on the source, destination, or pattern data.*/- /**
* @I915_ENGINE_CLASS_VIDEO:** Video engines (also referred to as "bit stream decode" (BSD) or* "vdbox") support instructions that perform fixed-function media* decode and encode.*/- /**
* @I915_ENGINE_CLASS_VIDEO_ENHANCE:** Video enhancement engines (also referred to as "vebox") support* instructions related to image enhancement.*/
- /* should be kept compact */
- /**
* @I915_ENGINE_CLASS_COMPUTE:** Compute engines support a subset of the instructions available* on render engines: compute engines support Compute (GPGPU) and* programmable media workloads, but do not support the 3D pipeline.*/- I915_ENGINE_CLASS_COMPUTE = 4,
- /* Values in this enum should be kept compact. */
- /**
* @I915_ENGINE_CLASS_INVALID:** Placeholder value to represent an invalid engine class assignment.*/
On Mon, Apr 25, 2022 at 11:41:36AM +0100, Tvrtko Ursulin wrote:
On 22/04/2022 20:50, Matt Roper wrote:
We're now ready to start exposing compute engines to userspace.
While we're at it, let's extend the kerneldoc description for the other engine types as well.
Cc: Daniele Ceraolo Spurio daniele.ceraolospurio@intel.com Cc: Tvrtko Ursulin tvrtko.ursulin@linux.intel.com Cc: Vinay Belgaumkar vinay.belgaumkar@intel.com Cc: Jordan Justen jordan.l.justen@intel.com Cc: Szymon Morek szymon.morek@intel.com UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14395 UMD (compute): https://github.com/intel/compute-runtime/pull/451
The compute one points to a commit named "Add compute engine class for xehp" but content of which seems more about engine query, including the yet non-existent distance query (and more)?! I certainly does not appear to be adding a definition of I915_ENGINE_CLASS_COMPUTE. This needs clarifying.
Hi Syzmon, any updates on the compute UMD merge request here? Is there a different merge request we should reference for now that just uses the I915_ENGINE_CLASS_COMPUTE without also relying on the DRM_I915_QUERY_DISTANCE_INFO that we aren't upstreaming just yet?
I believe distance info is only useful for multi-tile platforms and isn't necessary for general use of compute engines on a single tile platform.
Thanks.
Matt
Hi Matt,
On Fri, Apr 22, 2022 at 12:50:06PM -0700, Matt Roper wrote:
We're now ready to start exposing compute engines to userspace.
While we're at it, let's extend the kerneldoc description for the other engine types as well.
I would make two different patches. The kerneldoc description is the biggest part of the lines added here.
Andi
Cc: Daniele Ceraolo Spurio daniele.ceraolospurio@intel.com Cc: Tvrtko Ursulin tvrtko.ursulin@linux.intel.com Cc: Vinay Belgaumkar vinay.belgaumkar@intel.com Cc: Jordan Justen jordan.l.justen@intel.com Cc: Szymon Morek szymon.morek@intel.com UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14395 UMD (compute): https://github.com/intel/compute-runtime/pull/451 Signed-off-by: Matt Roper matthew.d.roper@intel.com
drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt.c | 1 + drivers/gpu/drm/i915/i915_drm_client.c | 1 + drivers/gpu/drm/i915/i915_drm_client.h | 2 +- include/uapi/drm/i915_drm.h | 62 +++++++++++++++++++-- 5 files changed, 60 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c index 0f6cd96b459f..46a174f8aa00 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c @@ -47,7 +47,7 @@ static const u8 uabi_classes[] = { [COPY_ENGINE_CLASS] = I915_ENGINE_CLASS_COPY, [VIDEO_DECODE_CLASS] = I915_ENGINE_CLASS_VIDEO, [VIDEO_ENHANCEMENT_CLASS] = I915_ENGINE_CLASS_VIDEO_ENHANCE,
- /* TODO: Add COMPUTE_CLASS mapping once ABI is available */
- [COMPUTE_CLASS] = I915_ENGINE_CLASS_COMPUTE,
};
static int engine_cmp(void *priv, const struct list_head *A, diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 92394f13b42f..c96e123496a5 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -1175,6 +1175,7 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR, [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR, [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR,
[COMPUTE_CLASS] = GEN12_GFX_TLB_INV_CR,diff --git a/drivers/gpu/drm/i915/i915_drm_client.c b/drivers/gpu/drm/i915/i915_drm_client.c index 475a6f824cad..18d38cb59923 100644 --- a/drivers/gpu/drm/i915/i915_drm_client.c +++ b/drivers/gpu/drm/i915/i915_drm_client.c @@ -81,6 +81,7 @@ static const char * const uabi_class_names[] = { [I915_ENGINE_CLASS_COPY] = "copy", [I915_ENGINE_CLASS_VIDEO] = "video", [I915_ENGINE_CLASS_VIDEO_ENHANCE] = "video-enhance",
- [I915_ENGINE_CLASS_COMPUTE] = "compute",
};
static u64 busy_add(struct i915_gem_context *ctx, unsigned int class) diff --git a/drivers/gpu/drm/i915/i915_drm_client.h b/drivers/gpu/drm/i915/i915_drm_client.h index 5f5b02b01ba0..f796c5e8e060 100644 --- a/drivers/gpu/drm/i915/i915_drm_client.h +++ b/drivers/gpu/drm/i915/i915_drm_client.h @@ -13,7 +13,7 @@
#include "gt/intel_engine_types.h"
-#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_VIDEO_ENHANCE +#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_COMPUTE
struct drm_i915_private;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 35ca528803fd..a2def7b27009 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -154,21 +154,71 @@ enum i915_mocs_table_index { I915_MOCS_CACHED, };
-/* +/**
- enum drm_i915_gem_engine_class - uapi engine type enumeration
- Different engines serve different roles, and there may be more than one
- engine serving each role. enum drm_i915_gem_engine_class provides a
- classification of the role of the engine, which may be used when requesting
- operations to be performed on a certain subset of engines, or for providing
- information about that group.
- engine serving each role. This enum provides a classification of the role
- of the engine, which may be used when requesting operations to be performed
- on a certain subset of engines, or for providing information about that
*/
- group.
enum drm_i915_gem_engine_class {
- /**
* @I915_ENGINE_CLASS_RENDER:** Render engines support instructions used for 3D, Compute (GPGPU),* and programmable media workloads. These instructions fetch data and* dispatch individual work items to threads that operate in parallel.* The threads run small programs (called "kernels" or "shaders") on* the GPU's execution units (EUs).*/- /**
* @I915_ENGINE_CLASS_COPY:** Copy engines (also referred to as "blitters") support instructions* that move blocks of data from one location in memory to another,* or that fill a specified location of memory with fixed data.* Copy engines can perform pre-defined logical or bitwise operations* on the source, destination, or pattern data.*/- /**
* @I915_ENGINE_CLASS_VIDEO:** Video engines (also referred to as "bit stream decode" (BSD) or* "vdbox") support instructions that perform fixed-function media* decode and encode.*/- /**
* @I915_ENGINE_CLASS_VIDEO_ENHANCE:** Video enhancement engines (also referred to as "vebox") support* instructions related to image enhancement.*/
- /* should be kept compact */
/**
* @I915_ENGINE_CLASS_COMPUTE:** Compute engines support a subset of the instructions available* on render engines: compute engines support Compute (GPGPU) and* programmable media workloads, but do not support the 3D pipeline.*/I915_ENGINE_CLASS_COMPUTE = 4,
/* Values in this enum should be kept compact. */
/**
* @I915_ENGINE_CLASS_INVALID:** Placeholder value to represent an invalid engine class assignment.*/I915_ENGINE_CLASS_INVALID = -1
};
-- 2.35.1
From: Daniele Ceraolo Spurio daniele.ceraolospurio@intel.com
Cc: Vinay Belgaumkar vinay.belgaumkar@intel.com Signed-off-by: Daniele Ceraolo Spurio daniele.ceraolospurio@intel.com Signed-off-by: Matt Roper matthew.d.roper@intel.com Reviewed-by: Matt Roper matthew.d.roper@intel.com --- drivers/gpu/drm/i915/i915_pci.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index b60492826478..7739d6c33481 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -1037,7 +1037,8 @@ static const struct intel_device_info xehpsdv_info = { BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) | BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) | - BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7), + BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7) | + BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3), .require_force_probe = 1, };
@@ -1056,7 +1057,8 @@ static const struct intel_device_info xehpsdv_info = { .platform_engine_mask = \ BIT(RCS0) | BIT(BCS0) | \ BIT(VECS0) | BIT(VECS1) | \ - BIT(VCS0) | BIT(VCS2) + BIT(VCS0) | BIT(VCS2) | \ + BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3)
static const struct intel_device_info dg2_info = { DG2_FEATURES,
On Fri, Apr 22, 2022 at 12:50:07PM -0700, Matt Roper wrote:
From: Daniele Ceraolo Spurio daniele.ceraolospurio@intel.com
Cc: Vinay Belgaumkar vinay.belgaumkar@intel.com Signed-off-by: Daniele Ceraolo Spurio daniele.ceraolospurio@intel.com Signed-off-by: Matt Roper matthew.d.roper@intel.com Reviewed-by: Matt Roper matthew.d.roper@intel.com
Reviewed-by: Andi Shyti andi.shyti@linux.intel.com
Andi
dri-devel@lists.freedesktop.org
-
Andi Shyti -
Kumar Valsan, Prathap -
Matt Roper -
Tvrtko Ursulin -
Yang, Fei