On Wed, Oct 10, 2018 at 07:06:33PM -0700, Abhinav Kumar wrote:

Fix the dsi clock names in the DSI 10nm PLL driver to match the names in the dispcc driver as those are according to the clock plan of the chipset.

You should also update the clock diagram names at the top of the file.

Sean

Signed-off-by: Abhinav Kumar abhinavk@codeaurora.org

drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c index 41bec57..8304024 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c @@ -690,7 +690,7 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm)

hws[num++] = hw;

• snprintf(clk_name, 32, "dsi%dpllbyte", pll_10nm->id);

• snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_10nm->id); snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);

  /* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */

@@ -739,7 +739,7 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm)

hws[num++] = hw;

• snprintf(clk_name, 32, "dsi%dpll", pll_10nm->id);

• snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_10nm->id); snprintf(parent, 32, "dsi%d_pclk_mux", pll_10nm->id);

  /* PIX CLK DIV : DIV_CTRL_7_4*/

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